HK1141628B - Process for preparing an electronic device - Google Patents

Description

Method for manufacturing electronic device

Technical Field

The present invention relates to a method for producing an electronic device using a protective layer, and to an improved electronic device, in particular an Organic Field Effect Transistor (OFET), produced by such a method.

Background and Prior Art

Organic Field Effect Transistors (OFETs) are used in display devices and logic circuits. Conventional OFETs typically include a source, drain and gate electrode, a semiconductor layer containing an Organic Semiconductor (OSC) material, and a gate insulator layer containing a dielectric material.

To prepare a bottom-gate device, source and/or drain electrode layers comprising a metal or metal oxide are typically deposited onto a dielectric layer provided on a substrate. This is typically done by a sputtering process followed by a lithographic etching process to remove the unwanted areas.

Another conventional method of preparing a bottom gate OFET involves applying a patterned bank structure (banksstructure) onto the dielectric and source/drain layers, followed by deposition of an OSC layer (typically by ink jet printing) onto the bank structure, the dielectric and the electrode layers. For the positioning of the OSC layer, the surface of the bank structure is usually subjected to a plasma treatment process before applying the OSC layer, for example byExposure to CF₄Plasma or O₂Plasma is generated. CF (compact flash)₄The plasma causes the creation of a Teflon-like, extremely hydrophobic surface (very low surface energy), which prevents the inkjet droplets from being deposited with sufficient accuracy into the bank structure cavity.

However, it can be seen that in the OFET preparation method described above, the electrode sputtering method and the plasma treatment method may cause significant damage to the exposed portion of the surface of the dielectric layer. As a result, the performance of the device subjected to such a process deteriorates.

It is therefore an object of the present invention to provide an improved method for the preparation of electronic devices, in particular OFETs, which does not have the disadvantages of the prior art methods and which allows a time, cost and material efficient mass production of electronic devices, in particular an improved protection of dielectric layers and other functional layers against plasma surface treatment techniques or plasma-assisted deposition techniques applied during device manufacturing. It is a further object of the present invention to provide an improved electronic device, in particular an OFET, obtained by such a method. Other objects of the present invention will become readily apparent to the skilled artisan from the following detailed description.

It has been found that these objects can be achieved by providing the methods, materials and devices claimed in the present invention.

Summary of The Invention

The invention relates to a method of preparing an electronic device comprising a dielectric layer and at least one further functional layer, comprising the steps of: applying one or more additional layers or components over the dielectric layer or functional layer, wherein a protective layer is applied over the dielectric layer or over the functional layer prior to applying the additional layers or components. The purpose of the protective layer is to reduce or prevent damage in the dielectric layer or further functional layer that may be caused by subsequent manufacturing or processing steps of the device, in particular subsequent steps of applying or processing one or more additional layers or components.

The invention further relates to a method of manufacturing an electronic device, wherein at least one additional functional layer is applied onto the protective layer, and the protective layer is optionally partially removed after at least one of the additional layers is applied or processed.

The invention further relates to a method of manufacturing an electronic device comprising the steps of: applying a protective layer (4) over the dielectric layer (3) or over the Organic Semiconductor (OSC) layer (7), optionally subjecting the protective layer to a plasma treatment and/or applying further layers on at least some parts of the protective layer (4), optionally patterning the further layers, and optionally removing those parts of the protective layer (4) that have been exposed to the plasma or that are not covered by the further layers after patterning. Preferably, the further layer is a conductor, very preferably an electrode.

The invention further relates to a method of manufacturing an electronic device as described above and below, wherein those parts of the protective layer (4) which are not covered by the conductor or electrode layer provided thereto are removed.

The invention further relates to an electronic device obtained by the method as described above and below.

Preferably, the electronic device is an Organic Field Effect Transistor (OFET), an Integrated Circuit (IC), a Thin Film Transistor (TFT), a Radio Frequency Identification (RFID) tag, an Organic Photovoltaic (OPV) device, a sensor or a memory.

Brief Description of Drawings

Fig. 1a depicts an OFET according to the prior art.

Fig. 1b depicts an OFET obtained by the process according to the invention.

Fig. 2a and 2b show exemplarily a bottom gate OFET obtained by the method according to the invention.

Fig. 3a and 3b show exemplarily a top gate OFET obtained by the method according to the invention.

Fig. 4 and 5 show schematically a preferred process for the preparation of OFETs according to the invention.

Fig. 6a and 6b show the transfer characteristics of an OFET device according to comparative example 1.

Fig. 7a-c show the transfer characteristics of the OFET device according to example 1.

Fig. 8 shows the transfer characteristics of the OFET device according to example 2.

Fig. 9a and 9b show the transfer characteristics of the OFET device according to example 3.

Detailed Description

In the method of manufacturing an electronic device according to the invention, a thin sacrificial or protective layer (hereinafter "protective layer") is deposited on top of the (optionally crosslinked) dielectric material. The protective layer protects the surface of the dielectric material from damage that may be caused by subsequent processing or manufacturing steps during device fabrication, such as electrode deposition or plasma treatment.

Fig. 1a shows a conventional OFET according to the prior art, comprising a substrate (1a), a functional layer (e.g. for planarization or black-out) (1b), a gate electrode (2), a dielectric layer (3), source and drain electrodes (5), first and second bank structures (6a, 6b), an OSC layer (7) and an inkjet passivation layer (8).

During the manufacture of such devices, the electrode (5) is applied onto the dielectric material (3), typically by a sputtering method, and patterned by etching and/or lithographic patterning. The bank structures (6a, b) are applied and patterned by lithographic methods (lithographical processes). The OSC layer (7) and the passivation layer (8) are typically applied by inkjet deposition. The bank structure (6b) is typically subjected to a plasma treatment (e.g. with O) prior to ink jetting the OSC layer (7)₂Or Ar or CF₄Plasma) to improve its surface for the ink jet process. It can be seen that the dielectric material is a result of the above described electrode deposition/patterning and plasma treatment process(3) And the critical interface between OSC (7) is usually severely compromised. As a result, the performance of such devices deteriorates.

It has now been found that these damages can be reduced or even completely prevented and the device performance can be significantly improved if the dielectric material is covered with a protective layer before depositing the electrodes and processing the bank structure.

This is shown in fig. 1b, which shows a device obtained by the method according to the invention, comprising the assembly of fig. 1a, and further comprising a protective layer (4). The protective layer (4) is applied such that it completely covers the dielectric layer (3) before the source and drain electrodes (5) are deposited and before the bank structure (6b) is plasma treated. As a result, those parts of the protective layer (4) which are not covered by the electrode and exposed to the plasma (not shown in fig. 1b) are damaged by the plasma or the electrode sputtering process, thus preventing the dielectric material (3) from such damage and thus acting as a "sacrificial layer" of the dielectric material. Therefore, it is preferred to remove these parts of the protective layer after the plasma treatment and before the ink deposition of the OSC layer (7), so that the original dielectric material/OSC interface (3)/(7) (indicated by the arrow) is restored.

The method of manufacturing an electronic device according to the invention is suitable for protecting a dielectric material from plasma assisted processes, i.e. exposure to a plasma of energetic particles or beams, for example with O₂Ar or CF₄Or a mixture thereof. The method is also suitable for protecting the dielectric material from damage caused by deposition methods (e.g., when the electrode is applied or patterned, including but not limited to sputtering methods, vapor or vacuum deposition methods, and subsequent lithographic etching).

Preferred electronic devices include the following components:

-an optional substrate (1),

-one or more conductors, preferably electrodes (2, 5),

-OSC(7)，

-an insulator (3) comprising a dielectric material,

-a protective layer (4) between the insulator and conductor and/or between the OSC and conductor.

A preferred embodiment of the present invention relates to a method of making a Bottom Gate (BG), Bottom Contact (BC) electronic device comprising the following components in the following order:

-an optional substrate (1),

-a gate (2),

-an insulator layer (3) comprising a dielectric material,

-a source and a drain (5),

-an OSC layer (7),

-a protective layer (4) between the insulator layer and the source and drain electrodes.

Fig. 2a exemplarily depicts a simplified BG/BC OFET according to this embodiment. Wherein (1) is a substrate, (2) is a gate electrode, (3) is a dielectric layer, (4) is a protective layer, (5) is a source electrode and a drain electrode, and (7) is an OSC layer.

The method of making such a device comprises the steps of: applying a gate electrode (2) on a substrate (1), applying a dielectric layer (3) over the gate electrode (2) and the substrate (1), applying a protective layer (4) over the dielectric layer (3), applying source and drain electrodes (5) over the protective layer (4), optionally removing those portions of the protective layer not covered by the source and drain electrodes (5), and applying an OSC layer (7) over the electrode (5) and the dielectric layer (3).

Another preferred embodiment of the invention relates to a method of making a BG, Top Contact (TC) electronic device comprising the following components in the following order:

-an optional substrate (1),

-a gate (2),

-an insulator layer (3) comprising a dielectric material,

-an OSC layer (7),

-a source and a drain (5),

-a protective layer (4) between the OSC layer and the source and drain electrodes.

Figure 2b exemplarily depicts a simplified BG/TC OFET according to this embodiment. Wherein (1) is a substrate, (2) is a gate electrode, (3) is a dielectric layer, (4) is a protective layer, (5) is a source electrode and a drain electrode, and (7) is an OSC layer.

The method of making such a device comprises the steps of: applying a gate electrode (2) on a substrate (1), applying a dielectric layer (3) over the gate electrode (2) and the substrate (1), applying an OSC layer (7) over the dielectric layer (3), applying a protective layer (4) over the OSC layer (7), applying source and drain electrodes (5) over the protective layer (4), and optionally removing those portions of the protective layer not covered by the source and drain electrodes (5).

Another preferred embodiment of the present invention relates to a method of making a Top Gate (TG), bottom contact electronic device comprising the following components in the following order:

-a substrate (1),

-a source and a drain (5),

-an OSC layer (7),

-an insulator layer (3) comprising a dielectric material,

-a gate (2),

-a protective layer (4) between the insulator layer and the gate.

Fig. 3a exemplarily depicts a simplified TG/BC OFET according to this embodiment. Wherein (1) is a substrate, (5) is a source electrode and a drain electrode, (7) is an OSC layer, (3) is a dielectric layer, (2) is a gate electrode, and (4) is a protective layer.

The method of making such a device comprises the steps of: applying source and drain electrodes (5) on a substrate (1), applying an OSC layer (7) over the source and drain electrodes (5) and the substrate (1), applying a dielectric layer (3) over the OSC layer (7), applying a protective layer (4) over the dielectric layer (3), applying a gate electrode (2) over the protective layer (4), and optionally removing those portions of the protective layer not covered by the gate electrode (2).

Another preferred embodiment of the present invention relates to a method of making a TG, top contact electronic device comprising the following components in the following order:

-a substrate (1),

-an OSC layer (7),

-a source and a drain (5),

-an insulator layer (3) comprising a dielectric material,

-a gate (2),

-a protective layer (4a) between the OSC layer and the source and drain electrodes and/or a protective layer (4b) between the insulator layer and the gate electrode.

Fig. 3b exemplarily depicts a simplified TG/TC OFET according to this embodiment. Wherein (1) is a substrate, (5) is a source electrode and a drain electrode, (7) is an OSC layer, (3) is a dielectric layer, (2) is a gate electrode, (4a) and (4b) are protective layers.

The method of making such a device comprises the steps of: applying an OSC layer (7) on a substrate (1), optionally applying a protective layer (4a) on top of the OSC layer (7), applying source and drain electrodes (5) on top of the OSC layer (7) or the protective layer (4a), optionally removing those parts of said protective layer (4a) that are not covered by the source and drain electrodes (5), applying a dielectric layer (3) on top of the source and drain electrodes (5), optionally applying a protective layer (4b) on top of the dielectric layer (3), applying a gate electrode (2) on top of the dielectric layer (3) or the protective layer (4b), and optionally removing those parts of said protective layer (4b) that are not covered by the gate electrode (2).

Figure 4 schematically shows a method of making a BG/BC electronic device according to another preferred embodiment of the present invention. Such a preferred method comprises the steps of:

a) one or more first electrodes (2) are provided on a substrate (1),

b) providing a layer (3) of a dielectric material on the substrate (1) and the first electrode (2),

c) providing a protective layer (4) on top of the dielectric layer (3),

d) one or more second electrodes (5) are provided on the protective layer (4),

e) providing a photoresist layer (6) over the second electrode (5),

f) the photoresist (6) is treated by a suitable method to leave a pattern of areas with and without photoresist (6) over the second electrode (5),

g) removing those parts of the second electrode (5) not covered by the photoresist (6),

h1) the photoresist (6) is removed and,

i1) removing those parts of the protective layer (4) which are not covered by the second electrode (5),

k1) optionally treating the remaining part of the protective layer (4), for example by washing, to remove residues, such as ions, doping sites, etc., caused by step f), and

m1) applying the OSC layer (7) onto the uncovered parts of the dielectric layer (3) and the second electrode (5), or, instead of steps h1) -m1),

h2) removing those parts of the protective layer (4) which are not covered by the second electrode (5),

i2) optionally curing the remaining part of the protective layer (4),

k2) the photoresist (6) is removed and,

m2) optionally treating the remaining part of the protective layer (4), for example by washing, to remove residues, such as ions, doping sites, etc., caused by step f), and

n2) applying the OSC layer (7) onto the uncovered parts of the dielectric layer (3) and the second electrode (5).

Fig. 5 schematically illustrates a method of fabricating a BG/BC gate electronic device according to another preferred embodiment of the present invention. Such a preferred method comprises the steps of:

a) one or more first electrodes (2) are provided on a substrate (1),

b) forming a layer (3) of a dielectric material on the substrate (1) and the first electrode (2),

c) providing a protective layer (4) on top of the dielectric layer (3),

d) one or more second electrodes (5) are provided on the protective layer (4),

e) providing a bank structure layer (6) over the protective layer (4) and the second electrode (5) such that it at least partially covers the protective layer (4) and the second electrode (5),

f) subjecting the bank structure layer (6), and those parts of the protective layer (4) not covered by the second electrode (5) or the bank structure layer (6), to a plasma treatment,

g) removing those parts of the protective layer (4) which are not covered by the second electrode (5) or the bank structure layer (6),

h) optionally treating the remaining part of the protective layer (4), for example by washing, to remove residues, such as ions, doping sites, etc., caused by step f), and

i) an OSC layer (7) is applied onto the dielectric layer (3) and the uncovered parts of the second electrode (5).

In the method described above and shown in fig. 4 and 5, the first electrode (2) is preferably a gate electrode and the second electrode (5) is preferably a source/drain electrode. The top gate and/or top contact may be prepared similarly to the methods described above and in fig. 4 and 5.

Once applied, the protective layer in at least some portions of the device will preferably remain in the final device, i.e., it will not be removed during further fabrication or processing steps. For example, the protective layer will typically remain on those portions of the dielectric or OSC layer that are covered by the electrodes. For this reason, the protective layer should preferably be stabilized in those parts, for example by curing or other suitable methods which improve its solubility, so that it cannot be removed (together with the electrode). On the other hand, the protective layer should preferably remain soluble in those parts not covered by the electrode, so that it can be at least partially removed in a subsequent step.

This can be achieved by chemically altering the protective layer material during or after a sputter/etch process is performed to apply or pattern the electrode.

In addition, the protective layer should exhibit sufficient adhesion to the electrode applied thereto. This can be achieved by a suitable choice of protective layer material and protective layer thickness.

In another preferred embodiment, the protective layer is altered during exposure to the plasma such that its solubility changes, e.g., becomes more hydrophilic, such that it can be developed in an orthogonal, polar solvent. In this case, the non-etched portions of the protective layer will remain in the device and only the damaged portions will be removed.

After plasma treatment or electrode application, the protective layer may be removed from those portions of the dielectric layer or OSC layer that are not covered by the electrode. This can be achieved by standard methods such as wet chemical removal. After (partial) wet-chemical removal of the protective layer, the initial properties of the dielectric layer are restored.

The protective layer should be selected to be thick enough to protect the initial dielectric surface, e.g., from the highly reactive species formed in the plasma-assisted process. Preferably, the thickness of the protective layer is 1-500nm, very preferably 1-100 nm.

In another preferred embodiment, the protective layer is thin enough that the electrode deposited through the mask "stabilizes" (due to penetrating sputtered ions) the underlying protective layer (so that no lift-off occurs) and the original dielectric/OSC layer surface can be restored by developing the unexposed protective layer in a suitable solvent ("self-patterning concept"). The thickness of the protective layer according to this preferred embodiment is preferably 1 to 500nm, very preferably 1 to 100 nm.

The protective layer material is preferably an organic material, but may also be an inorganic material, such as a vacuum deposited oxide, solution processable nanoparticles, which may be conductive or non-conductive, or hybrids thereof. Preferably it is selected from solution processable or materials which can be deposited by vacuum deposition techniques, for example parylene such as p-xylylene (as disclosed in US 3,342,754), very preferably from solution processable organic polymers.

A wide range of materials are suitable for the protective layer. In addition to good adhesion to the electrode as described above, the protective layer material should preferably also exhibit one or more of the following properties:

good adhesion to standard dielectrics used for the preparation of electronic devices,

high structural integrity, for example by using a polymer or amorphous material with a high glass transition temperature, or a cross-linked material, or by using a material comprising one or more functional groups that can be cross-linked in a subsequent processing or development step (i.e. after application on the dielectric/OSC layer), for example by thermal or photo-curing,

good dry etching resistance, for example by using Si-containing or fluorinated polymers, polymers with aliphatic cage structures (such as adamantane and the like), polyimides and the like,

a low dielectric constant, preferably in the range of the dielectric constant of the dielectric layer,

high UV absorption, for example via mixed in highly UV-absorbing molecules,

-a material comprising antioxidant properties, groups or components,

-a material comprising conductive or semiconductive properties, groups or components,

-a low gas permeability,

high resistance to photoresist stripping.

This can be achieved by using a single material or a combination of materials (mixture) which allows a selective adaptation to the specific process.

If a protective layer is applied between the OSC layer and the electrode (e.g. in a BG/TC device as shown in fig. 2 b), the protective layer material itself or the selected thickness should not be so insulating that the device performance is not so negatively affected.

In another preferred embodiment, the protective layer material has a high etch resistance for plasma-based processes. The protective layer has in particular the function of protecting the underlying layer from energetic particles or beams. This protective function can be enhanced by increasing the protective layer thickness, or by using protective layer materials with improved stability to these energetic particles or beams. If materials with high stability are used, the thickness can be reduced, which is advantageous for the device geometry.

Further preferred are protective layer materials having a high UV absorbance or comprising one or more functional groups or components having a high UV absorbance, in particular in the wavelength range of less than 300 nm.

The protective layer material should be chosen such that it has no negative effect, or only a small degree of negative effect, on the transistor performance, especially in those parts of the protective layer that will be covered by the electrodes and will remain in the final device, especially in those parts that are located near the channel of the transistor. For example, if the protective layer contains an insulating material and has a high thickness, it may block injection of charge carriers into the OSC layer. On the other hand, a protective layer containing a material having a high dielectric constant may reduce charge carrier mobility. In addition, the reactive products generated by the plasma treatment method may be transferred from the protective layer to the OSC layer. In some cases, reactive products, such as ions, doping sites, etc., may be removed by selective treatment (e.g., washing) steps.

Suitable and preferred protective layer materials include, but are not limited to, perfluorinated or partially fluorinated organic polymers, polyimides such as those commercially availableThose of the series (Hitachi), polycycloolefins are available, for example, from the commercial marketSeries (Promerus LLC),Series (TiCona) orThose of the series (Zeon Chemicals), dielectric polymers with additional functional groups, for example polycycloolefins with Alkoxysilane or vinylalkoxysilane groups, such as those of the commercially available Alkoxysilane Aprima series (Promeris LLC), UV absorbing polymers such as polyacenaphthylene or copolymers thereof, or curable precursors of the above polymers.

Particularly preferably, the protective layer material is selected from highly soluble fluoropolymers, such as those available commerciallyFluoropolymers of the series (Asahi Glass), such as perfluoro (1-butenyl vinyl ether) homo-cyclic polymer (homocyclopolymer) of formula 1 [ poly (1, 1, 2, 4, 4, 5, 5, 6, 7, 7-decafluoro-3-oxa-1, 6-heptadiene)]，

Or from commercial sourcesSeries (DuPont) fluoropolymers, such as poly [4, 5-difluoro-2, 2-bis (trifluoromethyl) -1, 3-dioxole-co-tetrafluoroethylene of formula 2,

and also polyacenaphthylene of formula 3,

poly-N-vinylcarbazole of the formula 4,

poly (2-vinylnaphthalene) of formula 5,

poly (4-vinylbiphenyl) of formula 6,

or poly (1-vinylnaphthalene) of formula 7,

wherein n is an integer > 1, 0 < x < 1 and 0 < y < 1, or a copolymer comprising one or more units of formulae 1-7 above. The polymers of formulas 3-7 are commercially available from Aldrich.

If the device is subjected to CF₄Plasma treatment, the risk of damage due to UV absorption will be higher than O₂A plasma method. Many materials tend to crosslink under those conditions. Silicon-containing protective layer materials are particularly preferred for this case, for example curable polysilsesquioxanes such as HardSil^TMThose of the series (commercially available from Gelest inc., Morrisville PA, USA) or AS Hardcoat^TMOr SHC^TMMaterials from the series (obtained from Momentive Performance materials Inc., Wilton, CT, USA) such AS AS4000 Hardcoat^TM、AS4700 Hardcoat^TMOr SHC^TM5020, or a thermosetting silicone resin such as those commercially available from Techneglas, Perrysburg OH, USA.

In another preferred embodiment of the invention, the protective layer comprises, preferably consists of, the same material as the dielectric layer. This has the advantage that the adhesion of the protective layer is improved and the stress during the process, for example caused by different thermal coefficients of the individual layers, is reduced.

In another preferred embodiment, the dielectric layer material comprises a compound having one or more reactive groups that can react with the protective layer material in a subsequent reaction step, for example grafted onto or copolymerized with the protective layer material, to achieve covalent bonding between said materials.

Other components or functional layers of the electronic device, such as the substrate, insulator, conductor or electrode and the OSC may be selected from standard materials and may be fabricated and applied to the device by standard methods. Materials and manufacturing methods suitable for this piece of assembly and layer are known to the skilled person and described in the literature.

Application methods include liquid coating and vapor or vacuum deposition. Preferred deposition techniques include, but are not limited to, dip coating, spin coating, ink jet printing, letterpress printing, screen printing, doctor blade coating, roll printing, reverse roll printing, offset lithography printing, flexographic printing, rotary printing, spray coating, brush coating, or pad printing. Ink jet printing is particularly preferred as it allows the preparation of high resolution layers and devices.

In general, the thickness of the functional layers in the electronic device according to the invention may be from 1nm (in the case of a monolayer) to 10 μm, preferably from 1nm to 1 μm, more preferably from 1nm to 500 nm.

Various substrates can be used for the manufacture of organic electronic devices, such as glass or plastic, plastic materials are preferred, examples include alkyd resins, allyl esters, benzocyclobutene, butadiene-styrene, cellulose acetate, epoxy polymers, ethylene-chlorotrifluoroethylene, ethylene-tetrafluoroethylene, glass fiber reinforced plastics, fluorocarbon polymers, hexafluoropropylene vinylidene fluoride copolymers, high density polyethylene, parylene, polyamides, polyimides, aramids, polydimethylsiloxanes, polyethersulfone, polyethylene naphthalate, polyethylene terephthalate, polyketones, polymethylmethacrylate, polypropylene, polystyrene, polysulfone, polytetrafluoroethylene, polyurethane, polyvinylchloride, silicone rubber, silicone. Preferred substrate materials are polyethylene terephthalate, polyimide and polyethylene naphthalate. The substrate may be any plastic material, metal or glass coated with the above materials. The substrate should preferably be homogeneous to ensure good pattern definition. To enhance carrier mobility, the substrate may also be uniformly pre-aligned by extrusion, stretching, grinding or by photochemical techniques to induce orientation of the organic semiconductor.

The dielectric material of the insulator layer may be an inorganic or organic material or a composite of both materials. Preferably the insulator is solution coated, which allows for environmental processing, but may also be deposited by various vacuum deposition techniques. When the insulator is patterned, it can function as interlayer insulation or as a gate insulator for an OFET. Preferred deposition techniques include, but are not limited to, dip coating, spin coating, ink jet printing, letterpress printing, screen printing, doctor blade coating, roll printing, reverse roll printing, offset lithography printing, flexographic printing, rotary printing, spray coating, brush coating, or pad printing. Ink jet printing is particularly preferred as it allows the preparation of high resolution layers and devices. Optionally, the dielectric material may be crosslinked or cured to achieve better solvent resistance and/or structural integrity and/or to enable patternability (photolithography). Preferred gate insulators are those that provide a low dielectric constant interface to the OSC.

Suitable and preferred organic dielectric materials include, but are not limited to, fluorinated para-xylene, fluorinated polyaryl ethers, fluorinated polyimide polystyrene, poly (. alpha. -methylstyrene), poly (. alpha. -vinylnaphthalene), poly (vinyltoluene), polyethylene, cis-polybutadiene, polypropylene, polyisoprene, poly (4-methyl-1-pentene), poly (4-methylstyrene), poly (chlorotrifluoroethylene), poly (2-methyl-1, 3-butadiene), poly (p-xylylene), poly (. alpha. -alpha. '-alpha' -tetrafluoro-p-xylylene), poly [1, 1- (2-methylpropane) bis (4-phenyl) carbonate]Poly (cyclohexyl methacrylate), poly (chlorostyrene), poly (2, 6-dimethyl-1, 4-phenylene ether), polyisobutylene, poly (vinylcyclohexane), poly (vinyl cinnamate), poly (4-vinylbiphenyl), poly (1, 3-butadiene), polyphenylene. Further preferred are copolymers, including regular, random or block copolymers such as poly (ethylene/tetrafluoroethylene), poly (ethylene/chlorotrifluoroethylene), fluorinated ethylene/propylene copolymers, polystyrene-co-alpha-methylstyrene, ethylene/ethyl acrylate copolymers, poly (styrene/10% butadiene), poly (styrene/15% butadiene), poly (styrene/2, 4-dimethylstyrene). Further preferred are those obtained commerciallyOf the series (TiCona)Polymers, polycycloolefins, e.g. from commercial sourcesThose of the series (Promeris LLC) and highly soluble perfluoropolymers such as those available commerciallySeries (Asahi Glass) orThose of the series (DuPont).

For certain devices, it may be preferable to use dielectric materials having a high dielectric constant. Suitable and preferred organic dielectric materials of this type include, but are not limited to, for example, polyvinyl alcohol, polyvinyl phenol, polymethyl methacrylate, cyanoethylated polysaccharides such as cyanoethyl pullulan, high dielectric constant fluoropolymers such as polyvinylidene fluoride, polyurethane polymers, and poly (vinyl chloride/vinyl acetate) polymers. Suitable and preferred inorganic dielectric materials of this type include, but are not limited to, for example, TiO₂、Ta₂O₅、SrTiO₃、Bi₄Ti₃O₁₂、BaMgF₄Barium zirconium titanate or barium strontium titanate.

In a preferred embodiment of the invention, the insulator layer comprises or consists of an organic dielectric material having a low dielectric constant, preferably having a relative dielectric constant of 1.1 to less than 3.0, for example as disclosed in WO 03/052841. Suitable and preferred materials for this embodiment include, but are not limited to, polypropylene, polyisobutylene, poly (4-methyl-1-pentene), polyisoprene, poly (vinylcyclohexane), or copolymers containing monomer units of at least one of these materials, polycycloolefins such as those derived from at least one of these materialsThose of the series, and fluoropolymers, in particular fromOrThose of the series.

In a further preferred embodiment of the invention, the dielectric layer comprises or consists of the same material as the protective layer.

A conductor is, for example, an electrode for an OFET or another electronic device, or an interconnection between an OFET and another component. The conductor may also serve as part of a passive circuit element in the OFET circuit, such as a capacitor, conductor or antenna for an RFID tag. The conductor or electrode may be deposited by liquid coating, such as spray coating, dip coating, web coating or spin coating, or by vacuum deposition or vapor deposition methods.

Suitable conductor and electrode materials and methods of applying them are known to the skilled person. Suitable electrode materials include, but are not limited to, inorganic or organic materials, or composites of the two. Examples of suitable conductor or electrode materials include polyaniline, polypyrrole, PEDOT or doped conjugated polymers, other dispersions or pastes of graphite or particles of metals such as Au, Ag, Cu, Al, Ni or mixtures thereof as well as sputter-coated or evaporated metals such as Cu, Cr, Pt/Pd, etc., and semiconductors such as ITO. Organometallic precursors deposited from the liquid phase may also be used.

The OSC materials and methods of applying the OSC layer may be selected from standard materials and methods known to the skilled person and described in the literature.

In the case of an OFET device, when the OFET layer is an OSC, it may be an n-or p-type OSC, which may be deposited by vacuum or vapour deposition, or preferably from solution. Preferred OSCs have a value of greater than 10^-5cm²V^-1s^-1The FET mobility of (1).

The OSC is used, for example, as an active channel material in OFETs or as a layer element of organic rectifying diodes. Preferred are OSCs deposited by liquid coating to allow environmental processing. The OSC is preferably spray coated, dip coated, web coated or spin coated or deposited by any liquid coating technique. Inkjet deposition is also suitable. The OSC may optionally be vacuum or vapour deposited.

The semiconductor channel may also be a composite of two or more semiconductors of the same type. Alternatively, the p-type channel material may, for example, be mixed with the n-type material to achieve the effect of doping the layer. Multiple semiconductor layers may also be used. For example, the semiconductor may be inherently close to the insulator interface and the highly doped region may also be coated next to the intrinsic layer.

The OSC material may be any conjugated aromatic molecule containing at least three aromatic rings. The OSC preferably contains a 5-, 6-or 7-membered aromatic ring, more preferably contains a 5-or 6-membered aromatic ring. Such materials may be monomers, oligomers, or polymers, including mixtures, dispersions, and blends.

Each of the aromatic rings optionally contains one or more heteroatoms selected from Se, Te, P, Si, B, As, N, O or S, preferably from N, O or S.

The aromatic ring may be optionally substituted with: alkyl, alkoxy, polyalkoxy, thioalkyl, acyl, aryl or substituted aryl, halogen, especially fluorine, cyano, nitro or from-N (R)³)(R⁴) An optionally substituted secondary or tertiary alkylamine or arylamine of formula (I), wherein R³And R⁴Each independently is H, optionally substituted alkyl, optionally substituted aryl, alkoxy or polyalkoxy. When R is³And R⁴When alkyl or aryl, they may be optionally fluorinated.

The rings may be optionally fused or may be linked to a conjugated linker such as-C (T)₁)＝C(T₂) -, -C ≡ C-, -N (R ') -, -N ═ N-, (R ') -N-, -N ═ C (R ') -, are linked. T is₁And T₂Each independently represents H, Cl, F, -C ≡ N or lower alkyl, especially C_1-4An alkyl group; r' represents H, optionally substituted alkyl or optionally substituted aryl. R'When alkyl or aryl, they may be optionally fluorinated.

Other OSC materials that may be used in the present invention include the following compounds, oligomers and derivatives of compounds:

conjugated hydrocarbon polymers such as polyacenes, polyphenylenes, poly (phenylenevinylenes), polyfluorenes, including oligomers of those conjugated hydrocarbon polymers; fused aromatic hydrocarbons such as tetracene, chrysene, pentacene, pyrene, perylene, coronene or substituted derivatives thereof; an oligomeric para-substituted phenylene group such as para-quaterphenyl (P-4P), para-pentabiphenyl (P-5P), para-hexabiphenyl (P-6P), or a soluble substituted derivative thereof; conjugated heterocyclic polymers such as poly (3-substituted thiophene), poly (3, 4-disubstituted thiophene), polybenzothiophene, polydibenzothiophene, poly (N-substituted pyrrole), poly (3, 4-disubstituted pyrrole), polyfuran, polypyridine, poly-1, 3, 4-oxadiazole, polydibenzothiophene, poly (N-substituted aniline), poly (2-substituted aniline), poly (3-substituted aniline), poly (2, 3-disubstituted aniline), polyazulene, polypyrene; a pyrazoline compound; polyselenophene; a polybenzofuran; a polybenzazole; poly-pyridazine; a biphenylamine compound; a stilbene compound; a triazine; substituted metallic or metal-free porphines, phthalocyanines, fluorophthalocyanines, naphthalocyanines or fluoronaphthalocyanines; c₆₀And C₇₀A fullerene; n, N' -dialkyl, substituted dialkyl, diaryl or substituted diaryl-1, 4, 5, 8-naphthalenetetracarboxylic diimide and fluoro derivatives; n, N' -dialkyl, substituted dialkyl, diaryl or substituted diaryl 3, 4, 9, 10-perylenetetracarboxylic acid diimides; bathophenanthroline; diphenoquinone; 1, 3, 4-oxadiazole; 11, 11, 12, 12-tetracyanonaphthalene-2, 6-p-benzoquinodimethane; alpha, alpha ' -bis (dithieno [3, 2-b2 ', 3 ' -d)]Thiophene); 2, 8-dialkyl, substituted dialkyl, diaryl, or substituted diaryl bisthiophene anthracene; 2, 2' -dibenzo [1, 2-b: 4, 5-b']A dithiophene. Preferred compounds are those from the above list and their soluble derivatives.

Particularly preferred OSC materials are substituted heteroacenes or pentacenes, especially 6, 13-bis (trialkylsilylethynyl) pentacenes, or their heteroacene derivatives or substituted derivatives, as described in US 6,690,029 or WO 2005/055248a 1.

Optionally, the OSC layer comprises one or more organic binders to adjust the rheological properties, for example as described in WO 2005/055248a 1.

Unless the context clearly dictates otherwise, the plural forms of terms used herein are to be understood as including the singular form and vice versa.

Throughout the description and claims of this specification, the words "comprise" and "contain" and variations of the words, for example "comprising" and "comprises", mean "including but not limited to", and are not intended to (and do not) exclude other components.

It will be appreciated that variations may be made to the foregoing embodiments of the invention, which still fall within the scope of the invention. Each feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

All of the features disclosed in this specification may be combined in any combination, except combinations where at least some of the features and/or steps are mutually exclusive. In particular, the preferred features of the invention are applicable to all aspects of the invention and may be used in any combination. Also, features described in non-critical combinations may be used separately (not in combination).

It should be understood that many of the features described above, particularly those of the preferred embodiments, are inventive in their own right and not just as part of the embodiments of the invention. Independent protection may be sought for these features in addition to or in lieu of any of the presently claimed inventions.

The present invention will now be described in more detail with reference to the following examples, which are illustrative only and do not limit the scope of the present invention.

Examples

Unless otherwise specified, the OFETs described in the examples are bottom gate OFETs and include the following materials and parameters:

source and drain (S/D): au coating

Gate (G): patterned Al gate

Channel width (W): 1000 μm (length of S and D facing each other)

Channel length (L): 50 μm (distance of S and D from each other)

Capacitance (C): 3nF/cm²Estimated thickness 1000nm

Dielectric material:(Promerus LLC)

OSC material: 1% of a polytriarylamine of the formula I (PTAA), n 50,

all H capping

Formula I

Unless otherwise indicated, the OFETs described in the examples were prepared by the following process steps, with step 7 (protective layer application), step 9 (plasma treatment) and step 10 (protective layer development and removal) being optional steps:

1) mixing a commercially available glass substrate (2000 from Corning Glass) was sonicated in 3% Deconex at > 50C for 30min, then rinsed with DI water,

2) a 25nm Al gate layer was evaporated through a shadow mask,

3) the surface of the substrate was treated by spin coating adhesion promoter Lisicon M009 (from Merck KGaA),

4) by applying an insulator material(promeus LLC) a solution in MAK containing a photoinitiator was spin coated onto the device at 1500rpm for 30s to apply the dielectric layer,

5) heating the dielectric layer to 120 ℃ for 1min on a hot plate and curing by exposure to UV light (254nm) for 30s, followed by heating to 120 ℃ for 3min on a hot plate,

6) by Lisicon^TMM008 (from Merck KGaA) reactive washes,

7) spin coating and drying (1min, 100 ℃) the protective layer on a hot plate,

8) evaporation of Au electrode through mask (25nm)

9) Exposing the device to O in a Tepla microwave oven₂Plasma, plasma for 1min, 500W,

10) the protective layer is developed (< 1min soak time, spun off) and washed with a suitable solvent,

11) treatment with SAM (Lisicon)^TMM001, Merck) and optionally an OSC layer.

To measure the performance of an OFET, a voltage is applied to the transistor relative to the potential of the source. In the case of a p-type gate material, when a negative potential is applied to the gate, positive charge carriers (holes) accumulate in the semiconductor on the other side of the gate dielectric material (for an n-type channel FET, a positive voltage is applied). This is called accumulation mode. Capacitance/area C of the gate dielectric material_iThe amount of charge so induced is determined. When a negative potential V is applied_DSWhen applied to the drain, the accumulated carrier generation source-drain current I_DSIt depends mainly on the density of the accumulated carriers and, importantly, their mobility in the source-drain channel. Geometric factors such as drain and source configurations, dimensions and distances also affect the current. Typically, a range of gate and drain voltages are swept during the study of the device. The source-drain current is described by equation (1):

equation (1)

Wherein V₀Is an offset voltage, I_ΩIs an ohmic current independent of the gate voltage and is due to the finite conductivity of the material. Other parameters have been described above.

For electrical measurements, the transistor samples were mounted on a test clip. Microprobe connections to the gate, drain and source were made using Karl Suss PH100 microprobe heads. They were interfaced with a Hewlett-Packard 4155B parameter analyzer. Will leakThe voltage was set to-5V and the gate voltage was swept from +20 to-60V in 0.5V steps. After this, the drain voltage is set to-60V and the gate is scanned again between +20V and-60V. Cumulatively, when | V_G|＞|V_DSWhen, the source-drain current follows V_GLinearly changing. Thus, the field effect mobility can be given by I of equation 2_DSvs.V_GCalculating the gradient (S):

equation (2)

All field effect mobilities referenced below were calculated in this manner (unless otherwise noted). When the field effect mobility varies with the gate voltage, the value is taken therein as | V in the accumulation mode_G|＞|V_DSThe highest level reached in the mechanism of l.

The off-current of the transistor is defined as the lowest current recorded during the gate sweep from +20V to-60V. This is proposed for both of the drain voltages used. The on/off ratio of the device is defined at-60V V_gOpen current at divided by V_dThe lowest off current for-60V scan.

Comparative example 1: without protective layer, with and without plasma Preparation of OFETs in the case of the processing step

A first series of OFET devices was prepared by the above steps 1-6, 8 and 11 without applying and developing a protective layer (steps 7, 10) and without plasma treatment (step 9).

A second series of OFET devices was prepared as described above, butIs plasma treated (step 9, exposure to O) prior to the application of the electrodes in step 8₂Plasma, 1min, 1000W in a Tepla 400 microwave oven). The performance of the device was measured as described above.

Table 1 and fig. 6a show the transfer characteristics, mobility and on/off ratio of OFETs prepared without a plasma treatment step.

TABLE 1

Table 2 and fig. 6b show the transfer characteristics, mobility and on/off ratio of the OFETs prepared in the presence of a plasma treatment step.

TABLE 2

It can be seen that O of the dielectric material₂Plasma treatment has a destructive effect on the performance of OFETs. The mobility and the on-current are reduced by more than two orders of magnitude. A possible explanation may be that the surface of the dielectric material is polarized by the treatment and thus becomes high-k. This in turn significantly degrades the performance of the device.

Example 1: with protective layers of different thicknesses, 500W O was used ₂ Plasma treatment step preparation OFET

A series of OFET devices with protective layers of different thicknesses were prepared and plasma treated by the above steps 1-11. The dielectric material (step 4) is(available from Promerius LLC). The protective layer material (step 7) is an acenaphthylene polymer (polyacenaphthylene, Aldrich) of the following formula

Mw＝5000-10000

After plasma treatment (exposure to O)₂Plasma, 1min, 500W, 500ml/min in a Tepla 400 microwave oven) the source and drain electrodes were applied to the two series of devices (step 8). In use of O₂After plasma treatment (step 9), the protective layer was developed and washed (step 10) using a 1: 1 isopropanol: cyclohexanone mixture (immersion for 10 seconds, spin-coating for 5 seconds, washing with isopropanol).

The OSC material (step 11) is the PTAA of formula I shown above.

The performance of the device was measured as described above.

Table 3 and FIG. 7a show that at 500W O₂Transfer characteristics, mobility and on/off ratio of OFETs typically measured after plasma treatment (step 9) on devices prepared without a protective layer (steps 7, 10).

TABLE 3

L/W(μm)	Thickness of protective layer (nm)	On/off ratio	μ(cm2/Vsec)
				50/500	-	102	1-2×10-4

Table 4 and FIG. 7b show that at 500W O₂Transfer characteristics, mobility and on/off ratio of OFETs typically measured after plasma treatment (step 9) on devices prepared with a 60nm protective layer (steps 7, 10).

TABLE 4

L/W(μm)	Thickness of protective layer (nm)	On/off ratio	μ(cm2/Vsec)
				50/1000	60	103-4	1-2.2×10-3

Table 5 and FIG. 7c show that at 500W O₂Transfer characteristics, mobility and on/off ratio of OFETs typically measured after plasma treatment (step 9) on devices prepared with a 15nm protective layer (steps 7, 10).

TABLE 5

L/W(μm)	Thickness of protective layer (nm)	On/off ratio	μ(cm2/Vsec)
				50/1000	15	＞103	2-3×10-3

It can be seen that O for the unprotected dielectric material₂Plasma processing can have a destructive effect on the performance of OFETs. The mobility and the on-current are reduced by two orders of magnitude. In contrast, devices with protective layers have significantly improved performance with high mobility and on/off ratio.

It can also be seen from the above examples that a protective layer as thin as 15nm can be used to maintain OFET performance after 500W plasma treatment.

Example 2: with a protective layer of 60nm thickness, 1kW O was used ₂ Plasma treatment step preparation OFET

Table 6 and fig. 8 show the transfer characteristics, mobility and on/off ratio of OFETs typically measured after plasma treatment (step 9) on devices prepared with a 60nm protective layer step (steps 7, 10). Comparison with example 1₂The intensity of the plasma was doubled (1kW instead of 500W).

TABLE 6

L/W(μm)	Thickness of protective layer (nm)	On/off ratio	μ(cm2/Vsec)
				50/500	60	＞103	2-3×10-3

To fully restore the initial device performance (benchmark in the comparative example), using higher microwave power (1kW) to generate the plasma requires a thicker protective layer (60 nm minimum). Thinner protective layers do not restore the original device performance and result in lower mobility, on/off, and positive turn-on.

Example 3: using CF with and without a protective layer ₄ Plasma treatment process Preparation of OFET

A first series of OFET devices was prepared by steps 1-6, 8 and 11-12 above, without applying a protective layer (steps 7, 10). A second series of OFET devices, comprising the above-described protective layer with a thickness of 60nm, was prepared as described above (steps 7, 10). The dielectric material (step 4) is(available from Promerius LLC). The protective layer material (step 7) was Hardsil AR (from Gelest).

After plasma treatment (step 9, exposure to 1: 1 CF)₄Argon plasma, 1min, 1000W, 250ml/min CF₄250ml/min argon, in a Tepla 400 microwave oven) before applying the source and drain electrodes to the two series of devices (step 8). These plasma conditions are typically used to modify the surface of the bank structure (H;)₂The O contact angle is changed to about 110 deg.). After treatment with CF 4: Ar plasma (step 9), the protective layer was developed and washed (step 10) (soak 10 seconds, spin coat 5 seconds, wash with isopropanol) using a 1: 1 isopropanol: cyclohexanone mixture.

The OSC material (step 11) is the PTAA of formula I defined above.

The performance of the device was measured as described above.

Table 7 and fig. 9a show the transfer characteristics, mobility and on/off ratio of OFETs typically measured after plasma treatment (step 9) on devices prepared without protective layer steps (steps 7, 10).

TABLE 7

L/W(μm)	Thickness of protective layer (nm)	On/off ratio	μ(cm2/Vsec)
				50/500	-	0	0

Table 8 and fig. 9b show the transfer characteristics, mobility and on/off ratio of OFETs typically measured after plasma treatment (step 9) for devices prepared with a protective layer step (steps 7, 10).

TABLE 8

L/W(μm)	Thickness of protective layer (nm)	On/off ratio	μ(cm2/Vsec)
				50/500	60	103	1-3×10-3

It can be seen that CF₄Ar plasma condition ratio of O₂The plasma conditions (examples 1, 2) are so severe that no reasonable field effect can be observed without a protective layer. The use of a 60nm protective layer is suitable for preventing the deterioration of the OFET performance.

Claims (34)

1. A method of making an electronic device comprising a dielectric layer and an organic semiconductor layer, comprising the steps of: applying an electrode on top of the dielectric layer or the organic semiconductor layer, characterized in that a protective layer is applied on top of the dielectric layer or on top of the organic semiconductor layer before applying the electrode and an electrode is applied on at least some parts of the protective layer and the protective layer is partially removed after applying or processing the electrode; wherein the electronic device is an organic field effect transistor, a thin film transistor, a radio frequency identification tag, an organic photovoltaic device, a sensor, or a memory.

2. The method according to claim 1, comprising the steps of: applying a protective layer (4) on top of the dielectric layer (3) or on top of the organic semiconductor layer (7), subjecting the protective layer to a plasma treatment and applying electrodes on at least some parts of the protective layer (4).

3. A method according to claim 2, wherein the electrode is patterned.

4. A method according to claim 3, wherein those parts of the protective layer (4) which have been exposed to the plasma or which are not covered by the electrode after patterning are removed.

5. A method according to claim 2, wherein those parts of the protective layer (4) which are not covered by the electrode layer provided thereon are removed.

6. The method according to claim 1, wherein said organic field effect transistor is a bottom gate, bottom contact electronic device comprising the following components in the following order:

-a substrate (1),

-a gate (2),

-an insulator layer (3) comprising a dielectric material,

-a source and a drain (5),

-an organic semiconductor layer (7),

-a protective layer (4) between the insulator layer and the source and drain electrodes.

7. The method according to claim 6, comprising the steps of: the method comprises the steps of applying a gate electrode (2) on a substrate (1), applying a dielectric layer (3) over the gate electrode (2) and the substrate (1), applying a protective layer (4) over the dielectric layer (3), applying source and drain electrodes (5) over the protective layer (4), and applying an organic semiconductor layer (7) over the source and drain electrodes (5) and the dielectric layer (3).

8. A method according to claim 7, wherein after said step of applying the source and drain electrodes (5) on the protective layer (4), those parts of said protective layer not covered by the source and drain electrodes (5) are removed.

9. The method of claim 1, wherein the organic field effect transistor is a bottom gate, top contact electronic device comprising the following components in the following order:

-a substrate (1),

-a gate (2),

-an insulator layer (3) comprising a dielectric material,

-an organic semiconductor layer (7),

-a source and a drain (5),

-a protective layer (4) between the organic semiconductor layer and the source and drain electrodes.

10. The method according to claim 9, comprising the steps of: the gate electrode (2) is applied on the substrate (1), the dielectric layer (3) is applied over the gate electrode (2) and the substrate (1), the organic semiconductor layer (7) is applied over the dielectric layer (3), the protective layer (4) is applied over the organic semiconductor layer (7), and the source and drain electrodes (5) are applied over the protective layer (4).

11. A method according to claim 10, wherein after said step of applying the source and drain electrodes (5) on the protective layer (4), those parts of said protective layer not covered by the source and drain electrodes (5) are removed.

12. The method of claim 1, wherein the organic field effect transistor is a top-gate, bottom-contact electronic device comprising the following components in the following order:

-a substrate (1),

-a source and a drain (5),

-an organic semiconductor layer (7),

-an insulator layer (3) comprising a dielectric material,

-a gate (2),

-a protective layer (4) between the insulator layer and the gate.

13. The method according to claim 12, comprising the steps of: the source and drain electrodes (5) are applied on the substrate (1), the organic semiconductor layer (7) is applied over the source and drain electrodes (5) and the substrate (1), the dielectric layer (3) is applied over the organic semiconductor layer (7), the protective layer (4) is applied over the dielectric layer (3), and the gate electrode (2) is applied over the protective layer (4).

14. A method according to claim 13, wherein after said step of applying the gate electrode (2) over the protective layer (4), those parts of said protective layer not covered by the gate electrode (2) are removed.

15. The method of claim 1, wherein the organic field effect transistor is a top-gate, top-contact electronic device comprising the following components in the following order:

-a substrate (1),

-an organic semiconductor layer (7),

-a source and a drain (5),

-an insulator layer (3) comprising a dielectric material,

-a gate (2),

-a protective layer (4a) between the organic semiconductor layer and the source and drain electrodes and/or a protective layer (4b) between the insulator layer and the gate electrode.

16. The method according to claim 15, comprising the steps of: an organic semiconductor layer (7) is applied on the substrate (1), source and drain electrodes (5) are applied on the organic semiconductor layer (7) or the protective layer (4a), a dielectric layer (3) is applied on the source and drain electrodes (5), and a gate electrode (2) is applied on the dielectric layer (3) or the protective layer (4 b).

17. A method according to claim 16, wherein after the step of applying the organic semiconductor layer (7) on the substrate (1), a protective layer (4a) is applied on top of the organic semiconductor layer (7).

18. A method according to claim 16, wherein after the step of applying the source and drain electrodes (5) on the organic semiconductor layer (7) or the protective layer (4a), those parts of said protective layer (4a) which are not covered by the source and drain electrodes (5) are removed.

19. A method according to claim 16, wherein the protective layer (4b) is applied over the dielectric layer (3) after the step of applying the dielectric layer (3) over the source and drain electrodes (5).

20. A method according to claim 16, wherein after the step of applying the gate electrode (2) over the dielectric layer (3) or the protective layer (4b), those parts of said protective layer (4a) which are not covered by the gate electrode (2) are removed.

21. The method according to claim 1, comprising the steps of:

a) one or more first electrodes (2) are provided on a substrate (1),

b) providing a layer (3) of a dielectric material on the substrate (1) and the first electrode (2),

c) providing a protective layer (4) on top of the dielectric layer (3),

d) one or more second electrodes (5) are provided on the protective layer (4),

e) providing a photoresist layer (6) over the second electrode (5),

f) the photoresist (6) is treated by a suitable method to leave a pattern of photoresist and areas without photoresist (6) over the second electrode (5),

g) removing those parts of the second electrode (5) not covered by the photoresist (6),

h1) the photoresist (6) is removed and,

i1) removing those parts of the protective layer (4) which are not covered by the second electrode (5),

m1) applying an organic semiconductor layer (7) onto the uncovered parts of the dielectric layer (3) and the second electrode (5), or replacing steps h1) -m1) with steps h2) -n2),

h2) removing those parts of the protective layer (4) which are not covered by the second electrode (5),

k2) the photoresist (6) is removed and,

n2) applying the organic semiconductor layer (7) onto the uncovered parts of the dielectric layer (3) and the second electrode (5).

22. A method according to claim 21, wherein i1) is followed by washing the remaining part of the protective layer (4) to remove residues caused by step f).

23. A method according to claim 21, wherein h2) is followed by curing the remaining part of the protective layer (4).

24. Method according to claim 21, wherein k2) is followed by washing the remaining part of the protective layer (4) to remove residues caused by step f).

25. The method according to claim 1, comprising the steps of:

a) one or more first electrodes (2) are provided on a substrate (1),

b) forming a layer (3) of a dielectric material on the substrate (1) and the first electrode (2),

c) providing a protective layer (4) on top of the dielectric layer (3),

d) one or more second electrodes (5) are provided on the protective layer (4),

e) providing a bank structure layer (6) over the protective layer (4) and the second electrode (5) such that it at least partially covers the protective layer (4) and the second electrode (5),

f) subjecting the bank structure layer (6), and those parts of the protective layer (4) not covered by the second electrode (5) or the bank structure layer (6), to a plasma treatment,

g) removing those parts of the protective layer (4) which are not covered by the second electrode (5) or the bank structure layer (6),

i) an organic semiconductor layer (7) is applied to the dielectric layer (3) and the uncovered parts of the second electrode (5).

26. The method according to claim 25, wherein g) is followed by washing the remaining part of the protective layer (4) to remove the residue caused by step f).

27. A method according to claim 1 or 2, wherein the device is exposed to a plasma of energetic particles after the protective layer (4) is applied.

28. The method of claim 27, wherein the plasma is O₂Ar or CF₄Plasma or mixtures thereof.

29. A method according to claim 1 or 2, wherein the thickness of the protective layer is 1-500 nm.

30. A method according to claim 1 or 2, wherein the protective layer comprises an organic or inorganic material.

31. The method of claim 30, wherein the protective layer comprises a material selected from the group consisting of organic polymers, inorganic oxides, both of which are solution processable or vacuum deposited.

32. The method of claim 30, wherein the protective layer comprises a nanoparticle material that is solution processable or vacuum deposited.

33. The method of claim 30, wherein the protective layer comprises a polymer selected from the group consisting of: partially or perfluorinated organic polymers, polyimides, polycycloolefins having alkoxysilane or vinylalkoxysilane groups, curable polysilsesquioxanes, thermosetting polysiloxane resins, polyacenaphthylene, poly-N-vinylcarbazole, poly (2-vinylnaphthalene), poly (4-vinylbiphenyl), and poly (1-vinylnaphthalene).

34. An electronic device obtained by the method according to one of claims 1 to 33.