HK1141195B - Method for forming solid blind vias through the dielectric coating on high density interconnect (hdi) substrate materials - Google Patents

Description

Method of forming solid blind via through dielectric coating on high density interconnect HDI substrate material

Technical Field

The present invention relates to electronic circuit assemblies, and more particularly to circuit assemblies including High Density Interconnect (HDI) substrates and their manufacture.

Background

Electrical components (e.g., resistors, transistors, and capacitors) are typically mounted on a circuit panel structure, such as a printed circuit board. A circuit board typically comprises a substantially planar sheet of dielectric material with electrical conductors disposed on a major planar surface or on both major surfaces of the sheet. The conductors are typically formed of a metallic material, such as copper, and are used to interconnect electrical components mounted to the board.

Microelectronic circuit packages are prepared in various sizes. One package level includes a semiconductor chip containing a plurality of microcircuits and/or other components. Such chips are typically made of semiconductors such as silicon. The intermediate packaging level, also referred to as a Chip Scale Package (CSP), may include a multilayer substrate and a plurality of chips. These intermediate package levels may be attached to larger scale circuit cards, motherboards, etc. The intermediate package level serves a variety of purposes throughout the circuit assembly including structural support, transitional integration from smaller scale circuits to larger scale boards, and heat dissipation of circuit elements. Substrates used in conventional intermediate package levels include various materials, such as ceramics, fiberglass reinforced polyepoxides, and polyimides.

There is an increasing demand for circuit panel structures that provide high density, complex interconnections. Such a need may be addressed by a multi-layer circuit panel structure; however, there are serious drawbacks to manufacturing such a multilayer circuit assembly. As more and more circuit layers are applied, it is difficult to align holes (hole) and vias (via) by drilling holes in the dielectric layer. Laser drilling is the most common method of forming vias, which can significantly increase the cost of manufacturing such circuit assemblies.

Generally, a multi-layer panel is made by providing a single, double-sided circuit panel with appropriate conductors thereon. The panels are then stacked one on top of the other with one or more layers of uncured or partially cured dielectric material, often referred to as "prepregs", disposed between each pair of adjacent panels. Such a laminate is typically cured under heat and pressure to form a monolithic block. After curing, holes are typically drilled through the stack at locations where electrical connections between different boards are desired. The resulting hole or "through via" is then typically coated or filled with a conductive material by plating the interior of the hole to form a plated through via. It is difficult to drill holes with a high depth to diameter ratio, and therefore the holes used in such assemblies must be relatively large and take up a lot of space in the assembly.

In applications where circuit layers are built up one on top of the other, dielectric materials typically separate the circuit layers. Polymeric dielectric materials commonly used in circuit assemblies are thermoplastic or thermoset polymers. The thermoset material is typically first cured to form a conformal coating. Although a conformally coated substrate may contain through-holes that coincide with the perforated substrate, blind holes are typically formed by drilling (e.g., by a laser).

It is desirable to provide a method of forming solid blind or protruding conductive structures in a substrate by using fabrication techniques that reduce the cost of via formation compared to mechanical and laser drilling techniques.

Disclosure of Invention

In a first aspect, the present invention provides a method comprising the steps of: applying a first removable material over the conductive core; making an opening in the first removable material to expose a portion of the conductive core; plating a conductive material onto the exposed portion of the conductive core; applying a second removable material over the plated portion of conductive material; removing the first removable material; electrophoretically applying a dielectric coating to the conductive core; and removing the second removable material.

In another aspect, the present invention provides a method comprising the steps of: applying a layer of a first conductive material on a substrate, the substrate having a dielectric coating on a conductive core and a conductive via extending through an opening in the dielectric coating; applying a layer of a first removable material on the first conductive material; forming an opening in the first removable material to expose a region of the conductive material to be plated; plating a second conductive material onto the exposed areas of the first conductive material; applying a layer of a second removable material over the first and second conductive materials; forming an opening in the second removable material to expose a region of the second conductive material to be plated; and plating a third conductive material onto the exposed areas of the first conductive material.

In another aspect, the invention provides a method comprising: forming a first substrate by: (a) applying an electrodepositable dielectric coating onto a conductive surface; (b) curing the dielectric coating; (c) depositing an adhesion layer and a seed layer onto the dielectric coating; (d) applying a layer of a first removable material onto the seed layer; (e) forming an opening in the first removable material to expose a region of the seed layer; (f) electroplating a first conductive material onto the exposed areas of the seed layer; (g) applying a layer of a second removable material; (h) forming an opening in the second removable material to expose a region of the first conductive material; (i) plating a second conductive material onto the exposed areas of the first conductive material; (j) removing the first and second removable materials; and (k) removing the unplated portion of the seed layer; repeating steps (a) to (k) to form a second substrate; and laminating the first and second substrates together with a layer of dielectric material between the first and second substrates, forming at least one interconnect between the first and second substrates.

In another aspect, the present invention provides a method comprising the steps of: applying a layer of a first conductive material to a substrate, the substrate having a dielectric coating on a conductive core and a conductive via extending through an opening in the dielectric coating; plating a first conductive material and patterning the first conductive material to form a circuit layer; applying a layer of plating resist on the just patterned circuit layer; forming an opening in the plating resist to expose a region of the patterned circuit layer to be plated; plating a second conductive material onto the exposed areas of the first conductive material; and removing the plating resist.

Drawings

Fig. 1 is a plan view of a core layer of a substrate.

FIG. 2 is a cross-sectional view of the core layer of FIG. 1 taken along line 2-2.

Fig. 3 is a plan view of an intermediate structure.

Fig. 4 is a cross-sectional view of the intermediate structure of fig. 3 taken along line 4-4.

Fig. 5 is a plan view of an intermediate structure.

Fig. 6 is a cross-sectional view of the intermediate structure of fig. 5 taken along line 6-6.

Fig. 7 is a plan view of an intermediate structure.

Fig. 8 is a cross-sectional view of the intermediate structure of fig. 7 taken along line 8-8.

Fig. 9 is a plan view of an intermediate structure.

Fig. 10 is a cross-sectional view of the intermediate structure of fig. 9 taken along line 10-10.

Fig. 11 is a plan view of an intermediate structure.

FIG. 12 is a cross-sectional view of the intermediate structure of FIG. 11 taken along line 12-12.

Fig. 13 is a plan view of an intermediate structure.

Fig. 14 is a cross-sectional view of the intermediate structure of fig. 13 taken along line 14-14.

Fig. 15 is a plan view of a substrate.

Fig. 16 is a cross-sectional view of the substrate of fig. 15 taken along line 16-16.

Fig. 17 is a plan view of an intermediate structure.

FIG. 18 is a cross-sectional view of the intermediate structure of FIG. 17 taken along line 18-18.

Fig. 19 is a plan view of an intermediate structure.

Fig. 20 is a cross-sectional view of the intermediate structure of fig. 19 taken along line 20-20.

Fig. 21 is a plan view of an intermediate structure.

Fig. 22 is a cross-sectional view of the intermediate structure of fig. 21 taken along line 22-22.

Fig. 23 is a plan view of an intermediate structure.

FIG. 24 is a cross-sectional view of the intermediate structure of FIG. 23 taken along line 24-24.

Fig. 25 is a plan view of an intermediate structure.

FIG. 26 is a cross-sectional view of the intermediate structure of FIG. 25 taken along line 26-26.

Fig. 27 is a plan view of an intermediate structure.

FIG. 28 is a cross-sectional view of the intermediate structure of FIG. 27 taken along line 28-28.

Fig. 29 is a plan view of an intermediate structure.

FIG. 30 is a cross-sectional view of the intermediate structure of FIG. 29 taken along line 30-30.

Fig. 31 is a plan view of an intermediate structure.

FIG. 32 is a cross-sectional view of the intermediate structure of FIG. 31 taken along line 32-32.

Fig. 33 is a plan view of the substrate.

Fig. 34 is a cross-sectional view of the substrate of fig. 33 taken along line 34-34.

Detailed Description

In one aspect, the present invention provides a method of fabricating a conductive bump component (e.g., a solid blind via or post) that extends through a dielectric coating of a circuit board or substrate that may be used as a Chip Scale Package (CSP) component or as a High Density Interconnect (HDI) substrate.

Referring to the drawings, FIG. 1 is a plan view of a sheet of conductive material 10 that may be used to form a conductive core of a substrate or circuit board, and FIG. 2 is a cross-sectional view of the core of FIG. 1 taken along line 2-2. Optional openings or vias 12 and 14 may be provided in the core.

The core may be a conductive material such as a nickel-iron alloy. One preferred nickel-iron alloy is INVAR (a trademark owned by Imphy s.a. company, Rue de Rivoli avenue 168, paris, france) containing approximately 64 weight percent iron and 36 weight percent nickel. Such alloys have a lower coefficient of thermal expansion compared to the silicon material used to make the chip. A low coefficient of thermal expansion is desirable in order to prevent failure of the bond between successively larger or smaller scale layers of a circuit board or chip scale package due to thermal cycling during storage or normal use. When a nickel-iron alloy is used as the conductive core, a layer of copper metal can be applied to all surfaces of the conductive core to form an enhanced conductivity Cu/Invar/Cu structure. The layer of copper metal can be applied by conventional means such as electroplating or metal vapor deposition. The layer of copper may typically have a thickness of 1 to 20 microns.

In other embodiments, the substrate core layer may comprise any of a variety of materials, such as metals that may be, for example, untreated or galvanized steel, aluminum, gold, nickel, copper, magnesium, or alloys of any of the foregoing, as well as conductive carbon-coated materials or metalized non-conductive materials (e.g., sputtered ceramic or coated plastic). More specifically, the substrate may comprise a metal core selected from copper foil, nickel-iron alloy, and combinations thereof. The substrate may also be a perforated substrate composed of any of the foregoing metals or combinations thereof.

In some embodiments, the thickness of the conductive core may be about 20 to 400 microns, preferably 150 to 250 microns. The core may include a plurality of holes, which may or may not be of uniform size and shape. In one embodiment, when the holes are circular, the diameter of the holes may be about 8 mils (203.2 microns). The holes may be larger or smaller, if desired.

A layer of a first removable material, which may be a resist (also referred to as a plating resist), is applied over the core. This is illustrated in fig. 3 and 4, where fig. 3 is a plan view of the intermediate structure 16 including the substrate of the core 10 coated with the plating resist 18, and fig. 4 is a cross-sectional view of the intermediate structure of fig. 3 taken along line 4-4. As shown in fig. 5 and 6, the plating resist may be patterned using known techniques to make openings in the plating resist and expose portions of the conductive metal core where blind studs (stud) and other protruding members are intended to be located. For example, the plating resist may be imaged (image) and developed to create one or more openings 20, 22, and 24 in the plating resist and to expose one or more portions 26, 28, and 30 of the conductive core surface where blind vias, conductive studs, or other protruding features are desired.

The plating resist may be a negative-working photoresist that can be developed and stripped in a caustic solution, or a positive-working photoresist that can be developed and stripped in an acidic solution. In the example of fig. 4, a stacked plating resist is used. The openings are covered (tent over) with a layer of plating resist. Other types of removable coatings that can be filled into the holes or painted on the walls of the holes can also be used.

Negative-working photoresists include liquid or dry film type compositions. The liquid composition may be applied by roll coating (rolling application) techniques, curtain coating (curl application) or electrodeposition. Preferably, the liquid photoresist is applied by electrodeposition, more preferably by cationic electrodeposition. The electrodepositable composition comprises an ionic polymeric material which may be cationic or anionic and may be selected from polyesters, polyurethanes, acrylics and polyepoxides.

If the first removable material is a photosensitive material, after the photosensitive layer is applied, a photomask having the desired pattern can be placed over the photosensitive layer and the layered substrate exposed to a sufficient level of an appropriate source of actinic radiation. The term "sufficient degree of actinic radiation" as used herein refers to that degree of radiation which polymerizes monomers in the radiation-exposed regions in the case of a negative-acting resist, or which depolymerizes or otherwise renders a polymer more soluble in the case of a positive-acting resist. This results in a difference in solubility between the radiation exposed region and the radiation shielded region.

The photomask may be removed after exposure to the radiation source and the layered substrate developed using a conventional developer to remove the more soluble portions of the photosensitive layer and expose selected areas of the underlying metal layer. The metal exposed in this step can then be etched using a metal etchant that converts the metal to a water-soluble metal complex. The soluble complex can be removed by water spraying.

As shown in fig. 7 and 8, the substrate is then plated with a conductive material such as copper. Thus, conductive material will be deposited in the openings in the plating resist and on the exposed areas of the conductive substrate, resulting in the formation of conductive raised features such as pillars or posts 32, 34, and 36 at the location of the exposed areas. For plating, the substrate may be immersed in a plating bath and a voltage applied between the core and the bath. Since the plating resist is electrically non-conductive, plating only occurs where there are openings in the plating resist.

After electroplating and post formation, a second removable material 38, 40 and 42 is applied. As shown in fig. 9 and 10, a second removable material is formed on top of the protruding members. The second removable material may be an electrodepositable photoresist. The electrodepositable photoresist may be applied only to the areas of the structure having exposed metal, i.e., the posts or pillars formed during the plating step. In one embodiment, the electrodepositable photoresist is a positive-acting cationic photoresist and can be developed and stripped in an acidic solution. The electrodepositable photoresist may also be a negative-working photoresist that can be developed and stripped in a caustic solution.

Suitable positive-working photosensitive resins include any of those known to those skilled in the art. Examples include dinitrobenzyl functional polymers. Such resins have high photosensitivity. In one example, the photosensitive layer of resin is a composition comprising a dinitrobenzyl functional polymer, typically applied by spraying. Nitrobenzyl functional polymers are also suitable. The photosensitive layer can also be an electrodepositable composition comprising a dinitrobenzyl functional polyurethane and an epoxy-amine polymer. Since the areas covered by the electrodepositable photoresist in this example need not be exposed to dissolve the desired features, the coating need not be a resist, but rather a removable coating.

The first removable material is then removed. If the first removable material is a photoresist, the substrate may be exposed to Ultraviolet (UV) radiation to photodegrade or depolymerize the photoresist covering the tops of the pillars or posts, as shown in FIGS. 11 and 12. Alternatively, the step of exposing the photoresist to light may be omitted, as the photoresist may be replaced with another type of removable material.

By using different materials for the first and second removable materials, different chemical reactions can be used to remove those materials. Thus leaving the second removable material 38, 40 and 42 intact on top of the stakes or posts.

A dielectric coating 44 is then applied electrophoretically, as shown in fig. 13 and 14, to conformally coat the conductive substrate except in those areas covered by the second removable material remaining on top of the pillars, posts, or other components. Only the areas with exposed metal are coated with a dielectric material. The tops of the posts or pillars are still covered by electrodepositable photoresist (or other removable coating) and, therefore, are not coated with dielectric material. If the step of exposing the photoresist to light is performed, it may be performed before or after the application and curing of the dielectric material.

A dielectric coating is applied to the exposed surfaces of the core to form a conformal coating thereon. As used herein, a "conformal" film or coating refers to a film or coating having a substantially uniform thickness that conforms to the core profile (topograph) including the surfaces within the pores in the core (but, preferably, not occluding the pores). The dielectric coating film thickness is typically between 5 and 50 microns. Smaller film thicknesses may be desirable for various reasons. For example, a dielectric coating having a smaller film thickness may enable smaller scale circuitry to be formed. However, the thickness of the dielectric coating may be determined by the performance requirements of the finished substrate.

The dielectric material is a non-conductive substance or insulator. For high frequency, high speed digital applications where the capacitance of the substrate and coating are critical to the reliable operation of the circuit, it is desirable to use materials with low dielectric constants.

The dielectric coating may be formed from any of a variety of coating compositions. The dielectric coating may be formed from a thermoplastic composition that, once applied, volatilizes or evaporates off the solvent (i.e., organic solvent and/or water) to form a film of the dielectric coating on the substrate. The dielectric coating may also be formed from a curable or thermoset composition that, once applied to a substrate and cured, forms a cured film of the dielectric coating. The dielectric coating may be applied by any coating application technique to provide a coating having a desired dielectric constant to ensure sufficient insulating and fire resistant properties.

The dielectric coating may be applied by any suitable conformal coating method including, for example, dip coating, vapor deposition, electrodeposition, and autophoretic deposition. Examples of dielectric coatings applied by vapor deposition include: parylene (including substituted and unsubstituted parylene); a silsesquioxane; and polybenzocyclobutene. Examples of dielectric coatings applied by electrodeposition include: acrylic, epoxy, polyester, polyurethane, polyimide or oil-based resin compositions for the anode and cathode. The use of an electrodeposited coating takes advantage of the fact that the top of the via/stub is sufficiently isolated from the applied electrodeposited dielectric coating.

In particular embodiments, the dielectric coating may be formed by electrodepositing an electrodepositable photosensitive material. In this embodiment, the dielectric coating may be applied to the core by electrodepositing an electrodepositable coating composition comprising a resinous phase (resin phase) dispersed in an aqueous medium, wherein the resinous phase contains covalent bond halogens in an amount of at least 1 weight percent based on the total weight of resin solids present in the resinous phase. In another embodiment, a dielectric material that is not photosensitive may be used.

The electrodepositable coating composition may be applied electrophoretically to a conductive substrate (or a substrate that has been rendered conductive by metallization). The voltage applied for electrodeposition may vary and may be, for example, as low as 1 volt to as high as several thousand volts, but is typically between 50 and 500 volts. The current density is typically between 0.5 and 5 amps per square foot (0.5 and 5 milliamps per square centimeter) and trends downward during electrodeposition, indicating the formation of an insulating conformal film on all exposed surfaces of the substrate. After the coating is applied by electrodeposition, it is typically cured, typically at elevated temperatures ranging from 90 ℃ to 300 ℃ over a period of 1 to 40 minutes, to form a conformal dielectric coating over all exposed surfaces of the core.

After the dielectric coating is applied, the dielectric coating can be removed at one or more predetermined locations to expose one or more portions of the substrate surface. The dielectric coating can be removed by various methods (e.g., by ablation techniques). Such ablation is typically performed using a laser or by other conventional techniques, such as mechanical drilling and chemical or plasma etching techniques. If a photosensitive dielectric coating is used, it can be exposed and developed to form the openings.

Furthermore, the substrate surface may be pretreated or prepared for application of the dielectric material prior to application of the dielectric coating. For example, it may be suitable to wash, rinse, and/or treat with an adhesion promoter prior to applying the dielectric material.

Finally, as shown in fig. 15 and 16, the second removable material (which may be photoresist) is removed, leaving a finished substrate 46. To obtain the structure of fig. 15 and 16, the dielectric coating is cured or partially cured (if necessary), and the remaining photoresist (or other removable coating) 38, 40 and 42 is removed. At this point, the substrate is ready for further processing such as sputtering, plating, and etching. The end result is a conformally coated substrate with one or more solid vias extending through the dielectric material 44 to the metal core 10.

The above process may be repeated multiple times for each layer in a multilayer substrate or circuit board. Finally, the multiwall sheet can include posts, or other protruding members that form connections from the outermost layer to an inner layer, from an inner layer to another inner layer, from an inner layer to a core, and/or from the outermost layer to a core.

The thickness of the layer of removable material may be selected so that it corresponds to the desired height of the plated pillars and/or studs and the desired dielectric thickness.

Solid posts, studs or other protruding features may be used as micro blind holes that enable electrical connections to be made through the dielectric layer. The posts may also be used for positioning and anchoring of boards stacked into the multilayer package. Additionally, the posts, studs, and other protruding members may serve as thermal conductors to transfer heat from the chip or other component to the exterior of the package.

In another aspect, the invention provides a method of fabricating a multilayer substrate, chip scale package, or other circuit component using a multilayer build-up process with pad-to-pad connections. In this aspect, the invention provides a process for bonding multilayer substrates and forming electrical connections between the bonded layers.

In one embodiment, the method begins by coating a substrate having solid metal vias with a thin layer of conductive material (e.g., sputtered and/or electroplated copper). Next, a layer of a first removable material is applied over all areas. Preferably, the first removable material is an electrodepositable resist. If the removable material is a plating resist, it is imaged and developed in the areas to be plated. Then, a conductive material such as copper is electroplated to a desired thickness, preferably a thickness of a plating resist. Next, a layer of a second removable material is applied. If the second removable material is a plating resist, it is imaged and developed to expose only the areas for the solid via posts and pillars. Copper is electroplated again to a desired thickness, preferably the thickness of the second layer plating resist. Thus, solid blind studs and pillars are formed. Then, all plating resists were removed. This process will be described in more detail with reference to fig. 17-34.

As shown in fig. 17 and 18, starting from the substrate of fig. 15 and 16, a thin layer of metal 50, such as copper, is applied over the dielectric coating 44 on the core 10. Copper may be deposited by initially using electroless deposition (i.e., depositing metal by chemical means rather than by electrodeposition) and then plating additional metal to the desired thickness. Alternatively, a seed layer (also referred to as a tie layer) of a metal such as chromium or nickel may be sputtered onto the coated substrate, followed by a layer of copper, which is then plated to the desired thickness.

Then, as shown in fig. 19 and 20, a conventional plating resist 52 may be applied on the substrate with the thin copper layer. As shown in fig. 21 and 22, resist 52 may be patterned using known techniques to expose areas 54, 56, and 58 where vias, blind vias, other raised structures, and/or circuitry are to be located.

Fig. 23 and 24 show that metal 60, such as copper, is again electroplated onto the substrate. However, in this step, copper is plated only on the exposed areas of the core. With the plating completed, as shown in fig. 25 and 26, a second layer of plating resist 62 is applied. As shown in fig. 27 and 28, this layer of resist is patterned using known techniques to expose areas 64, 66 and 68 where blind vias or other protruding structures are to be located.

Fig. 29 and 30 show the electroplating of copper onto a substrate to form raised features 70, 72 and 74 such as solid through-holes and blind studs or posts. Once plating is complete, all plating resist is removed from the substrate, leaving the structure 76 shown in fig. 31 and 32.

The substrate is then subjected to a metal etchant that removes all of the thin metal in the unplated areas, but only a portion of the metal in the plated areas, leaving structure 78 as shown in fig. 31 and 32. The substrate is etched in such a way that all of the "seed layer" of copper is removed. As a result, copper in other areas is also etched away. However, this only reduces the total thickness and line width of the copper traces.

This process may be repeated multiple times to build additional circuit layers on the substrate. When completed, the substrate is ready to be stacked with another substrate. Solid posts, studs or other components may be used as micro blind vias to enable electrical connections to be made through the dielectric layer. The posts may also be used for positioning and anchoring of boards stacked into the multilayer package. Additionally, the posts, studs, and other components may act as thermal conductors, transferring heat from the chip or other component to the exterior of the package.

In another aspect, the invention provides a method of plating a thin layer of copper onto a dielectric material after sputtering. Then, a plating resist is applied to plate (plate up) a desired circuit. Instead of stripping the plating resist, another layer of plating resist is applied and the posts plated. These studs can be used for connection through holes and for laminate anchoring. Then all plating resists are stripped and the thin copper layer on top of the dielectric material is etched away. Then, another similar substrate material is ready to be laminated with the substrate.

More specifically, this aspect provides techniques for joining together two or more circuit boards or package substrate layers. To do this, solid vias or posts are plated onto the circuit to a height greater than the thickness of the laminar dielectric material that can be used to insulate the joined circuit layers. The whole process is as follows:

1) an electrodepositable dielectric coating is applied onto the conductive surface. The dielectric coating is cured.

2) An adhesion layer (e.g., chromium) and a seed layer (e.g., copper) are sputter deposited on all surfaces of the dielectric material.

3) A layer of plating resist is applied to the sputtered substrate.

4) The resist is patterned.

5) Copper is plated in a pattern, thereby depositing copper onto the areas of the sputtered seed layer where circuitry is to be formed.

6) A second layer of plating resist is applied.

7) The second layer of resist is patterned to make openings in the resist. These openings may be over the area of the circuit and may be at locations where it is desired to form an interconnect between two stacked layers.

8) Copper is plated in a pattern, thus forming solid posts.

9) Stripping the two layers of plating resists.

10) The seed layer that was not plated is removed.

11) Substrates are laminated together with a layer of dielectric material therebetween, thus forming an interconnect between the substrates.

Additional conductors or contacts may be formed by chemical, mechanical or laser ablation or using masking techniques to prevent the application of a coating over selected areas, or to remove portions of the dielectric coating in a predetermined pattern to expose portions of the conductive core. A layer of metal is then applied to portions of the dielectric coating to form the conductors and contacts. Metallization of at least one dielectric coating may also be used to form contacts and conductors adjacent to the surface of the dielectric coating.

Metallization is typically performed after the removal step by applying a layer of metal to all surfaces, enabling formation of metallized vias (i.e., through vias) through the substrate and/or metallized vias (i.e., blind vias) to (but not through) the core.

Alternatively, the metallization may be performed prior to the removal step, followed by additional metallization if necessary. The metal applied in this metallization step may be any of the aforementioned metals or alloys, as long as the metal or alloy has sufficient electrical conductivity. Typically, the metal applied in the above-described metallization step is copper. The metal may be applied by conventional electroplating, seed electroplating, metal vapor deposition, or any other method that provides a uniform metal layer as described above. The thickness of the metal layer is typically about 5 to 50 microns.

To improve the adhesion of the metal layer to the dielectric coating prior to the metallization step, all surfaces may be treated with ion beam, electron beam, corona discharge or plasma bombardment followed by application of an adhesion promoter layer to all surfaces. The adhesion promoter layer may have a thickness ranging from 50 to 5000 angstroms and is typically a metal or metal oxide selected from chromium, titanium, nickel, cobalt, cesium, iron, aluminum, copper, gold, tungsten, and zinc, and alloys and oxides thereof.

After metallization, a photosensitive layer (formed from a "photoresist" or "resist" composition) may be applied to the metal layer. Optionally, the metallized substrate may be cleaned and pretreated prior to applying the photosensitive layer; for example, treatment with an acidic etchant removes oxidized metal. The photosensitive layer may be a positive or negative photosensitive layer. The photosensitive layer typically has a thickness of about 2 to 50 microns and may be applied by any method known to those skilled in the art of photolithographic processing. Additive or subtractive processing methods may be used to produce the desired circuit pattern.

After the circuit pattern is prepared on the substrate, other circuit elements may be attached in one or more subsequent steps to form a circuit assembly. Additional components may include one or more multi-layer circuit assemblies, smaller scale components such as semiconductor chips, interposer layers, larger scale circuit cards or motherboards, and active or passive components, prepared by any of the processes of the present invention. These components may be attached using conventional adhesives, surface mount techniques, wire bonding, or flip chip techniques.

It is understood that any process of the present invention may include one or more additional steps without departing from the scope of the present invention. Also, the order in which the steps are performed may be changed, if necessary, without departing from the scope of the present invention.

As used in this description, unless otherwise indicated, numerical parameters are approximations that may vary depending upon the desired properties sought to be obtained. Accordingly, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques, or by taking into account typical manufacturing tolerances.

Moreover, it should be understood that any numerical range recited herein is intended to include all sub-ranges subsumed therein. For example, a range of "1 to 10" is intended to include all sub-ranges between and including the minimum value of 1 and the maximum value of 10 (i.e., having a minimum value equal to or greater than 1 and a maximum value of equal to or less than 10).

Although the invention has been described with respect to several examples, it will be apparent to those skilled in the art that various changes in the described examples may be made without departing from the scope of the invention as set forth in the following claims.

Claims (16)

1. A method of making an electrically conductive protrusion member, comprising the steps of:

applying a first removable material over the conductive core;

forming an opening in the first removable material to expose a portion of the conductive core;

plating a conductive material onto the exposed portion of the conductive core;

applying a second removable material over the conductive material;

removing the first removable material;

electrophoretically applying a dielectric coating to said conductive core; and

the second removable material is removed.

2. The method of claim 1, wherein the first and second removable materials are removed using different chemical reactions.

3. The method of claim 1, wherein the first removable material comprises a negative-acting resist and the second removable material comprises a positive-acting resist.

4. The method of claim 1, wherein the first removable material comprises a positive-working resist and the second removable material comprises a negative-working resist.

5. The method of claim 1, wherein the dielectric coating is cured.

6. The method of claim 1, further comprising the steps of:

a conductive layer is applied on all surfaces of the dielectric coating.

7. The method of claim 6, wherein the conductive layer is applied electrolessly.

8. The method of claim 7, wherein the conductive layer is also electroplated.

9. The method of claim 6, wherein the conductive layer is sputtered.

10. The method of claim 9, wherein the conductive layer is also electroplated.

11. A method of making an electrically conductive protrusion member, comprising the steps of:

applying a layer of a first conductive material to a substrate having a dielectric coating on a conductive core and a conductive via extending through an opening in the dielectric coating;

applying a layer of a first removable material onto the first conductive material;

forming an opening in the first removable material to expose areas of the first conductive material to be plated;

plating a second conductive material onto the exposed areas of the first conductive material;

applying a layer of a second removable material onto the first conductive material and the second conductive material;

forming an opening in the second removable material to expose areas of the second conductive material to be plated; and

plating a third conductive material onto the exposed areas of the second conductive material.

12. The method of claim 11, wherein applying the layer of the first conductive material onto the substrate comprises:

depositing a seed layer using electroless deposition; and

plating the first conductive material onto the seed layer.

13. The method of claim 12, further comprising the steps of:

removing the first removable material; and

and etching the seed layer.

14. The method of claim 11, wherein applying the layer of the first conductive material onto the substrate comprises:

sputtering and depositing a seed layer; and

plating the first conductive material onto the seed layer.

15. The method of claim 14, further comprising the steps of:

removing the first removable material; and

and etching the seed layer.

16. The method of claim 11, wherein the first removable material and the second removable material are plating resists.