HK1035255B - Method and apparatus for a serial access memory - Google Patents

Description

Method and apparatus for serial access to memory

Technical Field

The present invention relates to serial access memory devices, and more particularly to an access method and architecture that allows a pipelined scheme to read the contents of these devices.

Background

Serial memory devices typically have a single input pin and a single output pin to provide I/O. While there are many product-specific and proprietary protocols for accessing these devices, many industry standards are known and are in the public domain. For example, I²C is a two-wire standard, Microwire is a three-wire standard, and Serial Peripheral Interface (SPI) is a four-wire standard.

One advantage of using a non-standard protocol is that the memory device and its interface can be custom designed to provide very high speed access. However, this sacrifices in that these devices are generally suitable for very specific applications, which in turn are not readily versatile. More importantly, there is now only one device vendor for such devices. On the other hand, standard interfaces such as SPI provide the advantages of a universal interface. However, such schemes often result in devices that lack optimal performance characteristics.

The address bits of the target memory location are shifted in serially on each rising edge of the clock, starting with the most significant bit, as specified for reading the memory in an SPI compliant device. After the last address bit is clocked in, the most significant bit of the target byte is latched (latch out) on the falling edge of the clock immediately following the last address bit. Then, from the time the last bit of the address is received by the device, there may be approximately half a clock cycle time for the subsequent sequence of events to occur: a memory page must be selected; the bits of the selected byte within the page must be detected (sense); and must prepare the most significant bit of the clock out.

Each of these events causes a delay. For example, the capacitive load causes a delay due to the time required to charge the selected word line and the data line of the selected memory cell. Then, the sense amplifier requires additional time to detect the state of each data line (i.e., bit) including the memory cell. This sequence of events imposes an upper limit on the operating frequency of the device. The clock frequency cannot exceed the time period required to allow line charging and sense amplifier operation. Currently, this upper limit is on the order of 2MHz to 5 MHz.

Attempts to increase the read access speed of serial memory are disclosed in U.S. Pat. No. 5,663,922. The' 922 patent discloses a serial memory device in which the memory array is broken into two half-arrays (M1, M2, fig. 1). Each half array is accessed to generate one byte from it upon receipt of all but the last bit of the address. Each half-array has associated read circuitry (SA1, SA2) for detecting eight bits comprising one byte, i.e. a bank of eight sense amplifiers per half-array. The output of the read circuit feeds into a Multiplexer (MUX). The multiplexer is controlled to select the appropriate byte based on the last address bit received.

One point to note in the' 922 patent is that additional circuitry is required to support the memory array divided into multiple sub-arrays. This increases the complexity and cost of manufacturing such devices. More significantly, each sub-array requires a column of sense amplifiers to sense the accessed byte within the sub-array. The consumption of silicon real estate and power by sense amplifiers is notorious. Thus, while the device of the' 922 patent reduces read access times, the size and power burden of the circuitry providing such capability outweighs the benefits realized by the circuitry.

There is a need to implement high speed read access in a serial memory without using additional circuitry. It is also desirable to provide this capability without additional power requirements.

Disclosure of Invention

In accordance with the present invention, a method of accessing a serial memory includes serially clocking in N address bits of a target memory cell. The memory array is accessed when several (less than N) address bits have been clocked in. This partial address corresponds to two or more possible memory locations (including the target location). The data lines of each possible cell are selected and detected. More specifically, only a subset of the data lines of each such cell are detected. Upon receipt of subsequent bits of the target address, the address range is reduced by half, resulting in a reduction of half the number of possible cells. In the halved possible memory cells (still including the target cell), a second subset of data lines is selected and sensed in addition to the first subset of sensed data lines. Thus, although the entire address of the target unit has not been received, some bits of the target unit have begun to be detected. More specifically, since all data lines are not sensed, the number of sense amplifiers required for this operation is kept to a minimum.

In one embodiment of the invention, some of the sense amplifiers are reused when subsequent bits of the target address are received, thereby further reducing the number of sense amplifiers required to read the target cell. This is possible because the number of possible cells is reduced by half when receiving subsequent address bits.

Brief description of the drawings

Fig. 1 is a block diagram of a serial memory device.

Fig. 2 shows a logic diagram of the Y decoder circuit of fig. 1 in accordance with the present invention.

Fig. 3A and 3B illustrate an exemplary implementation of the decoder circuit shown in fig. 2.

4A-4B are timing diagrams illustrating the relative timing of address bits and data bits according to various embodiments of the invention.

Fig. 5 is a flow chart of the operation of the present invention.

Fig. 6A-6D show the active lines during operation of a device according to the present invention.

Fig. 7A-7E show another embodiment of the Y decoder of the present invention and the active lines during its operation.

Fig. 8 shows a third embodiment of the Y decoder according to the present invention.

Fig. 9 is an implementation of the switching circuit shown in fig. 8.

Preferred embodiments of the invention

Although the present invention does not require an SPI interface, the serial memory device of FIG. 1 operates according to the SPI standard and is also suitable for use with devices such as I²C or Microwire standards, among other bus standards. The serial memory 100 includes external pads (pads) including an address/DATA IN pad 122 for serial input of address and DATA bits, a DATA OUT pad 124 for serial DATA outputAnd a clock pad 126 for an externally provided clock signal.

The memory matrix 102 includes a plurality of memory cells organized into rows and columns. Each row (aka page) of memory is addressed by the X portion of the memory address and each column of memory within a page is addressed by the Y portion of the memory address. Each column of memory is made up of a set of bit lines 107, typically eight bits, including memory cells. The bit lines 107 of each column feed a Y-decoder 106.

For purposes of illustration only, it is assumed that the memory device 100 uses 16-bit addressing, and more specifically, that the X portion of the address occupies the upper 12 bits of A₁₅-A₄The Y part occupies the lower 4 bits A of the address word₃-A₀. Assume further that each memory cell is eight bits of data. Thus, the memory matrix 102 is a 4096 row by X16 column array, each column consisting of eight bit lines. It will be clear, however, that the invention can be easily scaled up or down to meet other address sizes and different sizes of X and Y parts of the address word. Data sizes other than eight bits may also be used.

The address/DATA IN pad 122 feeds into the address buffer circuit 112. The address buffer circuit provides the X and Y portions of the target address. The X portion of the address feeds an X decoder 104, which X decoder 104 is coupled to the memory matrix 102 and selects the designated memory page. The Y portion of the address feeds into Y decoder 106, and Y decoder 106 selects the designated memory location in the selected page. As will be shown below, Y-decoder 106 includes sense circuitry for sensing the bit lines of the accessed memory cells. Y decoder 106 also includes circuitry for outputting the bit of the target cell on DATA OUT pad 124.

The address/DATA IN pad 122 accepts an externally supplied serial bit stream and feeds it into the input buffer 108. As described below, the input buffer 108 includes circuitry for storing a bit stream to be written to a page or portion thereof. Control logic 110 provides control signals and timing signals for operating various components, including memory device 100.

The structure of the Y decoder 106 will now be discussed with reference to fig. 2. The Y-decoder of the present invention includes a decoder circuit 200 that receives as inputs the eight bit lines 107 from each column of the memory matrix 102. Remember, for purposes of illustration, the memory array is a 4096 row by 16 column array of eight-bit data. Then, the number of bit lines fed into decoder circuit 200 is 128(16 × 8). The decoder circuit 200 includes a set of eight output data lines D7-D0 for each byte (i.e., bytes B0-B15) in the array, which in turn provides a one-to-one mapping between the input bit lines and the output data lines.

At address control lines A2_ SEL and A1_ SEL and address line A₃-A₀Under control of (2), the steerable decoder circuit 200 functions as either a 16-4 decoder or a 16-2 decoder or a 16-1 decoder. If only A2 is powered on (assert), the decoder circuit will output a four-byte data line with the two high address bits equal to A₃、A₂. If only A1_ SEL is powered up, the decoder circuit will output a two-byte data line with the three high address bits equal to A₃、A₂、A₁. Finally, when either A2_ SEL or A1_ SEL is not powered up, the decoder circuit will generate the address bit A₃-A₀One byte of the address.

Turning now to fig. 3A, an exemplary implementation of decoder circuit 200 is shown. Each byte has an associated string of decoding transistors 402. By coupling its decoding transistor to the appropriate address line A₃-A₀And/or its complement (completion) occurs. Each byte also has an associated set of pass transistors 404 that gate their respective data lines D7-D0. The pass transistor 404 for a given byte is switched by the termination line 401 of the decode chain 402 for that byte. Thus, for example, if address line A₃-A₀Presenting "0110," the address will be decoded by the decode chain of byte 6, as shown by the bold line of FIG. 3A. Its respective pass transistor will be turned on via the termination line 401 and then pass its data line D7-D0 directly to the output of the decoder circuit 200.

As described above, A2_ SEL and A1_ SELThe control lines change the behavior of the decoder circuit 200. This is achieved by using OR gates 410, 412. The address lines A1 and A2_ SEL lines feed the OR gate 410. The address lines A0 and A2_ SEL and A1_ SEL lines feed the OR gate 412. Address bits a1 and a0 represent the low order bits of an address. When A2_ SEL is powered up, A is pushed₁And A₀All four of (a) in combination, thereby designating location a₃And A₂So that decoder 200 can output the following four bytes: a. the₃，A₂，0，0；A₃，A₂，0，1；A₃，A₂1, 0; and A₃，A₂1, 1, and A₁And A₀Is irrelevant. For example, FIG. 3B shows in bold lines when A₃＝0、A₂1 and the byte activated when a2_ SEL is powered up. Thus, powering up A2_ SEL causes decoder circuit 200 to function as a 16-4 decoder. Similarly, when A1_ SEL is powered up, A is pushed₀A combination of address lines. Then, specifying A3, a2, and a1 would yield the following two bytes: a. the₃，A₂，A₁0 and A₃，A₂，A₁,1. Thus, powering up A1_ SEL results in the 16-2 decoder operating.

A description will now be returned of the Y decoder 106 shown in fig. 2. The data lines of decoder circuit 200 are coupled to a four-wire bus 204, a two-wire bus 202, and a six-wire bus 206, respectively. The four-wire bus 204 is made up of wires 7-0, 7-1, 7-2, and 7-3. The two-wire bus 202 is made up of wires 6-1 and 6-0. The six-wire bus 206 is made up of wires 5, 4, 3, 2, 1, and 0.

Each line of the four-wire bus 204 couples together the most significant bit of each fourth byte, i.e., the D7 data line from decoder 200. In turn, line 7-0 couples together the D7 data lines of every fourth byte, beginning with byte B0. Line 7-1 couples together the D7 data lines of each fourth byte, starting with byte B1. Line 7-2 couples together the D7 data lines of each fourth byte, starting with byte B2. Line 7-3 couples together the D7 data lines of each fourth byte, starting with byte B3. In the example of an array consisting of 16 columns of bytes, the D7 bits of bytes B0, B4, B8, and B12 are coupled together by line 7-0; the D7 bits of bytes B1, B5, B9, and B13 are coupled together by line 7-1; the D7 bits of bytes B2, B6, B10, and B14 are coupled together by line 7-2; and the D7 bits of bytes B3, B7, B11, and B15 are coupled together by line 7-3.

Followed by a two-wire bus 202. Here, the data line for the second most significant bit (D6) of every other byte is coupled to either the 6-0 line or the 6-1 line. Specifically, the second-highest data line of every other byte, beginning with byte B0, is coupled to line 6-0, and the second-highest data line of every other byte, beginning with byte B1, is coupled to line 6-1. Thus, the even byte D6 lines, beginning with B0, are coupled to line 6-0. Similarly, the odd byte D6 line is coupled to line 6-1.

Finally, a six-wire bus 206 couples each of the remaining six data lines (D5-D0) of each byte together. Thus, as shown in FIG. 2, the D5 data line for each byte is coupled to line 5 of the six-wire bus, the D4 data line for each byte is coupled to line 4, the D3 data line for each byte is coupled to line 3, and so on.

Ignoring the time of flight through transistors 211-218, the Y-decoder 106 also includes sense circuits (sense amplifiers) 220-231, each having an input coupled to one of the lines in bus 202-206. Thus, lines 7-0 of the four-wire bus 204 are coupled to the inputs of the readout circuit 220 to read the data on lines 7-0. Similarly, line 7-1 of the four-wire bus 202 is coupled to the input of readout circuit 221 to read the data on line 7-1, and so on. Coupled in this manner, sense circuit 220-223 senses the most significant bit (D7) of every four adjacent bytes (e.g., bytes B0-B3, B4-B7, and so on). In the same manner, the next most significant bit (D6) of each two adjacent bytes (e.g., bytes B0 and B1, B2 and B3, B4 and B5, and so on) is read by the read circuits 224 and 225. Finally, the sensing circuit 226-231 senses the remaining bits (D5-D0) of each byte.

The output of each of the sensing circuits 220 and 223 feeds into a 4: 1 selector 232. The selector 232 is composed of address line A₁、A₀To control, the output of selector 232 feeds into position L7 of latch 240.The outputs of the sensing circuits 224 and 225 feed into a 2: 1 selector 234. Selector 234 is composed of address line A₀To control, the output of selector 234 feeds into position L6 of latch 240. Finally, the output of each of sensing circuits 226-231 feeds into the respective positions L5-L0 of latch 240. Latch control line 242 is driven by control logic 110 to provide a timed latch sequence for data latches from sense circuits 220 and 231. The output of latch 240 feeds into 8: 1 selector 236, which is controlled by selector control BIT _ SEL. The output of the selector 236 is coupled to the output pad 124.

Now returning to transistor 211-218. Transistors 211 and 214 couple the respective lines of the four-line bus 204 and the two-line bus 202 to their respective sensing circuits. Transistors 215 and 217 couple all four lines of the four-line bus 204 into the readout circuit 223. Similarly, transistor 218 couples two lines of the two-wire bus 202 into the readout circuit 225. Transistor 211 and 214 are turned on when the control signal SENSE-AHEAD is HI, and transistor 215 and 218 are turned on by inverter 219 when SENSE-AHEAD is LO.

According to the SPI interface, the address bits of the target memory location are shifted in serially, starting with the most significant bit, on each clock rising edge. After the last address bit is clocked in, the highest order bit of the target byte is latched on the falling edge of the clock immediately following the last address bit.

The operation of the present invention will now be described with reference to fig. 1, 2, 4A, 4B, 5 and 6A-6C. In FIG. 4A, each clock rising edge is identified relative to the address bits that are clocked in; for example, at clock A₁₅Move up into address bit A₁₅At clock A₁₄Move up into address bit A₁₄And so on.

Serially shifting in each address bit of the target until the high order bit A, which includes the X portion of the target address, has been shifted in₁₅-A₄And steps 502 and 503. At clock A₄At this point, the X portion of the target address is sent to X decoder 104. This is done by appropriately buffering the incoming address bits in address buffer circuit 112 and receiving bit A₁₅-A₄And sending the X part to the X decoder. Thus, the row (page) where the target byte is located is known. Next, the address bits of the Y portion of the target address are shifted in while the row is selected by the X decoder 104, steps 504A, 504B.

As shown by the dashed lines in FIG. 5, the page selection and receipt of the next address bit are concurrent operations to pass event E of steps 504A and 504B₀To identify. Receive address bits until A has been shifted in₂Bit, steps 504B, 505.

Clock A shown in FIG. 4A₂At, address bit A has been received₃And A₂Address buffer circuit 112 feeds these two address bits to Y-decoder 106. Control logic 110 powers on A2_ SEL to decoder circuit 200, resulting in a signal having the same A₃And A₂Four bytes of data lines in the selected row of address bits, STEP 506A. Assume that the target byte is located at byte position B5, namely A, of the selected row₃/A₂To "01", bytes B4 ("0100"), B5 ("0101"), B6 ("0110"), and B7 ("0111") are generated. Control logic 110 also holds the SENSE-AHEAD control line HI to couple and SENSE the four D7 data lines of the four selected bytes to and from the four SENSE circuits 220 and 223. At the same time, the next address bit is shifted in, step 506B. Event line E₁Indicating the concurrency of these two events.

Fig. 6A shows the active lines (shown in black) at this time, showing detection of the D7 data line. It can be seen that the detection of target byte B5 has begun before the Y address is completely received. In practice, by detecting the D7 line of these four bytes, based on address bit A₃And A₂To make a prediction of the target byte. Although not shown in black in FIG. 6A, the four D6 data lines of bytes B4-B7 feed the two D6 readout circuits 224, 225. At this time, however, the output is indeterminate because each readout circuit is reading the outputs of two data lines. Likewise, the outputs of D5-D0 are disjointed because each is receiving four data lines from the four selected bytes. Since the output of the sensing circuit 224 and 231 is indeterminateAt this point, nothing is done, so the sense circuits can be provided with enable circuits so that they can be turned off to save power.

At clock A₁Where receives A₁At address, control logic 110 powers A1_ SEL but not A2_ SEL to decoder circuit 200. This results in a high order address A₃-A₁The decoding of (c) results in two bytes sharing these high order address bits, namely "010" in the example where the target byte is byte B5. Thus, bytes B4 and B5 are generated. As a result, only two of the original four D7 data lines continue to be detected, STEP 508A. In addition, the two D6 data lines for the two selected bytes are now detected, STEP 508B. The prediction of the target byte continues. At the same time, move into A₀A bit. Event line E₂Indicating the concurrency of these events.

FIG. 6B shows the active lines (shown in black) at this time, illustrating the detection of the D7 and D6 data lines. As shown in FIG. 6A, each of sense circuits 226-231 receives data lines D5-D0 from bytes B4 and B5, and thus its output is indeterminate. Then, the readout circuit 226-231 remains in the off state. Furthermore, circuits 222 and 223 may be disabled to save power because the target byte is neither B6 nor B7.

At event E₃When at clock A₀During the period shift into A₀Bit-wise, control logic 110 will neither power up the A2_ SEL line nor the A1_ SEL line, so that decoder circuit 200 will produce a clock with A₃-A₀The addressed target byte, byte B5. This leaves only one of the original D7 data lines, step 510A. In addition, now, data line D7 has been detected and is ready to be shifted out of data line D7. At the same time, only one of the original two D6 data lines remains selected and will continue to be detected, step 510B. At this point, parallel detection of the data lines D5-D0 of the target byte begins, STEP 510C. Finally, selectors 232 and 234 select address bit A₁And A₀The determined sensing circuit output. The control logic 110 instructs the latch line 242 to latch D7, D6, and finally D5-D0 in sequence. FIG. 6C shows this timeThe effective line at the point. Note that sense circuits 220 and 222 and 224 can be turned off to conserve power, while sense circuits 226 and 231 remain active.

At clock A₀At the trailing falling edge, the data line D7 of the target byte is shifted out, and the bit is detected as early as clock A five half cycles ago₂The process is started. Similarly, as shown in FIG. 4A and by clock D6, data bit D6 is ready to be shifted out at the next falling edge. Note that the detection of data line D6 also begins as early as five half cycles ago. Similarly, the data line D5 is detected five half cycles before being shifted out. However, for data lines D4-D0, the detection of each successful data line will occur two half cycles longer than the previous data line. Thus, before output, D4 will be detected for seven half cycles and D0 will be detected for fifteen half cycles.

As described above, a device that is suitable for the prior art SPI must complete row selection and data detection within a half cycle after receiving the last address bit to start data output on the falling edge. The half period is t in FIG. 4A₁As shown. The predictive mode of operation of the present invention provides a double improvement: first, row selection is started as soon as the X part of the address is received; second, data detection of the target byte begins as soon as some Y address bits are clocked in. The timing sequence in FIG. 4A illustrates that the present invention can achieve a time (t) of at least five half cycles₂) To detect the data bits of the target byte. Thus, the clock used in the device of the present invention may run five times faster than the prior art device. In practice, this multiple is slightly higher than five because, in the present invention, the row selection occurs prior to data detection.

Operation of the device continues, taking into account the reading of subsequent bytes. Address buffer circuit 112 simply increments the current address. In the first case, when the next byte is on the same page, this simply involves incrementing the Y portion of the address, while the row remains unchanged. In the second case, when the next byte is on a new page, both the X and Y portions of the address change.

Referring to fig. 6D, consider the first case where the next byte is on the same page as the previous byte, namely byte B6. Control logic 110 now does not power up the SENSE-AHEAD line. This turns off transistors 211 and 214 and turns on transistors 215 and 218, which in turn feeds all of the D7 lines to sensing circuit 223 and all of the D6 lines to sensing circuit 225. Since the present invention is no longer in prediction mode at this point, there is no longer a need to detect more than one D7 or D6 line at a time, so the A1_ SEL and A2_ SEL are not powered up. Then, when byte B6 is selected by incrementing the address, only the eight data lines of B6 will feed into their respective sense circuits. A further feature of the selectors 232 and 234 is that the sensing circuits 223 and 225 are selected, respectively, in response to not powering on sense-AHEAD. Fig. 6D shows the effective line in this case.

Turning to FIGS. 4A-4B, it can be seen that after the D5 clock, at the time of latching the data bits D5-D0, the sense circuit becomes detectable for the next byte. Then, in case (scenario) a shown in fig. 4B, the address is incremented sometime after the clock D5. The data lines D7-D0 of the next byte are detected shortly thereafter. This provides the next byte with more than five half-cycles of sensing time, thus preparing to shift out the D7 bit of the next byte at clock D7 shown in fig. 4B.

Consider next the case where the next byte is on a new page. The SENSE-AHEAD line is again not powered up and the address is incremented. At this time, both the X and Y portions of the address change. Then, in case B of FIG. 4B, the address is incremented sometime after the D5 clock. However, a row selection must now be made to select the next page. Thus, the step of detecting the new first byte must be delayed for some time. As can be seen from the timing diagram, the detection step can be delayed until the rising edge after clock D2, which is approximately four half cycles. This ensures that five half cycles are available to detect the first byte of a new page. However, in the preferred embodiment, since row selection occurs almost immediately after the address increment, data detection for the next byte can begin immediately as shown in FIG. 4B. In both cases, the row select and snoop steps can take many clock cycles, since there is always a byte being clocked out that has been snooped and stored in latch 240.

In the embodiment of the Y decoder shown in fig. 2, twelve sensing circuits are used. Referring now to fig. 7A, a Y decoder 106 in accordance with the present invention is depicted that utilizes ten sensing circuits. It will become apparent that the sensing circuitry may be reduced by reusing some of the sensing circuitry during decoding of the target byte. The portion of the Y decoder shown in fig. 7A that is the same as that shown in fig. 2 retains its respective original reference numerals. The decoder circuit 200 shown in fig. 2 and 3 is used in the present embodiment.

The sense-ahead transistors 711 and 718 are temporarily omitted and the four-wire bus 204 and the two-wire bus 202 are coupled to the multiplexer 740 and 743. Each multiplexer is a one-out-of-two selector having a left input line labeled "1" input, a right input line labeled "0" input, and a one-bit multiplexer selector input 772. A "1" input is produced at its output when the multiplexer selector input is powered up (i.e., HI), and a "0" input is produced when the multiplexer selector is not powered up (i.e., LO). This applies to multiplexers 740-761 shown in FIG. 7A.

The D7 data line of the four-wire bus 204 is coupled to the "1" input of multiplexers 740-743 as shown. Specifically, line 7-0 is coupled to the "1" input of multiplexer 740, line 7-1 is coupled to the "1" input of multiplexer 741, line 7-2 is coupled to the "1" input of multiplexer 742, and line 7-3 is coupled to the "1" input of multiplexer 743.

The two-wire bus 202 with the D6 data line is coupled to the "0" input of multiplexer 740-743 in another manner. The 6-0 line is then coupled to the "0" input of multiplexers 740 and 742, and the 6-1 line is coupled to the "0" input of multiplexers 741 and 743. As described above with reference to FIG. 2, six-wire bus 206 is coupled to sense circuitry 226 and 231.

The outputs of each of multiplexers 740-743 are fed into sensing circuits 720-723, respectively. The output of each sensing circuit is fed to two multiplexers 750, 751 in turn. More specifically, sensing circuits 720 and 721 feed the "1" and "0" inputs, respectively, of multiplexer 750, while sensing circuits 722 and 723 feed the "1" and "0" inputs, respectively, of multiplexer 751.

Finally, the outputs of multiplexers 750 and 751 are cross-coupled to multiplexers 760 and 761. In particular, multiplexer 750 is coupled to the "1" input of multiplexer 760 and the "0" input of multiplexer 761, while multiplexer 751 is coupled to the "1" input of multiplexer 761 and the "0" input of multiplexer 760. The output of multiplexer 760 feeds the L7 latch of data latch 240 and the output of multiplexer 761 feeds the L6 data latch. The L5-L0 data latches are coupled to the outputs of sense circuits 226-231, respectively, as shown.

Multiplexer controller 710 provides control signals a-F that are coupled to multiplexer selector input 772 of multiplexers 740-761. The control signals A-F being address bits A₁-A₀Control lines A2_ SEL and A1_ SEL, and the SENSE-AHEAD line. Signals A-F are defined by the following logical formulas:

A＝A2_SEL^(～A2_SEL & ～A₁)^～SENSE-AHEAD，

B＝A2_SEL^(～A2_SEL & ～A₁)，

C＝A2_SEL^(～A2_SEL & A₁ & SENSE-AHEAD)，

D＝A2_SEL^(～A2_SEL & A₁)，

E＝～A₀^～SENSE-AHEAD，and

F＝～A₁^～SENSE-AHEAD，

here:

symbol ^ is a logical OR;

symbol & is a logical sum;

taking a complement from symbol to finger;

a2_ SEL at A₂True at clock; and

a2_ SEL at A₁And A₀True at the clock.

The sense push transistor 711-718 functions in the same manner as its counterpart shown in FIG. 2, i.e., controls the flow of the D7 line and the D6 line during the prediction mode operation, and then sequentially accesses the memory cells in series. In FIG. 7A, transistors 711 and 718 are arranged so that when SENSE-AHEAD is L0, all of the D7 lines feed the "1" input of multiplexer 740 and all of the D6 lines feed the "0" input of multiplexer 742.

In operation, the Y decoder 106 shown in FIG. 7A proceeds according to the timing diagrams shown in FIGS. 4A and 4B. For the following discussion, reference is made to FIGS. 7B-7E and assume that the target cell is byte B6 of the selected row (Y portion of the target address, "0110"). As described above, the decoder circuit 200 is at A₂Four candidate bytes, bytes B4-B7, are generated at the clock. The SENSE-AHEAD line is energized, SENSE advance transistors 711 and 713 are conductive, sending the four D7 data lines of bytes B4-B7 into the "1" input of each multiplexer 740 and 743. The A2_ SEL line is powered at this time, which causes multiplexer controller 710 to power up control signals A-D according to the logic formula above, thereby selecting the "1" input of multiplexer 740 and 743, and feeding the D7 line into sensing circuit 720 and 723. Fig. 7B shows the effective line.

In A₁At clock, decoder circuit 200 generates bytes B6 and B7; that is, these bytes share the same high order address bits: a. the₃-A₁,"011". At this time A2_ SEL is not powered up due to address bit A₁To "1", so multiplexer controller 710 energizes control signals C and D to select the "1" inputs of multiplexers 742 and 743. As a result, multiplexers 742 and 743 continue to feed the D7 lines of bytes B6 and B7 into sense circuits 722 and 723, while data line D7 of bytes B4 and B5 is disconnected from sense circuits 720 and 721. Although the idea of disconnecting the data line from its sensing circuit while detecting data seems to be contrary to the straight lineIt is felt that the D7 line of bytes B4 and B5 is no longer needed, because at this point neither byte B4 nor B5 is the target byte. These readout circuits can be reused. Since A and B from the multiplexer controller 710 are L0, the "0" inputs of multiplexers 740 and 741 are selected to feed the D6 data lines of bytes B6 and B7 into the readout circuits 720 and 721, which are then reused. Fig. 7C shows the active line.

In A₀At clock time, the address of the target byte is fully known, so decoder circuit 200 generates byte B6. Slave clock A₁The control signals a-D remain unchanged. In addition, multiplexer controller 710 powers up the E and F control lines. E control line is A₀Which selects one line in each pair of D6 and D7 by operating multiplexers 750 and 751. In this case, since A₀'0' so the "1" input of multiplexers 750, 751 are selected, resulting in the D6 and D7 lines from byte B6. Control line F operates multiplexers 760 and 761 to switch the D6 and D7 lines so that they feed into their appropriate positions in latch 240. F signal is based on A₁The address bit because it determines how multiplexers 740-743 are paired between the D6 and D7 data lines. FIG. 7D shows active lines, including D5-D0 data lines.

Finally, the SENSE-AHEAD line is not powered up for subsequently accessed memory cells. This couples (bond) the four lines 7-0 to 7-3 of the four-wire bus 204 together by turning on transistors 715 and 717 by turning off transistors 711 and 713, which feed the "1" input of the multiplexer 740. Similarly, two lines 6-0 and 6-1 are coupled together by transistor 718 and fed into the "0" input of multiplexer 742. Multiplexer controller 710 selects the "1" inputs of multiplexers 740, 750, and 760 to feed the D7 line to sensing circuit 720 within latch L7. Similarly, multiplexer controller 710 selects the "0" input of multiplexer 742 to feed the D6 line into sensing circuit 722, from where the "1" inputs of multiplexers 751 and 761 are selected to send the D6 line into the L6 latch. Fig. 7E shows the data flow of the subsequent byte, byte B7.

The embodiments of the invention shown in fig. 2 and 7A use twelve and ten sensing circuits, respectively. Selectively switching the data lines to these sense circuits using multiplexing circuits results in a reduction of the sense circuits achieved by the embodiment of fig. 7A when sense circuits are available to clock subsequent bits of the address into the memory device.

Fig. 8 shows an embodiment that extends the principle of reusing the readout circuit to another step. Elements previously introduced and discussed in fig. 2 and 7A retain their reference numbers. FIG. 8 introduces an additional set of multiplexers 850 and 853. These multiplexers have three inputs: a "2" input, a "1" input, and a "0" input. Each multiplexer 850-853 also has a two-bit selector input 874, where a "10" on selector input 874 produces a "2" input, a "01" on selector input 874 produces a "1" input, and a "00" on selector input 874 produces a "0" input.

The "2" inputs of multiplexers 850-853 are coupled to the outputs of each of multiplexers 740-743, respectively. Thus, the "2" input receives either the D7 data line or the D6 data line depending on the selection made in multiplexers 740-743. The "1" and "0" inputs of multiplexers 850 and 853 are coupled to lines 5 and 4, respectively, of bus 206. The outputs of multiplexers 850 and 853 feed the inputs of sensing circuits 820 and 823. The presence of multiplexers 740-743 and 850-853 allows the data lines D7, D6, D5 and D4 of the target byte to be fed into the sense circuit, as described below, while still providing the predictive mode of operation of the present invention.

The output of the sensing circuit feeds the inputs M-P of the switching circuit 860. The outputs Q-T of switch 860 feed the D7-D4 latches of data latch 240, respectively. The switching circuit 860 allows any input M-P to be switched to any output Q-T under the control of an eight bit control line 860. Fig. 9 shows an implementation of this switch.

Multiplexer controller 810 provides control signals a-I that are coupled to multiplexer selector inputs 872, 874, and 876. Control signalNumber is address bit A₁-A₀Control lines A2_ SEL and A1_ SEL, and the SENSE-AHEAD line. Signals A-I are defined by the following requirements for a non-predictive mode of operation, when SENSE-AHEAD is not powered up: the pass transistors 711 and 713 are turned off and the pass transistors 715 and 717 are turned on, which in turn couples all of the D7 data lines together and feeds them into the input "1" of the multiplexer 740. Likewise, pass transistor 714 is off and pass transistor 718 is on, all of the D6 data lines are tied together and feed them to the "0" input of multiplexer 742. Thus, in the non-predictive mode of operation, control signals A-I are energized so that multiplexer 740 generates its "1" input, multiplexer 850 generates its "2" input, and switch 860 routes its M input to its Q output, resulting in the transfer of data line D7 through sensing circuit 820 to the D7 data latch. Similarly, multiplexer 742 generates its "0" input, multiplexer 852 generates its "2" input, and switch 860 routes its O input to its R output, resulting in the transmission of data line D6 through sense circuit 822 to the D6 data latch. At the same time, line 5 of bus 206 corresponding to the D5 data line is routed through input "1" of multiplexer 851 and this line 5 is coupled from input N to output S of switch 860, locking the D5 data line into the D5 latch through readout circuit 821. Finally, line 4 of bus 206 corresponding to the D4 data line is routed through the "0" input of the 853 multiplexer, and this line 4 is coupled from input P to output T of switch 860 and then through sense circuit 823 into data latch D4.

The control signals A-I of the multiplexer controller 810 (see timing diagram of FIG. 4A) are further defined by the following requirements during the prediction mode of operation, when the SENSE-AHEAD is powered up: at the A2 clock, when four possible bytes are selected, each of the multiplexers 740- ­ 743 generates its "1" input, each of the multiplexers 850- ­ 853 generates its "2" input, and the four D7 data lines are then presented on their respective sense circuits 820- ­ 823 at the beginning of data detection.

In A₁At the clock and according to A₁The address bit, one pair of multiplexers (multiplexers 740 and 741 or multiplexers 742 and 743) will continue to produce a "1" input, then feed two of the D7 lines to the next stage of multiplexers. The other pair is switched to produce a "0" input, now with two possible D6 data lines. Multiplexers 850 and 853 continue to generate the "2" inputs. The effect is that two of the readout circuits will continue to detect the D7 data line, and the D7 line will be disconnected from the other two readout circuits to begin detecting the D6 data line.

In A₀At clock time, when all address bits are input, decoder circuit 200 will know the target byte and select that byte. Two of the four multiplexers 850-853 will be switched to the lines 5 and 4 that generate the bus 206 and detection of the D5 and D4 data lines will begin. At the same time, the sensing circuits 824-827 will also start detecting D3-D0. At the same time, the detection of the D7 data line for the target byte will be complete and ready for output, and the detection of the D6 data line will continue. Finally, the switches 860 are operated by control lines 876 to provide the necessary cross-switching of the inputs M-P to the outputs Q-R to ensure that the data lines D7-D4 are latched into their respective data latches.

The embodiments shown in fig. 2A, 7A and 8 show that by using multiplexing circuitry as appropriate, the need for readout circuitry can be reduced. Other designs are possible, each with different complexity and silicon asset requirements. The embodiment of fig. 2A is straightforward, but requires twelve sensing circuits. The embodiment of fig. 8 uses eight sensing circuits, but requires additional multiplexers and a more complex controller to operate the multiplexers. Although the disclosed embodiment is in A₂The clock provides predictive detection when operation can be started at an earlier clock to achieve greater speed increases. The particular implementation will depend on a tradeoff between these factors, including desired device speed, circuit complexity, memory size, chip size, and power requirements.

The disclosed embodiments of the present invention enable clocking the last bit of a target memory cellThe time between the time of the input and the time of clocking out the first bit of the target is reduced by a factor of five, allowing a five-fold increase in clock speed. However, a seven-fold reduction in time can be achieved using the principles disclosed herein. In the above discussion, the Y portion of the address is made up of four bits, and the predictive mode of operation of the present invention begins after the second bit of the Y portion is received. Referring to FIG. 4A, if the prediction mode starts after the first bit is received, the detection of the D7 data line will be at A₃Start on the clock, reducing the time by a factor of seven. In addition to the three decoding modes described, the necessary changes to the logic include altering decoder circuit 200 to provide 16-8 eight decodes; the reason for this is that in A₃There will be eight candidate bytes at the clock. Furthermore, additional sense amplifiers would be required. According to the architecture of FIG. 2, eight sense amps would be required to detect the eight candidate D7 data lines, four sense amps would be required to detect the four candidate D6 data lines, two sense amps would be required to detect the two possible D5 data lines, and five sense amps would be required to detect the D4-D0 data line of the target byte; a total of nineteen sense amplifiers are required. According to the architectures of FIGS. 7A and 8, the number of sense amplifiers may be reduced by using additional multiplexers, thereby reusing sense amplifiers available as the number of candidate targets decreases when additional address bits of the Y portion of the target address are available. On the other hand, the need for so many sense amplifiers may be an obstacle to this scheme. On the other hand, the reduction in time may allow the use of slower but simpler (and thus smaller) sense amplifiers, which may offset the size requirements caused by the increased number of sense amplifiers.

Alternatively, the prediction mode of operation may be delayed until all but the last bit of the target address has been clocked in. Referring next to FIG. 4A, when bit A₃-A₁When known, up to A₁The clock time is not until the D7 data line is detected. There are only two candidate bytes, so only two candidate D7 data lines are detected. In this configuration, nine sense amplifiers are required to achieve the targeting of the receive target address and the output targetThe time of a byte of a memory cell is reduced by three times, thus converting to a clock increase by three times.

In the disclosed embodiment, only one bit is detected early before each address bit is received. Then, referring to FIGS. 2 and 4A, at A₂The predictive sensing of the four candidate D7 data lines begins when address bit A2 is clocked. Predictive detection of two candidate D6 data lines begins when the next address bit, A3, is received. However, in another embodiment of the present invention, more than one data line per candidate byte may be detected early without departing from the scope and spirit of the present invention. For example, in A₂At the clock, four candidate bytes of the D7 and D6 data lines may be detected.

Generally, the preferred embodiment of the present invention is a prediction operation on the least significant bits of the target address (i.e., the Y portion of the address). However, the present invention is readily adapted to operate on the most significant portion of an address without departing from the principles of operation of the present invention and without sacrificing the benefits attainable by the present invention.

The preferred embodiment of the present invention operates on the most significant bits of the candidate byte, as required by the SPI protocol. Then, the D7 data line is detected before the D6 data line is detected, and so on. This causes the highest bit to be shifted out first, as per the SPI protocol. Alternatively, for protocols other than SPI, the invention may be implemented to operate on the least significant bit first, thereby outputting the least significant bit first. Then, the candidate byte's D0 data line may be detected first, followed by the D1 data line, and so on. This scheme is in keeping with the principles of operation of the present invention and enjoys the same benefits achieved by the embodiments of the invention disclosed above. Referring to fig. 2 and 3A, logic comprising decoder circuit 200 may be adapted to couple the bit zero line to the D7 data line, the bit one line to the D6 data line, the bit two line to the D5 data line, and so on, to enable detection of the low order bits of a candidate byte.

Claims (41)

1. In a serial memory device having a plurality of memory cells, the contents of each memory cell being comprised of a plurality of data bits, a method of reading the contents of a target memory cell comprising:

receiving a partial address of a target memory location;

detecting less than all of the data bits for each memory cell whose address includes the portion of the address;

receiving the remaining address bits, thereby making the target memory location known;

detecting the remaining data bits of the target memory cell while reading the first data bit; and

after the remaining data bits are detected, the remaining data bits are read.

2. The method of claim 1 wherein the step of detecting less than all of the data bits is a step of detecting only the first data bit, thereby initiating detection of the first bit of the target memory cell before receiving its address.

3. The method of claim 1, wherein the step of receiving the partial address includes receiving a first N number of address bits of the target memory location, N being less than a number of address bits comprising the address.

4. The method of claim 3 wherein the first N address bits are the N highest address bits.

5. The method of claim 1 wherein the step of receiving a partial address is the step of receiving all but the last bit of the address and the step of receiving the remaining address bits is the step of receiving the last bit of the address.

6. The method of claim 1, wherein the step of detecting less than all of the data bits is a step of detecting only a first data bit, and the step of receiving remaining address bits comprises:

receiving a next address bit of the target memory cell to generate a second partial address; and

for each memory cell whose address includes the second partial address, the second data bit is detected, thereby beginning detection of the second data bit of the target memory cell before its address is known.

7. The method of claim 6, wherein the step of receiving the partial address includes receiving the first N address bits of the address of the target memory location, such that the second partial address represents the first N +1 bits of the address, N +1 being less than the number of address bits comprising the address.

8. The method of claim 7, wherein the first and second data bits are first and second most significant data bits, respectively.

9. The method of claim 7, wherein the first N address bits are the highest address bits.

10. The method of claim 1, wherein the step of detecting less than all of the data bits is a step of detecting only a first data bit, and the step of receiving remaining address bits comprises:

receiving a last second address bit of the target memory cell to generate a second partial address; and

detecting a second data bit for each memory cell having an address comprising a second portion of the address, thereby beginning detection of the second data bit for the target memory cell before the address is known;

receiving a last address bit of a target memory cell to generate an entire address of the target memory cell; and

remaining data bits of the target memory cell are detected, wherein the detection of the first and second data bits is either in progress or completed.

11. The method of claim 10, wherein the first and second data bits are highest and next highest data bits, respectively.

12. In a serial memory device having an array of memory cells arranged in rows and columns, each memory cell having B bit lines and a unique address, each address being represented by a bits, a method of sensing the contents of a target memory cell comprising:

(i) serially receiving N address bits of a target memory cell, wherein N is less than A;

(ii) selecting a row of memory cells in the array according to the N address bits;

(iii) serially receiving I additional address bits and selecting bit lines corresponding to a first plurality of memory cells in the selected row, each such memory cell having an address with (N + I) bits that are the same as the (N + I) received address bits, (N + I) < A;

(iv) for each memory cell in the first plurality of memory cells, sensing a first subset of its bit lines;

(v) receiving a new address bit while detecting a first subset of bit lines of each of the first plurality of memory cells, thereby reducing the number of the first plurality of memory cells by half, resulting in a second plurality of memory cells; and

(vi) for each memory cell in the second plurality of memory cells, a second subset of its bit lines is detected.

13. The method of claim 12, wherein the detecting of step (iv) comprises detecting each bit line in the first subset by coupling them to a sensing circuit; step (v) comprises disconnecting half of the first subset of bit lines from the sense circuitry in response to receiving the next address bit, thereby making half of the sense circuitry available for use; and the detecting of step (vi) comprises detecting some of the bit lines in the second subset by coupling them to available sensing circuitry.

14. The method of claim 12, wherein the first subset of bit lines for each of the first plurality of memory locations consists only of the most significant bits of the memory location.

15. The method of claim 14, wherein the second subset of bit lines for each of the second plurality of memory cells consists only of the first and second most significant bits of the memory cell.

16. The method of claim 12 wherein the sensing step of step (iv) includes, for each memory cell in the first plurality, coupling a first one of its bit lines to one of F sense circuits, F being the number of memory cells in the first plurality.

17. The method of claim 16 wherein the sensing step of step (vi) includes selectively disconnecting half of the first bit lines from the sensing circuitry and, for each memory cell in the second plurality, coupling a second of its locations to the disconnected sensing circuitry.

18. The method of claim 17 wherein the first and second bit lines of each memory location are the two most significant bits.

19. A method of reading memory cells in a serial memory device, comprising the steps of:

receiving a partial address of a target memory location;

generating data bits of a first memory cell on the data lines whose address includes the partial address;

coupling a first data line of a first memory cell to a first set of sense amplifiers;

receiving a next address bit to generate a second partial address, such that only half of the addresses of the first memory cells include the second partial address, thereby eliminating the other half of the first memory cells; and

the second data lines of the remaining half of the first memory cells are coupled to a second set of sense amplifiers.

20. The method of claim 19, further comprising receiving the remaining address bits to generate a complete address and then knowing the target memory location; the data lines corresponding to the remaining data bits of the target memory cell are coupled to the third set of sense amplifiers while the first data line of the target memory cell is output.

21. The method of claim 19, wherein the first set of sense amplifiers comprises a first plurality of sense amplifiers and the second set of sense amplifiers comprises a second plurality of sense amplifiers.

22. The method of claim 19, wherein the second set of sense amplifiers is included in the first set of sense amplifiers, and wherein the step of coupling the second data lines of the remaining half of the first memory cells includes disconnecting the first data lines of the eliminated half of the first memory cells from their associated sense amplifiers and coupling the second data lines to the disconnected sense amplifiers.

23. The method of claim 22, further comprising receiving the remaining address bits to generate a complete address and then knowing the target memory location; the remaining data bits of the target memory cell are detected, and at the same time, a first data line of the target memory cell is output.

24. The method of claim 23, wherein the step of receiving the remaining data bits eliminates at least half of the remaining half of the first memory cells; the step of sensing remaining data bits of the target memory cell includes disconnecting the eliminated half of the first data lines of the remaining half of the first memory cells from their associated sense amplifiers, and coupling at least one of the remaining data bits to one of the disconnected sense amplifiers.

25. A serial memory device, comprising:

a memory array arranged in a plurality of rows, each row having a plurality of memory cells, each memory cell having a plurality of data bits, the memory array having bit lines for outputting the data bits of each memory cell of a selected row;

a decoder circuit coupled to receive bit lines from the memory array, the decoder circuit including data lines and a gating circuit, the gating circuit selectively coupling the bit lines of each memory cell of a selected row to the data lines in a one-to-one correspondence, the decoder circuit further including address lines operatively coupled to the gating circuit to couple selected ones of the bit lines to their respective data lines;

a first plurality of N sense amplifiers having inputs in electrical communication with the first data line corresponding to each Nth memory cell of the selected row; and

at least one sense amplifier having an input in electrical communication with one of the data lines of each memory cell in the selected row.

26. The serial memory device of claim 25 wherein the decoder circuit further comprises control lines operatively coupled to the gating circuit to synchronously couple the bit lines of the N selected memory cells to their respective data lines.

27. The serial memory device of claim 25 further comprising a second plurality of M sense amplifiers having inputs coupled to the second data line corresponding to each mth memory cell of the selected row, M being equal to N/2.

28. The serial memory device of claim 27 wherein each of the first data lines is the most significant bit and each of the second data lines is the second most significant bit.

29. The serial memory device of claim 27 further comprising an output buffer; a first selector circuit having a single output and having an input coupled to the outputs of the N sense amplifiers; a second selector circuit having a single output and having inputs coupled to the outputs of the M sense amplifiers, the outputs of the first and second selector circuits being coupled to the output buffer.

30. The serial memory device of claim 25 further comprising a control circuit having N independently powered enable lines, each of the enable lines coupled to one of the first sense amplifiers, each sense amplifier having circuitry for turning the sense amplifier on and off in response to a control signal being powered on its associated enable line; so that some sense amplifiers can be turned off while others are left on.

31. The serial memory device of claim 25 further comprising a first sense-advance circuit having N inputs coupled to the first data line and having N outputs, each output coupled to one of the first sense amplifiers, the first sense-advance circuit having a first selectable configuration in which each of the N inputs is in electrical communication with a respective output, the first sense-advance circuit having a second selectable configuration in which each of the N inputs is in electrical communication with only one of the N outputs.

32. The serial memory device of claim 31, further comprising:

a second plurality of M sense amplifiers, each sense amplifier having one input coupled to the second data line of each Mth memory cell of the selected row, M being equal to N/2; and

a second sense-advance circuit having M inputs and M corresponding outputs, each input coupled to one of the second data lines and each output coupled to one of the second sense amplifiers;

a second detection and propulsion circuit having a first selectable configuration in which each of its inputs is electrically coupled to its respective output, and a second selectable configuration in which all of its inputs are electrically coupled to only one of the outputs.

33. A serial memory device, comprising:

a memory array arranged in a plurality of rows, each row having a plurality of memory cells, each memory cell having a plurality of data bits, the memory array having bit lines for outputting the data bits of each memory cell of a selected row;

a decoder circuit coupled to receive bit lines from the memory array, the decoder circuit including data lines and a gating circuit, the gating circuit selectively coupling the bit lines of each memory cell of a selected row to the data lines in a one-to-one correspondence, the decoder circuit further including address lines operatively coupled to the gating circuit to couple selected ones of the bit lines to their respective data lines;

a plurality of N first buses, each bus coupled to the first data line of each Nth memory cell in the selected row;

a plurality of M second buses, each bus coupled to the second data line of each Mth memory cell in the selected row, M being equal to N/2;

a plurality of N sense amplifiers, each having an input and an output; and

a multiplexing circuit having input lines and output lines, the input lines being coupled to the first bus and the second bus, the output lines being coupled to the sense amplifiers, the multiplexing circuit further having control inputs for coupling selected ones of the first and second buses to the sense amplifiers;

so that N sense amplifiers share N and M buses.

34. The serial memory device of claim 33 wherein the multiplexing circuit comprises N2-1 multiplexers; each first data line is coupled to a first input of one of the 2-1 multiplexers; each second data line is coupled to the second inputs of two of the 2-1 multiplexers.

35. The serial memory device of claim 33 further comprising a second multiplexing circuit and a data latch, the second multiplexing circuit having an input coupled to the output of the sense amplifier and having an output coupled to the data latch.

36. The serial memory device of claim 33 further comprising a control circuit having N independently energizable enable lines, each of the enable lines coupled to one of the sense amplifiers, each sense amplifier having circuitry for turning the sense amplifier on and off in response to a control signal energized on its associated enable line; so that some sense amplifiers can be turned off while others are left on.

37. The serial memory device of claim 33 further comprising a third plurality of buses, each bus coupled to one of the remaining data lines of each memory cell in the selected row; the multiplexing circuit also has an input coupled to at least one of the third buses; so that the N sense amplifiers share the N first buses, the M second buses, and the at least one third bus.

38. The serial memory device of claim 37 wherein the multiplexing circuit includes first multiplexers and second multiplexers, each of the first multiplexers receiving as inputs one of the N buses and one of the M buses, each of the second multiplexers having inputs coupled to an output of one of the first multiplexers and at least one of the third buses; the second multiplexer has an output coupled to the sense amplifier.

39. The serial memory device of claim 38 further comprising a third multiplexer and a data latch, the third multiplexer having an input coupled to the output of the sense amplifier and having an output coupled to the data latch.

40. In a serial memory device having a plurality of memory cells, the contents of each memory cell being comprised of a plurality of data bits, a method of reading the contents of a target memory cell comprising:

receiving a first address of a target storage unit, wherein the first address is a partial address of the target storage unit;

detecting less than all of the data bits for each memory cell whose address includes the first address;

during the detecting step, (i) receiving one or more additional address bits to generate a second address, thereby reducing the number of memory cells containing the first address, and (ii) detecting one or more additional data bits per memory cell that is reduced; and

the detected data bits are read out.

41. The method of claim 40, wherein the step of receiving one or more additional address bits is a step of receiving remaining one or more address bits of the target memory cell, and the step of detecting one or more additional data bits is a step of detecting remaining one or more data bits of the target memory cell.