HK1034397B - An apparatus in a system for processing a received datastream and a method for processing the same - Google Patents

Description

Device and processing method in a system for processing a received data stream

Technical Field

The present invention relates to a digital symbol timing recovery network.

Background

The recovery of data from modulated signals carrying digital information in the form of symbols requires three functions at the receiver end: timing recovery for symbol synchronization, carrier recovery (frequency demodulation to baseband), and channel equalization. Timing recovery is a process by which the receiver's clock (time base) is synchronized with the transmitter clock. This allows the received signal to be sampled at an optimum point in time, thereby reducing slicing errors associated with the decision-directed process of the received symbol values. Carrier recovery is a process by which a received RF (radio frequency) signal, after being down-converted to a lower intermediate frequency band (e.g., near baseband), is frequency shifted to baseband so that modulated baseband information can be recovered. Adaptive channel equalization is a process by which the effects of condition changes and interference in a signal transmission channel can be compensated for. This process typically employs filters to remove amplitude and phase distortions due to the time-varying nature of the frequency of the transmission channel.

Disclosure of Invention

In accordance with the principles of the present invention, symbol timing recovery is enhanced by the cooperation of a symbol timing recovery network by a segment sync detector responsive to an output signal from a local channel equalizer.

The present invention provides apparatus in a system for processing a received data stream comprising an image representative signal, the apparatus comprising:

a symbol timing recovery network responsive to said received signal prior to equalization and responsive to a recovered synchronization component of said received signal to produce a symbol sampled signal;

a channel equalizer responsive to said received signal for producing an equalized signal; and

a synchronization recovery network responsive to said equalized signal for producing said recovered synchronization component; wherein

Said received signal comprising a vestigial sideband modulated signal comprising a high definition video data frame format represented by a symbol constellation, said data having a data frame format comprised of successive data frames including a field sync component preceding a plurality of data segments having associated segment sync components; and

the recovered synchronization component is the segment synchronization component.

The present invention also provides a method of processing a received data stream comprising an image representative signal, the method comprising the steps of:

performing channel equalization on the received signal;

recovering a synchronization component of said received signal in response to an equalized signal produced by said equalizing step; and

generating a symbol sampled signal in response to the pre-equalized signal generated prior to said equalizing step and in response to a recovered synchronization component generated by said synchronization recovering step; wherein

Said received signal comprising a vestigial sideband modulated signal comprising a high definition video data frame format represented by a symbol constellation, said data having a data frame format comprised of successive data frames including a field sync component preceding a plurality of data segments having associated segment sync components; and

the recovered synchronization component corresponds to the segment synchronization component.

Drawings

Fig. 1 is a block diagram of a portion of a High Definition Television (HDTV) receiver incorporating a timing recovery apparatus according to the principles of the present invention.

Fig. 2 shows a data frame format of a VSB-modulated signal according to the Grand Alliance (Grand Alliance) HDTV terrestrial broadcasting system in the united states.

Fig. 3 shows in detail the segment sync detector and symbol clock timing recovery network of fig. 1.

Fig. 4 shows signal waveforms useful for understanding the operation of fig. 3.

Detailed Description

In fig. 1, an analog input HDTV signal for terrestrial broadcast is processed by an input network 14 including Radio Frequency (RF) tuning circuitry and an intermediate frequency processor 16 including a dual conversion tuner for producing an Intermediate Frequency (IF) output signal, and a suitable Automatic Gain Control (AGC) control circuit. In this embodiment, the received signal is one proposed by the great alliance and adopted in the united states. A carrier suppressed multi-level 8-VSB modulated signal. Such a VSB signal is represented by a one-dimensional data symbol constellation in which only one coordinate contains the quantized data to be recovered by the receiver. Signals timed by the functional blocks shown are not shown to simplify the drawing.

As described in the large alliance HDTV system specification (1994, 14/4), VSB transmission systems employ a data frame format as shown in fig. 2 to carry data. A small pilot signal at the suppressed carrier frequency is added to the transmitted signal to help achieve carrier locking at the VSB receiver. Referring to fig. 2, each data frame includes two fields, wherein each field includes 313 segments of 832 multilevel symbols. The first segment of each field is called a field sync segment and the remaining 312 segments are called data segments. The data segments typically comprise MPEG compatible data packets. Each data segment contains four symbol segment sync components followed by 828 data symbols. Each field component comprises a four symbol segment sync component followed by a field sync component comprising a predetermined 511 symbol pseudo-random number (PN) and three predetermined 63 symbol PN sequences, said 511 symbol pseudo-random number sequences being inverted in successive fields. A VSB mode control signal (defining VSB symbol constellation size) immediately following the last 63PN sequence, this control signal immediately following the 96 reserved symbols and the 12 symbols copied by the previous field.

Continuing with fig. 1, the passband IF output signal from unit 16 is converted to a digital symbol data stream by an analog to digital converter 19. The output digital data stream from ADC19 is demodulated to baseband by a demodulator/carrier recovery network 22. This is done by a phase locked loop in response to a small reference pilot carrier in the received VSB data stream. Demodulator/carrier recovery network 22 produces an output I-phase demodulated symbol data stream. Demodulator/carrier recovery network 22 may include a demodulator of the type described in the large alliance system specifications or of the type described in co-pending U.S. patent application serial No.90/140257(t.j.wang filed 26/8/1998).

Associated with the ADC19 is a segment synchronization and symbol clock recovery network 24 in accordance with the present invention. The network recovers the repetitive data segment sync component of each data frame from the received random data. This segment sync is used to regenerate a phase-appropriate clock, e.g., 10.76M symbols/sec, which is used to control the sampling of the data stream symbols by the analog/digital converter 19. As discussed above in connection with fig. 3 and 4, the segment sync and symbol clock recovery network 24 uses a four-symbol correlation reference pattern and associated symbol data correlator to detect the segment sync.

The field sync detector 28 detects the data field sync component by comparing each received data segment to an ideal reference signal stored in the receiver's memory. In addition to the field sync, the field sync signal also provides a training signal for the adaptive channel equalizer 34. The NTSC co-channel interlace detector 30 performs NTSC co-channel interference detection and rejection. The signal is then adaptively equalized by an adaptive equalizer 34, which operates in a closed and subsequent decision directed mode. The equalizer 34 may be of the type described in the large alliance HDTV system specifications and in "VSB Modem Subsystem Design for grand alliance Digital Television Receivers," filed by w.bretal et al (IEEE transactions Consumer Electronics, 8. 1995). Equalizer 34 may also be of the type described in co-pending U.S. patent application No.09/102885 to Shiue et al. The output of the equalizer 34 advantageously facilitates operation of the segment synchronization and symbol clock recovery network 24 as will be described.

The equalizer 34 corrects for channel distortion, but the corresponding noise randomly rotates around the symbol constellation. Phase tracking network 36 removes residual phase and gain noise in the output signal from equalizer 34, including phase noise not removed by the preceding carrier recovery network in response to the pilot signal. The phase corrected signal is then trellis decoded (trellis decoded) by unit 40, deinterleaved by unit 42, Reed-solomon error corrected by unit 44, and dequantized by unit 46 using well-known procedures. The decoded data stream is then subjected to audio, video and display processing by unit 50. The functional blocks of fig. 1, in addition to a timing recovery network modified in accordance with the principles of the present invention, may use circuitry of the type described in the large alliance HDTV system specification (1994, 4/4) and in the aforementioned Bretl et al paper.

The demodulation process in demodulator/carrier recovery network 22 is implemented by an Automatic Phase Control (APC) loop to achieve carrier recovery using known techniques. The phase locked loop uses a pilot component as a reference for initial acquisition and a common phase detector for phase acquisition. The pilot signal is embedded in the received data stream, which contains a pattern that exhibits a similar random noise. The random data is essentially ignored by the filtering process of the demodulator APC loop. The 10.76M symbols/sec input signal to ADC19 is a near baseband signal having a VSB spectral center at 5.38MHz and a pilot component at 2.69 MHz. In the demodulated data stream from demodulator/carrier recovery network 22, the pilot component is down-shifted to DC. The demodulated data stream is provided to a segment sync and symbol clock recovery network 24, as shown in detail in fig. 3. When repetitive data segment sync pulses are recovered from the random data pattern of the received data stream, the segment sync is used to achieve proper symbol timing by regenerating a properly phased symbol rate sampling clock to control the sampling operation of the analog-to-digital converter 19.

Fig. 4 shows a portion of an eight level (-7 to +7) data segment with an associated data segment for an 8-VSB modulation constellation broadcast signal in accordance with the large alliance HDTV specification. The segment sync is generated at the beginning of each data segment and occupies 4 symbol intervals. The segment sync is defined by a pattern 1-1-11 corresponding to the amplitude level of the segment sync pulses from +5 to-5.

The four symbol segment sync is generated every 832 symbols but is difficult to locate in the demodulated VSB digital data stream because the data has a random-like, noisy characteristic. To recover the segment sync in this case, the demodulated I-channel data stream is provided to the input of a data correlator and a reference pattern having 1-1-11 characteristics is provided to the input of the correlator for comparison with the demodulated data. The correlator produces an enhancement of the consistency of every 832 symbols with the reference pattern. The enhanced data events are accumulated by an accumulator associated with the correlator. The inserted random (unenhanced) correlations disappear with respect to the enhanced correlation segment sync component. This process is well known. Networks for recovering segment synchronization in this manner are well known, for example, from the large alliance HDTV specification and from the aforementioned Bretl et al paper.

Fig. 3 shows the segment synchronization and symbol clock recovery network 24 in detail. The output data stream from demodulator 22 is provided to a signal input of phase detector 310 and to switch 318. Switch 318 may be programmed to pass either the output signal from demodulator 22 or the output signal from equalizer 34 on the segment sync recovery path to a 832 symbol correlator 320. The other signal input of the phase detector 310 receives an output signal from a segment sync generator 328 in the segment sync recovery path that includes a correlator 324. The correlation reference pattern generator 330 is coupled to the correlator 320, and the segment integrator and accumulator 324. Reference pattern generator 330 provides a 1-1-11 segment sync reference pattern (see fig. 4).

The output from the correlator 320 is integrated and accumulated by unit 324. Segment sync generator 328 includes a comparator having a predetermined threshold and is responsive to the output of unit 324 by generating a segment sync component at an appropriate time in the data stream corresponding to the segment sync interval. This occurs when the accumulation of enhanced data events (generation of segment syncs) exceeds a predetermined threshold. The generation of the segment sync component marks that the signal has been captured. The event is indicated by data stored in a register of the generator 328. This register is monitored by the controller 344 to determine if signal capture has occurred, as described above.

The phase detector 310 performs a timing recovery function. Phase detector 310 compares the phase of the segment sync generated by element 328 with the phase of the segment sync present in the demodulated data stream from demodulator/carrier recovery network 22 and generates an output error signal indicative of the symbol timing error. The error signal is low pass filtered by an Automatic Phase Control (APC) filter 334 to produce a signal suitable for controlling a 10.76MHz voltage controlled crystal oscillator (VCXO) 336. Oscillator 336 provides a 10.76MHz symbol sampling clock to ADC 19. The sampling clock exhibits correct timing when the phase error signal is substantially zero by the operation of the APC, indicating that the symbol timing (clock) recovery has been completed. The segment sync generated by unit 328 is also provided to other decoding circuitry and Automatic Gain Control (AGC) circuitry (not shown). The output of filter 334 is provided to the input of detector 340. The output 331 of the sync generator 328, which indicates whether signal lock (capture) has been completed, is provided to one input of the microcontroller 344.

Switch 318 is optional but may be programmed to pass the output of demodulator 22 or the output of equalizer 34 to correlator 320 on the synchronization recovery path. In the illustrated preferred embodiment, the switch 318 is programmed to continuously connect the output of the adaptive equalizer 34 to the correlator 320. In another system having different operating requirements, for example, the switch 318 may be programmed to initially connect the output of the demodulator 322 to the correlator 320 when the system is first powered up or reset, and then connect the output of the equalizer 34 to the correlator 320 after a predetermined event interval.

In the preferred embodiment of fig. 3, initially, the VCO336 is set to operate at a predetermined stable frequency when the system is first powered up or after the system is reset. In this example, the frequency corresponds to an extreme (maximum or minimum) frequency value in a predetermined frequency range. This initial frequency deviates significantly from the desired symbol timing frequency or a multiple thereof, since it has been observed that equalizer 34 can converge faster in the blind mode of operation by using such an initial frequency than by using a timing frequency that is very close to the desired timing frequency. With the equalizer output connected to the correlator 320 via switch 318, the equalizer 34 is reset and allowed to converge for a predetermined (programmed) amount of time, e.g., 50 ms. The time interval is selected corresponding to the time required for the equalizer to operate sufficiently stably. The time interval may be determined empirically based on the requirements of a particular system. At this point, when the equalizer operation has stabilized, the phase control network comprising units 320, 324, 328, and 310 is reset and allowed to control the operation of oscillator 336 via filter 334 and control voltage input 349 to oscillator 336. Oscillator 336 is operated from the initial (reset) predetermined frequency condition described above.

The described control mechanism improves the performance of the timing recovery network because channel impairments of its input data, such as multipath images, are significantly reduced or eliminated by the equalizer 34. In particular, the timing recovery mechanism improves the ability of the network to acquire and maintain signals under strong multipath conditions. The ability of the disclosed apparatus to recover segment synchronization under adverse conditions such as multipath enhances the speed and accuracy of the symbol timing recovery process.

When signal acquisition is initiated, the adaptive equalizer 34 operates in a blind mode using a known blind equalization algorithm, such as a Constant Modulus Algorithm (CMA). After, for example, 50ms, the equalizer output is deemed good enough to facilitate the segment synchronization and timing recovery process for generating an appropriate sampling clock by oscillator 336. After the symbol timing and the appropriate sampling clock of the ADC unit 19 have been established, the segment synchronization and symbol clock recovery network 24 continues to receive the equalized output signal from the equalizer 34 to improve tracking performance under, for example, strong multipath signal conditions. At this point, the equalizer 34 typically operates in a steady state decision directed mode.

According to one feature of the arrangement of fig. 3, a DC control voltage 349 from unit 348 is used to shift the operating frequency range of oscillator 336. This is accomplished by a network that includes detector 340, microcontroller 344, and level shifter 348. The network improves the symbol acquisition performance and the frequency acquisition performance described below. The detector monitors the steady state operating condition of the oscillator 336 essentially by sensing a predetermined DC level at the output of the filter 334. Sync generator 328 provides an output signal 331 that is such that signal capture has been achieved. Controller 344 is responsive to the output signal from detector 340 and to output signal 331 from sync generator 328 to cause level shifter 348 to generate a control voltage 349 that causes the oscillator to shift its operating frequency range until a steady state operating frequency is reached. The signal acquisition process is repeated each time the oscillator operating frequency range is shifted. Repeating the signal acquisition process includes resetting the network element and setting the VCO336 to operate at a predetermined initial frequency, as described above.

A voltage controlled crystal oscillator (VCXO), such as that used by oscillator 336, has a limited frequency range in which the oscillator can operate with a stable, linear, control voltage versus output frequency transfer function, or response curve. To increase this linear operating frequency range, if signal capture is not achieved within a given time, the DC control voltage 349 from unit 348 moves the oscillator transfer function to a different frequency range without changing the desired linear characteristics. The frequency range shifting capability adjusts the oscillator steady state operating voltage as a function of the correct steady state frequency to produce more reliable symbol timing acquisition.

The configuration of detector 340, microcontroller 344 and level shifter 348 allows symbol timing to be captured over a wider range of frequencies than would be possible in a conventional architecture without these elements (i.e., oscillator 336 controlled solely by the output of filter 334). In conventional arrangements, if the frequency range produced by the oscillator in response to the output of the filter 334 does not include the actual symbol frequency of the received symbol, the timing loop will not lock and the sampling provided by the ADC19 will be at risk. Furthermore, the linear response of the oscillator frequency to the control voltage may deteriorate as the control voltage deviates from its median value. This effect may cause the acquisition performance of the timing recovery network to deteriorate when the steady state oscillator operation requires the frequency control voltage (from filter 334) to be close to its extreme value (maximum or minimum). The network comprising elements 340, 344, and 348 significantly reduces or eliminates these performance penalties.

When the control signals from detector 340 and generator 328 indicate that the received signal has been properly captured, microcontroller 344 maintains the current operating conditions, but when the signal has not been captured within a predetermined time, then the frequency range of oscillator 336 is moved up and down via unit 348.

When operation of microcontroller 344 is initiated, for example after being reset, controller 344 causes level shifter 348 to output a predetermined, standard DC voltage based on the parameters of oscillator 336 and the operating parameters of the overall system. This nominal control voltage causes oscillator 336 to center its control voltage versus output frequency transfer function in its nominal position. Symbol timing recovery is then attempted via elements 320, 324, 328, and 330 as discussed. If the recovery process fails because the actual symbol timing frequency is above the current frequency range of the oscillator, the controller 334 will direct the unit 348 to generate a different control voltage resulting in a different frequency range covered by the oscillator control voltage versus frequency response. This novel rate range may include the actual symbol timing frequency. If signal acquisition is not achieved during a predetermined "time out," the frequency range is shifted. As described above, controller 344 monitors the output of filter 334 and a register in sync generator 328 and determines whether signal capture is achieved, as evidenced by synchronization consistent with the segment sync interval recovered by generator 328. If signal recovery is not achieved during the "time-out" period, a different oscillator frequency is selected and the signal acquisition process is repeated as described above. If after a predetermined time the output of filter 334 indicates that oscillator 336 is in a steady state operating condition and the control voltage indicates that segment synchronization has been restored, the frequency range will not move.

In another embodiment, failure to capture a signal may be indicated by a high error output by Reed-Solomon error detection and correction unit 44 (fig. 1), which unit 44 may be monitored by microcontroller 344. When the Reed-Solomon error detector indicates that the error in good performance is negligible, it indicates that the signal is captured and the operation of the oscillator will remain unchanged.

When the symbol timing is first acquired for a particular channel, the symbol timing frequency is unknown. Although the transmitter and receiver symbol frequencies should be the same, significant variations may occur at the receiver end. In this example, after each signal acquisition failure, a predetermined search instruction, or algorithm, will be implemented by the controller 344 to determine the next centered control voltage to be used, i.e., greater than or less than the initial value. For example, in a simple example, level shifter 348 provides only two available control voltages in response to instructions from controller 344. The first time is to use an initial, or default, control voltage. If the attempt to achieve timing lock fails, a second control voltage and associated frequency range will be used in response to instructions from the controller 344. In more complex systems, level shifter 348 may provide three or more control voltages and associated frequency ranges.

After the channel symbols have been captured for the first time, detector 340 compares the steady state voltage from filter 344 with a local reference voltage representing an optimum voltage in a small predetermined operating range. The controller 344 saves in memory the direction in which the oscillator voltage should be adjusted for the frequency conversion function to place the control voltage from the unit 348 close to the predetermined optimum value. The controller 344 uses this control voltage value as a default value for the next time the channel is acquired.

The moving operation advantageously extends the range of symbol frequencies that can be captured. Also, instead of starting the search for the best oscillator control voltage to the frequency-centered voltage at the same point when a channel is acquired, the best estimate may be used after the first acquisition. In addition, the oscillator control voltage is shifted toward its optimum value for acquisition, eliminating dependency on the accuracy of the time symbol timing frequency and variations in the oscillator voltage versus frequency response due to implementation tolerances such as component value tolerances.

Claims (2)

1. In a system for processing a received data stream containing an image representative signal, apparatus comprising:

a symbol timing recovery network responsive to said received signal prior to equalization and responsive to a recovered synchronization component of said received signal to produce a symbol sampled signal;

a channel equalizer responsive to said received signal for producing an equalized signal; and

a synchronization recovery network responsive to said equalized signal for producing said recovered synchronization component; wherein

Said received signal comprising a vestigial sideband modulated signal comprising a high definition video data frame format represented by a symbol constellation, said data having a data frame format comprised of successive data frames including a field sync component preceding a plurality of data segments having associated segment sync components; and

the recovered synchronization component is the segment synchronization component.

2. A method for processing a received data stream comprising an image representative signal, the method comprising the steps of:

performing channel equalization on the received signal;

recovering a synchronization component of said received signal in response to an equalized signal produced by said equalizing step; and

generating a symbol sampled signal in response to the pre-equalized signal generated prior to said equalizing step and in response to a recovered synchronization component generated by said synchronization recovering step; wherein

Said received signal comprising a vestigial sideband modulated signal comprising a high definition video data frame format represented by a symbol constellation, said data having a data frame format comprised of successive data frames including a field sync component preceding a plurality of data segments having associated segment sync components; and

the recovered synchronization component corresponds to the segment synchronization component.