HK1033200B - Fuse circuit having zero power draw for partially blown condition - Google Patents

Description

Fuse circuit with local fuse state zero power absorption

Technical Field

The present invention relates generally to fuse circuits, and more particularly to a fuse circuit having a zero power draw (power draw) in a partially blown state.

Background

Fuse circuits are commonly used in a variety of semiconductor applications. As the storage density of semiconductor devices, such as memory devices, programmable logic devices, etc., continues to increase, the incidence of defective cells in any one device also increases. Unless these defects can be corrected in some way, defective semiconductor devices are discarded, thereby reducing yield. One common method of correcting these defects is to provide a large number of redundant cells in the device. When a defective cell is detected, a redundant cell may be substituted. The circuitry supporting these redundant cells typically includes a fusible link circuit that contains a fusible link that is selectively "blown" to activate one or more of the redundant cells.

Fuse circuits are also used to facilitate programming of Programmable Logic Devices (PLDs). Typically, the logic cells in a PLD are fabricated with a default (default) logic level, whether at logic HI (high) or logic LO (low). This is done by fusible links which either connect the output of the unit with V_CCOr to ground. When a blown link in a cell blows, the output of the cell is inverted.

An important consideration of such fusible links is that they all consume power. Certain problems exist when the fusible link is partially or incompletely fused. The result is a current path across the fuse, which is not required for two reasons: first, partial fuses can create an indeterminate connection state. Depending on the impedance of the partially blown fuse, the surrounding circuitry may "see" an open or short circuit. Thus, the device does not operate as expected. Second, even if the circuit sees an open circuit across the partially blown fuse, there will be current leakage across the fuse. The current magnitude may be 1 mua or greater, which generally increases the significant current sink (draw) in typical applications employing redundant circuitry.

What is needed is a fuse circuit that reliably provides a fully "blown" state. And requires that the fusible link circuit be as if it had blown completely even if the fusible link actually partially blown.

Disclosure of Invention

The invention provides a fuse circuit, which comprises a fusible link with a first end and a second end; first and second inverters, each of said inverters having an input coupled to said second terminal, said first inverter having a first output, said second inverter having a second output, each of said first and second outputs having a first logic potential and a second logic potential; a first switch coupled between a ground and the first terminal, the first switch having a control terminal coupled to receive the first output and having a conductive state when the first output is at the first logic potential; a second switch coupled between a power line and the second terminal, the second switch having a control terminal coupled to receive the second output and having a conductive state when the second output is at the second logic potential; and a first capacitor coupled between said power supply line and said control terminal of said first switch, and a second capacitor coupled between said ground line and said control terminal of said second switch.

Drawings

Preferred embodiments of the present invention are shown in the drawings.

Detailed Description

Referring to the drawings, a fuse circuit according to the present invention100 includes a fusible element 110 having a first terminal coupled to an N-channel transistor 144 and a second terminal coupled to a node 102. The drain and source of N-channel transistor 144 are connected between the second terminal of fuse 110 and ground. The source and drain of P-channel transistor 142 are connected at V_CCAnd a first end of the fuse 110.

The first inverter 120 is coupled between a first terminal of the fuse 110 and a control gate of an N-channel transistor 144. Capacitor 152 is coupled at V_CCAnd the control gate of transistor 144. The first inverter 120 includes an N-channel transistor that is weaker than its P-channel transistor. This is represented in the figure by the W/L ratio marker associated with inverter 120. As shown in the figure, the W/L ratio for the P-channel device is 4/.6, while the W/L ratio for the N-channel device is 2/8. The significance of the geometry of these devices is described below.

In the figure, the second inverter 130 is a circuit enclosed by a dotted line. The second inverter 130 is coupled between a first terminal of the fuse 110 and a control gate of a P-channel transistor 142. A second capacitor 154 is coupled between the control gate of transistor 142 and ground. The node 104 coupled to the output of the second inverter 130 represents the state of the fuse 110, i.e., whether it is in an intact state or in a blown state. As can be seen from the figure, the W/L ratio (W/L2/8) of P-channel transistors 132 and 134 including inverter 130 is smaller than the W/L ratio (W/L10/. 6) of N-channel transistor 136.

We discuss three cases of operation of the fuse circuit 100: the fuse circuit 110 is not touched to work in time; the working condition when the fuse wire is completely fused; and the working condition when the fuse wire is locally fused. Consider first the situation where the fuse element 110 is not touching in time. After power is turned on, capacitor 152 begins to charge, thereby turning on transistor 144, and capacitor 154 initially is at ground, which turns on transistor 142. This results in V_CCA current path to the fuse element 110. However, since the transistor 144 is turned on, the node 102 tends to become the ground potential, so that the output of the inverter 120 is madeBecomes HI. This keeps the transistor 144 in a conductive state. At the same time, transistors 132 and 134 are turned on, thereby causing node 104 to become V_CC. This leads to the result: (1) turning off the transistor 142, and (2) charging the capacitor 154 to keep the transistor 142 in an off state. Therefore, in the stable state of the fuse element 110 without being touched, the transistor 144 is kept in the on state by the inverter 120, and the transistor 142 is kept in the off state by the inverter 130. However, since the transistor 142 is in an off state, no current flows through the transistor 144. In addition, the initial current through transistors 132 and 134 lasts only long enough to charge capacitor 154, and then the current through these transistors stops. The potential at the output node 160 is held at V_CCWithout the power consumption of the fuse circuit 100.

As can be seen in the figure, the N-channel device of inverter 120 is weaker than the P-channel device. The effect is to raise the potential that node 102 must obtain before the inverter will output the LO. The reason for this is that even if the untouched fuse has some impedance (about 500 ohms) and the potential at node 102 is not actually ground, transistor 144 is prevented from falsely turning off when the fuse is untouched. However, by forming the appropriate dimensions for the P-channel device in inverter 120, the P-channel device can be made to turn on before the N-channel device, even if the potential at the inverter output is not at ground potential.

Consider next the situation when the fuse element 110 is fully blown. At this point, transistor 144 is disconnected from the rest of the circuit. However, as before, transistor 142 begins to conduct because capacitor 154 is initially at ground potential. As a result, the potential at node 102 approaches V_CC. This action has two effects: the output of inverter 120 becomes LO; but more importantly, transistor 136 is made conductive. The conduction of transistor 136 keeps node 104 and capacitor 154 at ground potential and keeps transistor 142 conductive. Since the transistor 144 is disconnected by the blown fuse, no current flows from V_CCAnd flows to ground. However, fromWith transistor 142 in the on state, the potential at node 102 remains at V_CCThus maintaining the LO output of inverter 130. Therefore, in steady state, the output node 160 is LO and there is no power dissipation through any circuit elements of the fuse circuit 100.

Consider the last case where the fuse element 110 is partially blown. In this case, the fuse element 110 is a high impedance element. As before, when the circuit is powered on, capacitor 152 turns on transistor 144 and the initial ground potential at capacitor 154 turns on transistor 142. Since the fuse element is partially fused, there is a secondary V_CCA current path to ground through the partially fused element. In addition, since the partially blown element is resistive, the potential at node 102 is higher than if the fuse element were left completely untouched. Because N-channel transistor 136 is much stronger than P-channel transistors 132 and 134, it will turn on faster, keeping transistor 142 conductive. This causes the potential at node 102 to continue to rise as the fuse current 100 continues to be powered on. The potential at node 102 eventually reaches a potential that turns on the N-channel transistor of inverter 120, which in turn causes the inverter output to become LO, turning off transistor 144. This allows the current path to ground to be eliminated regardless of the presence of the partially blown fuse element. Thus, the circuit 100 is as if the fuse element 110 had been fully blown, which is not the case in practice.

Claims (4)

1. A fusible link circuit, characterized by a fusible link having a first end and a second end;

first and second inverters, each of said inverters having an input coupled to said second terminal, said first inverter having a first output, said second inverter having a second output, each of said first and second outputs having a first logic potential and a second logic potential;

a first switch coupled between a ground and the first terminal, the first switch having a control terminal coupled to receive the first output and having a conductive state when the first output is at the first logic potential;

a second switch coupled between a power line and the second terminal, the second switch having a control terminal coupled to receive the second output and having a conductive state when the second output is at the second logic potential; and

a first capacitor coupled between the power supply line and the control terminal of the first switch, and a second capacitor coupled between the ground line and the control terminal of the second switch.

2. The fuse circuit of claim 1 wherein said first switch is an N-channel transistor and said second switch is a P-channel transistor.

3. The fuse circuit of claim 1 wherein the first inverter includes an N-channel transistor and a P-channel transistor connected in series, the N-channel transistor having a W/L ratio less than the W/L of the P-channel transistor.

4. The fuse circuit of claim 3 wherein the second inverter comprises an N-channel transistor and at least one P-channel transistor connected in series, the N-channel transistor having a W/L ratio greater than the at least one P-channel transistor.