HK1032481A - Reduction of gate-induced drain leakage in semiconductor devices - Google Patents

Description

Reducing gate-induced drain leakage current in semiconductor devices

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The present invention relates generally to semiconductor devices and, more particularly, to reducing gate-induced drain leakage.

In device fabrication, an insulating layer, a semiconductor layer, and a conductive layer are formed on a substrate. The patterned arrangement of these layers forms features and spaces. The minimum feature size of features and spaces depends on the resolution capability of the lithography system. The features and spaces are patterned to form devices such as transistors, capacitors, and resistors. These devices are then interconnected to perform the desired circuit functions, becoming Integrated Circuits (ICs). The layers and patterns for the various devices are formed using conventional fabrication techniques such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, and etching. These techniques are described in S.M. Sze, VLSI Technology, 2nd ed., New York, McGraw-Hill, 1988, which is incorporated herein by reference.

For Metal Oxide Semiconductor (MOS) devices, leakage current needs to be reduced in order to reduce power consumption. An important leakage component in MOS devices is the gate induced drain leakage current (GIDL), which is caused by the channel between the drain surface strips and the strips of the MOS field effect transistor, with the gate overlying the drain. At the time of manufacture, the interface state of the substrate is generated. These surface states increase the incidence of electron-hole pairs, enhancing GIDL. The effect of surface states on GIDL is described in detail in Chen et al, IEEE elec.dev.lett., 10, 216(1989), which is incorporated herein by reference.

The conventional technique to reduce GIDL is to raise the temperature of gate oxide formation to about 1000-. Such techniques are described in Joshi et al, IEEE elec.dev.lett., 12, 28, (1991), which is incorporated herein by reference. The oxidation temperature is increased to reduce the density of surface states of the substrate to reduce GIDL.

Increasing the oxidation temperature requires the use of a rapid thermal oxidation process (RTO). However, the oxidation using RTO results in a gate oxide that is less uniform than with an oxidation furnace. The non-uniformity of the gate oxide results in large variations in the threshold voltage of the device, which is undesirable.

Another technique to reduce GIDL is to implement a lightly doped drain (LLD) device. LLD devices reduce GIDL are described in Parke et al, IEEE trans. elec. dev., 39, 1694(1992), incorporated herein by reference. However, further reduction of GIDL is necessary for future ICs, such as 256M Dynamic Random Access Memories (DRAMs).

In view of the above, lower GIDL devices are desired.

The present invention relates to fabricating integrated circuits, and in particular, for reducing GIDL in MOS devices. The reduction in GIDL, in one example, is achieved by annealing the device in a non-oxidizing ambient such as NH3 and Ar. The anneal is preferably performed after the gate sidewall oxidation, which forms a sidewall liner to control diffusion under the gate. The non-oxidizing ambient anneal reduces the surface states, thereby reducing GIDL.

FIG. 1 shows a conventional MOS device;

FIGS. 2a-c illustrate a process for fabricating a MOS device according to an embodiment of the invention;

FIG. 3 shows the experimental results of the effect of the present invention on GIDL.

The invention relates to a semiconductor MOS device with reduced GIDL. For illustrative purposes, the present invention is exemplified by an n-channel MOS device. The invention is very broad, though. The invention is also applicable to p-channel devices. These devices are used in the manufacture of Integrated Circuits (ICs). These ICs include, for example, Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), and read-only memory (ROM). It may also be useful for other ICs such as application specific ICs (asics), incorporating DRAM logic (embedded DRAM), or other logic.

Typically, many ICs are fabricated on a wafer in parallel. After the processing is completed, the wafer is diced into dies and separated into individual chips. The chips are then packaged to form end products for use in consumer products such as computer systems, mobile phones, Personal Digital Assistants (PDAs), and other electronic products.

For convenience, an n-channel MOS device is described herein. Referring to fig. 1, a conventional n-channel device is shown. As shown, a device 110 is fabricated on a substrate 101. The substrate includes a p-type doped region, such as boron (B), underneath the device. The device includes a gate region 111, a source region 130 and a drain region 140. The source and drain regions are heavily doped n-type with phosphorus (P) or arsenic (As). The source and drain regions may be switched depending on the device operation. For purposes of discussion, drain and source are used interchangeably.

The gate region typically includes a poly (poly) layer 112 formed on a gate oxide 118. Alternatively, layer 112 comprises a polysilicon silicide layer comprising a layer of silicide on top of a polysilicon layer, forming a composite gate stack to reduce the sheet resistance of the gate. A nitride cap is deposited over the gate by Low Pressure Chemical Vapor Deposition (LPCVD). This cap layer acts as an etch stop in subsequent processing steps. The liner 120 is formed on the gate to limit the diffusion of the source and drain regions from bottom to top to the gate region, reducing the overlap capacitance. After liner formation, nitride 170 is deposited on the gate side, source, drain, and STI regions to provide a variable ion barrier, also acting as an etch stop.

An insulator layer (not shown) is formed over the device structure to provide insulation between the conductor layers (except for the contact locations) or to isolate the device structure as a protective layer from impurities, moisture and scratches. The insulating layer comprises phosphorus doped silicon dioxide, such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG).

As shown, the gate is grounded, and the source is connected to V_D(about 1.8-4.0V) a negative bias is formed between the gate and the drain. Such negative bias forms a deep depletion region in the gate/drain overlap region, 160 and 161 shown by dotted lines. The depletion region is significantly depleted of carriers (electron-hole pairs). The depletion region has the strongest electric field, causing an increase in the carrier generation rate. These generated carriers are swept out of the depletion region by the electric field quickly. The electrons are collected by the drain and the holes are collected by the p-well.

Of course the device structure as shown in fig. 1 is simplified for illustration. For example, an actual device may also include other regions, such as contacts, local interconnects, and capacitors. The formation of the different regions of the device structure is described in Wolf, Silicon Processing for the VLSI Era, vol.2, Lattice press, incorporated herein by reference.

In accordance with the present invention, a device for reducing GIDL is provided. Referring to fig. 2a-c, a process for fabricating a GIDL reduction device in accordance with an embodiment of the present invention is shown. In particular, the process forms an n-channel MOS device. As shown, a substrate 201, such as a silicon wafer. The major face of the substrate is not critical and any suitable orientation such as (110), (100) or (111) may be used.

A gate threshold voltage implant is made in the channel region to obtain the desired gate threshold voltage (V)_T). A gate stack is then formed by depositing a plurality of layers on the substrate. This includes forming oxide layer 218, for example by thermal oxidation. The oxide layer acts as a gate oxide. A gate layer 212 comprised of poly is then deposited over the gate oxide. Optionally, the gate layer is a compound layer such as a polysilicon silicide layer including a polysilicon layer with a silicide layer thereon. The silicide layer may be formed from a variety of silicides, including molybdenum (MoSi)_x) Tantalum (TaSi)_x) Tungsten (WSi)_x) Titanium silicide (TiSi)_x) Or cobalt silicide (CoSi)_x). The formation of the polycrystalline layer or the polysilicon silicide layer uses conventional techniques such as Chemical Vapor Deposition (CVD). Other deposition techniques may also be used. A capping layer 219 is formed on the gate layer. The capping layer comprises nitride or other barrier material.

Referring to fig. 2b, the gate stack is patterned using conventional lithographic and etching techniques. This technique involves depositing a photoresist layer and selective exposure with a mask and exposure source. The exposed or unexposed portions are removed during development depending on the polarity of the photoresist. The gate stack layer without photoresist protection is then etched with reactive ions to form the gate stack 211. The sidewalls of the gate stack are oxidized to form the liner 220. The thickness of the liner controls the amount of diffusion at the gate edge to reduce overlap capacitance.

In accordance with the present invention, the substrate is annealed after the gate sidewalls are oxidized. The anneal is a Rapid Thermal Anneal (RTA) process. The RTA temperature is preferably 800-1200 ℃, 900-1100 ℃ and more preferably 1000-1100 ℃. The annealing time ranges from 5 seconds to 2 hours, preferably from 5 to 90 seconds. The substrate is annealed in a non-oxidizing ambient. In one example, ammonia (NH) or argon (Ar) is used as the annealing ambient. The flow rate of ammonia gas in the ammonia gas annealing is 3-10 liters/minute, and preferably 5 liters/minute; the flow rate of argon in the argon annealing is 5-15L/min, preferably 10L/min. A mixture of ammonia and argon was also used to reduce GIDL. The flow rates of ammonia gas and argon gas are respectively 3-5 and 2-5L/min. The flow rates of ammonia and argon are preferably 3 and 2 liters/minute, respectively. It is believed that annealing passivates the surface states, resulting in reduced GIDL.

Alternatively, the anneal can be performed after the gate stack formation and before the gate sidewall oxidation. Annealing after gate sidewall oxidation is more effective at reducing GIDL than annealing after gate formation, but before gate sidewall oxidation. Annealing after gate formation increases the thickness of the gate oxide at the gate edges. The increase in the thickness of the gate oxide reduces tunneling between the bands, thereby reducing GIDL. However, increasing the gate oxide thickness can cause silicon to be converted to silicon dioxide (SiO)₂) The resulting volume expansion leads to increased stresses. This stress can be avoided by annealing after gate sidewall oxidation.

Experiments were conducted to measure the effect of annealing on GIDL according to the present invention. N-and p-channel FETs were tested. The test devices included in the experiment: 1) the gate sidewall is not annealed after oxidation; 2) annealing after gate sidewall oxidation with an argon flow of about 10 liters/minute at a temperature of about 1050 ℃ for about 60 seconds; 3) annealing after gate sidewall oxidation, ammonia flow was about 5 liters/min, temperature was about 1050 ℃, and time was about 60 seconds.

The results of the experiment are shown in FIG. 3. Curve 310 represents the GIDL measurement for an n-channel device and curve 320 represents the GIDL measurement for a p-channel device. As shown, there is a reduction in GIDL after annealing for both n-and p-channel devices. Although annealing in both environments reduced GIDL over unannealed, curve 320 illustrates that annealing of p-channel devices is more efficient with argon than ammonia. In contrast, the use of ammonia for n-channel devices is more effective than argon for reducing GIDL. Thus, annealing p-channel devices in argon and annealing n-channel devices in ammonia is preferred. Although not shown, annealing in a mixed gas ambient of ammonia and argon is also effective in reducing GIDL for n-and p-channel devices.

Referring to fig. 2c, a photoresist layer is deposited on the substrate and patterned as a mask for ion implantation. A dopant such As or P is implanted to form the drain 230 and the source 240. This results in a device that reduces GIDL.

Additional processing is performed. These processes include, for example, forming a nitride liner 270 to act as an etch barrier over the device in order to form borderless contacts. Next, an interlayer insulating material such as doped or undoped silicate glass is formed over the nitride liner. Contact opening formation to provide suitable connections as required, e.g. to V_DAnd a ground.

While the invention has been shown and described with reference to various embodiments, those skilled in the art may make modifications and changes to the invention without departing from the scope of the invention. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.

Claims (1)

1. A method of forming a random access memory circuit, comprising the steps of forming a support device comprising:

providing a semiconductor substrate;

forming a grid stack layer on the surface of the substrate;

etching the grid stack layer to form a grid stack;

oxidizing sidewalls of the gate stack to form a liner;

annealing the substrate in a non-oxidizing ambient to reduce surface states, thereby reducing GIDL;

and selectively implanting the substrate to form a doped region in the area adjacent to the gate.