HK1031041B - An electrical structure and a manufacturing method thereof - Google Patents

Description

Electrical structure and method of making the same

Technical Field

The present invention relates to structures and related methods of manufacture that reduce thermal strain in solder joints associated with solder balls connecting a Ball Grid Array (BGA) module to a circuit card.

Background

Modern circuit board structures have a BGA module mounted on a circuit card. A BGA module includes a substrate having an upper surface and a lower surface, such as a dielectric material of ceramic or plastic. An array of solder balls is secured to a corresponding array of conductive pads on the lower surface of the BGA module while one or more chips are secured to the upper surface of the BGA module. The corresponding circuit card is a pre-wired board that includes a dielectric material and an array of conductive pads on the board. One example of a circuit card is the motherboard of a computer. The circuit card pads serve as attachment points for receiving one or more BGA modules. Thus, each solder ball on the BGA module mounted on the circuit board is fixed to a conductive pad on the BGA module itself, as well as to a conductive pad on the circuit card. These conductive pads are respectively attached to the dielectric substrate of the BGA module and the dielectric board of the circuit card. Thus, each solder ball is a structural element that is mechanically fixed to the dielectric material plate on each side of the solder ball.

When the circuit card is heated or cooled, the solder balls are subjected to strain caused by the different rates of thermal expansion of the supporting dielectric structure. For example, circuit cards typically have a coefficient of thermal expansion of 14 to 22 ppm/deg.C (ppm represents parts per million), while the ceramic substrate of a BGA module has a smaller coefficient of thermal expansion of about 6 to 11 ppm/deg.C. If a plastic substrate material is used for the BGA module, the plastic substrate typically has an effective coefficient of thermal expansion of about 7 ppm/c at the location where the silicon chip constrains the expansion of the substrate. While the above materials and corresponding coefficients of thermal expansion represent the characteristics of BGA substrates and circuit cards, the materials are characterized by an inverse relationship in which the coefficient of thermal expansion of the BGA substrate is higher than the coefficient of thermal expansion of the circuit card to which the BGA module is attached.

Unfortunately, the strain of the solder balls caused by the differential thermal expansion mentioned above can cause fatigue failure of the BGA solder joints. U.S. patent 5,726,079(Johnson, 3/10/98), incorporated herein by reference, discloses a means to reduce the effects of differential thermal expansion. With this alternative measure, the chip mounted on the substrate is peripherally encapsulated with a dielectric material that is mechanically glued to the substrate. In addition, the chip is mechanically connected to conductive plates located on the upper side of the chip, wherein the conductive plates comprise a material such as stainless steel. Since the conductive plates and the substrate are mechanically bonded by the dielectric material encapsulated, structural bending caused by differences in thermal expansion is eliminated, and thermal expansion of the conductive plates moderates thermal expansion of the substrate of the BGA module. The material of the conductive plate is selected so that it has a coefficient of thermal expansion that eliminates bowing caused by a mismatch in the coefficients of thermal expansion of the substrate of the BGA module and the dielectric board of the circuit card. While this approach greatly extends the fatigue life of the BGA, it also increases the cost of the product due to the cost of the conductive plates and the process steps and associated equipment required to manufacture the encapsulated structure.

Disclosure of Invention

The present invention provides an inexpensive method, and an associated electrical structure, for reducing thermal strain on solder balls of a BGA module mounted on a circuit card. The essence of this approach is to increase the effective length of the connection structure between the BGA module and the circuit card that deforms due to differential thermal expansion. This reduces the strain in the connection structure, in particular in the solder balls. Thereby, increasing the length over which some deformation will occur effectively reduces the strain of the entire solder ball. In particular, the method of the present invention forms annular voids by removing material from the dielectric substrate of a BGA module, thereby causing solder balls to adhere to regions of dielectric material, wherein the regions of dielectric material are each substantially surrounded by the annular voids so formed. Annular voids may similarly be formed around areas of the circuit card's dielectric board that underlie the conductive pads of the circuit card to which the BGA module will be attached. Thus, if the annular void is formed to substantially, but not completely, surround the dielectric region, the method forms a peninsula of the dielectric region. Furthermore, if the annular void completely surrounds the dielectric region, the present invention forms an island of the dielectric region. The peninsula so formed is not separated from the remaining dielectric substrate (or plate), thereby leaving a thin dielectric connecting strip between the peninsula and the remaining dielectric substrate (or plate).

In general, the present invention provides a method of forming an electrical structure comprising the steps of:

providing a substrate comprising a dielectric layer having a first surface to which at least one conductive pad is secured; and

removing the first portion of the dielectric layer to form a void portion of the dielectric layer, wherein the void portion substantially surrounds the second portion of the dielectric layer, and wherein the pad is disposed on the second portion.

The present invention generally provides at least one electrical structure comprising:

a substrate comprising a dielectric layer having a first surface;

at least one conductive pad secured to the first surface; and

a void portion of the dielectric layer, wherein the void portion substantially surrounds a second portion of the dielectric layer, and wherein the pad is disposed on the second portion.

The invention has several advantages. The invention protects the integrity of the welding point and prolongs the fatigue life of the BGA module. The method of the present invention is inexpensive compared to other methods such as U.S. patent 5,726,079 (discussed above in the related art section). Furthermore, the present invention does not exclude the use of other methods, and may be used in combination with other methods, with only a small additional cost.

Drawings

Fig. 1 shows a front cross-sectional view of a BGA module secured to a circuit card.

Fig. 2 shows a front cross-sectional view of a BGA module secured to a circuit card with a void area surrounding the BGA pad and the dielectric material under the circuit card pad in accordance with the present invention.

Fig. 3 shows a front cross-sectional view of a BGA module attached to a circuit card with a void area surrounding the dielectric plate material under the circuit card pads in accordance with the present invention.

Fig. 4 shows a front cross-sectional view of a BGA module secured to a circuit card with a void area surrounding the dielectric substrate material under the BGA pad in accordance with the present invention.

Fig. 5 shows a top view of a substrate with a bond pad of a bond bar according to the invention.

Fig. 6 shows fig. 5 with a void region substantially surrounding, but not completely surrounding, the dielectric material under the pad.

Fig. 7 illustrates a top perspective view of a substrate having a void region substantially surrounding, but not completely surrounding, an under-pad dielectric material on the substrate.

Fig. 8 shows a top view of a substrate with one pad according to the present invention.

Fig. 9 shows fig. 8 surrounding the void region of the dielectric material under the pad.

FIG. 10 is a cross-sectional side view of the structure of FIG. 9 showing the wiring pattern connected to the bonding pad

Fig. 11 illustrates a top perspective view of a substrate having a void region completely surrounding an under-pad dielectric material on the substrate.

Detailed Description

Fig. 1 shows a front cross-sectional view of BGA module 20 secured to circuit card 30. BGA module 20 includes a dielectric substrate 22, a chip 26 secured to an upper surface 27 of substrate 22, BGA pads 24 secured to a lower surface 29 of substrate 22, and solder balls 28 secured to BGA pads 24 at a height L. The circuit card 30 includes a dielectric board 32 and circuit card pads 34 affixed to an upper surface 37 of the board 32. The circuit card may be any pre-wired board that includes a dielectric material, such as the motherboard of a computer. The solder balls 28 are attached to pads 34 on the circuit card 30, thereby connecting the BGA module 20 to the circuit card 30. The thermal strain on the solder balls 28 generated during thermal cycling is distributed over the height L. It is the intent of the present invention to modify substrate 22 and/or plate 32 to thereby redistribute strain over a height greater than L to increase the fatigue life of the fig. 1 structure.

Fig. 2 illustrates an embodiment of the present invention that increases the effective height of the strain distribution compared to the structure of fig. 1. Fig. 2 shows a front cross-sectional view of BGA module 40 secured to circuit card 50. BGA module 40 includes a dielectric substrate 42, a chip 46 secured to an upper surface 47 of substrate 42, BGA pads 44 secured to a lower surface 49 of substrate 42, and solder balls 48 secured to BGA pads 44 at a height H. The circuit card 50 includes a dielectric board 52 and circuit card pads 54 secured to an upper surface 57 of the board 52. The solder balls 48 are secured to the circuit card pads 54 thereby connecting the BGA module 40 to the circuit card 50. The inner height of the substrate 42 is Δ H₁Surrounding the substrate material beneath BGA pad 44. The height Δ H in the substrate 52₂Surrounding the board material below the circuit card pads 54. Without the annular gaps 43 and 56, the thermal strain would be distributed over the height H according to the prior art. However, with the annular gaps 43 and 56 according to the invention, the deformation is distributed over a greater height H + Δ H₁+ΔH₂Thereby reducing the strain across the solder ball 48. Annular voids 43 and 56 provide space whereby the substrate material under BGA pad 44 and the board material under circuit card pad 54 are less constrained, thereby increasing their compliance and relieving thermal strain in solder balls 48.

Fig. 3 illustrates an embodiment of the present invention that increases the effective height of the thermal strain distribution compared to the structure of fig. 1. Fig. 3 shows a front cross-sectional view of BGA module 60 secured to circuit card 70. BGA module 60 includes a dielectric substrate 62, a die 66 secured to an upper surface 67 of substrate 62, BGA pads 64 secured to a lower surface 69 of substrate 62, and solder balls 68 of height Y secured to BGA pads 64. The circuit card 70 includes a dielectric board 72, and circuit card pads 74 affixed to an upper surface 77 of the board 72. Solder balls 68 are attached to circuit card pads 74 thereby connecting BGA module 60 to circuit card 70. An annular gap 76 of height deltay in the substrate 72 surrounds the board material beneath the circuit card pads 74. Without the annular gap 76, the thermal strain would be distributed over the height Y according to the prior art. With the annular void 76 of the present invention, however, deformation is distributed over a greater height Y + ay, thereby reducing strain throughout the solder ball 68. The annular void 76 provides space whereby the substrate material beneath the circuit card pads 74 is less constrained, thereby increasing their compliance and relieving thermal strain in the solder balls 68.

Figure 4 illustrates an embodiment of the present invention that increases the effective height of the strain distribution compared to the structure of figure 1. Fig. 4 shows a front cross-sectional view of BGA module 80 secured to circuit card 90. BGA module 80 includes a dielectric substrate 82, a chip 86 secured to an upper surface 87 of substrate 82, a BGA pad 84 secured to a lower surface 89 of substrate 82, and a solder ball 88 secured to BGA pad 84 at a height Z. The circuit card 90 includes a dielectric board 92 and circuit card pads 94 affixed to an upper surface 97 of the board 92. Solder balls 88 are attached to circuit card pads 94, thereby connecting BGA module 80 to circuit card 90. An annular void 83 of height deltaz in substrate 82 surrounds the substrate material beneath BGA pad 84. Without the annular gap 83, the thermal strain would be distributed over the height Z according to the prior art. With the annular gap 83 of the present invention, however, the thermal shear stress is distributed over a greater height Z + az, thereby reducing the strain throughout the solder ball 88. The annular gap 83 provides space whereby the board material beneath the circuit card pads 94 is less constrained, thereby increasing their compliance and relieving thermal strain in the solder balls 88.

If the annular void in fig. 2-4 substantially, but not completely, surrounds the dielectric material under the pad, the peninsula of dielectric material under the pad will be defined by the annular void. Furthermore, if the annular void in fig. 2-4 completely surrounds the dielectric material under the pad, the island of dielectric material under the pad will be defined by the annular void.

Fig. 5-7 illustrate one process of the present invention for forming an annular void that substantially, but not completely, surrounds the dielectric material under the pad to create an island of dielectric material. The process begins with the structure of fig. 5, and fig. 5 shows a top view of a pad 112 on a substrate 110 with a wiring pattern 114 connected to the pad 112. Substrate 110 represents a dielectric substrate of a BGA module, or a dielectric board of a circuit card, as shown in fig. 1-3. Next, fig. 6 illustrates the result of forming an annular void 116 that substantially, but not completely, surrounds the dielectric material under the pad 112. Thereby, a peninsula 119 of dielectric material is created under the pad 112, wherein a strip 115 of dielectric substrate material connects the peninsula 119 to the rest 118 of the substrate 110 (see the substrate 110 of fig. 5). The bar 115 serves to mechanically support the wiring pattern 114, electrically connecting the pads 112 to the substrate 110 or an internal circuit of the BGA module or a circuit card including the substrate 110.

Peninsula 119 is shown in fig. 6 as including a larger area than pad 112 located on peninsula 119. Fig. 7 shows a perspective view of another structure of a substrate 128 with an annular void 126 substantially, but not completely, surrounding a peninsula of substrate material, where the area of peninsula 129 is substantially equal to the area of bond pad 122 located on peninsula 129. Strips 125 of dielectric substrate material connect the peninsulas 129 to the substrate 128 and mechanically support the wiring patterns 124 connected to the pads 122. The wiring pattern 124 electrically connects the pad 122 to the substrate 128 or an internal circuit of the BGA module or a circuit card including the substrate 128.

Fig. 8-11 illustrate one process of the present invention for forming an annular void completely surrounding the dielectric material under the pad to create an island of dielectric material. The process begins with the structure of fig. 8, and fig. 8 shows a top view of a pad 212 on a substrate 210. Substrate 210 represents a dielectric substrate for a BGA module or a dielectric board for a circuit card as shown in fig. 1-3. Next, fig. 9 shows the result of forming an annular void 216 that completely surrounds the dielectric material under the pad 212. Thereby, islands 219 of dielectric material are created under the pads 212, leaving the remainder 218 of the substrate 210 (see substrate 210 of fig. 8). Fig. 10 illustrates a cross-sectional view of the structure of fig. 9 showing wiring pattern 222 within via 220, where via 220 is contained within island 219. The wiring pattern 222 electrically connects the pads 212 upward to the internal circuit of the BGA module or to the circuit card including the substrate 210.

The island 219 is shown in fig. 9 as including a larger area than the pad 212 located on the island 219. Fig. 11 shows a perspective view of another structure of a substrate 238 with an annular void 236 completely surrounding an island 239 of substrate material, where the area of island 239 is substantially equal to the area of a pad 232 located on island 239. The wiring pattern (not shown) is similar to fig. 10 in that it is located within a via contained within island 239, with the wiring pattern up electrically connecting pad 232 to the internal circuitry of the BGA module or circuit card including substrate 238.

The annular voids of the present invention in fig. 2-11 may be formed by any method known to those of ordinary skill in the art. In particular, the annular void may be formed by laser ablation using any of a variety of types of lasers known to those skilled in the art. The actual laser used for this purpose is a frequency tripled Neolumuim YAG laser using a focused beam emitting ultraviolet light, high peak power, high repetition rate, and a diameter of 6 to 50 μm. Generally, the dielectric polymer absorbs the best ultraviolet energy and causes minimal thermal damage to the non-ablated portions. Useful wavelengths in the ultraviolet range are 355 nm. Since the area to be scanned is typically larger than the beam size, a raster scan can be formed to cover the area to be scanned. The scan pitch is typically 80% of the spot size to partially overlap the gaussian beam. Depending on the material, a repetition rate of 1,000Hz to 20,000Hz may be used, with a rate of 1,000Hz providing the highest power per pulse of 12KW, down to 0.5KW at 20,000 Hz. An example of a specific process is to scan the target area with a 14 μm beam at 2,000Hz, 8.3KW per pulse and a pulse spacing of 11 μm, ablating a circular pad on a substrate made of glass cloth reinforced epoxy material such as FR-4. Each time of scanningAbout 20 μm of material was removed. To remove 200 μm (0.008 inch), 10 scans were required. In addition to the Neolumuim YAG laser above, other laser technologies (e.g., CO) may be used₂Lasers and excimer lasers) achieve similar results.

Although the preferred embodiment described herein pertains to a void region surrounding an under-pad dielectric on a BGA module or on a circuit card, the present invention is applicable to any structure having an annular void region surrounding an under-pad dielectric on a dielectric substrate.

While preferred and specific embodiments of the present invention have been described herein for purposes of illustration, it will be apparent to those skilled in the art that many modifications and variations may be made. It is therefore intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims (18)

1. A method of forming an electrical structure comprising the steps of:

providing a substrate comprising a dielectric layer having a first surface to which at least one conductive pad is secured, and

removing the first portion of the dielectric layer to form a void portion of the dielectric layer, wherein the void portion substantially surrounds the second portion of the dielectric layer, and wherein the pad is disposed on the second portion.

2. The method of claim 1, wherein the removing step is accomplished by a laser.

3. The method of claim 1, wherein the removing step produces a strip connecting the second portion to a remaining portion of the dielectric layer.

4. The method of claim 1, wherein the removing step produces a second portion that is not connected to all of the remaining portion of the dielectric layer.

5. The method according to claim 3, wherein the providing step further comprises providing an internal wiring pattern electrically connected to the pad, and wherein the removing step forms a strip of the dielectric layer under a portion of the internal wiring pattern.

6. The method according to claim 4, wherein the providing step further comprises providing an internal wiring pattern electrically connected to the pad, wherein the internal wiring pattern is contained in a via hole located under the pad.

7. The method according to claim 1, wherein the providing step further comprises providing an internal wiring pattern electrically connected to the pad, and wherein the removing step does not remove any portion of the internal wiring pattern.

8. The method of claim 7, further comprising the steps for forming a ball grid array module of:

providing a solder ball;

securing solder balls to the pads; and

a chip is attached to the second surface of the dielectric layer, wherein the chip is electrically connected to the internal wiring pattern.

9. The method of claim 8, wherein the affixing step is performed prior to the securing step.

10. The method of claim 8, further comprising securing the ball grid array module to the circuit card.

11. An electrical structure comprising:

a substrate comprising a dielectric layer having a first surface;

at least one conductive pad secured to the first surface; and

a void portion of the dielectric layer, wherein the void portion substantially surrounds a second portion of the dielectric layer, wherein the pad is disposed on the second portion.

12. The electrical structure of claim 11, wherein the strips of dielectric layer connect the second portion to the remainder of the dielectric layer.

13. The electrical structure of claim 11, wherein the second portion is not connected to all of the remaining portions of the dielectric layer.

14. The electrical structure of claim 12, further comprising an internal wiring pattern electrically connected to the pad, wherein said bar underlies a portion of the internal wiring pattern.

15. The electrical structure of claim 13, further comprising an internal wiring pattern electrically connected to the pad, wherein a portion of the internal wiring pattern is contained within the via hole located below the pad.

16. The electrical structure of claim 11, further comprising an internal wiring pattern electrically connected to the pad.

17. The electrical structure of claim 16, further comprising:

a solder ball fixed to the pad;

and a chip fixed to the second surface of the dielectric layer, wherein the chip is electrically connected to the internal wiring pattern.

18. The electrical structure of claim 17, further comprising a circuit card attached to the solder balls.