HK1026079B - Programmable crystal oscillator and method for use in programming crystal oscillator - Google Patents

Description

Programmable crystal oscillator and method for programming a crystal oscillator

Technical Field

The invention relates to an oscillator of a programmable crystal. In particular, the present invention is directed to a programmable crystal oscillator having an adjustable capacitive load circuit coupled to a crystal.

Background

Crystal oscillators are widely used to generate timing signals to electronic hardware, such as computers, meters and telecommunications equipment. Crystal oscillators typically comprise a quartz crystal and an oscillator circuit that electrically excites the crystal to produce an oscillating signal at a resonant frequency determined by the physical characteristics of the crystal. An oscillator circuit or a separate output circuit (buffer) controls the waveform of the oscillating signal into a timed pulse train acceptable to electronic hardware.

The clocking frequency is specified by the electronic hardware manufacturer so that it varies over a wide frequency range. However, the resonance frequency of a crystal is determined by its physical properties, i.e., size, shape, crystal structure, and the like. Tailoring the resonant frequency of the crystal can be achieved by selecting the metal plated on the surface of the crystal. Thus, the manufacture of crystal oscillators is a complex process that is time consuming and expensive. Thus, the supplier of crystal oscillators has purchased a large number of crystal oscillators manufactured to have a variety of standard output frequencies. However, if the customer requires a custom frequency, the manufacturer must typically "start from scratch" by slicing the ingot into crystal slices of a particular size, and then subjecting the crystal slices to a number of processing steps (grinding, etching, and plating), all designed to achieve the customer-customized output frequency. Custom-made crystal oscillators are expensive and require long manufacturing set-up periods (months).

The manufacturing efficiency is very high due to the fact that all crystals can vibrate. However, if the resonant frequency of the crystal cannot be tailored to meet the frequency specification of one customer, the crystal is typically placed on a product list and is expected to be used to meet the frequency specification of another customer. In the case of customer-specific crystal oscillators, it is not uncommon for manufacturers to produce an excessive number of custom crystals to ensure that a sufficient batch of crystals can meet the customer's requirements (both output frequency and quality). The excess crystal oscillators are then placed on the product list. Maintaining a large inventory of crystalline products represents a significant manufacturing penalty.

Disclosure of Invention

Systems and methods consistent with the present invention address some of the shortcomings of conventional approaches by providing a timing circuit comprising: an oscillator circuit coupled to the crystal to produce a source frequency crystal, and a programmable load circuit coupled to the crystal. A frequency multiplier circuit is coupled to the oscillator circuit to receive the adjusted source frequency. In addition, a programming circuit is included to provide first programming data to the programmable load circuit to adjust the source frequency of the crystal, and second programming data to the frequency multiplier circuit. The multiplier circuit, in turn, provides an output frequency equal to the product of the adjusted source frequency and the multiplication factor specified by the second programming data.

Advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Furthermore, the advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Drawings

FIG. 1 is a plan view depicting an exemplary package configuration of a programmable crystal oscillator package according to an embodiment of the invention;

FIG. 2 is a block diagram of a programmable crystal oscillator according to an embodiment of the present invention;

FIG. 3 is a detailed circuit schematic of a programmable capacitive load circuit included in the programmable crystal oscillator of FIG. 2; and

fig. 4 is a schematic diagram of a phase-locked loop circuit included in the programmable crystal oscillator of fig. 2.

Detailed Description

Reference will now be made in detail to the present preferred embodiments of the invention, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

According to the invention, the programmable crystal oscillator is provided with a memory for storing the output frequency defining parameter. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to the crystal, thereby adjusting the source (resonant) frequency of the crystal. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. As a result, by storing appropriate parameters as programming data in memory and programming according to these parameters, nearly all crystals capable of oscillation can be used in a crystal oscillator according to the invention, which can then be programmed to produce a wide range of specific output frequencies. In addition, such frequency programming can be performed quickly and at low cost.

An embodiment of a programmable crystal oscillator according to the present invention is depicted in fig. 1. The oscillator 20 can be produced in a variety of industry standard sizes and has two basic packaging configurations, pin punch-through and Surface Mount (SMD), depending on the manner in which the oscillator is to be mounted in its particular application. The embodiment described herein has six input/output (I/O) terminals consisting of a tag clock terminal 21, a dedicated program input terminal 22, a ground (VSS) terminal 23, a power supply (VDD) terminal 24, a tag output terminal 25 and a clock signal output (F)_out) Program clock pulse input (CLK)_in) The terminal 26. As will be described in detail below, the program data is clocked by a clock pulse (CLK) provided to terminal 26_in) The time of control is entered through the terminal 22.

When programmable crystal oscillator 20 is programmed with programming data, it generates a clock signal output (F) on terminal 26_out) Its programmed frequency conforms to the customer specified target frequency (anywhere in a wide range, e.g., 380KHz to 175 MHz) and has an accuracy of 100ppm (parts per million) or better. Expressed as a percentage, 100ppm equals. + -. 0.01% of the target frequency. According to one feature of the invention, the crystal oscillator 20 includes a programmable read-only memory (PROM)50, (FIG. 2) in which data programmed in the form of customer data can be provided to the clock pulses (CLK) of the terminal 26 at the time the oscillator is programmed by the manufacturer_in) Under the timing control effected, this is sent via the program terminal 22. Thereafter, the customer data may be read out at terminal 25 by providing a clock pulse to terminal 21. If this signature data feature is omitted, the crystal oscillator package configuration shown in FIG. 1 can be reduced to 4 terminals.

Programmable crystal oscillator 20, which is described in more detail by the block diagram of fig. 2, includes a crystal blank 30 electrically connected between pins 31 and 32 on an integrated circuit chip for being energized by an oscillator circuit 34 and thereby generating a source oscillating signal. This oscillator circuit contains an arrangement of resistor, capacitor and inverter elements which are well known in the crystal oscillator art and therefore need not be described here. At the output of the oscillator circuit 34 as a reference frequency signal F_refThe frequency of the source oscillator signal that appears is determined largely by the physical characteristics of the wafer.

In accordance with a feature of the present invention, programmable crystal oscillator 20 accommodates a wide range of source frequencies, such as 5.6396MHz to 27.3010 MHz. That is, the source frequency may vary from crystal to crystal within this range without compromising the ability of crystal oscillator 20 to be programmed to output any customer-specified clock signal at a target frequency within, for example, the range of 380Khz-175MHz, with an industry standard accuracy of at least 100 ppm. In fact, the different crystal source frequencies need not be known in advance prior to programming.

Still referring to FIG. 2, oscillator circuit 34 outputs a reference frequency F that is provided to a frequency multiplier 36 (described in more detail in FIG. 4)_ref. Frequency multiplier at frequency F_PLLOutputs a clock signal to a frequency divider 38 which divides the frequency F_RLLDivided by a programmable parameter N received from the programming network 42 to produce a clock signal F that conforms to the customer-specified programming frequency_out。F_outAnd F_refThe signals are provided as separate inputs to a multiplexer 40. Under the control of program control logic in programming network 42, multiplexer 40 outputs clock signal F through output buffer 44 using path 43_outOr F_refAnd output to terminal 26.

In accordance with another feature of the present invention, the crystal oscillator further includes a pair of programmable load circuits 46 and 48, if necessary, to adjust the capacitive load on crystal 30, which in turn pulls the source frequency of the crystal within a frequency range that facilitates optimal programming of crystal oscillator 20 to achieve not only the customer specified output frequency accuracy, but also a low phase-locked loop frequency that facilitates stable operation of frequency multiplier 36.

Fig. 3 illustrates the load circuits 46 and 48 in greater detail. The load circuits 46 and 48 may each include, for example, a plurality of capacitors 77₁To 77_nAnd 87₁To 87_n. Capacitor 77₁To 77_nConnected respectively to ground and to a first switching element or transistor 78₁To 78_nAnd a capacitor 87₁To 87_nThen to ground and a second switching element or transistor 88, respectively₁To 88_nBetween the source electrodes of (1). As can also be seen from fig. 3, each transistor 78₁To 78_nIs controlled by an output 76 from programming network 42₁To 76_nA respective one of the outputs is connected, which is collectively shown as 76 in fig. 2. The drains of these transistors are commonly connected to a source frequency input path 79, which path 79 connects the crystal hold down 31 to the oscillator circuit 34. In a similar manner, gates are connected to respective outputs 86 from programming network 42₁To 86_n(indicated as 86 in fig. 2), and transistor 88₁To 88_nAre commonly connected to a source frequency input path 89 that connects the crystal hold down 32 to the oscillator circuit 34. Further, fixed capacitors 75 and 85 (each having a capacitance of, for example, 35 pf) are provided as a rated capacitance load of normal crystal blank 30.

The output path 76 to be selected in response to the parameters stored in the programming network 42₁To 76_nAnd 86₁To 86_nDriven high to energize or turn on transistor 78₁To 78_nAnd 88₁To 88_nA corresponding one of the. As a result, those capacitors 77 associated with the energized transistor are made to be conductive₁To 77_nAnd 87₁To 87_nCoupled to one of the source frequency input paths 79 and 89. Crystal blank 30 can thus be set according to the parameters stored in programming network 42And thus can "pull" the crystal source frequency to within a desired range, with the overall output frequency adjustment being accomplished by the frequency multiplier circuit 36. If no "pull" of crystal frequency is required, transistor 78 is not activated₁To 78_nAnd 88₁To 88_n。

Each capacitor 77₁To 77_nAnd 87₁To 87_nMay have a capacitance of, for example, 5 pf. In addition, a capacitor 77₁To 77_nAnd 87₁To 87_nSymmetrically connected to source frequency input paths 79 and 89, respectively, so that for each capacitor 77 connected to source frequency input path 79₁To 77_nMake the capacitor 87₁To 87_nA respective one of which is connected to the source frequency input path 89. Thus, the capacitor 77₁To 77_nAnd 87₁To 87_nFrom each bank of capacitors 77₁To 77_nAnd 87₁To 87_nOne of) are connected to input paths 79 and 89, respectively, and the incremental change in capacitance associated with each pair of capacitors may be 2.5 pf. As previously mentioned, this capacitive load adjustment pulls the source frequency of the crystal up or down as needed to adjust the reference clock signal frequency F_refTo the optimum frequency programming value for crystal oscillator 20.

As can be seen in fig. 4, frequency multiplier 36 includes a frequency divider 52 that divides a reference frequency F_refDivided by a programmable parameter Q stored in the programming network 42 and the resulting clock signal frequency is provided to a phase detector 54 of a Phase Locked Loop (PLL). The phase locked loop includes a charge pump 56, a loop filter 60 and a voltage controlled oscillator 58. the voltage controlled oscillator 58 generates the frequency F of the clock signal that is fed to the divider 38 of fig. 2_PLL. This clock signal frequency F_PLLAnd is also fed back to the second input of phase detector 54 through divider 64. Frequency divider 64 divides F_PLLThe frequency is divided by a programmable parameter P also stored within the programming network 42.

In operation, parameters Q and P (which will be below)Described in detail above) are provided from programming network 42 to program divider circuits 52 and 64, respectively. Thereby referencing the frequency F_refIs divided by the programming parameter Q in divider circuit 52. As described above, F_refResponsive to the source frequency of the crystal 30, and thus typically in the range of 5.64MHz to 27.3 MHz. If Q is an integer in the range of 132 to 639, the quotient F_refthe/Q (i.e., the output of divider 52) may fall within the range of 32KHz to 50KHz without regard to the source frequency of the crystal. Quotient F_refthe/Q is the loop frequency of the phase locked loop circuit shown in fig. 4.

The loop frequency is provided to phase detector 54 along with the output of divider 64, which typically outputs a control signal having a frequency substantially equal to the difference between the output frequencies of dividers 52 and 64. The control signal is then provided to a charge pump 56, which outputs a DC signal proportional to the frequency of the control signal. A loop filter 60 is provided at the output of the charge pump 56 to define the response of the phase locked loop.

The DC signal is then provided to a Voltage Controlled Oscillator (VCO)58, which outputs a clock signal F having a frequency controlled by the potential of the DC signal_PLL. Then the clock signal F_PLLFed back to one of the inputs of phase detector 54 through P-divider 64. Accordingly, in accordance with such a phase-locked loop arrangement, F_PLLEqual to the product of the loop frequency multiplied by the programmable P, P being an integer in the range 2048 to 4097, such that F_PLLIn the range of 87.5MHz to 175 MHz. Clock signal F_PLLIs also provided to a divider circuit 38 (see fig. 2) where it is divided by the following integer parameters taken from the programming network 42: 1. 2, 4, 8, 16, 32, 64, 128 or 256 and then output as the frequency Fout through the multiplexer 40 and the output buffer 44.

Phase detector 54, charge pump 56, loop filter 60, and VCO58 are all intended to represent a broad class of circuits that are applied to phase lock two input signals, as is well known in the art, and will not be described further.

In general, the output frequency F_PLLAnd F_refThe following equation is satisfied:

F_PLL＝F_ref(P/Q)

thus, F_PLLIs a multiple of the loop frequency. Accordingly, for relatively low loop frequencies, F_PLLFinally fine adjustments can be made in small loop frequency increments. If the loop frequency is too low, the phase locked loop may become unstable resulting in jitter. Therefore, it has been determined that the optimum loop frequency range is 32KHz to 50KHz, and the preferred range is 42.395KHz to 43.059 KHz. Loop frequencies above this range (but less than 200KHz) can also be used, with better output frequency resolution than that obtained by a conventional crystal oscillator PLL.

However, conventional crystal oscillator phase locked loops for digital circuit timing applications operate at significantly higher loop frequencies, i.e., greater than 200 KHz. At these frequencies, such a conventional crystal oscillator cannot achieve as high a frequency resolution as is attainable by the present invention. Typically, polysilicon capacitors and other low noise components, for example, are incorporated in the phase locked loop used in the present invention so that it can operate at loop frequencies in the preferred range of 42.395KHz to 43.059KHz with relatively little jitter.

As described in more detail in applicants' related patent application entitled "global distribution logistics network including strategic location center for customer-specified frequency-programmed crystal oscillators", serial No. 08/795,980, filed herewith and the contents of which are incorporated herein by reference, only P, Q and N parameters may not be sufficient to obtain an output frequency sufficiently close to a specified target frequency, such as within 100parts per milen (100 ppm). In this case, the crystal source frequency is pulled so that the resulting output frequency falls within an acceptable accuracy range, as described above.

Thus, the programmable crystal oscillator according to the present invention can be used to generate a wide range of output frequencies based on the crystal source frequency. The output frequency is obtained by adjusting the source frequency with a programmable capacitive load and operating the phase locked loop circuit at a relatively low loop frequency. Thus, for any crystal having a source frequency in the broad range of 5.6396HMz to 27.3010MHz, for example, a crystal oscillator output frequency within 100ppm or less of the specified target frequency can be obtained by simply storing the appropriate P, Q and N and crystal pull parameters in a PROM included in programming network 42. As noted in the referenced copending application, crystal oscillator 20 can be manufactured as a generic programmable crystal oscillator regardless of the customer-specified output frequency, and simply programmed over a matter of seconds to produce an output frequency in accordance with the customer specification. Therefore, it is not necessary to manufacture crystals of a plurality of standard frequencies, thereby simplifying the manufacturing process, speeding up and reducing the cost. This greatly reduces the preparation of the delivery from the customer's purchase order to the delivery of the product.

Although the invention has been described herein with reference to a standard micromachine-processed crystal blank which oscillates in the range 5.6396MHz to 27.3010MHz, as mentioned above, it will be appreciated that the invention can be implemented using industry standard clock crystals (mass produced to oscillate at 32.768 KHz). In this case, the desired low phase-locked loop frequency may be obtained without the need for divider 52 in multiplier 36 of fig. 4. Crystal blank 30 will then be coupled to the phase-locked loop circuit in a substantially direct-drive relationship. Depending on the mass production, the cost of the clock crystal is significantly lower than that of the microprocessor-based crystal, so that further savings can be realized in the production of the programmable crystal oscillator according to the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made in the programmable crystal oscillator of the present invention and the structure of such programmable crystal oscillator without departing from the scope or spirit of the invention.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims (90)

1. A timing circuit, comprising:

a programmable load circuit coupled to the crystal that generates the source frequency;

an oscillator circuit coupled to receive the source frequency;

a frequency multiplier circuit coupled to the oscillator circuit to receive the source frequency; and

a programming circuit configured to provide stored first programming data to the programmable load circuit to adjust the source frequency and to provide stored second programming data to the frequency multiplier circuit to cause the frequency multiplier to provide an output frequency equal to a product of the adjusted source frequency and a multiplication factor specified by the second programming data.

2. A timing circuit in accordance with claim 1, wherein said programmable load circuit is a programmable capacitive load circuit.

3. A timing circuit in accordance with claim 2, wherein said source frequency is provided through a source frequency path coupled to said crystal and said oscillator circuit, said programmable capacitive load circuit comprising:

a plurality of capacitors coupled to the ground electrode and coupling a selected one of the plurality of capacitors to the source frequency path.

4. A timing circuit in accordance with claim 3, wherein said programmable capacitive load circuit further comprises:

a plurality of switching elements each having a first terminal commonly connected to the source frequency path and a second terminal coupled to a respective one of the plurality of capacitors.

5. A timing circuit in accordance with claim 4, wherein said programming circuit generates a plurality of output signals in accordance with said first programming data stored therein, said plurality of output signals being provided to said programmable capacitive load circuit to actuate a selected one of said plurality of switching elements to connect a corresponding one of said capacitors to said path of said source frequency.

6. A timing circuit in accordance with claim 4, wherein each of said plurality of switching elements comprises a MOS transistor.

7. A timing circuit in accordance with claim 1, wherein said frequency multiplier comprises a phase-locked loop circuit.

8. Timing circuit according to claim 1, characterized in that said second programming data comprise a first parameter Q and a second parameter P, said output frequency (F)_PLL) And the regulating source frequency (F)_ref) Satisfies the following conditions:

F_PLL＝F_ref(P/Q)

9. a timing circuit in accordance with claim 7, wherein said frequency multiplier circuit comprises:

a first frequency divider for dividing the adjusted source frequency by a first parameter Q of the second programming data to generate a first frequency;

a second frequency divider included in the phase-locked loop circuit for dividing the output frequency by a second parameter P of the second programming data to generate a second frequency; and

a detector contained in the phase-locked loop circuit and coupled to receive the first and second frequencies, the detector outputting a control signal in response to the first and second frequencies to control generation of the output frequency.

10. A timing circuit in accordance with claim 9, further comprising:

a third divider circuit, coupled to the phase locked loop circuit and the programming circuit, for dividing the output frequency by a third parameter of the second programming data stored in the programming circuit.

11. A timing circuit in accordance with claim 7, wherein said adjusted source frequency is provided to a divider circuit coupled to said phase-locked loop circuit to produce a loop frequency of said phase-locked loop circuit that is less than 200 KHz.

12. A timing circuit in accordance with claim 11, wherein said loop frequency is within a range of 32KHz to 50 KHz.

13. A timing circuit in accordance with claim 11, wherein said loop frequency is within a range of 42.395KHz to 43.059 KHz.

14. A timing circuit in accordance with claim 9, wherein said detector outputs said control signal based on a phase difference between said first and second frequencies, said phase locked loop circuit further comprising:

a charge pump circuit receiving the control signal and outputting a DC signal accordingly;

a loop filter; and

a voltage controlled oscillator coupled to the charge pump through the loop filter, the voltage controlled oscillator generating the output frequency under control of the DC signal.

15. A timing circuit in accordance with claim 1, further comprising a dedicated external programming terminal for entering said first and second programming data for storage in a programmable read only memory included in said programming circuit.

16. A timing circuit in accordance with claim 1, further comprising:

a first PROM for storing mark data;

a programming end for programming the first PROM with the marking data; and

a first output terminal for reading said marking data from said first PROM.

17. A timing circuit in accordance with claim 16, further comprising:

a second PROM programmed by the first and second programming data entered through the programming terminal; and

and the second output terminal is used for outputting a clock signal, receiving clock pulses, triggering the marking data to the first PROM in a clock mode, and triggering the first programming data and the second programming data to the second PROM in a clock mode.

18. A timing circuit in accordance with claim 17, further comprising a second input terminal for receiving a clock signal to read said mark data from said first PROM onto said first output terminal.

19. A programmable timing circuit, comprising:

an oscillator circuit coupled to excite the crystal to generate a source frequency;

a capacitive load circuit coupled to the crystal and configured to be programmed with stored programming data to a desired load capacitance to selectively adjust the source frequency; and

a phase-locked loop circuit coupled to the oscillator circuit, the phase-locked loop circuit generating an output frequency as a product of the regulated source frequency and a multiplication factor,

wherein the multiplication factor is determined from programming data.

20. A programmable timing circuit in accordance with claim 19, further comprising:

a memory coupled to the phase-locked loop circuit and the capacitive load circuit for storing the programming data, the programming data including a first parameter for programming the capacitive load circuit to a desired load capacitance and a second parameter for programming the phase-locked loop circuit to the multiplication factor.

21. A programmable timing circuit in accordance with claim 20, wherein said memory comprises a PROM.

22. The programmable timing circuit of claim 20 wherein said crystal is coupled to said oscillator circuit by an input path, said capacitive load circuit comprising:

a plurality of capacitors coupled to a ground electrode; and

a plurality of switching elements, each of the switching elements having a first terminal coupled to a respective one of the plurality of capacitors and a second terminal coupled to the input path, the memory providing the first parameter as a plurality of signals to actuate a selected one of the plurality of switching elements to thereby couple the respective one of the plurality of capacitors to the input path.

23. A programmable timing circuit in accordance with claim 22, wherein each of said plurality of switching elements comprises a MOS transistor.

24. A programmable timing circuit in accordance with claim 20, further comprising a dedicated programming terminal that provides external access to said programming data stored in said memory.

25. A programmable crystal oscillator, comprising:

a crystal having an associated source frequency;

an oscillator circuit;

an input path coupling the crystal to the oscillator circuit;

a programmable capacitive load coupled to the input path for adjusting the source frequency according to a load parameter;

a frequency multiplier circuit comprising a phase-locked loop circuit coupled to the oscillator circuit through a frequency divider to receive the adjusted source frequency, the frequency divider to generate a loop frequency, the phase-locked loop circuit to multiply the loop frequency by a frequency parameter to generate a desired output frequency; and

a programming circuit coupled to the programmable capacitive load circuit and the phase locked loop circuit, the programming circuit storing the load and frequency parameters to program the capacitive load circuit and the phase locked loop circuit, respectively.

26. The programmable crystal oscillator of claim 25, wherein said crystal is an industry standard clock crystal having an associated source frequency of 32.768 KHz.

27. A circuit unit for providing an output frequency, comprising:

a programmable load circuit connected to a crystal for generating a source frequency;

an oscillator circuit connected to receive the source frequency;

a frequency multiplier circuit connected to the oscillator circuit to receive the source frequency;

a memory for storing first programming data for adjusting the programmable load circuit and storing second programming data for adjusting the frequency multiplier circuit; and

a memory controller for receiving an external input from outside the circuit unit for controlling the storage of the first and second program data.

28. The circuit cell of claim 27, wherein the external input comprises data specifying the first and second programmed data values.

29. The circuit cell of claim 27, wherein the external input comprises a clock signal for storing the first and second programming data.

30. The circuit element of claim 27 wherein the element is a circuit package.

31. A circuit unit according to claim 30, wherein the package has only four external electrical connections.

32. A circuit unit according to claim 30, wherein the package has only six electrical connectors.

33. The circuit element of claim 27 wherein the element is an integrated circuit chip.

34. A method of initializing an oscillator circuit that outputs an oscillation frequency, comprising:

providing a phase locked loop for generating an oscillating output frequency from an oscillating input frequency;

adjusting a parameter of the phase-locked loop so that the phase-locked loop can output a frequency near a predetermined frequency according to the input frequency of the oscillation; and

the crystal circuit is instructed to fix the impedance to change the input frequency of the oscillation so that the phase locked loop outputs a predetermined frequency.

35. The method of claim 34, wherein the impedance is a capacitance.

36. The method of claim 34, wherein the indicating step comprises fixing an impedance of the programmable load.

37. The method of claim 36, wherein the phase locked loop is disposed on an integrated circuit.

38. The method of claim 37, wherein the step of adjusting further comprises:

storing a programmed value in the integrated circuit to determine a multiplication factor of the phase locked loop; and

the programmed value is output to the phase locked loop.

39. The method of claim 37, wherein the programmable load is part of an integrated circuit.

40. A timing circuit, comprising:

a programmable load circuit that can be coupled to a crystal to receive a source frequency;

an oscillator circuit that may be coupled to receive the source frequency;

a frequency multiplier circuit coupled to the oscillator circuit to receive the source frequency; and

a programming circuit configured to provide stored first programming data to the programmable load circuit to adjust the source frequency and to provide stored second programming data to the frequency multiplier circuit to cause the frequency multiplier to provide an output frequency equal to a product of the adjusted source frequency and a multiplication factor specified by the second programming data.

41. A timing circuit in accordance with claim 40, wherein said programmable load circuit is a programmable capacitive load circuit.

42. A timing circuit in accordance with claim 41, wherein said source frequency is provided by a source frequency path, said source frequency path being coupleable to said crystal and said oscillator circuit, said programmable capacitive load circuit comprising:

a plurality of capacitors coupled to the ground electrode, coupling a selected one of the plurality of capacitors to the source frequency path.

43. A timing circuit in accordance with claim 42, wherein said programmable capacitive load circuit further comprises:

a plurality of switching elements each having a first terminal commonly connected to the source frequency path and a second terminal coupled to a respective one of the plurality of capacitors.

44. A timing circuit in accordance with claim 43, wherein said programming circuit generates a plurality of output signals in accordance with said first programming data stored therein, said plurality of output signals being provided to said programmable capacitive load circuit to actuate a selected one of said plurality of switching elements to connect a corresponding one of said capacitors to said path of said source frequency.

45. A timing circuit in accordance with claim 43, wherein each of said plurality of switching elements comprises a MOS transistor.

46. A timing circuit in accordance with claim 40, wherein said frequency multiplier circuit comprises a phase-locked loop circuit.

47. A timing circuit in accordance with claim 40, wherein said second programming data comprises a first parameter Q and a second parameter P, said output frequency (F)_PLL) And the regulating source frequency (F)_ref) Satisfies the following conditions:

F_PLL＝ F_ref(P/Q)

48. a timing circuit in accordance with claim 47, wherein said frequency multiplier circuit comprises:

a first frequency divider for dividing the adjusted source frequency by a first parameter Q of the second programming data to generate a first frequency;

a second frequency divider included in the phase-locked loop circuit for dividing the output frequency by a second parameter P of the second programming data to generate a second frequency; and

a detector contained in the phase-locked loop circuit and coupled to receive the first and second frequencies, the detector outputting a control signal in response to the first and second frequencies to control generation of the output frequency.

49. A timing circuit in accordance with claim 48, further comprising:

a third divider circuit, coupled to the phase locked loop circuit and the programming circuit, for dividing the output frequency by a third parameter of the second programming data stored in the programming circuit.

50. A timing circuit in accordance with claim 47, wherein said adjusted source frequency is provided to a frequency divider circuit to produce a loop frequency of said phase locked loop circuit of less than 200 KHz.

51. A timing circuit in accordance with claim 50, wherein said loop frequency is within a range of 32KHz to 50 KHz.

52. A timing circuit in accordance with claim 50, wherein said loop frequency is within a range of 42.395KHz to 43.059 KHz.

53. A timing circuit in accordance with claim 48, wherein said detector outputs said control signal based on a phase difference between said first and second frequencies, said phase locked loop circuit further comprising:

a charge pump circuit receiving the control signal and outputting a DC signal accordingly;

a loop filter; and

a voltage controlled oscillator coupled to the charge pump through the loop filter, the voltage controlled oscillator generating the output frequency under control of the DC signal.

54. A timing circuit in accordance with claim 40, further comprising a dedicated external programming terminal for entering said first and second programming data for storage in a programmable read only memory included in said programming circuit.

55. A timing circuit in accordance with claim 40, further comprising:

a first PROM for storing mark data;

a programming end for programming the first PROM with the marking data; and

a first output terminal for reading said marking data from said first PROM.

56. A timing circuit in accordance with claim 55, further comprising:

a second PROM programmed by the first and second programming data entered through the programming terminal; and

and the second output terminal is used for outputting a frequency based on the output frequency, receiving clock pulses, and clock-triggering the marking data to the first PROM and clock-triggering the first and second programming data to the second PROM.

57. A timing circuit in accordance with claim 56, further comprising a second input terminal for receiving a clock signal to read said mark data from said first PROM onto said first output terminal.

58. A programmable timing circuit, comprising:

an oscillator circuit that can be coupled to excite the crystal to generate a source frequency;

a capacitive load circuit, which may be coupled to the crystal and configured to be programmed with stored programming data to a desired load capacitance to selectively adjust the source frequency; and

a phase-locked loop circuit coupled to the oscillator circuit, the phase-locked loop circuit generating an output frequency as a product of the regulated source frequency and a multiplication factor.

59. A programmable timing circuit in accordance with claim 58, further comprising:

a memory coupled to the phase-locked loop circuit and the capacitive load circuit for storing programming data, the programming data including a first parameter for programming the capacitive load circuit to a desired load capacitance and a second parameter for programming the phase-locked loop circuit to the multiplication factor.

60. A programmable timing circuit in accordance with claim 59, wherein said memory comprises a PROM.

61. A programmable timing circuit in accordance with claim 59, wherein said crystal is coupled to said oscillator circuit by an input path, said capacitive load circuit comprising:

a plurality of capacitors coupled to a ground electrode; and

a plurality of switching elements, each of the switching elements having a first terminal coupled to a respective one of the plurality of capacitors and a second terminal coupled to the input path, the memory providing the first parameter as a plurality of signals to actuate a selected one of the plurality of switching elements to thereby couple the respective one of the plurality of capacitors to the input path.

62. A programmable timing circuit in accordance with claim 61, wherein each of said plurality of switching elements comprises a MOS transistor.

63. A programmable timing circuit in accordance with claim 59, further comprising a dedicated programming terminal that provides external access to said programming data stored in said memory.

64. A programmable crystal oscillator circuit, comprising:

an oscillator circuit;

an input path coupled to the oscillator circuit;

a programmable capacitive load coupled to the input path to provide a load to the input path;

a phase-locked loop circuit coupled to the oscillator circuit and the programmable capacitive load for generating a loop frequency in response to an output of the oscillator circuit, the phase-locked loop circuit operating at the loop frequency using a frequency parameter to generate a phase-locked loop output frequency; and

a programming circuit coupled to the programmable capacitive load circuit and the phase locked loop circuit, the programming circuit storing the load and frequency parameters to program the capacitive load circuit and the phase locked loop circuit, respectively.

65. A programmable crystal oscillator in accordance with claim 64, wherein said input path is configured to receive an industry standard clock crystal having an associated source frequency of 32.768 KHz.

66. A circuit unit for providing an output frequency, comprising:

a programmable load circuit;

an oscillator circuit connected to the programmable load circuit;

a phase locked loop connected to said oscillator circuit for generating a frequency in response to said oscillator circuit and said programmable load circuit;

an electrically programmable memory for storing first programming data for adjusting the programmable load circuit and storing second programming data for adjusting the phase locked loop; and

a memory controller for receiving an external input from outside the circuit unit for controlling the storage of the first and second program data.

67. The circuit cell of claim 66, wherein the external input includes data specifying the first and second programmed data values.

68. The circuit cell of claim 66, wherein the external input comprises a clock signal for storing the first and second programming data.

69. A circuit element as claimed in claim 66, characterized in that the element is a circuit package.

70. A circuit unit according to claim 69, wherein the package has only four external electrical connections.

71. A circuit unit according to claim 69, wherein the package has only six external electrical connections.

72. The circuit element of claim 66 wherein the element is an integrated circuit chip.

73. The circuit element of claim 66 wherein the memory stores data including a feedback value P for the phase-locked loop, a reference value Q for the phase-locked loop, and an oscillator adjustment value.

74. An integrated circuit, comprising:

a programmable capacitive load circuit comprising a set of selectable impedances and a set of semiconductor switches, each of the set of switches being coupled to a respective one of the selectable impedances;

an oscillator circuit connected to the programmable load circuit;

a phase locked loop connected to said oscillator circuit for generating a frequency in response to said oscillator circuit and said programmable capacitive load circuit;

a memory for storing first programming data for selecting an impedance by adjusting some switches of the programmable capacitive load circuit to be turned on or off, and storing a feedback value P of a phase-locked loop and a reference value Q of the phase-locked loop; and

control logic configured to allow input from outside of the integrated circuit to cause the memory to store the first programming data, the feedback value P, and the reference value Q.

75. A crystal oscillator adjustment circuit, comprising:

an oscillator circuit that may be coupled to a crystal, the oscillator circuit capable of generating a reference frequency;

a programmable capacitance adjustment circuit coupled to the oscillator circuit;

a frequency multiplier circuit coupled to the oscillator circuit;

means for storing data, the means operatively connecting the programmable capacitance adjustment circuit and the frequency multiplier circuit,

wherein the stored data includes data for selectively adjusting the impedance of the capacitance adjustment circuit and data for selectively adjusting the multiplication factor of the frequency multiplier circuit, an

Wherein the programmable capacitance adjustment circuit and the frequency multiplier circuit can modify the reference frequency to generate an output clock frequency.

76. A crystal oscillator adjustment circuit as defined in claim 75, wherein the programmable capacitance adjustment circuit is a programmable capacitive load circuit.

77. A crystal oscillator adjustment circuit as defined in claim 76, wherein the programmable capacitive load circuit comprises:

a plurality of capacitors that may be selectively coupled to the inputs of the oscillator.

78. A crystal oscillator adjustment circuit as defined in claim 77, wherein the programmable capacitive load circuit further comprises one or more switching elements, each switching element for selectively coupling a respective one of the plurality of capacitors to the input of the oscillator circuit.

79. A crystal oscillator adjustment circuit as defined in claim 78, wherein the data for selectively adjusting the capacitance of the capacitance adjustment circuit includes information selecting one or more of the plurality of switching elements to connect a respective one or more of the capacitors to the input of the oscillator circuit.

80. A crystal oscillator adjustment circuit as defined in claim 75, wherein the frequency multiplier circuit comprises a phase locked loop circuit.

81. A programmable phase-locked loop and oscillator adjustment circuit, comprising:

an oscillator circuit;

a programmable capacitive load circuit coupled to the oscillator circuit;

a phase-locked loop circuit coupled to the oscillator circuit; and

a programmable memory operatively connected to the programmable capacitive load circuit and the phase-locked loop circuit,

wherein the memory stores a capacitance load value for selectively adjusting a capacitance of the capacitance load circuit, a feedback value P of the phase-locked loop, and a reference value Q of the phase-locked loop, an

Wherein the programmable capacitive load circuit and the phase locked loop circuit can modify a reference frequency to produce an output frequency.

82. The programmable phase-locked loop and oscillator adjustment circuit of claim 81, wherein said programmable capacitive load circuit comprises:

a plurality of capacitors selectively coupleable to an input of the oscillator circuit.

83. The programmable phase-locked loop and oscillator adjustment circuit of claim 82, wherein the programmable capacitive load circuit further comprises one or more switching elements, each switching element for selectively coupling a respective one of the plurality of capacitors to the input of the oscillator circuit.

84. A programmable phase-locked loop and oscillator adjustment circuit as recited in claim 83, wherein the capacitive load value comprises information that selects one or more of the plurality of switching elements to connect a corresponding one or more of the capacitors to the input of the oscillator circuit.

85. A circuit unit for providing an output frequency, comprising:

programmable load circuit means for providing a programmable load;

oscillator circuitry connected to said programmable load circuitry;

frequency generating means comprising a phase locked loop connected to said oscillator circuit means for generating a frequency in response to an output of said oscillator circuit means and programmable load circuit means;

memory means for storing first programming data for adjusting said programmable load circuit means and second programming data for adjusting said frequency generating means; and

a memory control device for receiving an external input from outside of the circuit unit to control the storage of the first and second program data.

86. The circuit cell of claim 85, wherein the external input comprises data specifying the first and second programmed data values.

87. The circuit cell of claim 85, wherein the external input comprises a clock signal for storing the first and second programming data.

88. The circuit element of claim 85 wherein the element is a circuit package.

89. The circuit element of claim 85 wherein the element is an integrated circuit chip.

90. The circuit element of claim 85 wherein said memory means stores programming data including a feedback value P for the phase locked loop, a reference value Q for the phase locked loop, and an oscillator adjustment value.