HK1022559A - Optical disc system having circuitry for performing blank sector check on readable disc and method for operating same - Google Patents

Description

Optical disc system having circuit for checking blank sector on readable disc and operating method thereof

the application is a divisional application with application number 96101465.2, and the application date is 1996-18/1.

This application is a continuation of part of U.S. patent application No. 08/105,866, filed on 8/11/1993, which is a continuation of U.S. patent application No. 07/657,155, filed on 2/15/1991, now U.S. patent No. 5,265,079.

The present invention relates to data storage systems of the type which include a housing having an opening for receiving a removable cartridge in which an information recording medium can be housed for protection of the disc, and more particularly to a system for rapidly encoding and writing information in high density form onto an optical disc, and reading and decoding the written information.

With the widespread use of data processing systems and personal computers, the demand for large capacity data storage devices has increased, and optical data storage systems have become an increasingly common device to meet this growing demand. These optical data systems provide large capacity, relatively low cost memories that can be accessed quickly.

In optical disc systems, encoded video signals, audio signals, or other information signals may be recorded on a disc in the form of information tracks on one or both sides of the disc. The core of the optical storage system is to have at least one laser (or other light source). In a first mode of operation, the laser generates a high intensity laser beam which is focused onto a small spot on the information track of the rotating storage disk, and the high intensity laser beam raises the temperature of the recording surface of the material above its Curie point, causing the material to lose its magnetic properties at that point and be magnetized by the magnetic field in which the disk is located, whereby information is recorded in the form of magnetic domains on the disk, referred to as "pits" on the recording medium, by controlling the surrounding magnetic field or bias and causing the disk to cool below its Curie point in a controlled magnetic field environment.

Then, when the operator needs to reproduce or read the previously recorded information, the laser enters a second mode of operation in which the laser generates a low intensity laser beam which is then focused on the track of the rotating disc, which low intensity laser beam does not heat the disc above the curie point. However, the laser beam is reflected from the surface of the disc in a manner representative of the previously recorded information due to the presence of the previously formed pits, thereby enabling the previously recorded information to be reproduced. This type of information processing system has advantages of high recording density and accurate reproduction of recorded information because the laser light can be tightly focused.

A typical optical system component includes a housing having an insertion opening through which a user can insert a recording medium into a drive, the housing accommodating, among other things, mechanical and electrical subsystems for loading, reading, and writing an optical disc. The operation of these mechanical and electrical subsystems is typically under the exclusive control of a data processing system to which the drive device is connected.

In a typical system housing in which the disc cartridge is used, a turntable on which the disc is typically mounted for rotation on a system base plate may include a spindle having a magnet on which a hub is mounted for use, the magnet attracting the hub, thereby holding the disc in a desired position for rotation.

In an optical disc system, as described above, it is necessary to apply a magnetic bias to a disc during a writing operation by applying a desired magnetic field to at least a portion of the disc heated by a laser during the writing (recording or erasing) operation, and therefore, it is necessary to install a magnetic field biasing means that can be conveniently placed in a position close to the surface of the disc when the disc is positioned by a magnet associated with a spindle.

Various media or disc types used in optical data storage systems may be used to store digital information. For example, a standard optical disc system may use 51/4 inch discs, which may or may not be placed in a protective housing or box. If the optical disk is not fixedly mounted in the protective case, the operator can take out the disk from the protective case, and then the operator can put the disk on the loading mechanism by hand, taking care to prevent damage to the surface of the disk.

In addition, for convenience and protection, the disc may be placed in a cartridge or a cartridge, which is itself inserted into an insertion port of a drive and then is carried to a predetermined position, which is well known in the computer art, and the disc cartridge is composed of a cartridge case containing a disc on which data can be recorded.

Loading of disc cartridge

To protect the disc when the disc cartridge is outside the drive, the disc cartridge typically comprises at least one door or shutter, which is normally closed, the cartridge door may have one or more locking members associated therewith, and the corresponding disc drive apparatus comprises a mechanism for opening the door or shutter on the disc cartridge when the cartridge is pushed into the system, which mechanism may comprise a door chain connected to the locking members, thereby opening the shutter. When the cartridge is further inserted into the driving apparatus, the shutter is opened to partially expose the information recording medium contained therein. This allows the hub to be loaded onto a motor spindle or other drive mechanism and the read/write head to enter, biasing the magnetic field into the protective cartridge. The head is allowed to access all portions of the disc medium as the disc is rotated by the drive mechanism.

In order to save space in an optical storage system, it is desirable to minimize the size required for a device that loads and unloads disks on a spindle. Typically the tray loading and unloading apparatus varies depending on the type of tray used. A disc loading and unloading system, which typically uses disc cartridges, is typically capable of automatically transferring the disc cartridges from the receiving entrance to the spindle. A conventional disc loading and unloading system automatically unloads the disc from the spindle when the disc is no longer needed. The loading device for loading and unloading such a disc is generally constructed such that during loading (i.e., when the disc is moved from the eject position into the playback apparatus and onto the spindle), the optical disc is moved horizontally to the turntable parallel to the base plate and the turntable, and when the disc has been positioned on the turntable, the optical disc is vertically lowered onto the spindle perpendicular to the surface of the turntable, and once on the turntable, the spindle magnet attracts the hub fixed to the center of the medium, thereby clamping the optical disc in a rotatable condition for reading and writing.

When the operator finishes using the optical disc, the operator starts the eject operation. The most common method of ejecting the cartridge and the optical disc from the spindle is the technique used in most japanese drive devices. In this type of disk ejector, the "frame" of the disk cartridge has four pins on its sides, and the pins will rest on adjacent sheet metal rails. During the ejection of the optical disc, the housing raises the optical disc up and away from the spindle. Then, the apparatus horizontally moves the optical disk parallel to the base plate and the turntable to a disk receiving slot in front of the optical disk drive. When the disc is thus raised by the spindle during a disc unloading operation, sufficient upward force must be generated on the cartridge to overcome the magnetic clamping force holding the hub to the spindle magnet. The maximum upward force required to overcome the magnetic clamping force is generated by mechanical operation of the ejector rod or by activating an electrical ejector system.

In a typical electrical eject system, in which the unloader of the cartridge would lift the cartridge vertically to cut off the magnetic force between the spindle magnet and the hub, the eject motor must generate a large load to complete the removal of the cartridge. Next, when the operator chooses to use the electric exit system, a large motor with a large torque is required to generate a sufficient vertical upward force. Space must be reserved in the system housing to accommodate such a large motor, thereby increasing the overall size of the housing of the disk loader. In addition, large motors consume a significant amount of power.

It is therefore desirable to reduce the complexity of the optical disc drive while reducing the overall size of the optical disc drive to facilitate drive device adaptation for computer applications. To be able to receive an 51/4 inch cartridge and yet be small enough to fit into a personal computer, the disc drive must use compact and carefully positioned mechanical and electrical subsystems. In view of this, it is desirable to reduce the size of the required exit motor. One way to achieve this result is to reduce the amount of force required to break the magnetic clamping force holding the hub to the spindle magnet, by reducing which the eject motor in a smaller optical disc drive can be used, and thus it is desirable to design a disc loading apparatus in which the disc is not moved vertically upward away from the spindle magnet, but is "peeled" off the magnet.

A common method of attempting to achieve this peeling action is to rotate the turntable and spindle downward away from the disc, as discussed in U.S. patent No. 4,791,511, assigned to MarvinDavis and assigned to the Laser magnetic storage international (Laser magnetic storage international). However, it is still desirable to design a drive device in which the optical disk can be disengaged from the spindle magnet.

Focus and tracking actuation

In order to obtain an accurate read-out of the information stored on the optical disc, it is necessary to be able to move the objective lens in the focusing (i.e. perpendicular to the disc plane) or Z-direction, to focus the laser beam to a small spot on the exact position of the optical disc, to write or retrieve the information, and to position the beam on the exact center of the desired information track on the optical disc in the tracking (i.e. radial from the center of the optical disc) or Y-direction. The correction of focusing and tracking can be performed by moving the objective lens in the optical axis direction of the objective lens for focusing or in the direction perpendicular to the optical axis direction of the objective lens for tracking.

In these systems, the position of the objective lens in the focusing and tracking directions is usually adjustable by a control system, an actuator supports the objective lens and changes a position correction signal from a feedback control system into a movement of the objective lens. Most commonly, these actuators comprise a moving coil, a stationary magnet and a stationary yoke, wherein a magnetic field is generated in an air gap between the yoke and the magnet. U.S. patent No. 4,568,142 to lguma entitled "objective lens drive" describes an actuator of this type in which the actuator includes a rectangular magnet located within a U-shaped yoke. The yokes are spaced from each other by their opposing north poles, yet close enough to each other to form a magnetic circuit. A square focusing coil may be attached to the outside of the square objective lens, four tracking coils may be fixed to the corners of the focusing coil, and then the ends of the focusing coil are positioned within the air gap formed by each U-shaped yoke so that the focusing coil straddles the yoke. Since the focus coil must extend around these "center" or "inner" yoke plates, the coil cannot be wound as tightly as desired and the rigidity of the coil structure is compromised. Further, in this type of closed magnetic circuit design, locating the majority of the coil wires outside the air gap significantly reduces the efficiency of the actuator.

In many optical systems the coil stiffness in the air gap must be high and the coil decoupling resonance frequency should be above 10DHz and preferably above 25 KHz. In many types of previous actuator designs, a large number of coil wires are typically required in the magnetic air gap to achieve maximum efficiency of the motor. In order to place this large number of coils in the air gap and still accommodate the limited space constraints of the actuator design, the coils must be wholly or partially "freestanding", or must be wound on a bobbin that is as thin as possible. These types of coil structures have low stiffness and are typically decoupled at lower frequencies. The dynamic resonance properties of many actuator designs also cause the coil to unwind during operation.

Other actuator designs have used the same magnetic gap to improve the focusing and tracking motion forces so that the tracking coil can be glued to the focusing coil, or vice versa, in an attempt to save components, space and weight. In these types of designs, the decoupling frequency of the tracking coils, which are bonded to the separate focusing coils, is typically around 15KHz, significantly below the preferred decoupling frequency.

Focus detection

Optical recording and disc playback systems, such as those using optical storage discs, optical discs, or video discs, require precise focusing of the light beam that is directed onto the surface of the optical disc by an objective lens. The incident light beam is typically reflected by an objective lens and is then used to read out the information stored on the optical disc. After returning through the objective lens, a portion of the reflected beam is typically directed to a device designed to measure the focus of the beam impinging on the optical disc, by which device the information extracted from the reflected beam can be used to adjust the focus of the impinging beam by changing the position of the movable objective lens relative to the optical disc.

A number of techniques are known for detecting the focus of an illuminating beam. For example, U.S. patent nos. 4,423,495; 4,425,636, respectively; and 4,453,239 use a method of determining the focus of the beam called a "critical angle prism". In this method, an illumination beam reflected by a storage disc is made incident on a detection prism surface, which is disposed at a position very close to a critical angle with respect to the reflected illumination beam. When the focus of the light beam irradiated on the surface of the optical disc deviates from a desired state, a focus error signal may be obtained using a change in the amount of reflected light energy from the surface of the detection prism to adjust the focus of the irradiated light beam.

The critical angle prism approach typically requires precise adjustment of the orientation of the detection prism surface relative to the reflected beam. This requirement arises as a result of the reflective nature of the detection prism near the critical angle, which makes the focus error detection system based on this approach extremely sensitive. However, the critical angle technique has some disadvantages. First, the focus error signal is generated depending on the reflection of light at the interface between the surface of the detection prism and the air, so that a change in height changes the refractive index of the air, which causes a mis-focus readout (offset) to occur. Furthermore, the critical angle technique itself is not suitable for use in a system with poor focus detection.

Poor systems are becoming increasingly important because they can eliminate some types of noise that may be present in optical disc drive apparatus. The critical angle approach is not suitable for poor operation for two reasons. First, the transmitted beam produced by the detection prism is compressed along one axis, which makes it asymmetric with the reflected beam, and two beams that are symmetric are preferably chosen in the differencing system to determine the best characteristics for noise cancellation under varying conditions. Second, at some point on the critical angle prism reflectivity curve where the two beams are intensity balanced, the slope is too low to produce a useful differential focus error signal.

The focus detection means when compared to the critical angle technique disclosed in us patent No. 4,862,442, requires only a small and precise adjustment of the optical surface on which the reflected light beam is incident, in particular where the optical surface comprises a multi-layer dielectric coating having a reflectivity which varies continuously with respect to the angle of incidence of the reflected light beam, whereby it can be seen that rotational misalignment of the surface consisting of the multi-layer dielectric coating will have a smaller effect on the value of the focus error signal and the technique will also reduce the sensitivity of the angle. Furthermore, inaccuracies in the focus error signal produced by the multilayer dielectric system can occur with relatively small variations in the scanning beam wavelength. This sensitivity to wavelength variations is undesirable because the focus error signal is designed for focusing only of the illumination beam.

In addition, some systems using multilayer dielectric reflective surfaces provide a focus error signal that has only limited sensitivity. For example, FIG. 37 of U.S. Pat. No. 4,862,442 shows a particular reflectivity profile for a multilayer dielectric reflective surface whose slope of the reflectivity profile is proportional to the sensitivity of the focus error signal. The disclosed reflected intensity is in the range of about 0.75 to 0.05 at 42 to 48 degrees of incidence. This change in reflectivity is about a 10% angle, producing a relatively low sensitivity focus error signal.

There is therefore a need in the art for an optical device featuring a reflectivity profile that produces a highly sensitive focus error signal that is relatively insensitive to height variations and to color differences and that can be used in differential systems.

Tracking actuation

Optical data storage systems that use a focused laser beam for information recording and instant replay are attractive in the computer mass storage industry. Such optical data storage systems provide very high data rates with very high storage densities and provide fast random access to the data stored on information media, most commonly optical discs. In these types of optical disc storage systems, reading and writing data is typically accomplished using a single laser source that functions at two corresponding intensities. During each operation, light from the laser source passes through the objective lens, which focuses the beam onto a particular focal point on the optical disc. During data retrieval, the laser light is focused on the recording medium and is altered by the information of the data storage medium. The light is then reflected by the disc back to the objective lens, through the objective lens, and onto the photodetector. It is the reflected signal that transmits the recorded information. It is therefore particularly important that the objective lens and the focused beam with which information is read from the storage are focused precisely on the center of the correct track when writing information or reading information from the storage, so that information can be written and retrieved accurately.

In order to obtain accurate reading of information stored on an optical disc, it is necessary to be able to move the objective lens in the focusing (i.e., perpendicular to the plane of the optical disc) or Z-direction in order to focus the laser beam into a small spot on the exact location of the optical disc for writing or retrieving information, and to be able to move the objective lens in the tracking (i.e., upward) or Y-direction to position the beam on the kirsch center of the desired information track on the optical disc. The focusing and tracking correction can be performed by moving the objective lens in one of the further directions of the optical axis of the objective lens for focusing, or by moving the objective lens in a direction perpendicular to the optical axis for tracking.

In these systems, the position of the objective lens in the focusing and tracking directions is usually adjusted by means of a control system. The actuator supports the objective lens and changes a position correction signal from the feedback control system into a movement of the objective lens. As is known, not focusing light on a sufficiently small medium area will result in an excessively large disc portion being used for storing certain information or in an excessively large disc area being read out. Likewise, the inability to precisely control laser tracking will result in information being stored at the wrong location, or information at the wrong location being read.

In addition to switching along the Z-axis to achieve focus and switching along the Y-axis to achieve tracking, there are at least four ways of assisting motion for the actuator, each of which reduces the accuracy of the read and write operations and which is undesirable during normal operation of the system. These undesired modes of motion are rotation about the X-axis (orthogonal axes to both the X-direction and the Z-direction), or tilting; rotation about the Z axis, called yaw; rotation about the Y axis, called scrolling; and linear motion along the X-axis, or tangential translation. Movement in these directions is typically due to the motor and reaction forces acting on the cartridge and/or actuator. These movement patterns typically produce undesirable movements during tracking or focusing operations that can affect the alignment of the objective lens with respect to the optical disc.

An achromatic prism system is synthesized.

Optical disc systems typically use a combining prism for elliptically shaping the laser beam, for eliminating laser beam astigmatism, and/or for beam steering. References such as U.S. patent No. 4,333,173 to Yoneza-wa et al, U.S. patent No. 4,542,492 to letherme et al, and U.S. patent No. 4,607,356 to Bricot et al describe the use of a simple combining prism to form a light beam in optical disc applications.

Typically, synthetic prism systems have embedded films. To reflect part or all of the return beam (reflected by the optical medium) to the detection system. Us patent No. 4,573,149 to Deguchi et al describes the use of a thin film to reflect a return beam to a detection system. Further, as described in U.S. patent nos. 4,542,492 and 4,607,356, the entrance face of a combining prism is typically employed to reflect the returning light beam to a detection system. In general, it is preferred to have multiple detection channels. For example, in the case of an optical disc, one detector may provide data signals and the other detector may provide control signals, such as tracking and/or focus servo signals.

A typical problem with conventional prisms is that the composite prism is subject to chromatic dispersion which causes chromatic aberration in the transverse direction, in other words, as the wavelength of the light source changes, the resulting angle of refraction through the composite prism also changes. These variations can cause lateral beam displacement when focusing a light beam onto an optical medium such as an optical disc. In optical disc systems, small shifts of the light beam may cause erroneous data signals, e.g. if the shift is sudden and in the data direction, the light beam may jump over the data recorded on the optical disc.

If the light source (e.g., laser) is truly monochromatic, chromatic aberration of the prism will not cause problems. However, several factors often cause variations in the laser spectrum. For example, most laser diode responses vary with wavelength as power increases. In magneto-optical disc systems, the power increase occurs when the laser is pulsed from a low to a high power in order to write to the disc, as is well known in the art. This increase in laser power typically produces a wavelength shift of around 1.5 to 3 nanometers (nm) in a common system. More laser diodes also exhibit wavelength variations with temperature variations. In addition, random "mode hopping" can cause unpredictable wavelength variations, typically in the range of 1-2 nanometers. RF modulation is typically applied to a laser diode operating at read power to reduce the effect of "mode hopping" present on the system. However, RF modulation increases the spectral bandwidth and can change the center frequency, and is not typically used when the laser is operated at write power. In non-achromatic systems, transient variations in the wavelength of the incident light typically result in lateral beam shifts of the focused spot of a few hundred nanometers, which can cause significant errors in the data signal.

Beam correction of chromatic dispersion using a multi-element prism system is well known in the field of optical design. This approach is discussed in lessons, as described by Warren J.Smith, modern optical engineering, published by McGraw-Hill, 1966, pages 75-77. Further, some optical disc systems use a multi-element compound prism system, which is achromatic. However, the present representative multi-element prism system requires the separate installation of multiple prism elements, which adds expense and difficulty to manufacture, since each element must be carefully aligned with respect to the other elements in the system, and small deviations in alignment can cause significant variations in functionality, which also complicates quality control. Other prior art multi-element prism systems mount the elements as a single prism, but these prism systems require that the prism material for each prism be different in order for the system to be achromatic. Finally, the achromatic prior art system does not provide reflection of the return beam for the multiple detection system.

Data retrieval-transformation (Transition) detection

Various types of recordable and/or removable media have been used for data storage purposes for many years. Such media may include, for example, magnetic tape or disk in systems having various configurations.

Magneto-optical ("MO") systems are used to record data onto and retrieve data from magnetic disks. The process of recording in a magneto-optical system typically involves using a magnetic field to determine the polarity of a prevalent area on the disk while heating a localized area in the laser pulse, thereby fixing the polarity of the localized area. The local areas with fixed polarity are often referred to as pits. Some encoding systems use the presence or absence of pits on the disc to determine recorded data as "1" or "0", respectively.

When recording data, a binary input data sequence may be transformed by digital modulation into a different binary sequence having more desirable characteristics. For example, a modulator may transform m data bits into a codeword with n modulation code bits (or "digits"). In most cases, there are more code bits than data bits, i.e., m < n.

The density ratio for a particular recording system is typically expressed in terms of the formula (m/n) × (d +1), where m and n are determined as described above, and d is determined as the minimum number of occurrences of zero between 1. Thus, according to the above formula, the RLL 2/7/1/2 code has a density ratio of 1.5, and the GCR 0/3/8/9 code has a density ratio of 0.89.

To read data in MO systems, a focused laser beam or other optical device is typically directed onto the recording surface of a rotating optical disc such that the laser beam is selectively accessible on one of a plurality of tracks on the recording surface. The rotation of the laser beam reflected by the recording surface can be detected by rotation by Kerr. For example, a first pattern of Kerr rotational changes is represented as a first binary value and a second pattern of Kerr rotational changes is represented as a second binary value, then the output signal is generated from the first and second binary values generated at specific clock intervals.

While there is a continuing need for optical disc systems capable of storing ever increasing data densities, the ability to achieve high data storage densities has encountered certain limitations. In general, a reasonable upper limit for data density is determined in part by reliability requirements, the wavelength of light of the laser diode, the quality of the optical modulation, hardware cost, and speed of operation. Maximum data density is also affected by the ability to suppress various forms of noise, interference and distortion. For example, the greater the density of the loaded data, the greater the intersymbol interference may prevent accurate recovery of the data. In addition, since many of the transitional high-performance disc drive technologies have been limited to compatibility with legacy machines, signal processing techniques do not improve as rapidly as they could.

Existing magneto-optical read channels and other types of disc drive devices typically suffer from a number of problems when attempting to recover the stored data, due to the unintended presence of a DC component in the read signal. One reason for the occurrence of DC is due to the fact that asymmetric data patterns are recorded over many bytes or data segments. The symmetric data pattern can be authored as a pattern that averages a DC component of zero over a region of interest. However, since some sequences of recording bits are substantially random in many modulation codes, local areas of recorded data having special patterns of 1's and 0's will produce an asymmetric read signal with an unwanted DC component. Since the data pattern varies in time, the level at which DC appears will also vary, causing DC baseline drift, reduced threshold detection edges, and increased susceptibility to noise and other disturbances.

The undesired DC may also occur due to a change in pit size due to thermal effects acting on the writing laser or the storage medium. For example, an increase in spot size causes the pits to widen as the write laser heats up. When reading a recorded pit, the variation of the pit size will result in an asymmetric input signal having a DC component. Variations in pit size not only produce an undesirable DC but also cause instantaneous shifts in the relative position of the data, reducing the timing margin and leading to possible read errors.

Various attempts have been made to overcome the above problems, for example, various tape drive systems typically use DC-free codes, such as 0/3/8/10 codes, otherwise referred to as 8/10 codes. Since the 8/10 code requires 10 storage bits to produce 8 data bits, however, it is only 80% effective when attempting to record high density data, which is a disadvantage.

Another method of controlling DC generation includes using double differentiation. Such a method typically comprises detecting a peak of the first derivative of the input signal by detecting a zero crossing of the second derivative of the input signal. Thereby efficiently filtering out the DC component. One disadvantage of this approach is that differentiation or double differentiation can cause undesirable noise effects. A second drawback is that this approach may reduce the timing margin to an unacceptably low level (e.g., up to 50%).

In another approach to seeking DC presence, the data to be stored is randomized prior to recording so that the data pattern does not repeat over the data segment. However, this approach is not accepted by the ISO standard and may lack downward compatibility with previous disc drive systems. A further disadvantage of this approach is that it can be complicated to standardize the data.

Yet another method to control the occurrence of DC involves the use of so-called resync bytes between data segments. Such methods typically include inspecting and processing the data prior to recording it in order to reduce the occurrence of DC during playback. Before recording, two adjacent data segments are examined to determine whether the 1 and 0 pattern produces a positive DC, negative DC or no DC component upon playback. For example, if two adjacent data segments have the same DC polarity, one of the data segments is inverted before recording to the medium. However, in order to remain within the limits of a particular encoding system, it is necessary to write a resync byte between data segments so that a pattern of adjacent bits and flux reversals is appropriate. A disadvantage of this approach is that it will unnecessarily reduce all DC formation and the time constant must be determined so that the predictable DC formation will not affect performance. In addition, this method requires additional overhead, which includes a check of the data segments to determine their relative polarity.

Therefore, there is a need for a method and apparatus for reading stored data from a medium without suffering from undesirable DC formation, without generating unacceptable noise levels or significantly reduced timing levels, without requiring significant overhead or de-randomization algorithms, and while providing high data storage efficiency. Other aspects of data storage and data retrieval.

Recordable/removable optical discs are now available for use as data storage media. Magneto-optical recording is a commonly used technique for storing data on and/or retrieving data from optical discs. During recording, the magnetic field determines the polarity direction of a normal area on the disc, while a local area is heated in the laser pulse, thereby fixing the polarity of a smaller area, the local area with fixed polarity being commonly referred to as a pit. Some encoding systems use the presence or absence of pits on the optical disc to determine whether the recorded data is "1" or "0", respectively. For such pit-type recording, the most common coding system is the Run Length Limited (RLL)2.7 code, since it gives the highest data-to-pit ratio. However, this recording pattern does not result in higher densities, since the amplitude and timing margins decrease rapidly with increasing frequency.

A digital servo lead/lag compensation circuit is disclosed herein, which is suitable for use in a servo mechanism. The compensation circuit has a minimal effect on the phase and has a notch filter at a frequency that is half the digital sampling frequency. The compensation circuit uses a single lead, compound lag. The values of the compensated circuit and the digital sampling frequency are selected so that the compensation circuit has a filter notch frequency at the servo mechanical resonant frequency.

In particular, an optical disc drive system according to the present invention includes an optical assembly, a light source capable of transmitting light through the optical assembly, an objective lens subassembly for controlling light by the light source between the optical assembly and each information storage medium, an objective lens provided in the objective lens assembly, an actuator assembly suspending the objective lens subassembly for relative movement with the actuator assembly, a first servo motor for moving the objective lens subassembly in a tracking direction with respect to the actuator assembly, a second servo motor for moving the objective lens subassembly in a focusing direction with respect to the actuator assembly, a third servo motor for moving the actuator assembly in the tracking direction with respect to each medium, first electronics for controlling the first, second and third servo motors, a motor for moving each medium with respect to the objective lens subassembly, a motor for supporting each medium with a hub assembly, a light detector disposed in the path of light returned by each of the media, second electronic means responsive to the output signal of the light detector for decoding information carried in the light returned by each of the media, third electronic means for enabling the light source to emit light at a first intensity level to encode information on each of the media and read the encoded information at a second intensity level, data receiving means for receiving data storable on each of the media, data encoding means responsive to the data receiving means for reproducing data stored in a predetermined format, and data encoding means for directing data to the third electronic means, a magnetic field generator for generating a magnetic field on a portion of each of the media and for cooperating with the third electronic means and the light source to write and erase on each of the media, a cartridge loading assembly for movably positioning each of the media on the motor hub assembly, servo error detecting means connected to the first electronic means and provided on a light return path from each medium for detecting a return light characteristic varying with a position of the objective lens with respect to each medium, and a housing structure for positioning respective parts of the optical drive system with respect to each other. Each medium may be in the form of a disc having a number of data segments.

The first intensity level of the optical drive system according to an embodiment of the invention comprises a first write intensity level, a second write power level and a third write power level. According to another embodiment of the invention, the third electronic device comprises a preamplifier to drive the light source at the readout level. Other embodiments of optical systems according to the present invention include a mechanical isolator for absorbing mechanical energy having means for receiving the pole block assembly for movement therewith and means for providing an emergency stop upon contact with a structure that moves relative to the isolator. One embodiment of a mechanical insulation according to the invention is a boot (shoe) with a portion of the structure therein protected by waves within the shell structure, or a device for emergency stop contact with an object moving relative to the insulation. Or both such a boot and emergency stop device. Boots according to the present invention may include compression ribs thereon to absorb compressive forces acting on the boot.

The optical drive system of the present invention may alternatively be equipped with a mechanical isolator having a first means for mitigating undesired mechanical forces acting on the movable disk drive component, and a second means for supporting the first means between the drive portion and the source of unwanted mechanical forces, thereby providing mechanical isolation of the drive component. In this embodiment, the first means is a shock absorber which may be fitted with at least one compression rib, and the second means comprises a housing which is adapted to be fitted to the end of the pole block assembly. The first means is preferably comprised of a material that exhibits minimal creep and may be selected from the group consisting of silicone rubber, polyurethane and injection molded plastic. The first device is also equipped with a shock-absorbing and mechanical isolation in the form of an emergency stop, which is adapted to prevent the movable carriage from hitting a solid surface. Thermal expansion is also compatible with this aspect of the invention.

According to another aspect of one of the embodiments of the optical drive system according to the invention, the third electronic device further comprises a Colpitts type oscillator having a load circuit with an increased resistance. The load circuit preferably includes an inductor. The oscillator of the present embodiment has an increased power supply voltage, thereby facilitating an increase in r.f. modulation amplitude and a reduction in ringing. The third electronic device further includes a transistor having an emitter, a base, and a collector; a voltage source and a load resistor connected in series between the collector and the power source such that oscillator ringing is mitigated when a write pulse is supplied to the oscillator. The load inductor is preferably connected in series with the load resistor, and the write pulse is supplied to a junction between the load resistor and the load inductor. One embodiment of the third electronic device is to have a split capacitor tank circuit connected between the collector and ground across the emitter and collector of the transistor. The light source used with this embodiment of the invention is a laser, with the third electronic device further including a switch for passing current to the laser, and the digital logic device switching power to drive the laser with the switch, such that power is consumed only when the laser is energized, and improved up-down switching performance is achieved.

In a particular practical application, the first electronic device and the servo error detecting means further comprise an analog-to-digital converter having a reference voltage input, a clock input, an analog input, and a digital output, an information detecting means having a plurality of detection outputs for controlling the first, second, and third servo motors based on the detected information; a signal adding circuit having a sum signal output connected to the reference voltage input of the analog-to-digital converter and having a plurality of inputs connected to the plurality of sense outputs of the sensing device; a servo error signal circuit having a servo error signal output and a plurality of inputs, wherein the plurality of inputs are connected to the plurality of outputs of the detection means, the servo error signal output is a combination of the plurality of inputs and a portion of the sum signal output, the servo signal output is connected to the analog input of the analog-to-digital converter for conversion; a sampling clock connected to the clock input for controlling the converter to convert the servo error signal to a digital signal, which is normalized to a sum signal output; and a processing circuit having an input terminal connected to the digital output terminal and an output terminal of the analog-to-digital converter for controlling the servo motor.

In an alternative preferred embodiment, the first electronic means and the servo error detection means comprise an analog-to-digital converter having a reference voltage input, a clock input, an analog input and a digital output; a switch including first and second input terminals, an output terminal, a control input terminal for alternately connecting the first and second input terminals to the output terminal to supply an output thereof to the reference voltage input terminal; an information detecting device having a plurality of detection outputs for controlling the first, second and third servo motors based on the detected information; a signal summing circuit having a sum signal output connected to the first input of the switch and having a plurality of inputs connected to the plurality of sense outputs of the sensing device; a direct current voltage reference connected to the second input terminal of the switch; a control clock connected to the control input of the switch for activating the switch at a predetermined rate, thereby combining the sum signal and the dc voltage reference at the reference voltage input; a servo error signal circuit having a servo error signal output and a plurality of inputs, wherein the plurality of inputs are connected to a plurality of detection outputs of the detection device, the servo error signal output is a combination of the plurality of inputs and a portion of the sum signal output, and the servo signal output is connected to an analog input of the analog-to-digital converter for conversion; a sampling clock connected to the clock input terminal to control the converter to convert the servo error signal into a digital signal, which is normalized to a sum signal output, when the first input terminal of the switch is connected to the output terminal; and a processing circuit having an input connected to the digital output of the analog-to-digital converter and an output for controlling the servo motor. According to an aspect of this embodiment of the invention, the converter further comprises a plurality of analog inputs and a selection input for selecting one of the analog inputs for conversion. Preferably, the rate of the control clock is substantially equal to the sampling clock rate, and the analog input of the converter is selected in conjunction with the control clock such that the selectable servo error signal is converted and normalized to the sum signal at each additional sampling clock cycle.

Compression ribs are preferably provided on the shoe to absorb compressive forces acting thereon, and the oscillator has an increased supply voltage, thereby facilitating an increase in r.f. modulation amplitude and a reduction in ringing.

In another embodiment of an optical drive system according to the invention, the system comprises an optical assembly, a light source capable of transmitting light through the optical assembly, an objective lens subassembly for directing light from the light source between the optical assembly and each information storage medium, an objective lens disposed in the objective lens subassembly, light detection means disposed in the path of return light from each medium for measuring the total amount of light received by each medium, an actuator assembly suspending the objective lens subassembly for relative movement with the actuator assembly, means for monitoring loops and signals, a first servo motor for moving the objective lens subassembly in a tracking direction relative to the actuator assembly and for moving the objective lens to a first position upon focus capture, for moving the objective lens away from the first position to each medium to be read while searching for a maximum loop and signal, and for returning the objective lens from each medium, second servo motors for moving the objective lens sub-assembly relative to the actuator assembly in the focus direction, a third servo motor for moving the actuator assembly relative to the media in the tracking direction, first electronics for controlling the first, second and third servo motors, a motor for moving the media relative to the objective lens sub-assembly, the motor having a surface for supporting the media, second electronics responsive to signals output by the light detection means for decoding information carried in light returned by the media, third electronics for enabling the light source to emit light at a first intensity for encoding information on the media and at a second intensity for reading the information encoded thereon, data receiving means for receiving data storable on the media, data encoding means responsive to the data receiving means for reproducing the stored data in a predetermined format, data encoding means for transmitting data to the third electronic means, writing means for writing information on the media together with the third electronic means, a cartridge loading assembly for movably positioning the media on the motor surface, servo error detection means connected to the first electronic means and arranged in the path of light returned by the media for determining when the total light exceeds half of the measured peak value, for searching for a first zero crossing determined when the Quad Sum signal exceeds half of the peak amplitude, and for indicating to the first electronic means when the Quad Sum signal exceeds half of the peak amplitude for operating the completion of focusing by the second servo motor, and a housing structure for positioning the components of the optical drive system relative to each other. In a preferred embodiment of this aspect of the invention, the digital logic device comprises a CMOS buffer connected between electrical ground and the full supply voltage, and the switch comprises a bypass transistor. In embodiments using a disc medium, an amplifier is provided to evaluate a particular one of the sections to determine if the particular section is blank, and means are provided to prevent the amplifier from operating at maximum gain while evaluating the particular section. In practice, the means for disabling the amplifier may comprise a microprocessor for setting the AGC level of the amplifier.

In this embodiment of the invention, the first electronic means and the servo error detection means may be implemented as described above. In an embodiment, the optical drive system according to the invention may comprise a biasing coil arrangement for the magnetomotive generator. The bias coil means will comprise a winding; a return yoke having a body portion on which the windings are wound and a tip end with a flange protruding from the body portion overlying the winding surface; a first plate is arranged on the winding and provided with a first flange extending substantially perpendicularly to the first plate; and a second plate disposed on the winding on the magnetic circuit having the first plate and the return yoke, whereby the first flange radiates heat energy generated by the device when the winding is energized.

In embodiments using this aspect of the invention, the return yoke projects above the winding surface, the first plate has apertures allowing the return yoke to project therefrom, and at least one of the first or second plates includes a plurality of side flanges. Preferably, the side flanges are darkened to increase their heat radiation.

Alternatively, different embodiments of the optical drive system according to the invention may comprise a bias magnetic field generating means for directing a magnetic field through the spatial region. The bias field generating means will similarly comprise a winding for carrying current; a return yoke having a body around which the winding is wound and a tip having a flange which extends outside the body to overlie the winding surface; a first plate is disposed over the winding and has a plurality of vertical fingers extending from the winding, wherein the vertical fingers radiate thermal energy; a second plate disposed under the winding; a first pole piece having a magnetic flux in communication with the first plate; a second pole piece having a magnetic flux in communication with the second pole plate, a first end of the second pole piece being opposite the first end of the first pole piece through a region of space subject to the magnetic field. To use this aspect of the invention in embodiments, first and second plates are attached to the second ends of the first and second pole pieces, respectively, whereby the windings, return yoke, first and second plates are distanced from the main space region. Preferably, the return yoke projects from the winding surface, the first plate has apertures which allow the projecting return yoke to pass through, and the first plate includes a plurality of side flanges. The side flanges of the first plate are preferably aligned with the side flanges of the second plate. In a particular embodiment, the return yoke comprises an elongated rod and the distal end comprises a first end flange connected to a first end of the rod and a second end flange connected to a second end of the rod.

Other objects, advantages and features of the present invention will become more readily apparent to those skilled in the art from the following description and accompanying drawings. Brief description of the drawings

Fig. 1 is a perspective view of an optical disc drive apparatus embodying the present invention;

FIG. 2 is a top view of the optical disc drive apparatus of FIG. 1 with the drive apparatus housing removed;

FIG. 3 is a cross-sectional view of the optical disc drive apparatus of FIG. 1 taken in the direction of arrows 3-3 of FIG. 1;

FIG. 4A is a top view of an optical assembly of the optical disc drive apparatus of FIG. 1;

FIG. 4B is an optical path diagram of the optical disc drive apparatus of FIG. 1;

FIG. 5 is a system block diagram of an electronic device of the optical disc drive apparatus of FIG. 1;

fig. 6 is another perspective view of the optical disc drive apparatus with a disc cartridge to be inserted;

FIG. 7 is an exploded perspective view of the optical disc drive apparatus of FIG. 6 depicting the major subassemblies thereof;

FIGS. 8A and 8B are perspective views of the substrate depicted in FIG. 7;

FIG. 9 is a top view of the drive of FIG. 6 with parts removed to better illustrate the tiller, tiller drive gears, the motor driving these gears, and the operational relationship between these parts;

FIGS. 10A-10F are front and perspective views of the tiller;

11A-11C include front and perspective views of the left slider;

FIGS. 12A-12E are front and perspective views of the right slider;

FIG. 13 is a top plan view of the park arm in two positions, shown in plan, illustrating the act of parking the carriage behind the drive, with the drive at rest;

FIG. 13A is a perspective view of the optical disc drive apparatus of FIG. 1, particularly illustrating a fine actuator assembly holder supporting an optical device for focusing a laser beam on a data track of an optical disc;

FIGS. 14A-14C include front and perspective views of the parking arm;

fig. 15A and 15B are perspective views of the disk cartridge receiver;

FIGS. 16A and 16B are front elevation views of the drive unit of FIG. 6 with parts removed during cartridge insertion to better illustrate the release tabs, latches, and the operative relationship between these parts on the right door chain;

FIGS. 17A and 17B are perspective views of the latch which holds the cartridge receiver in an upward position;

FIG. 18 is a perspective view of a biasing coil assembly clamping device;

FIG. 19 is a perspective view of a biasing coil assembly;

FIG. 20 is a principal exploded view of the component biasing coil assembly;

FIG. 21 is a perspective view of a pivot rod or rail rotatably supporting a biasing coil assembly;

FIG. 22 is a perspective view of a bias coil assembly that may be mounted thereto and in turn mounted to the pivot rod depicted in FIG. 21;

Fig. 23 is a right side elevational view of the cartridge receiver and cartridge just before the cartridge eject operation is initiated, depicting the optical disc being mounted in an operative position on the spindle;

FIG. 24 is a right side elevational view of the cartridge receiver and cartridge during a cartridge ejection operation, depicting the cartridge unlatched and the disk disengaged from the spindle;

FIG. 25 is a right side elevational view of the cartridge receiver and cartridge during cartridge ejection, depicting the cartridge loading system in an upward position and the optical disc beginning to be ejected from the disc drive apparatus;

FIG. 26 is a schematic perspective view of an actuator according to the present invention;

FIG. 27 is a perspective view of a lens holding frame of the actuator of FIG. 26;

FIG. 28 is a perspective view of the actuator of FIG. 26 used with a recording system within a field housing;

FIG. 29 is a top plan view of the recording system of FIG. 28;

FIG. 30 is a right side elevational view of the recording system of FIG. 28;

FIG. 31 is a front elevational view of the recording system of FIG. 28;

FIG. 32 is a schematic view showing the magnetic fields generated by the actuator magnet pair of FIG. 26;

FIG. 33 is a perspective view of the focusing coils and permanent magnets of the actuator of FIG. 26;

FIG. 34 is a schematic cross-sectional view of the focusing coil and permanent magnet of the actuator of FIG. 26 taken along section line 34-34 of FIG. 33, illustrating the focusing force acting on the actuator;

FIG. 35 is a schematic cross-sectional view of the actuator tracking coil and permanent magnet of FIG. 26 illustrating the tracking force acting on the actuator;

FIG. 36 is a block diagram representation of a preferred embodiment of the beam focus detection apparatus of the present invention;

FIG. 37 is an enlarged top cross-sectional view of a differential version of the inventive beam splitting assembly (FTR prism);

FIG. 38 is a front view of first and second loop detectors included in the focus detection apparatus of the invention;

FIG. 39 is a graph showing reflectivity of an FTR prism as a function of servo beam incident angle;

FIG. 40 is a graph of the value of the differential focus error signal produced by a preferred embodiment of the apparatus of the present invention as a function of the position of the objective lens relative to the optical disc;

FIG. 41 schematically illustrates a representative optical read/write system in which the disk carrier and actuator assembly of the present invention can be used;

FIG. 42 is a perspective view of the carriage and actuator assembly;

FIG. 43 is an exploded view of the carriage and actuator assembly;

FIG. 44 is an exploded view of the actuator;

FIG. 45 is a schematic top view illustrating a large coarse tracking force acting on a component;

FIG. 46 is a side view further illustrating a large coarse tracking force;

FIG. 47 is an exploded view showing the focusing force acting on the actuator;

FIG. 48 is an exploded view showing fine tune tracking forces acting on the actuator;

FIG. 49A is a schematic top view showing the symmetry of a large coarse tracking force in a horizontal plane;

FIG. 49B is a schematic side view illustrating the symmetry of a large coarse tracking force in a vertical plane;

FIG. 50A is a schematic top view showing the symmetry of fine tuning the tracking force in the horizontal plane;

FIG. 50B is a schematic end view showing the alignment of the net fine tracking force with the center of mass of the fine tracking motor;

FIG. 51A is a schematic top view showing the symmetry of fine tuning tracking of the reaction force in the horizontal plane;

FIG. 51B is a schematic end view showing alignment of the net fine tracking reaction force with the center of mass of the fine tracking motor;

FIG. 52A is a schematic side view showing the symmetry of the focusing force in the horizontal plane;

FIG. 52B is a schematic end view showing the alignment of the net focusing force with the optical axis of the objective lens;

FIG. 53A is a schematic side view showing the symmetry of the focusing reaction in the horizontal plane;

FIG. 53B is a schematic end view showing the alignment of the net focus reaction force with the objective lens optical axis;

FIG. 54 is a schematic top view showing the deflection force and the fine tune motor reaction force generated in response to the deflection force;

FIG. 55A is a schematic side view showing the symmetry of the carriage levitation force in the horizontal plane;

FIG. 55B is a schematic end view showing alignment of the net carriage levitation force with the optical axis of the objective lens;

FIG. 56A is a schematic top view showing the symmetry of friction forces in a horizontal plane;

FIG. 56B is a schematic side view showing the frictional force aligned with the center of mass of the carrier;

FIG. 57 is a schematic end view showing the net inertial forces acting on the center of mass of the fine adjustment motor and the center of mass of the carriage corresponding to vertical acceleration;

FIG. 58A is a schematic side view showing the alignment of the net inertial force of the fine adjustment motor with the optical axis of the objective lens;

FIG. 58B is a schematic side view showing alignment of the net inertial force of the carriage with the optical axis of the objective lens;

FIG. 59A is a schematic top view showing inertial forces acting on components of the carriage and actuator assembly for horizontal acceleration;

FIG. 59B is a schematic top view showing the net inertial force for horizontal acceleration;

FIG. 60A is a schematic end view showing the inertial forces of the fine adjustment motor and carriage for acceleration above the flexure arm resonant frequency;

FIG. 60B is a schematic end view showing inertial forces of the fine adjustment motor and carriage for acceleration below the flexure arm resonant frequency;

FIGS. 61A-61D are graphs showing fine tracking position versus fine motor current;

FIGS. 62A-62C illustrate the effect of asymmetric focusing forces acting on the assembly;

FIG. 63 shows an alternative embodiment of a carriage and actuator assembly;

fig. 64 shows the operation of the actuator to move the objective lens holder in the focusing direction;

FIG. 65 illustrates the operation of the actuator to move the objective holder in the tracking direction;

FIG. 66 depicts a simple synthetic prism and shows the effect of dispersion in the prism;

FIG. 67 shows a prior art multi-element compound prism system;

FIG. 68 shows a representative air-spaced prism system in accordance with the present invention;

FIGS. 69 and 69A illustrate one embodiment of an air-spaced multi-element prism system of the present invention;

FIGS. 70, 70A and 70B show side, top and bottom plan views, respectively, of a plate prism of the embodiment of the prism system shown in FIG. 69;

FIGS. 71, 71A and 71B show side, top and bottom plan views, respectively, of a trapezoidal prism of the embodiment of the prism system shown in FIG. 69;

FIGS. 72 and 72A show side and plan views, respectively, of an optical surface of a color correcting prism embodiment of the prism system embodiment of FIG. 69;

FIG. 73 shows an alternative embodiment of an air-spaced multi-element prism system of the present invention;

FIGS. 74, 74A and 74B show side, top and bottom plan views, respectively, of the quadrilateral prism of the alternative embodiment shown in FIG. 73;

FIG. 75 is a block diagram representation of an optical data storage and retrieval system;

FIG. 76 is a series of Sample waveforms;

FIGS. 77A and 77B are waveform diagrams of symmetric and asymmetric input signals, respectively;

FIG. 78 is a block diagram of a read channel;

FIG. 79A is a detailed block diagram of stages of a read channel;

FIG. 79B is a detailed circuit diagram of a portion of an integrator stage;

FIGS. 80A-80E are graphs of frequency response of stages of a sense channel;

FIG. 80F is a group delay plot for each combination of stages in a read channel;

fig. 80G (1) -80G (4) are waveform diagrams showing signal waveforms at respective stages in a readout channel;

FIG. 81 is a block diagram of a peak detection and tracking circuit;

FIG. 82 is a schematic diagram of the peak detection and tracking circuit of FIG. 81;

FIG. 83 is a waveform diagram showing the tracking of a threshold signal through the input signal DC envelope;

FIGS. 84A-84D are graphs showing exemplary waveforms at various points in a read channel;

FIG. 85 is a block diagram representation of an optical data storage and retrieval system;

FIG. 86 is a series of waveforms representing uniform laser pulses in the pulsed GCR format, and non-uniform laser pulses in the RLL 2, 7 format;

FIG. 87 is a series of waveforms representing laser pulses for various data patterns adjusted by the write compensation circuit;

FIG. 88 is a schematic diagram showing a write compensation circuit;

FIG. 89 is a series of waveforms representing laser pulses with amplitude asymmetry correction;

FIG. 90 is a schematic diagram showing an amplitude asymmetry correction circuit;

FIG. 91 is a block diagram showing the basic relationship of the elements of the pulse thinning apparatus;

FIG. 92 is a series of waveforms representing threshold adjustment by a dynamic threshold circuit;

FIG. 93 is a schematic diagram of a dynamic threshold circuit;

FIG. 94 is a block diagram of an optical data storage and retrieval system incorporating downward compatibility;

FIG. 95 is a track layout diagram of a high-density optical disc;

FIG. 96 is a sector format diagram of a high-density optical disc;

FIG. 97 is a more detailed block diagram showing the read/write circuit diagram of FIG. 94;

FIG. 98 is a table for drawing each of 21 areas, tracks within an area, the number of sectors of each track within an area, the total number of sectors within an area, and the data writing frequency recorded in an area in the preferred format of the high-density optical disc;

FIG. 99 provides a table of equations for calculating the CRC bits for the ID field;

FIG. 100A is the top half of a table (Hex 00 to 7F) showing how 8-bit bytes on three address fields and on a data field, except for a resynchronization byte, are converted into channel bits on an optical disc;

FIG. 100B is the lower half of the table (Hex 80 to FF), which shows how the 8-bit bytes on the three address and data fields, except the resynchronization byte, are converted to channel bits on the disk;

FIGS. 101A to 119 are schematic electronic diagrams in a preferred embodiment of the invention;

FIG. 120 is a perspective view of a mechanical spacer and pole piece according to the first preferred embodiment;

FIG. 121 is a perspective view of the mechanical isolator in the second preferred embodiment;

FIG. 122 is a state diagram of a read mode firmware module for use with the present invention;

FIG. 123 is a state diagram of a write mode firmware module for use with the present invention;

FIG. 124 shows a Nyquist plot of the focus ring transfer function for selecting the number of closed ring peaks;

FIG. 125 is a graph of focus ring transfer function numerical response for an open and closed condition;

FIG. 126 is a graph of focus ring transfer function phase response for an open and closed condition;

FIG. 127 shows a graph corresponding to a focus compensation transfer function numerical response;

Fig. 128 shows a phase response curve of the focus compensation transfer function.

Description of the preferred embodiments

System overview: primary optical component, electrical and mechanical component

Referring initially to FIG. 1, an optical disc drive apparatus 10 is shown having a housing 14. The optical drive 10 may play and/or record a disc (not shown) placed in a removable optical disk cartridge 12. Alternatively, the optical disc may be placed in the housing 14 of the optical drive 10.

Referring now to FIGS. 2 and 3, wherein FIG. 2 shows a top view of the optical drive 10 with the housing 14 removed to show some of the important mechanical, electrical and optical components of the optical drive 10; FIG. 3 is a cross-sectional view of the optical drive 10 taken along line 3-3 of FIG. 1. In fig. 2, the base plate 16, the spindle 17, the linear actuator assembly 20, the objective lens carriage assembly 2, the optical assembly 24, the drive circuit board 26, and the flexible circuit connector 28 are shown. FIG. 3 shows the main circuit board 30, spindle motor 18, optics assembly circuit board 27, and drive circuit poles 26.

In short, the base plate 16 acts as a common base for the other components of the optical drive 10 and positions and aligns the components with each other, and the base plate 16 is preferably made of cast steel to reduce cost.

As shown in fig. 2, the linear actuator assembly 20 includes a pair of linear voice coil actuators 23, each voice coil actuator 23 being comprised of a rail 34 that is fixedly attached to the base plate 16. The rails 34 are substantially parallel to each other. Adjacent to each rail 34 is a pole piece 32, surrounding a portion of each pole piece 32 is one of the actuator coils 23, each actuator coil 23 being mounted on an opposing portion of the objective lens carriage assembly 22 such that when the coils 23 are selectively energized, the objective lens carriage assembly 22 will move along the rails 34. The actuator coil 23 is driven by a signal from a drive circuit board 26 which causes the objective lens carriage assembly 22 to move linearly relative to the optical assembly 24 and relative to an individual optical disc (not shown) inserted in the optical drive 10. In this manner, the objective lens carriage assembly 22 is enabled for coarse tracking of the disk.

The optical assembly 24 and the lens carriage assembly 22 together comprise the main optical components of the optical drive 10, the optical assembly 24 being fixedly mounted on the base plate 16 and comprising a laser, various sensing elements and optical components (not shown). In operation, the laser directs a beam from the optical assembly 24 toward the lens carriage assembly 22, and the optical assembly 24 sequentially receives a beam (not shown) returned by the lens carriage assembly 22. The lens carriage assembly 22 is mounted on the linear actuator assembly 20 as described above. The lens carriage assembly 22 contains a pentaprism (not shown), an objective lens (not shown), a servo motor (not shown) to focus the objective lens, and a servo motor (not shown) to fine-tune the position of the objective lens with respect to the linear actuator assembly 20 and the inserted optical disc to enable fine tracking of the optical disc. Electrical information and control signals are passed between the lens bracket assembly 22 and the circuit board 30 on the one hand, and between it and the drive circuit board 26 by means of the flexible circuit connector 28 on the other hand.

The optical assembly circuit board 27 contains a laser driver and a preamplifier (not shown). The drive circuit board 26 controls the spindle motor 18, the linear coil actuator 23 of the linear actuator assembly 20, and the servo motor of the lens carriage assembly 22. The drive circuit board 26 is controlled by a main circuit board 30. The main circuit board 30 includes most of the electronic components, and various design considerations (e.g., reducing noise, EMI, and power losses) need not be provided on the optical package circuit board 27 or the driver circuit board 26.

A spindle motor 18 is fixedly mounted on the base plate 16, and the motor 18 directly drives a spindle 17, which in turn rotates the optical disc.

An optical member: an optical assembly and an objective lens assembly.

Referring now to FIG. 4A, a top cross-sectional view of the optical assembly 24 is shown. The optical assembly 24 includes a housing 40, a semiconductor laser diode 42, a collimating lens 44, an achromatic prism 46, a synthetic expansion prism 48, a leakage beam splitter 49, a DFTR prism 50, a cylindrical lens 51, a readout lens 52, a microprism 54, servo detection sensors 56 and 58, a forward sensor 60, and a data detection sensor 62. These components are also shown in FIG. 4B, which shows the optical path diagram for laser beam 64. Fig. 4B shows the optical components of the optical assembly 24 working with the pentaprism 66 and objective lens 68 of the lens holder assembly 22. To facilitate the illustration of fig. 4B, a portion 70 of the laser beam 64 is shown between the pentaprism 66 and the objective lens 68, which is in the same plane as portions of the laser beam 64 that pass through the optical assembly 24. In practice, the pentaprism 66 is positioned to direct the laser beam portion 70 perpendicularly with respect to some portion of the laser beam 64 passing through the optical assembly 24.

With continued reference to FIG. 4B, it will be appreciated that, in operation, the laser beam 64 is a collimated beam produced by the lens 44 from a diverging beam emitted by the laser diode 42. The light beam 64 passes through the prisms 46 and 48, through the beam splitter 49 and out of the optical assembly 24 onto the lens holder assembly 22 where it passes through a pentaprism 66 and is focused on the disc surface by an objective lens 68.

Upon reflection from the optical disc, the reflected portion of the laser beam 64 passes back through the objective lens 68 and the pentaprism 66 and enters the optical assembly 24. A first portion of the beam 64 is reflected at the beam splitter interface between the prism 48 and the beam splitter 49, transmitted through the interface, focused by the readout lens 52, and enters the micro-prism 54 where the beam is divided by polarization into two portions, each of which is detected by the elements of the data detection sensor 62.

A second portion of beam 64 passes through beam splitter 49 and is internally reflected by combining prism 48. This second portion of beam 64 exits combining prism 48 and enters DFTR prism 50. In which this second portion of the beam 64 is split into two portions, each of which is focused by the cylindrical lens 51 onto a respective surface of a respective servo sensor 56 and 58. Accordingly, the sensors 56 and 58 generate signals that are directed to the optical assembly circuit board 27 where the signals are used to generate tracking and focus error signals. An electronic system: main circuit board, drive circuit board, and optical module circuit

Referring now to FIGS. 1, 2, 4A and 5, a system block diagram of the electronic subsystem of the optical drive 10 is shown in FIG. 5, wherein block 80 includes a read sensor preamplifier 82, a laser driver 84 and a servo sensor preamplifier 86. As shown in fig. 4A and 5, the read sensor preamplifier 82 is connected to the data detection sensor 62, and amplifies the signal generated by the data detector 62. Likewise, servo sensor preamplifier 86 is connected to servo detectors 56 and 58 and amplifies the signals generated by servo detectors 56 and 58. The laser diode 42 is connected to a laser driver 84 which provides a signal to drive the laser 42. The subsystems 82, 84 and 86 of block diagram 80 are grouped together on an optical package circuit board 27, which is located adjacent to the optical package 24. This reduces the distance that signals must be passed by sensor 62 to preamplifier 82 and by sensors 56 and 58 to preamplifier 86 to reduce the deleterious effects of noise on these signals. Since the signal generated by the laser driver 84 to drive the laser diode 42 has a relatively high frequency, good design practice requires positioning the laser driver 84 close to the laser diode 42.

Block 88 of FIG. 5 includes a spindle motor interface 90, a Mechanical Subassembly (MSA) interface 92, a position sensor interface 94, and a translation and display assembly 96. The components 90, 92, 94 and 96 of block 88 are disposed on the drive circuit board 26, the spindle motor interface 90 controls the spindle motor 18, and the MSA interface 92 interfaces with various display and switching components 96, including the front panel display, the ejection circuitry, and the switching with respect to the disk cartridge 12. The position sensor interface 94 is connected to the coil actuator 23 of the actuator assembly 20 and is powered by a power amplifier 102.

The remaining subsystems of the system block diagram of fig. 5 are provided on the main circuit board 30 shown in fig. 3. These subsystems include an analog read channel 100, encoder/decoder 104, SUSI chipset 106, buffer memory 108, and GLIC interface 110 and associated EEPROM 112. The main circuit board 30 also includes analog interface circuitry 114, a Digital Signal Processor (DSP)116, an embedded controller 118 and an associated RAM/EPROM 120. It should be noted that the optical drive 10 is a MO recordable drive and the power amplifier 102 also drives the bias coil 122.

Disc cartridge loading apparatus

Referring first to FIG. 6, a disk storage system is shown, generally designated 1-10. Figure 6 illustrates a replaceable disc cartridge 1-13 suitably positioned for insertion into an optical drive 1-10 comprising the disc loading and unloading apparatus of the present invention. The optical drive 1-10 includes a base 1-16 and a face plate 1-19, the face plate 1-19 including a tray receiving opening 1-22, a drive operation display lamp 1-25, and an eject button 1-28.

The optical disc system 1-10 is of the type having a focusing mechanism and a tracking mechanism, and further having a lens and a disc to be continued, wherein the mechanisms are controlled by a feedback loop, which preferably comprises an electronic circuit for generating servo signals for effectively calibrating the focusing mechanism and the tracking mechanism; first means for eliminating undesired mechanical forces acting on the movable optical drive component; and a second means for supporting the first means between the component and the source of the undesired mechanical force, thereby providing mechanical isolation of the component, these aspects of the invention will be described in more detail under a heading corresponding to the specific features of the invention.

The housing with the usual type of cartridge 1-13 includes an upper flat surface 1-31 and a lower flat surface 1-32 shown in figure 25. The cartridge 1-13 also has a label end 1-34 facing forward. In a preferred embodiment the forward label end 1-34 of the disc cartridge 1-13 is such that it is still visible to the user when the disc cartridge 1-13 is inserted into the optical drive 1-10. For example, the side walls 1-37 extend between the upper plane 1-31 and the lower plane 1-32, and the case further includes a rear wall 1-38 extending between the upper plane 1-31 and the lower plane 1-32 and parallel to the forward facing index end 1-34. Adjacent the label end 1-34 of the side wall 1-37 is a slot 1-40 for receiving a cartridge positioning pin 1-43 (fig. 8A-8B) located on the base plate 1-46.

The disc cartridge 1-13 also includes a cartridge door or shutter 1-49. The shutters 1 to 49 are sprung in the closed position by springs (fig. 6, 7 and 16). When the shutter 1-49 is open, it rests in the recess 1-52 of the upper plane 1-31. Since the optical drive 1-10 of the preferred embodiment reads both sides of the disc cartridge 1-13, the same shutters and recesses are also present on the lower flat surface 1-32, and these features are not shown in the drawings. The shutter typically has latches 1-55 (not shown) on the rear wall 1-38 of the cartridge 1-13.

Protected within the cartridge 1-13 is an optical disc 1-14 (fig. 23-25) having a metal hub 1-15. The optical discs 1-14 may be formed as a rigid substrate having a magnetic material coated thereon, as is known in the related art. Embedded in the layer of magnetic material are tracks of concentric or spiral ring shape. The magnetic cladding may be on one or both surfaces of a rigid substrate, and the coating may magnetically record data on the optical discs 1-14 by a magnetic transducer, commonly referred to as an optical head, and in the center of the rigid substrate is a metal hub 1-15.

Referring now to fig. 7, the main set of components within the optical drive 1-10 of the present invention comprises a bottom shell 1-16 in which a back plane 1-46 is placed. In fig. 7, the spindle motor 1-61 is shown mounted on the base plate 1-46. the spindle motor 1-61 comprises a spindle magnet 1-63 which attracts a metal hub 1-15 of an optical disc 1-14 (fig. 23-25) when the disc cartridge 1-13 is mounted in the optical drive 1-10. The displacement mechanism according to the invention is generally designated 1-67 and the displacement mechanism 1-67 comprises a left slide 1-70, a right slide 1-73 and a rudder stock 1-76, the displacement mechanism 1-67 being described more fully below. Also shown in fig. 7 are parking arms 1-79, which are positioned above left slide bar 1-70. The cartridge receiver is shown generally at 1-82, and in FIG. 7 is also shown a left door link 1-85, a right door link 1-88 and a receiving door 1-91, each of which is rotatably mounted on the cartridge receiver 1-82, in front of the cartridge receiver 1-82 is the drive panel 1-19. Finally, the rotatable magnetic bias coil assembly 1-94 is shown to be secured to a bias coil wall 1-97 with a bias coil clip 1-100 on the bias coil arm 1-97. These main components will be described in further detail later.

With continued reference to FIG. 7, it is shown that the bottom shell 1-16 includes side walls 1-103 and rear walls 1-106, and that on the inner base of the bottom shell 1-16 are four mounting locations 1-109 that may be used to secure the bottom panels 1-46. The bottom shells 1-16 will also house control electronics, which are not shown in the figure.

Referring now to fig. 8A and 8B, the structure of the bottom plates 1-46 will be described in further detail. The base plates 1-46 are mounted on the four mounting locations 1-109 (fig. 7) of the base shells 1-16, the base plates 1-46 having a plurality of components that are either molded in, embedded in, mounted to, or attached to the base plates, the base plates 1-46 being "stickers" that bring the plurality of components of the present invention together so that they interact. At the periphery of the floor panels 1-46, there are front walls 1-112, left outer side walls 1-115, left inner side walls 1-118, right outer side walls 1-121, right inner side walls 1-124, and rear vertical walls 1-127. The left and right exterior side walls 1-115, 1-121 each include a respective vertical slot 1-130, 1-133, respectively. The left vertical slots 1-130 may receive the left lift pins 1-136 (fig. 15A) of the disc cartridge receivers 1-82 when the disc cartridge receivers 1-82 are placed in the bottom plates 1-46, and the right vertical slots 1-133 may similarly receive the right lift pins 1-139 (fig. 15B) of the disc cartridge receivers 1-82.

Two cartridge positioning pins 1-43 of fig. 8B are placed near the front ends of the left and right outer side walls 1-115, 1-121, respectively, and these positioning pins 1-43 are adapted to fit into the grooves 1-40 (fig. 6) of the cartridge. When the pin 1-43 is located in the slot 1-40, the pin 1-43 retains the cartridge 1-13 and prevents it from moving radially (i.e., side-to-side) and longitudinally (i.e., front and back).

The spindle motor mount 1-142 is molded into the bottom of the base plate 1-46, allowing the spindle motor 1-61 (FIG. 7) to be secured to the spindle motor mount 1-142, for example, by spring clips (not shown) mounted on the center ribs 1-145.

The chassis 1-46 has various axes and mounting pins associated therewith. For example, the tiller shaft 1-148 is mounted on the base plate 1-46 adjacent to the main shaft motor mount 1-142. The other pins that secure the tiller spring pins 1-151 to the bottom of the base plate 1-46 near the front wall 1-112 (figure 8A) are mounted near the front wall 1-112 at the bottom of the base plate 1-46 and act as spindles for the gear of the exhaust gear train. The base plate 1-46 further includes a left slider groove 1-154 and a right slider groove 1-157, the slider grooves 1-154, 1-157 extending along the sides of the base plate 1-46. The left slider channel 1-154 is formed between the left outer sidewall 1-115 and the left inner sidewall 1-118. When in place, the left slide bar 1-70 is clamped between the left inner side wall 1-118 and the left outer side wall 1-115 and is seated in the left slide bar groove 1-154 (see FIGS. 9, 13 and 16A). Similarly, a right slider channel 1-157 is formed between the right outer sidewall 1-121 and the right inner sidewall 1-124, and when in place, the right slider 1-73 is sandwiched between the right inner sidewall 1-124 and the right outer sidewall 1-121 and carried in the right slider channel 1-157. The left and right slide bars 1-70, 1-73 are retained in their respective slots 1-154, 1-157, respectively, for example, by "ears" on spring clips (not shown) used to seat the spindle motor 1-61 on the spindle motor mount 1-142.

At the end of the right slider groove 1-157, adjacent to the rear vertical wall 1-127, a receptacle 1-160 is formed in the bottom plate 1-46, in which the rear portion of the right inner side wall 1-124 is merged with the rear portion of the right outer side wall 1-121. The receptacle 1-160 may receive a pivot pin 1-163 (fig. 17B and 17A) of a receiver door lock 1-166. The receiver door lock 1-166 has a vertical surface 1-169 (fig. 17B) upon which a door lock release tab 1-172 (fig. 7 and 16A) secured to the right door link 1-88 can act to release the receiver door lock 1-166.

The base plate 1-46 has an aperture 1-175 in the rear vertical wall 1-127 and a laser diode 42 (not shown) located behind the rear vertical wall between the left corner post 1-178 and the right corner post 1-181 will pass through the aperture 1-175 to impinge on a carrier 1-184 (best shown in fig. 9, 13, 13A, 16A and 16B) which contains optics for focusing the laser beam on the information track of the optical disc 1-14. The carriages 1-184 will be discussed further below.

The base plate 1-46 also has a hole 1-187 molded therein for receiving the spindle 1-190 of the parking arm 1-79 (fig. 14B). The hole 1-187 is integrally molded with the left inner sidewall 1-118, for example, fig. 9 shows the resting arm 1-79 with its pivot 1-190 seated in the hole 1-187. The optical drive 1-10 comprises an optical component 1-189, which operates similarly to the optical component 24 described above.

Referring now to fig. 14A to 14C, the characteristics of the parking arms 1-79 will be further described. In addition to the swivel axis 1-190, the parking arm 1-79 comprises a pressing end 1-193, the parking arm 1-79 being formed with a jaw 1-196 on the end remote from the pressing end 1-193, the jaw 1-196 having a long side 1-199 and a short side 1-202. When the resting arm 1-79 is in place, the jaw 1-196 rides over the lug 1-205 on the left slide bar 1-70 (FIG. 11C). The parking arm 1-79 can be seen more easily in its position in figures 9, 13, 16A and 16B, with its jaw 1-196 straddling the lug 1-205 of the left slide bar 1-70. Whereby the position of the parking arm 1-79 can be controlled by the positioning of the left slider bar 1-70 in the left slider bar slot 1-154.

As can be seen more conveniently in fig. 13, the parking arms 1-79 stop the carriages 1-184. The carriages 1-184 focus a laser beam from the holes 1-175 (fig. 8A and 8B) in the rear vertical walls 1-127 of the base plates 1-46. In particular, the carriage positions the laser beam over the center of the data track containing the data to be read. The carriages 1-184 straddle the support rails 1-208, fig. 9. Conventional magnetic means will drive carriages 1-184 along rails 1-208. The parking arm 1-79 driven by the left slider bar 1-70 will hold the tray 1-184 towards the rear of the drive device when the cartridge receiver 1-82 is in the upward position, which is illustrated in fig. 9 and 16A, and the parking arm 1-79 is shown in solid lines in fig. 13. When the left slider bar 1-70 is driven forward-facing by the tiller 1-76 during ejection of the disc cartridge 1-13, the parking arm 1-79 is turned by the lug 1-205 pressing on the short side 1-202 of the jaw 1-196 until the pressing end 1-193 of the parking arm 1-79 pushes the tray 1-184 towards the rear of the optical drive 1-10. When the cartridge receiver 1-82 is in the down position, the left slider bar 1-70 has been driven to the rear of the optical drive 1-10 by the tiller 1-76. In this case the lug 1-205, which has been driven backwards by the left slider bar 1-70, has turned the parking arm 1-79 towards the front of the optical drive 1-10. With the left slider bar 1-70 and the parking arm 1-79 in place, the carriage 1-184 is not affected by the pressure-actuated end 1-193 of the parking arm 1-79 and is free to move under the disc 1-13 in the optical drive 1-10.

The discharge mechanisms 1-67, which are best seen in fig. 7 and 9, include the following key features. The discharge motor 1-209 drives the discharge mechanism. In particular, the eject motor 1-209 drives a gear train which drives an output cam which in turn forces the tiller 1-76 (FIG. 9) to rotate in a first direction (counterclockwise in FIG. 9), thereby ejecting the disk cartridge 1-13 from the optical drive 1-10. When the withdrawal operation is initiated, the motor 1-209 drives the corresponding screw 1-211. The screw 1-211 is fixed on the central shaft of the exit motor 1-209, the screw 1-211 drives a first gearwheel 1-214 around a first shaft 1-217, the rotation of the first gearwheel 1-214 causes a first pinion 1-220 to rotate, which is fixed to the bottom of the first gearwheel 1-214, causing it to rotate around the first gear shaft 1-217. The first pinion 1-220 drives the second gearwheel 1-223 about the second gearwheel shaft 1-226, and the second pinion 1-229 is fixed to the top of the second gearwheel 1-223 so that it rotates with it about the second gearwheel shaft 1-226. The second pinion 1-229 in turn drives a third gearwheel 1-232 around a third gear shaft 1-235, the third gearwheel 1-232 driving a cam 1-238, which forces the rudder stock 1-76 to rotate around the rudder axle 1-148.

The tiller 1-76 will now be described with reference to fig. 10A-10F and fig. 9. The rudder stock 1-76 is rotatably mounted to the base plate 1-46 by a rudder stock shaft 1-148. The rudder stock spring hook 1-239 is moulded on an elongated part of the rudder stock 1-76 and the rudder stock spring 1-241 (figure 9) is connected between the rudder stock spring hook 1-239 and the rudder stock spring pin 1-151. The tiller spring 1-241 biases the tiller 1-76 in a second direction (clockwise in fig. 9) around the tiller axis 1-148, which is the loading direction, and it drives the right slide 1-73 forward and the left slide 1-70 backward, so that the cassette 1-13 is seated on the spindle motor 1-61. The tiller further includes a tiller skirt or web 1-244 that rides on top of the tiller gear system, thereby helping the backing gears seat on their respective gear shafts. The end of the rudder stock close to the skirt 1-244 of the rudder stock comprises a U-shaped jaw 1-247 and the end of the rudder stock remote from the skirt 1-244 comprises a similar U-shaped jaw 1-250. The U-shaped jaw 1-247 is rotatably mounted around the cylindrical connecting post 1-253 of the left slide bar 1-70 (FIG. 11C), and similarly the U-shaped jaw 1-250 of the tiller 1-76 is rotatably mounted around the cylindrical connecting post 1-256 of the right slide bar 1-73 (FIG. 12E). Thereby, the rudder stock 1-76 is pivotally connected to the front ends of the left and right slide bars 1-70, 1-73, respectively. In addition, since the left and right slide bars 1-70, 1-73 are held in their respective slide bar slots 1-154, 1-157 by spring clips (not shown) that also position the spindle motor 1-61, the rudder stock 1-76 is held on the rudder stock shaft 1-148 by the interaction between the U-shaped jaws 1-147, 1-250 and the cylindrical attachment posts 1-253, 1-256.

When the tiller 1-76 is turned in a first direction (counter clockwise in fig. 9), the left slide bar 1-70 is driven forward in the left slide bar slot 1-154, while the right slide bar 1-73 is simultaneously driven backward in the right slide bar slot 1-157. Thus, rotation of the tiller 1-76 in a first direction (counterclockwise in FIG. 9) raises the disk cartridge receiver 1-82 so that the disk cartridge 1-13 may be ejected from or loaded into the optical drive 1-10. On the other hand, when the tiller 1-76 is turned in the second direction (clockwise, in fig. 9), the left slide bar 1-70 is driven backwards in the left slide bar slot 1-154, while the right slide bar 1-73 is simultaneously driven forwards in the right slide bar slot 1-157. Rotation of the tiller 1-76 in this direction lowers the disk cartridge receiver 1-82 to place the disk on the spindle motor. Raising and lowering of the cartridge receiver 1-82 by rotation of the tiller 1-76 will be discussed further below.

As described above, the left slide bar 1-70 is loaded in the left slide bar slot 1-154, and the right slide bar 1-73 is loaded in the right slide bar slot 1-157 by the rudder stock 1-76. The slide bars 1-70, 1-73 will be described in further detail below.

Referring now to FIGS. 11A-11C, the left slide bar 1-70 is characterized as follows, the left slide bar including a cylindrical connecting post 1-253 on its front end. On the first recess 1-259 there is a resting arm lug 1-205. The parking arm 1-79 slides along the first recess 1-259 of the left slide bar 1-70 under the action of the lug 1-205. S-shaped slots 1-262 may be formed in the left slide bar 1-70 such that when the left slide bar 1-70 is positioned in the left slide bar slot 1-154, the S-shaped slots 1-262 are open to the left outer side wall 1-115, adjacent to and behind the left vertical slots 1-130. When the cartridge receiver 1-82 is in place on the bottom plate 1-46, the left lift pin 1-136 (fig. 15A) of the cartridge receiver 1-82 is seated in the left vertical groove 1-130 of the bottom plate 1-46, which is longer than the thickness of the left outer sidewall 1-115. Thus, the left lift pin 1-136 extends through the left vertical slot 1-130 and rides in the S-shaped slot 1-262 on the left slide bar 1-70. When the cartridge receiver 1-82 is thus seated on the lower plate 1-46, since the left lift pin 1-136 is loaded in the vertical groove 1-130 and the S-shaped groove 1-262, the cartridge receiver 1-82 is restricted from moving forward or backward and can only move vertically upward and downward. The vertical slots 1-130 limit the back and forth movement of the cartridge receiver 1-82, while the S-shaped slots 1-262 on the left slide bar 1-70 determine the vertical height of the cartridge receiver. In other words, the cartridge receiver 1-82 is at the highest position, the lowest position, or somewhere between the highest and lowest positions, at any particular time depending on which portion of the S-shaped slot 1-262 is behind the vertical slot 1-130.

The second recess 1-265 is on top of the left slide bar 1-70. Horizontal pins (not shown) may be mounted to the bottom plates 1-46 to slide along the second recesses 1-265. The horizontal pin (not shown) will limit the maximum forward position and the maximum backward position of the left slide bar 1-70, since the pin will press against the edge of the second recess 1-265 to one of the extreme positions of the left slide bar.

The rearmost end of the left slide bar 1-70 includes a notch 1-268, which is best shown in FIGS. 11B and 7. Notches 1-268 are located on the moving end 1-272 of the left slider bar 1-70. notches 1-268 can receive lever arms 1-275 of the bias coil arms 1-97 of FIG. 7. the lever arms 1-275 rotate the bias coil arms 1-97 depending on the position of the left slider bar 1-70, particularly, depending on the position of the notches 1-268. The moving end portion 1-272 of the left slider bar 1-70 is carried in a groove 1-278 (fig. 8B) on the left outer side wall 1-115 of the bottom plate 1-46.

Referring now to FIGS. 12A-12E, the features of the right slide bar 1-73 will be given. The rudder stock 1-76 is connected to the right slider bar 1-73 by the cylindrical connection post 1-256 as described above. The right slide bar 1-73 has an S-shaped slot 1-281 formed therein, the S-shaped slot 1-281 being an inverted version of the S-shaped slot 1-262 on the left slide bar 1-70. It is best shown in figure 7. After careful consideration of fig. 7, it will be clear that the S-shaped grooves 1-262, 1-281 will be turned mirror-inverted with respect to each other when the slide bars 1-70, 1-73 are attached to the rudder stock 1-76, which arrangement is necessary because the slide bars 1-70, 1-73 will move in opposite directions under the influence of the rudder stock 1-76. The S-shaped slot 1-281 on the right slide bar 1-73 is also open to the right outer side wall 1-121 when the right slide bar 1-73 is in its operative position in the right slide bar slot 1-157. Similar to that described above with respect to the left slide bar 1-70, when the cartridge receiver 1-82 is in place on the base plate 1-46, the right lift pin 1-139 (FIG. 15B) is carried in the right vertical slot 1-133 (FIG. 8B), and since the right lift pin 1-139 is longer than the thickness of the right outer sidewall 1-121, the right lift pin 1-139 protrudes from the right outer sidewall 1-121 through the right vertical slot 1-133 and is carried in the S-shaped slot 1-281 on the right slide bar 1-73. The right vertical slots 1-133 limit the movement of the right lift pins 1-139 parallel to the longitudinal axis of the base plates 1-46 (i.e., parallel to a line passing vertically through the front walls 1-112 and the rear vertical walls 1-127). Since the right lift pins 1-139 are seated in the S-shaped slots 1-281, the vertical height of the cartridge receiver 1-82 will be determined by the position of the right lift pins 1-139 in the S-shaped slots 1-281. The S-shaped slots 1-281 on the right slide bar 1-73 move behind the right vertical slots 1-133 at the same speed but in the opposite direction as the S-shaped slots 1-262 on the left slide bar 1-70 move behind the left vertical slots 1-130. However, the inverted mirror image design of the S-shaped slots 1-262, 1-281 ensures that the left and right lift pins 1-136, 1-139, respectively, remain at substantially the same vertical height at the bottom of the base plates 1-46 at any given time.

Still referring primarily to FIGS. 12A-12E, the right slide bar 1-73 includes the following additional features, with the recessed portion 1-284 being provided on the top surface of the right slide bar 1-73. A pin (not shown) may be mounted horizontally across the right slider bar slot 1-157 to slide along the recessed surface 1-284. The horizontal pin sliding along the recessed surface 1-284 will limit the maximum forward and backward movement of the right slide bar 1-73 because the horizontal pin will reach the edge of the recess 1-284 at the limit of the movement of the right slide bar 1-73. The right slide bar 1-73 also includes a notched area 1-287 to receive the dog 1-290 (FIGS. 17A and 17B) of the receiver latch 1-166. The rising portion 1-293 is provided on the rear end of the right slide bar 1-73. When the tiller 1-76 is turned in a first direction (counterclockwise in fig. 13) to drive the right slide bar 1-73 backwards in the right slide bar slot 1-157, a locking action will occur between the receiver latch 1-166 dog 1-290 and the raised portion 1-293 of the right slide bar 1-73. In particular, a first sliding surface 1-296 (FIG. 17A) on the holding pawl 1-290 slides over a second sliding surface 1-299 (FIGS. 12C and 12E) on the raised portion 1-293 of the right slide bar 1-73. When the surfaces 1-296 and 299 slide past each other, the spring-loaded holding pawl 1-290 in the direction of the arrow 1-302 of FIG. 17A enters the right slide bar 1-73 notch area 1-287 which holds the right slide bar 1-73 in the rearward position, and then, brings the cartridge receiver 1-82 to its uppermost position. When the cartridge receiver is in this position any cartridge 1-13 in the optical drive 1-10 will be ejected or alternatively the cartridge 1-13 may be loaded into the optical drive 1-10.

The S-shaped grooves 1-262 and 1-281 of the left and right sliders 1-70, 1-73 play an important role in the detachment operation performed by the present invention when the disk cartridge is mounted on and dismounted from the spindle motor, respectively. This effect of the S-shaped grooves 1-262, 1-281, which are suitable for use in the present invention to produce the disengaging action, will be discussed further below.

Referring now to fig. 15A and 15B, the disk cartridge receivers 1 to 82 and the respective components provided thereon will be described. The cartridge receiver 1-82 is integral and is a plastic molded piece with the left door lever 1-85 (fig. 7) and the right door lever 1-88 added. When the optical drive 1-10 is fully assembled, the cartridge receiver 1-82 will be carried on the left and right outer side walls 1-115, 1-121 of the chassis 1-46. The disk cartridge receiver 1-82 moves vertically up and down as the lift pins 1-136, 1-139 move up and down according to their respective S-shaped grooves 1-262, 1-281. The cartridge receiver 1-82 also rocks slightly up and down about an imaginary transverse axis passing through the left and right lift pins 1-136, 1-139, and this slight rocking motion, together with the up and down motion, produces the proper disengaging action achieved by the present invention. The cartridge receiver 1-82 may be removed or ejected from the remainder of the mechanism if the cover of the optical drive 1-10 is removed.

The cartridge receiver 1-82 has left and right cartridge-receiving channels 1-305 and 1-308 formed thereon, and a stopper shutter 1-311 is provided at the rear of the right cartridge-receiving channel 1-308 to prevent improper insertion of the cartridges 1-13. As seen in fig. 6 and 7, the disc cartridge 1-13 has a pair of slots 1-314 molded into the side walls 1-37, and if the disc cartridge 1-13 is properly inserted, its rear wall 1-38 first enters the disc-receiving opening 1-22, and one of the slots 1-314 on the cartridge disc 1-13 will receive the stop bezel 1-311 and allow the disc cartridge 1-13 to be fully inserted into the optical drive 1-10. On the other hand, if the user first inserts the disc cartridge 1-13 with its leading label end 1-34 into the disc-receiving slot 1-22, the stop fence 1-311 will strike the label end 1-34 of the disc cartridge 1-13, thereby preventing the disc cartridge 1-13 from being fully inserted into the optical drive 1-10. The rear wall 1-317 of the disc cartridge receiver 1-82 has a recessed area 1-320 formed therein, which recessed area 1-320 allows a lock release tab 1-172 (fig. 16) mounted to the right door lever 1-88 to act on the vertical surface 1-169 (fig. 17B) of the receiver latch 1-166. Since the left and right door levers 1-85 and 1-88 are rotated toward the rear of the optical drive 1-10 as the disc cartridge 1-13 is inserted into the cartridge receiver 1-82, respectively, when the disc cartridge 1-13 is nearly fully inserted, the lugs 1-172 rotate by pressing against the vertical surfaces 1-169 of the receiver latch 1-166, and the rotation of the receiver latch 1-166 disengages the pawl 1-290 from its locked position on the raised portion 1-293 of the right slide bar 1-73. When the receiver latch 1-166 is released in this manner, the disk cartridge receiver 1-82 may be lowered to place the disk cartridge 1-13 in the operation position of the spindle motor 1-61.

Referring to fig. 7, 15A, 15B, 16A and 16B, the mounting of the left door lever 1-85 and the right door lever 1-88 with the receiver box 1-82 will now be described. Left and right door levers 1-85 and 1-88 may be mounted to rear corners of the cartridge receiver 1-82 adjacent to the rear walls 1-317, respectively. Specifically, the left door lever 1-85 is rotatably mounted to the disc cartridge receiver 1-82 at a first rotation point 1-323, and the right door lever 1-88 is rotatably mounted to the disc cartridge receiver 1-82 at a second rotation point 1-326. The door levers 1-85 and 1-88 are biased towards the front panel 1-19 of the optical drive 1-10 by springs (not shown) and, in operation, one or other of the door levers 1-85, 1-88 will open the cartridge shutter door and open the cartridge shutter 1-49 when a disc cartridge 1-13 is inserted into the optical drive 1-10. Whether the cartridge opening shutter 1-49 is opened by the left door lever 1-85 or the right door lever 1-88 is determined by which side of the disk cartridge 1-13 faces upward when the disk cartridge 1-13 is inserted into the optical drive 1-10. If the disk cartridge 1-13 is inserted with the first side facing upward, the right door lever 1-88 operates the shutter lock and opens the shutter 1-49. If the disk cartridge 1-13 is inserted with the other side facing upward, the left door lever 1-85 operates the shutter lock and opens the shutter 1-49. When no disc cartridge 1-13 is present in the optical drive 1-10, the door levers 1-85 and 1-88 will rest on the door lever stops 1-329, which are integrally formed as part of the cartridge receiver 1-82. These door lever stops 1-329 ensure that the free ends 1-332 of the door levers 1-85 and 1-88 are properly positioned to release the shutter lock and open the shutters 1-49 when the disk cartridge 1-13 is inserted into the optical drive 1-10.

Referring now to fig. 18-22, the magnetic biasing coil assemblies 1-94 will be described in greater detail. The bias coil assembly 1-94 is used during write and erase operations of the optical drive 1-10. The bias coil assembly 1-94 comprises a steel strip 1-335 enclosed in a coil 1-338. When the bias coil assembly 1-94 is positioned on the disks 1-14, as best shown in FIG. 23, it will extend radially beyond the disks 1-14 and thereby be able to generate a strong magnetic field on a radial strip of the disks 1-14, extending from near the spindle 1-62 (FIGS. 23-25) to the edge of the disks 1-14. When the discs 1-14 are rotated by the spindle motor 1-61 under the bias coil assembly 1-94, a magnetic field is generated over the entire surface of the discs 1-14, thus enabling a user to write information on all portions of the innermost to outermost tracks of the discs 1-14. The coils 1-338 and strips 1-335 are covered by the bias coil top case 1-341 and may be mounted to the bias coil bottom case 1-344.

Bias coil assemblies 1-94 are mounted to bias coil flexures 1-347, fig. 22, which are in turn mounted to bias coil arms 1-97, fig. 21. The bias coil arms 1-97 span the width of the base plates 1-46 and are rotatably mounted to the corner posts 1-178 and 1-181 of the base plates 1-46 by a pair of bias coil clips 1-100 (fig. 18), fig. 8A and 8B. The biasing coil clips 1-100 thus act as bearing blocks under which the biasing coil arms 1-97 can rotate. The biasing coil clips 1-100 include stop ledges 1-350, fig. 18, that will stop the upward movement of the cartridge receiver 1-82 during the ejection operation, as described in more detail below with reference to fig. 23-25. As previously described, the bias coil arm 1-97 includes a lever arm 1-275 that is operatively associated with a notch 1-268 on the rear end of the left slider bar 1-70 for raising and lowering the bias coil assembly 1-94. As the lever arm 1-275 engages the notch 1-268 on the left slider bar 1-70, the left slider bar 1-70 controls when the biasing coil assembly 1-97 is turned toward or away from the disk cartridge 1-13.

The biasing coil assembly 1-94 can swing or rotate about a point 1-353 near its center and it is spring biased downward. In this way, the bias coil assembly 1-94 is maintained parallel to the disk cartridges 1-13 in the lower position (i.e., the position depicted in FIG. 23 in which the disk cartridges 1-13 are fully loaded) and in the upper position (i.e., the position depicted in FIG. 25 in which the disk cartridges 1-13 are unloaded). The ability of the biasing coil assembly 1-94 to remain parallel to the disc cartridge 1-13 when in the upper position provides the required tolerances for the optical drive 1-10 to enable the disc eject operation to be performed, as described below. When in the lower position and loaded on the disk cartridge 1-13, the bias coil assembly 1-94 will rest on the disk cartridge 1-13 at three places.

Referring now further to fig. 23-25, the ejection of the disc cartridge 1-13 from the optical drive 1-10 will be described. Fig. 23 depicts the disc cartridge 1-13 with the hub 1-15 fully loaded on the spindle 1-62 of the spindle motor 1-61. In this structure, the bias coil assembly 1-94 is mounted in the disk cartridge 1-13 through the opened shutter 1-49. When the disc cartridge 1-13 is fully loaded in this way, the left slider bar 1-70 has been slid to its final position by the tiller 1-76 and the lever arm 1-275 of the biasing coil arm 1-97 has been pivoted towards the rear of the optical drive 1-10, and it is this pivoting of the lever arm 1-275 that causes the biasing coil assembly 1-94 to be loaded into the disc cartridge 1-13. Since the elevation pins 1-136 and 1-139 of the cartridge receiver 1-82 are restricted to vertical movement only due to the vertical slots 1-130 and 1-133 (fig. 8A and 8B), when the left slider bar 1-70 has been driven toward the rear of the optical drive 1-10 by the tiller 1-76, as depicted in fig. 23, the cartridge receiver 1-82 is driven to the lowest point of the S-shaped slots 1-262 and 1-281 by its elevation pins 1-133 and 1-136.

An intermediate stage of the exit process will now be described with reference to fig. 24. After the user starts ejecting the disc cartridge 1-13 from the optical drive 1-10, the eject motor 1-208 shown in FIG. 9 rotates the tiller 1-76 in a first direction (counterclockwise in FIG. 9). This rotation of the tiller pulls the left slider bar 1-70 towards the front of the optical drive 1-10 as shown in figure 24. As the left slider bar 1-70 slides forward, the notches 1-268 rotate the lever arms 1-275 forward, thereby raising the biasing coil assemblies 1-94 out of the cartridges 1-13. It can also be seen in fig. 24 that the lift pins 1-136 and 1-139 fixed to the cartridge receiver 1-82 will be pressed upward in the S-shaped grooves 1-262 and 1-281 by the movement of the tiller 1-76. Since the lift pins 1-136 and 1-139 are located at a point on the cartridge receiver where the transverse axis passing through the two lift pins 1-136 and 1-139 will no longer pass through the spindle 1-62, the "breakaway" effect will be obtained as the cartridge receiver 1-82 is lifted, which moves the hub 1-15 away from the spindle magnet 1-64. In other words, as shown in FIG. 24, the disks 1-14 are not lifted vertically off the spindles 1-62 during ejection. In contrast, when the lift pins 1 to 136 and 1 to 139 move along the respective S-shaped grooves 1 to 262 and 1 to 281, the rear portion of the disk cartridge 1 to 13 is lifted earlier than the front end of the disk cartridge 1 to 13 due to the positions of the lift pins 1 to 136, 1 to 139 of the cartridge receiver 1 to 82. This disengagement operation reduces the peak force required to remove the hub 1-15 from the magnetic clamp 1-64 of the spindle motor 1-61.

Still referring to fig. 24, it is apparent that after the cartridge receiver 1-82 has been raised a predetermined amount by the movement of the slide bars 1-70 and 1-73, the leading edge 1-356, fig. 15A, on the rear wall 1-317 of the cartridge receiver 1-82 will press against the lower surface of the stop rail 1-350 on the biasing coil clip 1-100, fig. 18. This contact between the bottom surface of the stop rail 1-350 and the top surface of the lip 1-356, together with the continued rotation of the tiller 1-76 and the resulting longitudinal movement of the slide bars 1-70 and 1-73, causes the cartridge receiver 1-82 to tilt slightly upward in figure 24. This occurs substantially near the point of contact between the stop ledges 1-350 and the lips 1-356 as the lifting pins 1-136, 1-139 continue to lift the receiver. This slight tilting movement of the disc cartridge receiver 1-82 effects what is referred to above as a "break away" operation.

FIG. 25 depicts the relative position of the optical drive 1-10 after the cartridge receiver 1-82 has completed a slight tilt up, and after the cartridge receiver 1-82 has pressed against a stop adjacent the disc-receiving bay 1-22. At this point, the left slider bar 1-70 has reached its forwardmost position and has pulled the lever arm 1-275 to its forwardmost position, thereby rotating the bias coil assembly 1-94 out of the housing 1-13. Thereby the bias coil assembly is brought in parallel and stopped above the disc cartridge 1-13, essentially against the inside of the top surface of the optical drive 1-10 or against a printed circuit board located on the inside of the top surface of the optical drive 1-10. The vertical movement of the biasing coil assembly 1-94 from its loaded position within the cartridge 1-13 to its raised position just described is preferably about 9 mm.

When the cartridge receiver 1-82 is raised to its uppermost position (about 5mm above the lowermost position), the right slider bar 1-73 (fig. 12A-12E) will be locked in its rearmost position by the receiver latch 1-166 (fig. 17A and 17B) as fully described above. When the disk cartridge receiver 1-82 is in the upper position depicted in fig. 25, the disk cartridge receiver 1-82 is positioned parallel to the bottom plate 1-46, ready to eject the disk cartridge 1-13. The elastic force of the door levers 1-85 and 1-88 biased toward the front end of the optical drive 1-10 and the elastic force of the cartridge shutter 1-49 biased toward the closed position as described above causes the cartridge 1-13 to be ejected from the optical drive 1-10 as shown in fig. 25.

The disc loading operation is substantially the reverse of the disc ejecting operation described above. Therefore, the operation of the tray will not be described in detail.

In the present invention, the required withdrawal force when the disk hub 1-15 is disengaged from the spindle magnet 1-64 can be effectively reduced by moving the disk 1-14 from the loading position to the unloading position. By using a "break away" motion according to the present invention, less force is required to move hubs 1-15 than a typical vertical lift system. In addition, the design saves the overall driver height. The above design accomplishes the disengagement of the hub 1-15 from the spindle magnet 1-64 by using a mechanism that uses the available space on the side of the optical drive 1-10, rather than requiring components that span the width of the base plate 1-46, tying the movement of the cartridge receiver 1-82 on both sides together and using additional height. Another beneficial feature of this design is the non-critical nature of most of the required dimensions. In addition, the bias coil actuator mechanism for loading the bias coil assembly into the disk cartridge 1-13 is simple and has a minimal number of wear points. The entire design is easy to assemble and can be made using simple and easy manufacturing components for most components.

While the foregoing description of the preferred embodiment of the invention has been presented, it will be apparent to those skilled in the art that many changes can be made without departing from the spirit or scope of the invention. The present invention can be used with media systems that do not require the bias coil assemblies 1-94 (i.e., phase change or write-once systems), for example, by eliminating the components used to operate the bias coil arms 1-97. In addition, although in the preferred embodiment the storage medium is a 5.25 inch magneto-optical disk cartridge, the present invention is applicable to all types of media and all sizes of drives.

Two-axis moving coil actuator

Figure 26 schematically illustrates a two-axis electromagnetic actuator 2-10 constructed in accordance with the present invention. The actuator 2-10 comprises an objective lens 2-12 arranged in a lens holder 2-14. The radial or tracking coil 2-16 is wound around and secured to the lens holder 2-14 such that it is positioned generally perpendicular to the Z-axis. The first and second focusing coils 2-18 and 2-20 are positioned on either side of the lens holder 2-14 and are fixed to the tracking coils 2-16 so as to be positioned generally perpendicular to the Y-axis. A first pair of permanent magnets 2-22 is positioned adjacent the first focussing coil 2-18 and a second pair of permanent magnets 2-24 is positioned adjacent the second focussing coil 2-20.

As shown in fig. 27, the lens holder 2-14 includes a generally rectangular flange 2-30 having a circular aperture 2-32 in the center thereof. The objective lens 2-12 is glued to the flange 2-30 at a position on top of the circular hole 2-32. The flanges 2-30 are supported by a generally I-shaped platform 2-34 having a pair of slots 2-44 formed in the edges of the platform for receiving and gripping the tracking coils 2-16 when the tracking coils are wound on the platform. The base 2-36 of the support platform 2-34 includes first and second T-shaped portions 2-46 and 2-48 having a slot 2-50 formed therebetween. As will be explained in more detail below, the base 2-36 serves as a mass balance for the lens holder 2-14. The flange 2-30, the platform 2-34 and the base 2-36 are leveled on both sides to form the first and second opposing faces 2-52 and 2-54 of the lens holder.

The focusing coils 2-18 and 2-20 are fixed to the tracking coils 2-16 such that the central axis of the focusing coils coincides with, intersects with, and is preferably perpendicular to the central axis of the tracking coils. The focusing coils 2-18 and 2-20 are preferably made of a thermo-adhesive wire having a layer of adhesive material thereon, and are preferably wound on a suitable tool or support. The coils 2-18 and 2-20 are preferably wound as tightly as possible around the support so that the wires do not deform. This tightness will vary with the type of wire, as will be appreciated by those skilled in the art. During winding, the focusing coils 2-18 and 2-20 are preferably heated to melt the adhesive layer on the wires, thereby increasing the compactness and hardness of the wound coils. The temperature is preferably chosen to be high enough to melt the bonding material, but not so high as to melt the insulation. After cooling, the coils 2-18 and 2-20 are removed from the support and these individual coils are then fixed to the tracking coils 2-16 in a known manner using a suitable adhesive.

The first individual focusing coils 2-18 and 2-20 are each elliptical in shape and have two elongated sides 2-56 connected by a pair of shorter ends 2-58. The sides 2-56 and ends 2-58 of the coils 2-18 and 2-20 surround an open or hollow annular center 2-60. The tracking coil 2-16 is wound around the I-shaped platform 2-34 of the lens holder 2-14 such that the coil is received and secured within the slot 2-44 and positioned against the opposing faces 2-52 and 2-54 of the lens holder. Referring to both fig. 26 and 27, the two focusing coils 2-18 and 2-20 are mounted to the tracking coils 2-16 such that the tracking coils are positioned within the center 2-60 of each focusing coil, and the focusing coils 2-18 and 2-20 are further positioned such that each coil is attached to opposite faces 2-52 and 2-54 of the lens holder 2-14. In this way the tracking coils 2-16 and the focusing coils 2-18 and 2-20 are rigidly fixed to the lens holder 2-14, whereby a more robust drive unit is obtained, which corresponds to a single body.

Referring to fig. 28, 29, 30 and 31, in operation, a light source element (not shown), typically a laser diode, emits a laser beam 2-70, fig. 31. The light beam 2-70 is incident on a prism 2-72 which reflects the light beam orthogonally up to the objective lens 2-12. The lens 2-12 converges the light beam 2-70 to a precise focal point or spot 2-74 on the surface of a recording medium, such as an optical disc 2-76. When hitting the optical disc 2-76 the light beam 2-70 is altered by the information stored on the disc 2-76 and will be reflected as a diverging beam carrying the same information as encoded on the disc 2-76, the reflected beam re-entering the objective lens 2-12 where it is collimated and reflected again via the prism 2-72 to a light detector (not shown) which can be used to detect the data stored on the disc 2-27. In addition, if the beam falling on the photodetector is unfocused or misaligned, an electronic measurement of the amount of misalignment or defocus is made and provided as feedback to a servo system (not shown) well known in the art for proper realignment of the objective lens 2-12 relative to the disc 2-76.

It is these feedback signals that determine the amount and direction of movement of the actuator 2-10 and the objective lens 2-12 carried thereon that is required to bring the beam into the desired focus position with respect to the disc 2-76. When radial or tracking movement is required to position the objective lens 2-12 under the center of a selected track on the optical disc 2-76, current is supplied to the tracking coil 2-16, which interacts with the magnetic field generated by the permanent magnet pair 2-22 and 2-24 to generate a force that moves the tracking direction of the actuator 2-10. These forces are generated according to Lorentz's law F ═ B · X · I · l, where F represents the force acting on the tracking coil 2-16, B represents the flux density of the magnetic field between the permanent magnet pairs 2-22 and 2-24, I represents the current through the tracking coil 2-16, and l represents the length of the coil 2-16. When the counter-clockwise direction of the current I supplied to the tracking coils 2-16 flows through the coils, a force is generated which moves the actuators 2-10 to the right, relative to the orientation of fig. 29, which is indicated by the arrows 2-15 in fig. 31. When the opposite or clockwise direction of the current supplied to the coils 2-16 flows through the coils, a force is generated that moves the actuators 2-10 to the left, as indicated by arrows 2-17 in fig. 31. In this way the actuator 2-10 is radially moved so as to position the objective lens 2-12 under the centre of the desired information track on the surface of the optical disc 2-76.

The movement of the actuator 2-10 to achieve focusing is generated when a current is generated in the two focusing coils 2-18 and 2-20 on the tracking coil 2-16 fixed to the side of the lens holder 2-14. When a current is supplied through these coils 2-18 and 2-20 to cause a current to flow in a counterclockwise direction in the plane of fig. 30, a force will be generated, the action of which moves the lens holder 2-14 and the objective lens 2-12 upward toward the surface of the optical disc 2-76, as indicated by arrows 2-19 in fig. 31, whereas when a current is supplied to cause a current to flow through the coils 2-18, 2-20 in a clockwise direction in the plane of fig. 30, a force will be generated which moves the lens holder 2-14 downward, as indicated by arrows 2-21 in fig. 31, or away from the surface of the disc 2-76.

Since the tracking coils 2-16 are integrated with the lens holder 2-14 and the focussing coils 2-18 and 2-20 in turn are directly integrated with the tracking coils 2-16, so that the coils and the lens holder behave as a "single body" and the frequency of decoupling of the coils with respect to the lens holder is significantly increased, it has been found with the actuator design of the invention that the decoupling frequency is up to 30 KHz.

Referring to fig. 28 and 29, the magnet pairs 2-22 and 2-24 remain stationary during movement of the lens holder 2-14 and are fixed within a generally rectangular housing or base 2-80. Two pairs of suspension wires 2-82 and 2-84 can be assembled to suspend the objective holder 2-14 between magnet pairs 2-22 and 2-24. The pairs 2-82 and 2-84 are mounted on a stationary printed circuit board 2-85, which is positioned vertically with respect to the lens holder 2-14 and serves to support the pairs 2-82 and 2-84. The wire pairs 2-82 and 2-84 are further secured to electrical contacts on a moving circuit board 2-87 which is also mounted in a vertical orientation on the lens holder 2-14. In particular, the free end of each focusing coil 2-18 and 2-20 is soldered to an electrical contact 2-86, so that current can be supplied to the focusing coils 2-16 and 2-18 through a second or bottom pair of wires 2-84 that is also soldered to contacts 2-86. The other free end of each focusing coil 2-18 and 2-20 may be soldered to the circuit board 2-87 and connected along electrical contacts 2-88. The free end of the tracking coil 2-16 and the first or top pair of suspension wires 2-82 may be soldered to electrical contacts 2-89 on the mobile circuit board 2-87 so that current may be supplied to the coil through the top pair of wires. The base 2-36 of the lens holder 2-14 serves as a mass balance which counteracts the weight of the objective lens 2-12 and the circuit board 2-87. The lens holder 2-14 is connected to the circuit board 2-87.

Alternatively, four bends may be used to suspend the lens holders 2-14. The flexure desirably acts as a parallel leaf spring that allows up and down movement of the objective holder 2-14 for focusing while preventing changes in the orientation of the optical axis of the lens 2-12. In this way the objective lens 2-12 will not tilt with respect to the surface of the optical disc 2-76 when the lens holder 2-14 is moved in the focus direction. Each bend further includes a narrow portion that operates like a hinge to allow some movement of the objective frames 2-14 in a side-to-side direction for tracking adjustment.

In addition to performing fine focus and tracking movements of the lens holder 2-14, it is often necessary to detect the position of the lens holder 2-14 relative to the base 2-80. For determining the position of the objective lens 2-12 in both tracking and/or focusing directions, the actuator 2-10 is equipped with a position sensor 2-90. Preferably, Light Emitting Diodes (LEDs) 2-92 are positioned on a side of the actuators 2-10 opposite the sensors 2-90 such that when the objective lens holder 2-14 is centered within the base 2-80, light emitted by the LEDs 2-92 will shine through the slots 2-50 on the lens holder 2-14 onto a portion of the sensors 2-90. The position sensitive detector may suitably be supplemented by sensors 2-90, and the sensors are positioned such that when the lens holder 2-14 is centred in the base 2-80, the light emitted by the LEDs 2-92 will pass through the slots 2-50 and will be distributed over the detector. Thus, when the lens holder 2-14 is moved in a side-to-side direction, i.e. the tracking direction, parts of the sensor 2-90 will be illuminated to indicate the position of the lens holder 2-14 in the tracking direction. Then, when the lens holder 2-14 is not centered with respect to the base 2-80, a portion of the light emitted by the LED2-92 will be blocked by the lens holder 2-14, causing the light to be distributed asymmetrically over the sensor 2-90. The asymmetrical distribution is then analyzed by known circuits and methods to determine the position of the lens holder 2-14 relative to the base 2-80.

When the control signals are generated by the servo system, a certain current will be supplied to the tracking coils 2-16 and/or the focusing coils 2-18 and 2-20 depending on the desired direction of movement of the lens holder 2-14 and the objective lens 2-12 mounted thereon. Such servo systems and feedback circuits to control the amount of current are well known in the art. As described above, this current interacts with the electromagnetic field generated by the permanent magnet pairs 2-22 and 2-24, generating a force that displaces the lens holder 2-14 and the objective lens 2-12 mounted thereon in the appropriate focusing or tracking direction.

The operation and structure of the focusing and tracking mechanism will now be described in more detail. As shown in fig. 32 and 33, the permanent magnet pairs 2-22 and 2-24 are oriented with opposite magnetic poles opposite to each other. More particularly, the first pair of magnets 2-22 includes a first or top magnet 2-100 and a second or bottom magnet 2-102 in a stacked relationship connected along a planar interface such that the north pole of the top magnet 2-100 and the south pole of the bottom magnet 2-102 are positioned adjacent the lens holder 2-14, as shown in FIG. 33. The second pair of magnets 2-24 includes a third or top magnet 2-104 and a fourth or bottom magnet 2-106 in a planar interfacing stacked relationship having opposite orientations such that the south pole of the top magnet 2-104 and the north pole of the bottom magnet 2-106 are positioned adjacent the lens holder 2-14 as shown in fig. 33. As shown in fig. 32, the magnetic field lines generated by this orientation start at the north pole of each magnet pair 2-22 and 2-24 and end at the south pole of each magnet pair. A ferrous plate 2-110 (shown in phantom for clarity) may be mounted to the permanent magnet side of each magnet pair 2-22 and 2-24 opposite the lens holder 2-14. The ferrous plates 2-110 effectively "shunt" the tracks emanating from the sides of the magnets 2-100, 2-102, 2-104 and 2-106 opposite the lens holder 2-14, thereby increasing the magnetic flux in the adjacent portions of the lens holder and producing a corresponding increase in actuator power.

The focusing forces acting on the actuators 2-10 are shown in more detail in fig. 34. When the current I is in the direction shown,i.e. out of the plane of the drawing adjacent to the top magnets 2-100, 2-104 and in from the plane of the drawing adjacent to the bottom magnets 2-102 and 2-106, to the focusing coils 2-18 and 2-20, forces FFOCUS1 and FFOCUS2 are generated which are translated to the lens holder 2-14 to accelerate or decelerate the moving object (lens holder) and to the pairs of suspension wires 2-82 and 2-84, which are bent to move the lens holder 2-14 and the associated objective lens 2-12 closer to the optical disc 2-76. Due to the curvature of the magnetic field lines as described above, the direction of the magnetic field is changed vertically in the focusing coils 2-18, 2-20. For example, for the focusing coils 2-18 positioned adjacent the first magnet pair 2-22, in the plane of fig. 34 that vertically cuts through the coils adjacent the top magnet 2-100, the magnetic field has a first direction at the top of the coils 2-18, denoted by B₁It is shown that, in a cross-section adjacent to the bottom magnet 2-102, the magnetic field has a second direction at the bottom of the coil 2-18, denoted by B₂And (4) showing. Current and magnetic field B according to Lorentz's law₁Interact to generate a first component force F acting on the portion of the focusing coil 2-18 adjacent to the top magnet 2-100₁And is in contact with the magnetic field B ₂Interacting to produce a second force component F acting on the focusing coil portion adjacent to the bottom magnet 2-102₂. When component force F₁And F₂When the horizontal portions are equal in size and opposite in direction, these horizontal component components cancel each other out to produce a resultant force F according to the vector addition principle_FOCUS1Which is vertically upward in the plane of fig. 34. Similarly, the horizontal force components on the other parts of the entire coil 2-18 cancel out to obtain a vertical resultant force which is strictly vertically upwards (i.e. vertically upwards without significant horizontal component) thus moving the lens holder 2-14 closer to the surface of the optical disc 2-76.

When the magnetic field lines generated by the second magnet pair 2-24 are opposite to the curvature generated by the first magnet pair 2-22, the direction of the magnetic field at any point on the focusing coils 2-20 is different from the direction of the magnetic field at the corresponding point on the focusing coils 2-18. Furthermore, the magnetic field acting on the coils 2-20 changes direction vertically along the coils due to the bending of the magnetic field lines. In the plane of fig. 34, which vertically cuts the coil adjacent to the top magnet 2-104 of the second magnet pair 2-24, the top magnetic field direction in the coil 2-20 is defined by B₃Express, and according to Lorentz's law will produce a direction F₃While the magnetic field direction on the bottom of the coil 2-20 is from B on the cross section adjacent to the bottom magnet 2-106 ₄Express, and generate a force F₄. The forces add up to produce a resultant force F_FOCUS2It is strictly vertically upward as shown.

Thus, it can be seen that the forces F acting on the focusing coils 2-18 and 2-20, respectively_FOCUS1And F_FOCUS2The lens holder 2-14 is moved upwards. Conversely, if current is supplied to the focusing coils 2-18 and 2-20 in the opposite direction, some force will be generated to move the lens holder 2-14 downward, or further away from the surface of the optical disc 2-76. The focusing coils 2-18 and 2-20 can accurately focus the laser beam exiting the objective lens 2-12 on the optical disc 2-76 by moving the objective lens 2-12 closer to or farther from the surface of the disc 2-76.

When a current is generated in the tracking coil 2-16 fixed to the lens holder 2-14, as shown in fig. 35, a movement is generated which causes the actuator 2-10 to affect fine tracking. In the plane of fig. 35, it horizontally bisects the tracking coils 2-16, having a direction B₁Acts on a cross section of the coil 2-16 located closest to the first magnet pair 2-22 and has a direction B₂Acts on the coil cross section 2-24 when located closest to the second magnet. For example, if the current I is supplied to the tracking coils 2-16 in a counter-clockwise direction, the force F₁Acting on the tracking coil portions adjacent to the first magnet pair 2-22, a force F ₂Acts on the tracking coil portion adjacent to the second magnet pair 2-24. These forces add under the law of vector addition to produce a resultant force F_TRACKIt can move the lens holders 2-14 to the right in the plane of fig. 35. When forces act on the tracking coils 2-16 in this way, they are transformed by the lens holder 2-14, accelerating or decelerating the moving object (lens holder), and to the pairs of suspension wires 2-82 and 2-84, which are bent in the respective directions to move the objective lens 2-12 and to accurately direct the laser beam emitted thereby in the center of the selected data track on the surface of the optical disc 2-76. Conversely, if the current I is supplied to the coils 2-16 in a clockwise direction, this results inThe resulting force of this will move the lens holder 2-14 to the left in the plane of fig. 35.

Thus, it can be seen that the coupling arrangement of the present invention further reduces the distance between the resultant forces acting on the coils 2-16, 2-18 and 2-20 and the optical axis of the objective lens 2-12, reducing the adverse modes of motion during focusing and tracking operations, such as wobble, roll and yaw.

With the actuator design of the invention, only two pairs of permanent magnets, i.e. a total of four magnets, and three coils are required to achieve movement in the tracking and focusing directions, thereby reducing the size and weight of the actuator and achieving a higher decoupling frequency. As the number of components for the actuator is reduced, it makes the actuator easier to manufacture and assemble than previous actuator designs with many coils, magnets, and pole pieces. In addition, since the tracking and focusing coils 2-16, 2-18 and 2-20 are directly coupled to the lens holders 2-14 without being wound on the yoke or pole, the coil rigidity and resonance frequency characteristics are significantly improved. Further, the direct coupling of coils 2-16, 2-18 and 2-20 reduces the distance between the point where effective tracking and focusing forces are generated and the objective lens optical axis, thereby reducing unwanted movements such as pan, roll and yaw.

The invention improves the motor characteristics. For an actuator constructed according to the invention, an optimum of 130m/s for the focus direction has been measured²(w) 70m/s for a radial direction²(w). These values are significantly higher than before. Those skilled in the art will recognize that the design of the present invention also ensures that approximately 40% of the coil wire is used, thereby increasing the efficiency of the actuator over previous designs.

A preferred embodiment of the two-axis electromagnetic actuator 2-10 has been described with reference to the coordinate system shown in fig. 26, in which the optical disc 2-76 is positioned above the objective lens 2-12, so that focusing can be accomplished by moving the actuator 2-10 up and down along the Z-axis, and tracking movement can be accomplished by moving the actuator along the Y-axis, side-to-side. However, those skilled in the art will recognize that the actuators 2-10 of the present invention may also be incorporated in optical systems having orientations other than those shown.

Focus sensing device

Fig. 36 is a block diagram of a preferred embodiment of the beam focus sensing arrangement 3-10 of the present invention. The device 3-10 comprises an optical device 3-12 for providing a servo light beam S showing the focus of the light beam 1 impinging on the optical disc 3-14. The servo beam S comprises a portion of the illumination beam 1 reflected by the disc 3-14. Techniques for generating such servo beams are well known to those skilled in the art. An optical system, i.e. an optical device 3-12 for generating a servo light beam S, is described, for example, in us patent No. 4,862,442, which is incorporated herein by reference. The operation of the optical means 3-12 will be briefly explained further below.

As shown in fig. 36, the optical device 3-12 includes a laser source 3-16 that produces a linearly polarized beam B. The light beam B is collimated by the collimator lenses 3-18 and the collimated light beam is guided onto the objective lenses 3-24 by the optical splitting devices 3-20, and then the collimated light beam is converged onto the surface of the optical disc 3-14 by the objective lenses 3-24. For example, the optical disc may comprise a CD disc, a video disc or an optical storage disc. The disc 3-14 reflects the illumination beam focused thereon back to the beam splitting means 3-20 through the objective lens 3-24. Those skilled in the art will appreciate that the beam splitting means 3-20 may comprise a first beam splitter (not shown) for redirecting a first part of the reflected illumination beam so as to form the servo beam S. The beam splitting means 3-20 will typically also comprise a second beam splitter (not shown) for redirecting a second portion of the reflected illumination beam to produce a data beam carrying information stored on the optical disc 3-14. The servo beam S may be refracted by the FTR prisms 3-30, the design and construction of which will be discussed more fully below.

As described in detail below, the servo beam S is split by the FTR prisms 3-30 into a transmitted beam T and a reflected beam R. In the embodiment of fig. 36, the emitted and reflected beams T and R are substantially equal in cross-section and intensity. The transmitted beam T is incident on the first four-element detector 3-32 while the reflected beam R is incident on the second four-element detector 3-34. The intensity distributions corresponding to the emitted and reflected beams T and R are generated by quadruple detectors 3-32 and 3-34, which are used by control units 3-37 to generate Differential Focus Error Signals (DFES) indicative of the focus of the impinging beam 1 on the optical discs 3-14. A preferred embodiment of the control unit 3-37 and associated method for generating DFES is discussed below. The focus error signal may be used, for example, to control a mechanism (not shown) arranged to adjust the focus of the illumination beam 1 by varying the displacement of the objective lens 3-24 with respect to the disc 3-14.

FIG. 37 shows an enlarged top cross-sectional view of FTR prisms 3-30. The prism 3-30 includes first and second optical elements 3-35 and 3-36 sandwiching a separation layer 3-38, and the optical elements 3-35 and 3-36 may be made of glass having a refractive index greater than that of the separation layer 3-38. For example, in a preferred embodiment, the optical elements 3-35 and 3-36 may be made of glass having a refractive index of 1.55, while the separation layer 3-38 may be composed of a solid such as one of magnesium fluoride (MgF2) or silica (SiO2) having refractive indices of 1.38 and 1.48, respectively. The separation layers 3 to 38 may be made of liquid or air as long as the optical elements 3 to 35 and 3 to 36 have a large refractive index may not necessarily be made of solid.

The physical significance of the interaction of the light in the beam S with the layers 3-38 is briefly explained below. If the layers 3-38 and the optical elements 3-35 are not present, the well-known phenomenon of total internal reflection occurs at the inclined planes of the optical elements 3-36, emitting all the light beams S in the direction of the light beam R, however, some light can exist behind the inclined planes of the optical elements 3-36 in the form of "evanescent waves" that do not propagate. When the optical element 3-35 is brought close enough to the optical element 3-36, this energy will couple into the element 3-35 without loss and propagate in the direction of the beam T. This phenomenon is called Frustrated Total Reflection (FTR). In this case, if the FTR prism is positioned relative to the light beam S such that the angle of incidence A of the light beam S on the separating layers 3-38 is close to the frustrated total reflection region, the transmitting and reflecting wires will have a steep slope (angular sensitivity). This allows the manufacture of very sensitive focus sensing systems. In addition, the emission and reflection curves for this system based on the FTR principle are relatively insensitive to the wavelength of light of the light beam S, compared to the curves for the multilayer structure.

The prisms 3-30 may be made by first depositing a release layer on either of the two optical elements by conventional thin film techniques. The interconnected optical elements may then be bonded to the exposed surface of the release layer with an optical adhesive. Although the refractive indices of the first and second optical elements 3-35 and 3-36 are usually chosen to be the same, it is also possible to choose different refractive indices. In a preferred embodiment, the first and second optical elements have the same refractive index, in such a geometry that the emitted and reflected light beams T and R have substantially the same cross-section.

As shown in the front view of fig. 38, the first quaternary detector 3-32 includes first, second, third and fourth photocells 3-40, 3-42, 3-44 and 3-46, which respectively generate electrical signals corresponding to the intensity of the emission beam T incident thereon, hereinafter referred to as T1, T2, T3 and T4. Similarly, the second four-element detector 3-34 includes fifth, sixth, seventh and eighth photosensors 3-50, 3-52, 3-54 and 3-56, respectively, which provide electrical signals corresponding to the incident reflected light beam R, hereinafter referred to as R1, R2, R3 and R4. The light measuring elements may be PIN diodes, wherein the level output by each diode is proportional to the light energy it receives.

When the objective lenses 3-24 of fig. 36 are positioned with respect to the discs 3-14 such that the beam I is correctly focused, the light rays contained in the servo beam S are collimated (i.e. substantially parallel) and thus incident on the separating layers 3-38 at substantially the same angle a, as shown in fig. 37. In contrast, when the objective lens 3-24 does not focus the beam on the plane occupied by the surface of the disk 3-14, the rays constituting the servo beam S will either converge on each other or diverge. All light rays within the servo light beam S will therefore impinge on the separating layers 3-38 at substantially the same angle when the light beam I is properly focused, whereas light rays of various angles of incidence will access the addressed separating layers 3-38 when the light beam I is not focused. The prisms 3-30 are designed such that the reflectivity and transmission of the separating layer 3-38 are extremely sensitive to the angle of the light energy incident on the separating layer 3-38. Thus, the spatial distribution in the intensity of the emitted and reflected beams T and R will vary as the focus position of the beam I relative to the surface of the discs 3-14 changes. I.e. a suitably focused beam I, generates a sufficiently collimated servo beam S so that all light rays therein are subject to the same degree of reflection by the separating layers 3-38. Thus, the transmitted and reflected beams T and R will be substantially uniform in intensity when the beam I is properly focused. In contrast, a converging or diverging servo beam S will produce emitted and reflected beams T and R with a non-uniform spatial intensity distribution, because the light rays in the servo beam S are reflected to different degrees by the separating layers 3-38. By detecting the spatial variation in the intensity of the emitted and reflected beams, the optical detectors 3-32 and 3-34 generate electrical signals that can be used to generate DFES indicative of the location of focus of the optical beam I.

The manner in which DFES can be combined, depending on the degree of collimation of the servo beam S, can be further understood with reference to fig. 39. Fig. 39 shows the reflectivity of the FTR prisms 3-30 (intensity of the light beam R ÷ intensity of the light beam S) as a function of the angle of incidence of the light rays in the servo light beam S with respect to the separating layers 3-38. Specifically, the curves of FIG. 39 show the reflectivities Rs and Rp of prisms 3-30 in response to illumination with S-polarized and P-polarized light energy at a wavelength of 0.78 μm. The reflectivity curve of fig. 39 is for an FTR prism 3-30 having a separating layer 3-38 with a thickness of 4.5 μm and a refractive index of 1.38 sandwiched by a glass element with a refractive index of 1.55. As shown in FIG. 39, the prisms 3-30 are preferably positioned at an angle of incidence A1 with respect to the servo light beam S such that the prisms 3-30 operate near the operating point P. I.e. at the working point P the prisms 3-30 are positioned such that a beam I properly focused on the disc 3-14 results in a well collimated servo beam S having an angle a₁Light rays impinging on the separating layers 3-38. Since the reflectivity of the prisms 3-30 is approximately 0.5 at the operating point P, the average intensity of the transmitted and reflected beams produced by the optical device 3-12 including the prisms 3-30 is substantially equal.

When the separation between the objective lens 3-24 and the disc 3-14 is changed such that the servo beam S is de-collimated in a converging or diverging manner, a first part thereof will be larger than a ₁Is projected onto the separating layers 3-38. For example, the incident angle A in FIG. 39₂The corresponding portion of the servo beam will then experience a reflectivity of approximately 0.7. Since the first servo beam portion experiences a reflectivity of only 0.5 when the servo beam S is sufficiently collimated, the areas of the detectors 3-32 and 3-34 that receive portions of the reflected and transmitted beams R and T from the first servo beam portion will gather more and less light energy, respectively, than when the beam I is properly focused. Similarly, the area of detectors 3-32 and 3-34, which sum is at less than angle A₁Angle of incidence A₃The portions of the second portion of the servo light beam S that are incident on the separate layers 3-38, which are optically aligned with the transmitted and reflected light beams T, R, will be illuminated by more and less light energy, respectively, than under appropriate focusing conditions. DFES is generated in response to electrical signals generated by the photodetectors 3-32 and 3-34 that represent the non-uniformity of the spatial distribution of the intensity of the transmitted and reflected beams T and R. Moreover, because in the preferred embodiment described herein the prisms 3-30 are non-light absorbing, the change in intensity of the transmitted beam T caused by the change in the angle of incidence of a portion of the servo beam S is reflected as an equal and opposite change in the magnitude of the portion of the reflected beam R produced by the same servo beam portion. The non-differential error signal can be generated independently from the transmitted or reflected beam using the following formula:

(1) FES (transmissive) ═ T1+ T2) - (T3+ T4)

(2) FES (reflected) (R1+ R2) - (R3+ R4) in a differential system, a differential error signal is generated by the control unit 3-37 according to:

(3)DFES＝(R1+R2+T3+T4)-(T1+T2+R3+R4)

the control units 3 to 37 include circuits for performing the operation of the formula (3), and generate DFES according to these operations. Pre-amplifiers (not shown) are included to amplify the electrical signals from the photo-detectors 3-32 and 3-34 before processing by the control unit 3-37.

The use of the bi-directional four-way optical detector arrangement described herein results in the synthesis of a differential focus error signal having reduced sensitivity to certain imperfections in the optical beam which are not the effect of inaccuracies in the focus position of the optical beam relative to the discs 3-14. Since the local reduction in servo beam intensity, independent of the focus position of the beam, affects detectors 3-32 and 3-34 in substantially the same way, this reduction does not affect the value of DFES due to the corresponding cancellation produced in equation (3).

In the background of the invention as described above, the existing focusing system is not generally suitable for performing the differential focus detection apparatus described by the formula (3). In particular, it is a feature of the present invention that the FTR prisms 3-30 are capable of providing transmitted and reflected beams of substantially the same cross-section and intensity, so that both can be effectively used to synthesize DFES.

In addition to providing DFES for maintaining the focus of the light beam I in a direction perpendicular to the surface of the disc 3-14, the electrical outputs from the light detectors 3-32 and 3-34 may also be used by the control unit 3-37 to generate a Tracking Error Signal (TES). TES represents the radial position of the light beam I with respect to a conventional spiral or concentric guiding track (not shown) embossed on the surface of the disc 3-14. The TES enables the light beam I to follow the guiding track regardless of the eccentricity therein, which is achieved by controlling a mechanical device (not shown) which is effective to adjust the radial position of the objective lens 3-24 relative to the disc 3-14. TES is calculated by the control means 3-37 based on the electrical outputs from the light detectors 3-32 and 3-34 as follows:

(4)TES＝(T1+T3+R3+R1)-(T2+T4+R2+R4)

furthermore, methods are disclosed in e.g. us 4,707,648, in which a tracking error signal can be derived from the relation existing between the change in spatial intensity of the servo beam and the tracking position of the beam.

It is always desirable in perhaps most systems for controlling the focus of a light beam relative to an optical disc to generate both tracking and focus error signals in response to the electrical output of a light detecting element. Since it is known that at least one loop light detector is generally required to generate both focus and tracking error signals, embodiments of the invention disclosed herein are described with reference to a loop light detector. It is also known, however, that the focus error signal can be derived from an electrical signal generated by a light detector having only two independent light sensitive areas (dual element detector). Thus, in applications where only a focus error signal needs to be generated, one light detecting element may replace the first and second elements 3-40 and 3-42 of the light detectors 3-32 and one light detecting element may replace the third and fourth elements 3-44 and 3-46. Similarly, one light detecting element may be used in place of the fifth sixth elements 3-50 and 3-52 of the light detectors 3-34, and one element may be used in place of the seventh eighth elements 3-54 and 3-56.

The slope of the reflectivity curve of fig. 39 near the operating point P is proportional to the sensitivity of the DFES produced by the devices 3-10. In particular, the sensitivity of the device 3-10 to focus changes of the light beam I increases with increasing slope of the sensitivity curve. It is therefore an object of the present invention to provide prisms 3-30 which are characterized by a reflectivity curve which is as steep as possible.

The shape of the reflectivity curve of fig. 39 near the operating point P can be varied by adjusting the thickness of the separation layers 3-38. For example, increasing the thickness of the separation layers 3-38 will shift the minimum reflectance angle Am toward the limiting angle Ac shown in fig. 39 without affecting the value of the limiting angle Ac. Thus, increasing the thickness of the separation layer may increase the slope of the reflectivity curve near the operating point P. Similarly, decreasing the thickness of the separation layers 3-38 may increase the angular displacement between the limit angle Ac and the minimum reflectance angle Am. The shape of the reflectivity curve of the prisms 3-30 can be varied to adjust the sensitivity of the DFES. A suitable slope may be obtained by, for example, using a separating layer having a thickness greater than half the wavelength of the light beam I.

The value of the limiting angle Ac can be adjusted by changing the refractive index of the separation layer 3-38 with respect to the glass elements 3-35 and 3-36. In this way, the adjustment of the thickness of the separation layer in combination with the adjustment of the refractive index of the separation layer and the surrounding glass elements can be produced using the prisms 3-30 according to the desired reflectivity profile.

Fig. 40 is a plot of the nominal values of dfes (ndfes) produced by the apparatus 3-10 as a function of the deviation of the objective lens 3-24 from the desired displacement of the disc 3-14.

The data of FIG. 40 was again obtained using prisms 3-30 having a 4.5 μm thick 1.38 index release layer sandwiched between glass elements having an index of refraction of 1.55, with prisms 3-30 being illuminated with a 0.78 μm wavelength servo beam. As shown in fig. 40, the value of DFES is preferably zero when there is a desired displacement between the objective lens 3-24 and the disc 3-14. The sign (+ or-) of DFES represents that the displacement between the objective lens and the disc surface is larger or smaller than required for proper focusing. As mentioned above, the DFES may be used to control a mechanism (not shown) for adjusting the distance between the objective lens 3-24 and the disc 3-14. It is reasonably important to note that the slope of NDFES is approximately 0.16 μm '(-1') at the operating point defined by 0 (zero) disk displacement.

Although it has been described that the servo beam S should be substantially collimated when incident on the separating layers 3-38, the invention is not limited to configurations that produce only a collimated servo beam. When using a converging or diverging servo beam, a misalignment of the focus position of the beam will change the degree to which it converges or diverges. Those skilled in the art will appreciate that the focus detection apparatus of the present invention may be used to generate DFES based on such changes in convergence or divergence.

The focus detection apparatus of the present invention has been shown to overcome the disadvantages inherent in other focus detection systems by providing transmitted and emitted light beams of substantially identical shape and intensity from which a highly accurate, amplitude (amplitude) insensitive focus error signal can be uniquely derived. The focus detection techniques disclosed herein still retain certain characteristics that are present in related focus detection systems, such as low sensitivity to mechanical vibrations, low sensitivity to disk tilt, and enhanced thermal stability.

Seek actuator

Fig. 41 schematically illustrates the operation of an exemplary optical read/write system 4-50 for reading data from an information storage medium, such as an optical disc 4-54, at a precise location 4-52. While the illustrated systems 4-50 are write-once or WORM systems, those skilled in the art will appreciate that the carriage and actuator assembly of the present invention may also be used in magneto-optical erasable systems. Information is transferred to and read from the disc 4-54 by means of a light beam 4-56 generated by a light source 4-58, which passes through several elements, including a cube-shaped beam splitter 4-60, which splits the light beam 4-56 according to its polarization, a quarter-wave plate 4-62, which changes the polarization of the light beam 4-56, a collimator lens 4-64 and an objective lens 4-66, which jointly act to direct the light beam 4-56 to a desired position 4-52 on the disc 4-54.

In operation, the light source 4-58 (which is typically a laser diode) emits a light beam 4-56 toward the convex collimating lens 4-64. The collimator lens 4-64 converts this source light beam 4-56 into a parallel linear S-polarized light beam 4-70 and directs it towards the beam splitter 4-60. The cube-shaped beam splitter 4-60 is formed by joining two right angle prisms 4-72 and 4-74 along their respective hypotenuses and includes a polarization sensitive coated beam splitter 4-60 that separates and/or combines beams of different polarization states, i.e., linear S-polarization and linear P-polarization, between the two hypotenuses forming a beam splitting interface 4-76. The separation is accomplished by a polarization sensitive coating that transmits a linear P-polarized beam and reflects a linear S-polarized beam. The light from the beam splitter 4-60 passes through a quarter wave plate 4-62 which converts the linearly polarized light beam 4-70 into a circularly polarized light beam 4-78. The circularly polarized light beam 4-78 exits the quarter wave plate 4-62 and enters the actuator 4-80.

The actuator 4-80 comprises a mirror 4-82 which reflects the light beam 4-78 perpendicularly upwards towards the objective lens 4-66. The objective lens 4-66 converges the circularly polarized light beam 4-78 to a precise focal point 4-52 on the surface of the disc 4-54. When illuminated onto the disc 4-54, the circularly polarized light beam 4-78 is altered by the information stored on the disc 4-54 and reflected as a diverging circularly polarized light beam 4-84 carrying the same information as the information encoded on the disc 4-54. The reflected circularly polarized light beam 4-84 re-enters the objective lens 4-66 to be collimated. The light beam 4-84 is again reflected from the mirror 4-82 and re-enters the quarter wave plate 4-62. After emerging from the quarter-wave plate 4-62, the circularly polarized light beam is converged into a linearly P-polarized light beam 4-86. As the linear P-polarized beam is transmitted through the beam splitter 4-60 and not reflected at the splitting interface, the beam 4-86 continues to enter the photodetector 4-88, which detects the data stored on the disk 4-54. Furthermore, if the beam 4-86 falling on the photodetector 4-88 is defocused or misaligned, the degree of misalignment or defocusing is electronically measured as feedback for a servo system (not shown) to re-align the objective lens 4-66 correctly.

Fig. 42 illustrates an electromagnetic cradle and actuator assembly 4-100 constructed in accordance with the present invention. This assembly may be used in conjunction with an optical assembly 4-102 to read and write data on the surface of an optical disc as described above in connection with fig. 41, where the light source 4-58, the detector 4-88, the collimating lens 4-64, the quarter wave plate 4-62 and the beam splitter 4-60 are all contained within the assembly 4-102. The spindle motor 4-104 is located adjacent to the assembly 4-100 and rotates an optical disc (not shown) about the rotational axis a of the assembly 4-100. The assembly 4-100 comprises a carriage 4-106 having a first and a second bearing surface 4-108 and 4-110 slidably mounted on a first and a second guide rail 4-112 and 4-114, respectively, and an actuator 4-116 mounted on the carriage 4-106. It will be appreciated that the guide rails 4-112 and 4-114 provide a frame for movement of the carriage. A light beam 4-120 emitted from a light source 4-58 in an optical assembly 4-102 enters the actuator 4-116 through a circular aperture 4-118 and is reflected by a mirror mounted inside the actuator through an objective lens 4-122 defining an optical axis O to the surface of the disc. It will be appreciated that the axis of rotation a of the disc is parallel to the optical axis O of the objective lenses 4-122.

The carriage 4-106 and the actuators 4-116 thereon are moved horizontally along the guide rails 4-112 and 4-114 in the tracking direction by a coarse tracking motor to access the respective information tracks on the disc surface. The tracking motor comprises two permanent magnets 4-130 and 4-132 each of which is fixed to the C-shaped outer pole pieces 4-134 and 4-136, respectively. The two inner pole pieces 4-138 and 4-140 span the ends of the outer pole pieces 4-134 and 4-136, thereby forming a rectangular box around the permanent magnets 4-130 and 4-132. The two equal length coarse tuning coils 4-142 and 4-144 are equal in length and are fixed to the vertical plates 4-174 and 4-176 of figure 43 and surround the inner pole piece with sufficient clearance to move over the pole pieces 4-138 and 4-140 as the carriage 4-106 moves in the tracking direction. In the present embodiment, these coarse tuning coils 4-142 and 4-144 are the only movable parts of the coarse tracking motor. As will be explained in more detail below, the actuator 4-116 may also move the objective lens 4-122 closer to or further from the disc, so as to focus the emitted light beam 4-120 at a desired location on the disc surface.

Fig. 43 is a detailed view of the carriage 4-106 and the actuator 4-116. The carriage 4-106 includes a generally rectangular base 4-150 to which the actuator 4-116 is secured. The susceptor 4-150 has a substantially flat top surface 4-152 in which a generally rectangular chamber 4-154 is formed. The first bearing surface 4-108 is cylindrical, while the second bearing surface 4-110 is constituted by two oval bearing portions 4-160 and 4-162, approximately equal in length and meeting inside the seat 4-150. The spacing of the guide rails 4-112 and 4-114 with respect to the optical axis O is chosen such that each bearing surface 4-108 and 4-110 is subjected to the same amount of preload (prelad). The bearing surfaces 4-108 and 4-110 are also designed so that the two surfaces have substantially the same surface area in contact with the rails 4-112 and 4-114. The length of the load-bearing portion making up the second load-bearing surface is approximately equal to the length of the first load-bearing surface, although minor differences in length may be required to account for wear.

Two vertical walls 4-156 and 4-158 extend upwardly from the top surface 4-152 of the base 4-150 near the ends of the chambers 4-154. The base 4-150 also includes two land areas 4-164 and 4-166 that form the ends of the base 4-150 above the support sections 4-108 and 4-110. The step 4-168 connects the top surface 4-152 of the base 4-150 with the second land area 4-166. A first U-shaped notch 4-170 is formed in the first land area 4-164 and a second U-shaped notch 4-172 is formed in the second land area 4-166 and the step 4-168.

The coarse tuning coils 4-142 and 4-144 are fixed to two vertical plates 4-174 and 4-176, respectively. The plates 4-174 and 4-176 are located in notches 4-180 and 4-182, respectively, at the ends of the bases 4-150. The base 4-150 further includes a mass balance plate 4-184 secured to the bottom surface 4-186 of the base 4-150 by screws 4-188, and a mass balance projection 4-190 extending outwardly from the base 4-150 adjacent the first coarse tuning coil 4-142. The circular hole 4-192 is formed at the front side of the base 4-150 and receives the light beam 4-120 emitted from the light assembly 4-102 in fig. 42. The bracket 4-196 having the circular hole 4-198 therein is disposed between the second vertical wall 4-158 and the first plateau region 4-164 along the front side 4-194 of the base 4-150. The holder 4-196 further comprises an indentation 4-200 which receives the light detector 4-202 such that the light detector 4-202 is located between the holder 4-196 and the first plateau region 4-164.

The actuator 4-116, commonly referred to as a "2-D" actuator for two-dimensional (degree) movement, i.e. focusing and tracking, is mounted between the vertical walls 4-156 and 4-158 and the land areas 4-164 and 4-166. A prism (not shown) is located within the chamber 4-154 of the base 4-150 for refracting the light beam 4-120 emitted from the light assembly 4-102 such that the light beam exits the actuator 4-116 through the objective lens 4-122. The objective lens 4-122 is located in a lens holder 2-210 which is connected to a focus and fine tracking motor which moves the objective lens 4-122 to accurately align and focus the outgoing light beam 4-120 at a desired position in the plane of the optical disc. The objective lenses 4-122 define an optical axis O extending vertically through the center of the lenses.

The elements of the actuators 4-116 can best be seen in fig. 44. Lens holder 4-210 is substantially rectangular and includes a substantially rectangular opening 4-212 therethrough. The top surface 4-214 of the lens holder 4-210 comprises a circular collar 4-216 located between two shoulders 4-218 and 4-220. A circular aperture 4-222 having a diameter substantially equal to that of the circular collar 4-216 is formed in the bottom surface 4-224 of the lens holder. The rectangular focusing coil 4-230 is located within the rectangular opening 4-212 of the lens holder 4-210. Two elliptical thin tracking coils 4-232 and 4-234 are located at the corners of a first end 4-240 of the focusing coil 4-230 and two other identical tracking coils 4-236 and 4-238 are located at the corners of a second end 4-242 of the focusing coil 4-230. A first pair of U-shaped pole pieces 2-244 surrounds a first end 4-240 of the focusing coil 4-230 and the tracking coils 4-232 and 4-234 attached to the first end, while a second pair of U-shaped pole pieces 4-246 surrounds a second end 4-242 of the focusing coil 4-230 and the tracking coils 4-236 and 4-238 attached to the second end. Furthermore, two permanent magnets 4-250 and 4-252 are located between the respective pole piece pairs 4-244 and 4-246, adjacent to the respective tracking coils 4-232, 4-234 and 4-236, 4-238.

Two top curved arms 4-260 and 4-262 are connected to the top surface 4-214 of the lens holder 4-210 and two further bottom curved arms 4-264 and 4-266 are connected to the bottom surface of the lens holder 4-210. Each flexure arm is preferably constructed of an etched or stamped sheet of metal (typically steel or beryllium copper) having a thickness on the order of 25 to 75 μm. For simplicity, only flexure arms 4-260 will be described. It should be noted, however, that the remaining flexure arms 4-262, 4-264 and 4-266 are substantially identical in construction. The flexure arm 4-260 includes a first vertical portion 4-270 connected to first, second and third horizontal portions 4-272, 4-274 and 2-276. The third horizontal portion 4-276 is also connected to a cross arm 4-280 at right angles thereto. The first horizontal portion 4-272 includes a shoulder 4-218 that is connected to a corresponding shoulder 4-218 on the lens holder 4-210. In a similar fashion, the shoulders of the second top curved arms 4-262 are connected to corresponding shoulders 4-220 and the shoulders of the bottom curved arms 4-264 and 4-266 are connected to corresponding structures on the bottom surface of the lens holder 4-210.

The curved arms 4-260, 4-262, 4-264 and 4-266 are also connected to the support 4-290. The support member 4-290 includes a central indentation 4-292 that receives the second pair of pole pieces 4-246. A projection 4-294 is formed on each side of the notch 4-292 on the top and bottom surfaces of the support member 4-290. The cross arm portions 4-280 of the flexure arms 4-260 and 4-262 are connected to these projections 4-294, while the flexure arms 4-264 and 4-266 are connected to corresponding projections on the bottom of the support 4-290, so that the lens holder 4-210 is suspended from the support 4-290 in common. The support 4-290 also includes holes 4-296 for receiving the leds 4-300. The diodes 4-300 are aligned with the apertures 4-198 in the brackets 4-196 of fig. 43 and the photodetectors 4-202 located within the notches 4-200 on the brackets so that when the light emitting diodes 4-300 are activated, substantially collimated light is emitted from the apertures 4-198 of the brackets 4-196 and is incident on the photodetectors 4-202. Depending on the position of the lens holder 4-210 relative to the support 4-290, the light emitted by the diode 4-300 will fall on different parts of the detector 4-202. By analyzing the amount of light incident on the detectors 4-202, a position correction signal can be generated to determine the amount of displacement required for accurate focusing and tracking at the desired location on the surface of the disc.

In the illustrated embodiment, the fine adjustment motor generally comprises a lens holder 4-210, an objective lens 4-122 focusing coil 4-230 and fine tracking coils 4-232, 4-234, 4-236 and 4-238. The carriage generally comprises a base 4-150, coarse tracking coils 4-142 and 4-144, a support 4-196, and photo detectors 4-202, a support 4-290, vertical plates 4-174 and 4-176, a mass balance plate 4-184 and a screw 4-188, permanent magnets 4-250 and 252, pole pieces 4-244 and 4-246, and bearing surfaces 4-108 and 4-110.

Referring to the above description in conjunction with fig. 43 and 44, the coarse tracking coils 4-142 and 4-144 have equal sizes and are symmetrical about the optical axis O of the objective lens. Furthermore, the tracking coil pairs 4-232, 4-234 and 4-236, 4-238 have equal dimensions symmetrical about the optical axis O of the lenses 4-122. The mass balance plates 4-184 and mass balance protrusions 4-190 are advantageously selected to compensate for the mass of the supports 4-290, flexure arms 4-260, 4-262, 4-264, 4-266, bearing surfaces 4-108, 4-110, supports 4-196 and photodiodes 4-202, so that the center of mass of the carrier and the center of mass of the fine and focus actuator (including the plate shoes 4-244, 4-246, permanent magnets 4-250, 4-252, focus coils 4-230, and tracking coils 4-232, 4-234, 4-236, 4-238) substantially intersect the optical axis O of the lenses 4-122. As will be explained in more detail below, the alignment of these centers of gravity with the optical axes of the lenses 4-122 and the symmetry of the forces and reactions of the motors acting on the carriages 4-106 and the actuators 4-116 ensure that the movement patterns which would adversely affect the position of the objective lenses 4-122 are minimized.

Referring to fig. 45, the permanent magnets 4-130, 4-132 adjacent to the coarse tracking coils 4-142, 4-144 produce a magnetic field B whose field lines extend inward into the coarse tracking coils 4-142 and 4-144. When the coarse tracking movement is to position the objective lens 4-122 under a selected track on the optical disc, a current is fed to the coarse tracking coils 4-142, 4-144. The interaction of the current with the magnetic field B generates a force that moves the carriage 4-106 in the tracking direction. The force is generated according to Lorentz's law F ═ B · X · I · l, where, as described above, F represents the force acting on the focusing coil, B represents the magnetic flux density of the magnetic field between the two permanent magnets, I represents the current flowing through the focusing coil, and l represents the length of the coil. For example, when feeding inA coarse tracking coil 4-142 generates a force F in the direction of arrows 4-320 when a current I flows through the portion of the coil located in the magnetic field B in a direction into the plane of FIG. 45_Coarse1. Similarly, when a current I flows through the portion of the second tracking coil 4-144 that is in the magnetic field B that is in a direction out of the plane of FIG. 45, a force F in the direction of arrows 4-322 is generated_Coarse2. Force F_Coarse1And F_Coarse2Causing the carriage 4-106 to move horizontally to the left.

In contrast, FIG. 46 shows the force F if the direction of the current I in the tracking coils 4-142, 4-144 within the magnetic field B is reversed _Coarse1And F_Coarse2The carriage will be moved in the direction into the page in fig. 46 (to the right in fig. 45). The amount of movement in the tracking direction depends on the amount of current supplied to the coarse tuning coils 4-142 and 4-144. In this way, the movement of the carriage 4-106 positions the objective lens such that the laser beam 4-120 emerging from the lens 4-122 is focused in the desired information track on the surface of the optical disc.

When the control signal is generated by the optical component 4-102, a given current is applied to the fine tracking coils 4-232, 4-234, 4-236 and 4-238 or to the focusing coils 4-230, depending on the direction of the required displacement of the lens holder 4-210 and the objective lens 4-122 attached thereto. Such servo systems and feedback circuits for controlling the amount of current are well known. The interaction of this current and the electromagnetic field generated by the permanent magnet 4-250, 4-252 generates a force that moves the lens holder 4-210 and the objective lens 4-122 attached thereto in the appropriate tracking or focusing direction. If, for example, a repositioning in the focus direction according to the focus error signal is desired, this signal is transmitted to a servo amplifier (not shown) which generates a current through the focus coils 4-230. As described above, the force is generated according to Lorentz's law F ═ B · X · I · l.

Referring now to FIG. 47, the permanent magnets 4-250 and 4-252 of the two-dimensional actuator 4-116 are aligned such that the south pole of each magnet 4-250, 4-252 faces the lens holder 4-210. In this configuration, a magnetic field B is formed, the field lines of which emanate from the magnets 4-250, 4-252 and are directed towards the inside of the lens holder 4-210, as shown. When a current I flows in the focusing coil 4-230 and through the coil 4-230 portion in the magnetic field B in the direction shown, an upward force FFocus is generated in each portion of the focusing coil 4-230, which is transferred to the flexure arms 4-260, 4-262, 4-264, and 4-266, causing the flexure arms to flex, thereby moving the lens holder 4-210 and the associated objective lens 4-122 closer to the optical disc. Conversely, when the current I is moved in the opposite direction to that described above, a downward force is generated on the flexure arms, thereby moving the lens holder 4-210 and the objective lens 4-122 away from the disc surface. The magnitude of the displacement depends on the magnitude of the current applied to the focusing coils 4-230. By moving the objective lens 4-122 closer to or away from the disc surface, the laser beam 4-120 emerging from the objective lens 4-122 is accurately focused in the desired information track on the disc by the focusing coil 4-230.

As shown in fig. 48, the movement of the actuator 4-116 to achieve fine tracking occurs when currents are generated in the 4 fine tracking coils 4-232, 4-234, 4-236, and 4-238, which are fixed to the focusing coil 4-230. When a current is applied to the tracking coil in the direction shown through the portion of the tracking coil that is within the magnetic field B, a force FTrack is generated, moving the lens holder 4-210 to the right. When the force FTrack acts on the tracking coils 4-232, 4-234, 4-236 and 4-238, they are transmitted via the focusing coils 4-230 and the lens holder 4-210 to the bending arms 4-260, 4-262, 4-264 and 4-268, which are bent in the respective directions, whereby the objective lens 4-122 is moved to the right in fig. 48 in the direction of the force. When current is passed through tracking coils 4-232, 4-234, 4-236, and 4-238 in the opposite direction, a force is generated that moves lens holder 4-210 to the left. The currents applied in the fine tracking coils 4-232, 4-234, 4-236 and 4-238 are relatively small compared to the currents applied in the coarse tracking coils 4-242, 4-244, and thus these fine tracking coils are also much smaller in size than the coarse tracking coils in order to increase the resonance frequency, so that a higher servo bandwidth is possible in order to control for a tighter tracking error.

Fig. 49A-56B are schematic views of actuators and carriage assemblies 4-100 illustrating the symmetry and balance of forces achieved with the design of the present invention.

Fig. 49A is a schematic diagram illustrating the coarse tuning or carrier electrodynamic symmetry acting on the actuators 4-116 in the horizontal plane. When a current is applied to the coarse tracking coils 4-142 and 4-144 as described above, a force F is generated_Coarse1And F_Coarse2Which are concentrated in the portions of the coarse tuning coils 4-142, 4-144 located near the permanent magnets 4-130 and 4-132, respectively. The first coarse tuning coil 4-142 is selected to be equal in size to the second coarse tuning coil 4-144 and the current in each coil is made the same so that the force F acting on the coil is made to be equal_Coarse1And F_Coarse2Are equal. Furthermore, the distance L of the coils 4-142 and 4-144 from the objective lens 4-122 is coarsely adjusted_C1And L_C2Equality and thus the resulting moments about the optical axis O about the objective lenses 4-122, thus minimizing longitudinal side-to-side rocking (yaw) of the carriage. In fig. 49B, the coarse electromotive force F is shown on the vertical plane_Coarse1And F_Coarse2Of the center of (c). Due to force F_Coarse1And F_Coarse2Aligned vertically with the center of the carrier mass CMC (i.e., they typically intersect a line perpendicular to the radial direction and to the optical axis containing the carrier mass center CMC), the torques about the horizontal axis are equal and the carrier pitch (pitch) that can cause the prism to angularly deflect the beam to introduce a tracking offset is reduced.

Fine tracking electrodynamics in the horizontal and vertical planes are shown in fig. 50A and 50B. Force F resulting from the excitation of the thin tracking coils 4-232, 4-234, 4-236 and 4-238 within the magnetic field produced by the permanent magnets 4-250 and 4-252_Track1And F_Track2Are concentrated between the thin tracking coil pairs 4-232, 4-234 and 4-236, 4-238 and extend horizontally in the tracking direction. The coils are of equal size and the amount of current applied is equal, so that the resultant force F_Track1And F_Track2Are equal. Further, the distances LT of the thin tracking coils 4-232, 4-234, 4-236 and 4-238 from the optical axis O of the lenses 4-122 are equal. The resulting torque about the optical axis O is equal so that the longitudinal side-to-side rocking of the lens holder 4-210 and the lens 4-122 thereon about the vertical axis is reduced. As shown in FIG. 50B, the resultant fine tracking force F_TrackActing on fine-tuning electric partsThe center of mass of the CMF is divided to minimize lens holder tilt.

Fig. 51A shows a reaction force F from the fine tracking motor_React1And F_React2They track the motor force F along the fine adjustment shown in FIG. 50A_Track1And F_Track2The opposite direction acts on the carriers 4-106. These reaction forces F_React1And R_React2Acting on the pole pieces 4-244 and 4-246 on the tracking coils 4-232, 4-234, 4-236 and 4-238 on each side of the lens holder 4-210. As described above, the force F is tracked _Track1And F_Track2Are equal in size. Furthermore, the pole shoes 4-244, 4-246 are also of the same size, so that a reaction force F is generated_React1And F_React2Are equal. Because the pole pieces 4-244 and 4-246 are equidistant from the optical axis O of the lenses 4-122 by the same distance LR, the torque about the optical axis O is equal in magnitude, thereby reducing rotation about a vertical axis or longitudinal side-to-side rocking. FIG. 51B shows the resultant reaction force F in the vertical plane_React. As shown, the reaction force F_ReactActing on the mass centre CMF of the fine adjustment motor as a whole, at a distance LRM above the mass centre CMC of the carrier, a torque will act on the carrier 4-106. However, because of the distance LRM and the reaction force F_React1And F_React2Are relatively small and so this torque is also relatively small and does not significantly affect the performance of the carrier.

The resulting focusing force F acting on the actuators 4-116_Focus1And F_Focus2As shown in fig. 52A. Focusing force F_Focus1And F_Focus2Concentrated on the portion of the focusing coil 4-230 located between the tracking coils 4-232, 4-234, 4-236 and 4-238 and the pole pieces 4-244, 4-246, close to the permanent magnets 4-250 and 4-252. The focusing coils 4-230 are wound in the openings 4-212 of the lens holder 4-210 of fig. 44, with the same current flowing through each side of the coils 4-230 adjacent to the magnets, thereby creating equal forces F on the sides of the lens holder 4-210 _Focus1And F_Focus2The lens holder 4-210 and the objective lens 4-122 thereon are moved in the vertical direction. The coil is paired in the opening 4-212 of the lens holder 4-210Is arranged symmetrically so that the force F generated_Focus1And F_Focus2Are equidistant from the optical axis O of the objective 4-122 by an equal distance LF. In this configuration, the torque generated about the optical axis O of the lenses 4-122 is equal, thereby reducing the lateral side-to-side (roll) of the lens holder 4-210. Further, as shown in fig. 52B, when viewed from the end of the carriage, the focusing force F_Focus1And F_Focus2(in the figure, F)_Focus) Aligned with the center of mass CMC of the carriage mass, thereby reducing pitch and yaw of the carriage 4-106.

The response to the focusing force F is shown in the plane of FIG. 53A_Focus1、F_Focus2And the generated reaction forces FFR1 and FFR 2. They and focusing force F_Focus1、F_Focus2Are equal and opposite and are concentrated near the fine-tuning-motor permanent magnets 4-250, 4-252 in the middle of the pole shoes 4-244, 4-246. As described above, the focusing force F_Focus1、F_Focus2Equal, and thus reaction force F_FR1、F_FR2And are also equal. Further, the reaction force F_FR1、F_FR2A distance L from the optical axis O of the objective lenses 4-122_FREquality, thereby further reducing pitch and roll. Further, as shown in FIG. 53B, the reaction force F when viewed from the end of the brackets 4 to 106_FR1、F_FR2(in the figure, F)_FR) And center of mass CM of the carrier mass _CAlignment, thereby reducing pitching and rolling of the carriage.

The forces F generated by the flexure arms 4-260, 4-262, 4-264 and 4-266 on the lens holder 4-210 are shown in FIG. 54_Flex1、F_Flex2. Force F shown_Flex1、F_Flex2Acting on the upper curved arms 4-260, 4-262, it will be apparent to those skilled in the art that the same forces also act on the lower curved arms 4-264, 4-266. Force F acting on upper bent arms 4-260, 4-262_lex1、F_Flex2Respectively, on the crossbar portions 4-280 of the arms 4-260, 4-262, respectively, which secure the arms to the support 4-290. When these forces F are applied, as described above_Flex1、F_Flex2When acting on the curved arms 4-260, 4-262, these curved arms are bent in the appropriate direction, so that fine tracking is achieved. To make it possible toThe bent arms 4-260, 4-262 are kept in their bent state and the fine adjustment motor generates a reaction force F_RA、F_RBConcentrated at the pole shoes 4-244 and 4-246 on each side of the lens holder 4-210. As described above, the bending force F_Flex1And F_Flex2At a distance L from the optical axis O of the focusing lenses 4-122_FlexAnd a reaction force F_RA、F_RBAre respectively at a distance L from the optical axis O_RA、L_RB. It will be apparent to those skilled in the art that the torques about the optical axis O resulting from these pairs of forces are unequal because (F)_Flex1+F_Flex2)L_FlexIs not equal to (F)_RA L_RA+F_RB L_RB). However, because these forces have been effectively decoupled from the carrier except at very low frequencies (typically about below 40Hz), they do not affect the performance of the actuator under most normal operating conditions.

As described above, the carriage 4-106 includes two bearing surfaces 4-108 and 4-110 that are slidably mounted on guide rails 4-112 and 4-114 to position the carriage 4-106 under each data track on the optical disc. In effect, the carriers 4-108, 4-110 act as "springs" that hold the carriages 4-106 above the tracks 4-112, 4-114. Loaded with "spring" stiffness force F_Bearing1、F_Bearing2As shown in fig. 55A. Force F_Bearing1、F_Bearing2Are concentrated on the contact points between the bearing surfaces 4-108, 4-110 and the rails 4-112, 4-114 and extend down through the center of the rails. As described above, the surface contact area between the bearing surfaces 4-108 and the rails 4-112 is approximately equal to the surface contact area between the bearing surfaces 4-110 and the rails 4-114, and thus these stiffness forces F_Bearing1、F_Bearing2Are substantially equal. The bearing surfaces 4-108, 4-110 are at equal distances L from the optical axis O of the lens_BearingThereby equalizing the torques about the optical axis O generated by these forces and thus reducing the longitudinal side-to-side rocking of the bracket. Referring to FIG. 55B, in the vertical plane, the net carriage suspension force F_BearingActing on a point exactly intermediate the two bearings and aligned with the optical axis O.

Function ofFrictional forces F on the carriers 4-108, 4-110 and the rails 4-112 and 4-114_Friction1A、F_Friction1BAnd F_Friction2As shown in fig. 56A. Since the first bearing surface 4-108 comprises two parts 4-160 and 4-162, there are two frictional forces F _Friction1A、F_Friction1BEach associated with a respective bearing portion 4-160, 4-162, centred on the middle of the bearing surface, in the direction of the area in contact with the rails 4-114. Second frictional force F_Friction2Acting on the second bearing surface 4-108 and centred on the middle of the bearing surface, in the direction of contact with the rails 4-112, as shown. Since the contact area of the bearing portions 4-160 and 4-162 forming the first bearing surface 4-110 is substantially equal to the contact area of the second bearing surface 4-108 and the preload and coefficient of friction of the two bearing surfaces are the same, the friction force F is_Friction1A、F_Friction1BThe sum being equal to the friction force F_Friction2. The bearing surfaces 4-112 and 4-114 are at equal distances LF from the optical axis O of the focusing lenses 4-122 and thus equal resultant moments about the optical axes of the lenses. In the vertical plane, the force F_Friction1A、F_Friction1BActing on the contact areas between the rails 4-112, 4-114 and the bearing surfaces 4-108, 4-110, as shown in fig. 56B, they are advantageously designed to cooperate with the centre of mass CM of the carriage_CHorizontally aligned, thereby reducing the torque about the center of mass that can produce pitching and yawing of the carriage.

Fig. 57-60 illustrate the inertial forces acting on the carriage 4-106 and the actuator 4-116 from both vertical and horizontal accelerations. The inertial forces acting on the fine adjustment motor and carriage in response to the vertical acceleration of the assembly are shown in fig. 57. First downward inertial force F in FIGS. 57 and 58A _1FEqual to the mass of the fine-tuning motor multiplied by the acceleration, which acts on the center of mass CM of the fine-tuning motor_F. Second downward inertial force F in fig. 57 and 58B_1CActing on the centre of mass CM of the carriage_CAnd equals the mass of the carriage multiplied by the acceleration. FIGS. 58A and 58B further illustrate the inertial force F_1FAnd F_1CHorizontally aligned with the optical axis O of the objective lenses 4-122.

FIG. 59A illustrates aThe inertial forces used on the coarse line graphs 4-142, 4-144 and the fine motor pole shoes 4-244, 4-246 respectively to generate the acceleration of the carrier and the fine motor. Inertial force F_IC1Acting on the centre of the upper part of the first coarse adjustment coil 4-142, the inertial force F_IC2Acting at the center of the upper part of the second coarse tuning coil 4-144. As mentioned above, the coils 4-142 and 4-144 are of the same size, so that the mass of the first coil 4-142 equals the mass of the second coil 4-144. Each force F_IC1And F_IC2Is equal to the mass of the respective coil multiplied by the acceleration, so that the inertial forces acting on the coils 4-142 and 4-144 are equal. Because of the distance L of the coils 4-142, 4-144 from the optical axis O of the objective lens 4-122_CAre equal, so that the inertial force F_IC1And F_IC2The resulting moments about the optical axis are generated equally. Similarly, because the pole pieces 4-244 and 4-246 of the fine tuning motor are of equal size and are equidistant from the optical axis O, the inertial force F acting on the pole pieces _IP1、F_IP2Equal, the resulting moments about the optical axis O of the objective lenses 4-122 are equal. The same analysis applies for all other elements or "sub-assemblies" of the carriage and actuator assembly, and as explained in detail below, the inertial forces generated by the horizontal and vertical accelerations above the resonant frequency of the flexure arm are balanced and symmetrical to the optical axis O. Net inertial force F of fine-tuned motor and carriage acting on assembly for producing horizontal acceleration_IFAnd F_ICAnd then acts along a straight line intersecting the optical axis through the center of the bracket as shown in fig. 59B. Net inertial force F due to coarse adjustment of the motor_ICEqual to the mass of the coarse motor times the acceleration, while the net inertial force F due to the fine motor is_IFEqual to the mass of the fine adjustment motor multiplied by the acceleration.

At high frequencies, i.e. at the lens holder-flexure arm resonance frequency, about 40Hz, the elements of the assembly 4-100 are decoupled and therefore do not influence the position of the objective lens 4-122 when accelerated in the tracking direction. Therefore, the inertial force differs for accelerations above or below the resonance frequency of the bending arm. The horizontal acceleration inertial force at high frequency is shown in fig. 60A. At these high frequencies, the actuators 4-116 and the carriages 4-106 are decoupled, so that the mass of the fine adjustment motors is equal to First inertial force F at acceleration₁₁Acting on centre of mass CM of fine-tuning motor_FA second inertial force F equal to the mass of the coarse motor multiplied by the acceleration₁₂Centre of mass CM centred on the carrier part_C。

Fig. 60B illustrates the inertial force of the horizontal acceleration below the resonant frequency of the flexure arm. At these low frequencies, the fine-tune motor portion and the carriage portion move as a unit, with a net center of mass CM_C'. As shown, the net center of mass CM_C' located at the center of mass CM of the carrier_CIs vertically above by a distance X, thereby coarsely adjusting the motor force F_Coarse1、F_Coarse2And friction force F_Friction1And F_Friction2No longer moving to CM with present_CThe' brackets are center-of-mass aligned. The symmetrical design of the assemblies 4-100 ensures that the carrier center of mass CM is displaced vertically, although the carrier center of mass CM is displaced vertically_CDoes not displace in the horizontal plane, so that the forces acting on the carrier remain symmetrical about the center of mass and the optical axis O, but are displaced from the center of mass by CM_CMove to CM_C' independently.

Furthermore, the symmetry of the design ensures that no center of mass CM occurs when the elements or subcomponents of the carrier are decoupled at high frequencies_CHorizontal displacement of (2). For example, at frequencies on the order of KHz, the fine tune motor pole pieces 4-244, 4-246 and magnets 4-250, 4-252 will decouple. However, due to the symmetry of the design, the center of mass does not shift in the horizontal plane. Because there is no mass centre CM _CThe reaction force of the focus motor does not cause pitching or yawing of the carriage above those frequencies at which the sub-assemblies become "undamped". Thus, by having the optical axis O and center of mass of the lenses 4-122 aligned horizontally, the position of the lenses "in the storm eye" is not affected by resonance of the lenses at that position, the motors and the reaction forces acting on the assemblies 4-100.

Fig. 61A and 61B are Bode transfer plots of fine tracking position versus fine motor current for the actuators 4-116 of the present invention, where the mass of the fine motor is 1.9 grams and the mass of the objective lens suspended above it is 0.24 grams. As shown in FIG. 61A, the actuator exhibits a near ideal dB curve 4-310 with a slope of approximately 40dB/de cade, and an ideal phase shift curve 4-312, as shown in FIG. 61B. The dB and phase shift curves are represented by traces 4-310 and 4-312, respectively, and fig. 61C and 61D represent curves for the same transfer function when the lens is decentered by 0.15mm in the horizontal or tracking direction. Both the dB and phase shift curves with traces of 4-410 'and 4-412', respectively, reveal a perturbation, or spur, at about 3.2 KHz. The phase margin is recessed by approximately 25 degrees, reducing loop damping and increasing settling time and overshoot. From the viewpoint of lens positioning, the horizontal shift of the lens position disturbs the balance or symmetry of the fine tracking forces acting on the lens, generating a torque around the optical axis of the lens to cause longitudinal side-to-side rocking. Thus, it can be seen that the balancing of forces about the optical axis O of the lenses 4-122 in the assembly 4-100 will significantly improve tracking positioning.

Fig. 62A-62C illustrate the effect of asymmetric focusing forces acting on the components 4-100. FIG. 62A illustrates the tracking signal when crossing tracks having a track pitch of 1.5 μm, as shown by traces 4-320, where each sine wave corresponds to one information track on the surface of the optical disc. In fig. 62B, the focusing force is concentrated on the fine tuning motor center of mass CMF and the optical axis O. The upper curve 4-322 shows the current applied to the focusing coil during this process, while the lower curve 4-324 shows the tracking error signal when tracking a particular track for a focusing acceleration of 0.75m/s '(2') at a focusing current of 0.1 Amp. As shown, the tracking error signal is practically unaffected by the focus current. FIG. 62C shows the effect on the current and tracking error signals as in FIG. 62B when the focusing force is offset about 0.2mm from the center of mass CMF and the optical axis. The corresponding curves are represented by traces 4-322 'and 4-324', respectively. The tracking signal is now significantly affected by the focus current. At the same focusing current and acceleration, a tracking offset of 0.022 μm was generated. The total allowable tracking offset in an optical drive is typically in the range of 0.05 μm to 0.1 μm. Thus, the tracking offset is significantly reduced by calibrating the focusing force as shown in fig. 62B.

FIG. 63 illustrates another embodiment of the carriage and actuator assembly 4-400 in which the center of mass of the 2-D actuator coincides with the carriage center of mass. The center of mass of the fine adjustment motor coincides with the center of mass of the carriage and is aligned with the optical axis, except for being substantially symmetrical about the optical axis of the objective lens. The carriage and actuator assembly 4-100 of the first embodiment is suitable for most of the frequency range. However, the assembly 4-400 of this alternative embodiment may be used in situations where it is desirable to avoid a shift in the center of mass of the carrier at frequencies below the resonant frequency of the flexure arms.

The assembly 4-400 comprises a carriage 4-406 having first and second bearing surfaces 4-408 and 4-410, substantially identical to those of the assembly 4-100, slidably mounted on a guide rail (not shown), and a two-dimensional actuator 4-416 mounted within the carriage 4-406. The cradle 4-406 includes a pair of coarse tracking coils 4-412, 4-414 located in notches 4-417 and 4-418 formed in the cradle 4-406 adjacent the bearing surfaces 4-408, 4-410, respectively, and which function to move the cradle 4-406 horizontally in a tracking direction, as shown in fig. 65, to access individual information tracks on the surface of the optical disc.

The actuator 4-416 comprises a lens holder 4-420 on which an objective lens 4-422 is mounted. A pair of shoulders 4-424 formed on the top surface of the carrier 4-406 support a pair of top flexure arms 4-426 that are attached to the top surfaces of a pair of projections 4-428 formed on the lens holder 4-420. A pair of bottom flexure arms 4-429, identical in construction to top flexure arms 4-426, are supported by corresponding shoulders (not shown) in the bottom of the bracket and are attached to corresponding bottom surfaces of projections 4-428 on lens holder 4-420. The light beam 4-430 enters the actuator 4-416 through the elliptical hole 4-432 and is reflected along the optical axis O' by a mirror (not shown) contained within the actuator 4-416 through the objective lens 4-422. The actuator 416 is also connected to a focus and fine tracking motor which moves the lenses 4-422 so that the emerging beam is precisely aligned and focused on the desired location on the disc surface. The focus and fine tracking motors comprise two permanent magnets 4-440, 4-442 mounted at opposite ends of the lens holder 4-420. An elliptical thin tracking coil 4-444 is mounted on each permanent magnet 4-440, 4-442, adjacent to the carriage bearing surface 4-408, 4-410. The focusing coils 4-448 are mounted on the top and bottom surfaces of the carrier 4-406 and supported by shoulders formed in the interior of the carrier so that the lens holder 4-420 is located between the focusing coils 4-448.

The coarse tracking movement of the carriage 4-406 and the actuator 4-416 takes place in the same way as for the assembly 4-100 shown in fig. 46, 47. When a current is applied to the coarse tracking coils 4-412, 4-414 in the presence of a magnetic field, a force is generated according to Lorentz's law, the action of which causes the carriage 4-406 and the actuator 4-416 to move in the tracking direction, as shown in fig. 65, thereby positioning the objective lens 4-422 below the respective information track on the optical disc.

Fig. 64 illustrates the operation of the actuator 4-416 for moving the lens holder 4-420 and the objective lens 4-422 thereon in the focusing direction. When a current is generated in the focusing coils 4-448, an electromagnetic field 4-450 is induced in each coil. The electromagnetic fields 4-450 are oriented differently for each focusing coil as shown. In the example shown, both permanent magnets 4-440, 4-442 are attracted by the bottom focusing coil 4-448 (not shown) and repelled by the top focusing coil 4-448, thus moving the lens holder 4-420 towards the bottom focusing coil 4-448 and away from the top focusing coil 4-448, thus moving the objective lens 4-422 further away from the disc surface, the magnitude of the displacement depending on the strength of the derived electromagnetic field.

In a similar manner, FIG. 65 shows permanent magnets 4-440, 4-442 interacting with thin tracking coils 4-444. Energization of the tracking coil 4-444 causes the lens holder 4-420 to move horizontally in the tracking direction to the right or to the left, depending on the direction of current through the coil. For example, in the presence of the magnetic field 4-460 as shown, the lens holder 4-420 and objective lens 4-422 move to the left. In this manner, the thin tracking coil 4-444 functions to more accurately position the optical beam exiting the lens 4-422 in the center of the desired information track on the optical disc.

In the discussion that follows, the labeled forces and lengths correspond to those discussed above in connection with assemblies 4-100. For ease of illustration, the prime notation "'" will be used to discuss the corresponding values, while reference is made to fig. 46, 49B, 50A, 51A-53A, 55A, 56A, 58A and 58B, which are used in discussing the lengths and forces associated with the assemblies 4-100.

As mentioned above, the coarse tracking motor operates in the same manner as the coarse tracking motors in assemblies 4-100. The coarse tracking coils 4-412 and 4-414 have the same size and are equidistant from the optical axis O' of the objective lens 4-422. The same current is applied to the coil, resulting in a force F corresponding to that in FIG. 46_Coarse1' and F_Coarse2', at equal respective distances L from the optical axis O_C1' and L_C2' FIG. 49B, acts on the carriers 4-406. In the vertical plane, these forces F_Coarse1' and F_Coarse2Along the radius direction and the mass center C of the fine adjustment motor_MF' (FIG. 58A) and the center of mass C of the carrier_MC' (FIG. 58B) the two coincident centers of mass are aligned to reduce pitch and yaw of the carriage and actuator. In a similar manner, the bearing surfaces 4-408 and 4-410 are equidistant from the optical axis O 'such that the carrier suspension forces are also symmetrical about the optical axis O'. See FIG. 55A for comparison, each force F _Bearing1' 1 and F_Bearing2Distance L from optical axis O_Bearing1' are equal, so that the resulting torques about the optical axis are equal, thereby further reducing the pitch and yaw of the carriage and the actuator. The surface area of each load bearing in contact with the rail is designed to be substantially equal so that the friction forces acting on the carriages 4-406 are substantially equal. Because the bearing surfaces 4-408 and 4-410 are equidistant from the optical axis O', the torque about the optical axis is equal and longitudinal side-to-side rocking of the bracket and actuator is minimized. The assembly is also designed so that the friction forces are aligned in a vertical plane with the centre of mass of the carrier 4-406 and the actuator.

The fine tracking coils 4-444 are equal in size and the applied currents are also equal, so that the fine tracking forces acting on the actuators are equal. Furthermore, the thin tracking coils 4-444 are at an equal distance LT 'from the optical axis O', see fig. 50A, so that the torque around the optical axis is equal. In the vertical plane, these forces F_Track1' and F_Track2' AND actuator 4-416 and carriage 4-406 to reduce pitch and yaw of the actuators 4-416. Responsive to a tracking force F, since the fine tracking forces acting on the assembly are equal_Track1' and F_Track2The reaction force F generated thereby_React1And F_React2See fig. 51A, also equivalent. These reaction forces are equidistant from the optical axis at a distance LR' and are aligned with the center of gravity in a vertical plane, equalizing the torque about the optical axis and thereby reducing longitudinal side-to-side rocking.

Similarly to the above, the focusing coils 4-448 are of substantially equal size and the currents applied thereto are equal, so that the resulting force F acting on the actuator is equal_Focus1' and F_Focus2' equal. However, in the present embodiment, the focusing coils 4 to 448 are equally spaced from the center of gravity where the fine adjustment motor and the carriage coincide with each other, so that the torques about the optical axis O' are equal. Furthermore, see FIG. 52A, because of the focusing force F_Focus1' and F_Focus2' equality, focusing reaction force F acting on the fine adjustment motor as a whole_FR1、F_FR2(see FIG. 53A) equal and spaced from the center of gravity C of the motor as a whole_MF' and center of gravity C of the bracket as a whole_MC'are equal, and therefore the torque about the optical axis O' generated by the reaction force is equal, so that the pitch and yaw of the actuator is further reduced.

Bending force F acting on actuator and fine adjustment motor_Flex1′、F_Flex2' and a reaction force F generated in response to the bending force_RA′、F_RB' is in fact the same as that shown for assemblies 4-100 in figure 54. Because the bending and reaction forces are not symmetrical about the optical axis O ', the torques about the optical axis O' produced by these force pairs are not equal. However, except at low frequencies (typically below about 40Hz), these forces are effectively decoupled from the carriers 4-406, and therefore, under most operating conditions, these torques affect the performance of the actuator.

Thus, the electrodynamic and reactive forces acting on the assembly 4-400 are symmetrical about the optical axis O' and are in a vertical plane and fine-tune the center of gravity C of the motor as a whole_MF' and weight of the carrier as a whole C_MC' alignment. Due to the fact thatTo fine tune the center of gravity of the motor ensemble and the carriage ensemble to coincide, the decoupling of the actuator 4-416 or any sub-components of the assembly 4-400 does not shift the center of mass from the forces and torques acting on the assembly 4-400, which are actually always balanced for all horizontal and vertical accelerations.

Anamorphic achromatic prism system

Fig. 66 shows a prior art optical system having a light source 5-102 providing an incident light beam 5-106, indicated by dashed lines, a simple anamorphic prism 5-108, a focusing lens 5-110, and an optical medium 4-112. The light beams 5-106 enter the prism at incident angles 5-114 with respect to the normal of the prism's entry face. Laser light sources typically produce an elliptical beam with some astigmatism, as is well known in the art. The anamorphic prisms 5-108 provide expansion along the minor axis of the ellipse, thereby correcting the ellipticity of the beam. The angles of incidence 4-114 are selected to provide the desired spread along the minor axis. Anamorphic prisms 5-108 also correct for astigmatism in the incident beams 4-106. The resulting correction beam 5-118 is focused by the lens 5-110 to form a spot 5-120 on the optical medium 5-112.

As long as the wavelength of the incident light beam 5-106 remains constant, a simple prism 5-108 is sufficient. In practice, however, as is well known in the art, the light source wavelength is generally varied due to temperature variations, power variations, random "state jumps", and other conditions. In magneto-optical disk systems, the laser power is constantly being switched between values for write operations and for read operations.

The angle of refraction of light at the material interface is calculated using Snell's law as is well known in the art:

n₁ Sinθ₁＝n₂ Sinθ₂

wherein:

n₁the refractive index of material 1;

θ₁angle of incidence with respect to normal;

n₂the refractive index of material 2; and

θ₂angle of refraction relative to normal.

This relationship controls the refraction of the light beam 5-106 as it enters the prism 5-108. As shown in FIG. 66, when a light beam of one wavelength enters anamorphic prisms 5-108, the light beam is refracted at a given angle determined by the refractive index of prisms 5-108 and the angle of incidence 5-114 of light beam 5-106. The light beam 5-118 resulting from the incoming light beam 5-106, corrected for ellipticity and, if possible, for astigmatism, enters the focusing lens 5-110 and produces a focused light spot 5-120 on the optical medium 5-112. However, the refractive index changes with wavelength. This is called dispersion. Thus, when the wavelength of the incident light beams 5-106 is changed, the refraction angle produced at the interface between the air and the prisms 5-108 is different from the refraction angle of the original wavelength. Fig. 66 shows the effect of the wavelength variation of the incident beams 5-106 in dash-dot lines. The incoming light beams 5-106 are refracted at different angles to produce light beams 5-122 which enter the focusing lenses 5-110 at different angles to form focused light spots 5-124 on the optical medium. As shown in fig. 66, spots 5-124 are separated from spots 5-120. This shift caused by a change in the wavelength of the incident beam is referred to herein as lateral beam drift.

Lateral beam drift can be avoided by not using anamorphic prisms 5-108. For example, the system may use a circular lens to provide a circular spot on the optical medium. However, a lens is used to form the circular spot. The lens then focuses only one circular aperture within the elliptical beam. This does not make efficient use of the power of the laser because the portion of the beam outside the aperture is discarded. Thus, a beam shaping system that does not use an anamorphic prism would not benefit from both ellipticity correction and astigmatism correction of the incident beam. The beam shaping capability of the anamorphic prism allows for the full use of laser power by expanding the elliptical beam into a circular beam, which is advantageous, especially in optical disc systems when increased power is required for writing operations.

Fig. 67 is a conventional configuration of a multi-element prism system 5-130, as is well known in the art. The system shown consists of three prism members 5-132, 5-134, 5-136, focusing lenses 5-138 and a reflective optical medium 5-140. The prism system 5-130 can be designed achromatic by suitably selecting the geometrical dimensions, refractive index and dispersion of the individual prism elements 5-132, 5-134, 5-136.

The prism system 5-130 shown in fig. 67 can also reflect the light beam reflected from the optical medium 5-140 to the detection system 5-144 by providing a beam splitting film 5-146 between the prisms 5-134 and 5-136.

As shown in fig. 67, the incoming light beam 5-148 passes through prisms 5-132, 5-134 and 5-136 and is then focused with lenses 5-138 to form a spot 5-137 on the optical medium 5-140. The light beam 5-148 is returned from the optical medium 5-140 into the prism 5-136 through the focusing lens 5-138 and reflected from the film 5-146 as light beam 5-150. The light beam 5-150 then enters the detection system 5-144.

If designed achromatic, a change in wavelength in the input light beam 5-148 should not cause a lateral drift of the focused spot 5-137 on the optical medium 5-140.

As mentioned before, it is advantageous that the optical system has more than one detector. Prism systems having an air gap in the optical path have significant advantages, particularly the ability to provide a compact, achromatic prism system capable of reflecting portions of the incident and reflected beams back into multiple detectors. Furthermore, a symmetrical correction prism can be added to existing anamorphic prism systems by using an air gap. Finally, an integral prism system with an air gap can provide a stable, compact, easily manufactured and easily installed prism assembly, which is advantageous.

To more fully explain the design of an achromatic prism system with an air gap between the prisms, reference is made to FIG. 68, which shows a two-element prism system 5-152 with the addition of a color correcting prism 5-154 to an anamorphic prism 5-156. The correcting prism has n ₁Has a refractive index and a simple anamorphic prism having n₂Is used as a refractive index of (1). As shown in FIG. 68, the angle in the system is *, α₁，α₂，α₃，α₄，α₅，α₆，α₇，β₁，β₂And beta_airAnd (4) showing. The deviation angle of the light beam from the incident beam is called α, where

α＝β₁+β_air-(α₇+*+β₂) And alpha₇The calculation can be done by repeatedly applying Snell's law and the geometry of the triangle.

Some design conditions are chosen to achieve the desired result (e.g., by the overall shift angle of the system). For example, to design an achromatic system, the condition is that α is constant over a certain wavelength range.

For a total desired offset angle α, a, from the incoming beam to the outgoing beam, the following conditions are satisfied:

A＝β₁+β_air-(α₇+*+β₂)

furthermore, in order to make the correction prisms 5-154 symmetrical prisms without net expansion of the incident beam, it can be added to simple anamorphic prisms 5-156 as shown in FIG. 68, provided that:

*＝Sin^-1[n₁ ^*Sin(β_1/2)]

by choosing this condition, the correction prism does not expand the incident beam. Thus, the corrective prism may be added to an existing anamorphic prism system selected to provide the appropriate expansion.

Finally, the prism assemblies 5-152 are suitably selected from the group consisting of₁，β₂，β_airAnd the dispersion of the glass can meet all the required design requirements.

In some cases, it may be desirable for the outgoing beam to have a significant offset angle relative to the incoming beam. An offset angle of, for example, 90 degrees may be advantageous. This may be achieved by providing total internal reflection in the prisms 5-156 before the beam exits the prism. This changes the above calculations, but still achieves the design goals by appropriately selecting the parameters.

Applying the above-described principle of adding a symmetrical correction prism to an existing anamorphic prism, a prism system is designed having a plurality of surfaces for reflecting the retro-reflected beams partially back to different detectors. The following describes embodiments that have a large offset angle between the incoming light and the outgoing light, have multiple reflections from different detection systems, and are an integral, airgap, achromatic prism system.

FIG. 69 shows an air-gap, anamorphic, achromatic prism system 5-170 according to the present invention. The prism system 5-170 shown in fig. 69 preferably has three prisms integrated. This has the advantage of allowing the prism assemblies 5-170 to be mounted as a single piece, as previously described. Because the prisms are joined together, they do not need to be mounted separately. This reduces installation time, increases system stability, reduces installation costs, and minimizes performance differences among different optical systems. The three prism elements are a flat plate prism 5-172, a trapezoidal prism 5-174, and a correction prism 5-176. FIG. 69 also shows the beam paths of beams 5-178, from sources 5-102, air gap beams 5-180, exit/reflected beams 5-182, first detector channel beams 5-184 to first detectors 5-185, second detection channel beams 5-186 to second detectors 5-187, and third detection beams 5-188 to third detectors 5-189. By providing an air gap between the correcting prism 5-176 and the plate prism 5-172, allowing the air gap beam 5-180 to pass through, the correcting prism 5-176 can be designed as a symmetric corrector without a net expansion of the incident beam 5-178. Thus, the correcting prism 5-176 may be attached to the combination of the flat plate prism 5-172 and the trapezoidal prism 5-174 to achromatize the prism system 5-170.

Fig. 69 also shows lenses 5-190 positioned to focus the outgoing light beams 5-182 on the optical media. Details of the design shown in FIG. 69, which were designed for substantially achromatic color at the design wavelength of 785 + -22 nm, will be discussed. At this wavelength, the system will have the following characteristics.

The plate prisms 5-172 are illustrated in detail in fig. 70, 70A and 70B. FIG. 70 is a side view of the flat plate prisms 5-172, with FIG. 70A being a top view illustrating the surfaces S15-200 and FIG. 70B being a top view illustrating the surfaces S25-202. The plate prism has light surfaces S15-200, light surfaces S25-202, light surfaces S35-204, surfaces S45-206, and surfaces S55-208. In one embodiment, the surfaces S15-200 and S25-202 are substantially parallel and separated by a distance, which is designated 5-210 in FIG. 70. In the examples herein, an advantageous number of distances 5-210 is 6.27 mm. Surfaces S55-208 and S35-204 are also substantially parallel in this embodiment. Surfaces S15-200 and S35-204 intersect and terminate at edges 5-211 (i.e., edges of S1/S3) at angles 5-212 (i.e., S1/S3 angles), which in this embodiment is advantageously 50 degrees 21 '+/-10'. Surfaces S35-204 and S25-202 intersect and terminate at edges 5-214; surfaces S25-202 intersect with surface S45206 and terminate at edges 5-216, surfaces S45-206 intersect with surfaces S55-208 and terminate at edges 5-218, and surfaces S55-208 intersect with S15-200 and terminate at edges 5-220, as shown in FIG. 70. In FIG. 70, surfaces S25-202. Has a length of 5-222 and a width of 5-224 in fig. 70A. In this embodiment, the length 5-222 is 13.34mm and the width 5-224 is 8.0 mm. In this embodiment, a useful dimension of the total length 5-225 of the prism is 23.61mm, and the distance 5-227 parallel to surface S1 from edge 5-218 to edge 5-220 is preferably 2.14mm, measured along a reference plane 5-226 defined perpendicular to surfaces S15-200 and surfaces S25-202. FIG. 70A is a plan view illustrating clear (clear) apertures 5-230 and 5-232 defined on surfaces S15-200. The clean aperture is simply an area on the prism surface that is required to meet the selected quality. In this example, the clear pore size is 8.5mm by 6.5mm ova. Preferably, the center of the aperture 5-230 is located such that its short axis is located a distance 5-233 from the edge 5-211 and its long axis is centered on the surface S15-200, as shown in FIG. 70A. In this embodiment, the centers of the clear apertures 5-232 have their short axes located a distance 5-234 from the edges 5-220 and their long axes located at the center of the surface S15-200. in this embodiment, the distance 5-233 is preferably 6.15mm and the distance 5-234 is preferably 5.30 mm.

The top view shown in FIG. 70B illustrates the clear aperture 5-235 defined on the surface S25-202. In this example, a clear aperture of 8.5mm by 6.5mm is defined as a circular oval whose center is such that the minor axis is 5-236 from the edge 5-214 and the major axis is centered on the surface S25-202, as shown in FIG. 70B. In this embodiment, the distance 5-236 is 5.2 mm. The surface portions defined by the clear aperture diameters 5-230, 5-232, and 5-235 preferably have a surface quality of at least 40/20, as is well known in the art. In the illustrated embodiment, BK7A grade high quality annealed glass is an optical material suitable for use in prisms 5-172, as is well known in the art.

FIG. 71 shows a detail of the trapezoidal prism 5-174 of the embodiment shown in FIG. 69. The trapezoidal prisms 5 to 174 have optical surfaces S65 to 240, optical surfaces S75 to 242, optical surfaces S85 to 244, and optical surfaces S95 to 246. Surfaces S65-240 and S75-242 terminate and intersect at edges 5-248. Surfaces S75-242 and S85-244 intersect and terminate at edges 5-250 at an intersection angle of 5-251. The angle 5-251 is preferably substantially 135 degrees. Surfaces S85-244 intersect with surfaces S95-246 and terminate at edges 5-252, preferably at an intersection angle 5-254 of 50 degrees 21' in this embodiment. Surfaces S95-246 intersect with surfaces S65-240 and terminate at edges 5-256. Surfaces S65-240 have lengths 5-258 as shown in FIG. 71. In this embodiment, the length of 5-258 is preferably 9.5 mm. Surfaces S65-240 and S85-244 are substantially parallel and are separated by a distance of 5-260, FIG. 71. In this embodiment, the distance 5-260 is 8.0mm, measured from a direction perpendicular to the surfaces S65-240 and S85-244. Edges 5-250 and 5-248 are separated by a distance of 5-261 along a plane 5-262 defined parallel to surfaces S85-244. In this embodiment, the distance of 5 to 261 is preferably 8.0 mm. FIG. 70A is a top plan view of the trapezoidal prisms 5-174 illustrating that the surfaces S65-240 and S95-246 are as shown in FIG. 71A. in this embodiment, the trapezoidal prisms 5-174 have a thickness of 5-263, which is preferably 8 mm. As shown in FIG. 71A, S65-240 has clear apertures 5-264, which in this embodiment are defined as a circular aperture with a diameter of at least 6.5mm, centered across the width of the surface, with the center of the circle being 5-265 a distance from the edge 5-248. In this embodiment, the distance of 5-265 is preferably 4.0 mm. Surfaces S95-246 have clear apertures 5-266 in their centers. In this example, the clear pore size of 5-266 is defined as the smallest rounded egg of 6.5mm by 8.5 mm.

FIG. 71B is a bottom plan view of trapezoidal prisms 5-174 illustrating surfaces S75-242 and S85-244 with clear apertures 5-268 and 5-270, respectively. As shown in FIG. 71B, the trapezoidal prism has a length of 5-272, measured along reference plane 5-262 from edge 5-252 to edge 5-248. The length of 5-272 in this embodiment is preferably 16.13 mm. In one embodiment, the clear pore size of surfaces S75-242 is 6.5mm by 9.2mm ova. The clear aperture is centered on the plane S75-242, and the minor axis is parallel to and centered between edges 5-248, 5-250. The cleaning aperture 5-270 is preferably a 6.5mm by 6.7mm circular oval centered on the surface S85-244 with its major axis centered between edges 5-250, 5-252 and parallel to edges 5-250, 5-252. In this embodiment, the surface quality of the clear apertures 5-264, 5-266, 5-268, and 5-270 is preferably 40/20, as is well known in the art.

Many of these prisms have a surface coating to facilitate the function of the prism. In this embodiment, the surfaces S65-240 have an anti-reflective coating with a transmission of 99.8% or greater at 90 ° ± 0.5 degree incidence angle. The coatings on surfaces S85-244 have a transmission of 98.5% or greater for internally incident light at an angle of incidence of 10.7 ° ± 0.5. Surfaces S95-246 have a coating of a low absorption film with a reflectivity > 90% for the polarization state (Rs) (i.e., normal to the plane of incidence) and 12.5% + -2.5% for the P polarization state (Rp) at an angle of incidence of 39' + -0.5 deg.. The material used for the trapezoidal prisms in fig. 69 and 71-71B is a BK7A grade high quality annealed optical glass, which is well known in the art.

Details of the color correction prisms 5-176 of the embodiment of the prism system 5-170 shown in fig. 69 are shown in fig. 72 and 72A. As shown, the color correction prisms 5-176 have optical surfaces S105-290, S115-292 and S125-294, forming triangular prisms. The surfaces S115-292 and S125-294 intersect and terminate at edges 5-296. Surfaces S105-290 and surfaces S125-294 intersect and terminate at edges 5-298. Preferably, surfaces S105-290 and S115-292 are symmetrical. The length of S125-294 is 5-300, in this case 7.78 mm. Thus, edges 5-296 are separated from edges 5-298 by a distance of 5-300. The angles at which S105-290 and S115-292 meet each other are referred to as 5-302. In embodiments 5-302 are preferably 38 deg. 20'. The surfaces S115-292 and S105-290 terminate at a distance 5-303 from S125-294, measured in a direction perpendicular to the surfaces S125-294. The distance 5-303 is 10.5mm in this embodiment.

FIG. 72A is a diagram of surfaces S105-290. In this embodiment, the prisms 5-176 have a thickness of 5-304, preferably a thickness of 5-304 of 8.0mm, and it is desirable that the surfaces S105-290 have oval clear apertures 5-306. In this embodiment, the clear aperture 5-306 is a round egg centered such that its long axis is parallel to and spaced from the intersection line 5-298 by a distance of 5-308. With its minor axis at the center of surface S105-290 as shown. In this embodiment, the clear aperture 5-306 is preferably defined as a 6.5mm by 2.8mm oval, and the surface quality of the entire clear aperture 5-306 is preferably 40/20, as is known in the art. In this embodiment, the surfaces S115-292 also have similar clear pore sizes defined on their surfaces.

Like the trapezoidal prisms 5-174, the color correction prisms 5-176 have plating on some of their surfaces to improve performance. In one embodiment, each of the surfaces S105-290, S115-292 has an anti-reflective coating (e.g., reflectance ≦ 3% at an incident angle of 35.5 ° ± 1.0 °, as is well known to those skilled in the art). In the present embodiment, the material of the correcting prisms 5 to 176 is SF11 class A high quality annealed glass.

After the above described prisms are assembled into the integral prism system of the present embodiment shown in FIG. 69, the reflection of a light beam having a wavelength of 785 + -22 nm is illustrated as follows, and for ease of discussion, a reference plane 5-237 is defined along one side of the prism system 5-170, as shown in FIG. 69A. The incident beam 5-178 from source 5-102 enters surface S105-290 at an angle of incidence of 5-326 and is parallel to reference plane 5-237. The light beam 5-178 exits the prism 5-176 as light beam 5-180 into the air gap and then enters the prism 5-172 through surface S25-202. A portion of the light beam reflects off the film at S95-246 and exits surface S35-204 as light beam 5-188. In one embodiment, the light beam 5-188 may be directed to a detection system 5-189. Because this reflected beam is part of the incident beam, the detection system 5-189 receiving the beam 5-188 can monitor the intensity of the incident beam. The remaining light beams that are not reflected on the films of surfaces S95-246 enter trapezoidal prisms 5-174, are internally reflected at surfaces S75-242 and exit as light beams 5-182 through surfaces S65-240.

In the illustrated embodiment, if the angle of incidence 5-236 of the light beam 5-178 is 35 ° 26 ', the light beam exits the prism 5-174 with a total shift of 87 ° 37 ' ± 5 ' from the incoming light beam 5-178 to the outgoing light beam 5-182, the outgoing light beam being parallel to the reference plane 5-237 with a deviation of ± 5 ', and the light beam 5-182 exiting the surface S65-240 with a deviation of ± 5 '.

The lens 5-190 focuses the light beam 5-182 on the optical medium 5-191. The light beam is reflected back through the lens and enters perpendicular to S65-240, internally reflects on surfaces S75-242, and then reflects on the film between the trapezoidal prism 5-174 and the flat prism 5-172. The resulting beam exits the trapezoidal prism 5-174 through the surface S85-244 as beam 5-184 with an offset angle of 5-238. The light beam 5-184 enters a first detector 5-185.

A portion of the light beam returning from the optical medium 5-191 also passes through the film and is reflected at the surface S25-202 to exit the plate prism 5-172 as the light beam 5-186. Such reflection is available because of the air gap in the prism system. In one embodiment, both beams 5-184 and 5-186 may be directed to separate detection systems 5-185 and 5-187, respectively. For example, detection system 5-185 may collect data signals and detection system 5-187 may collect detection signals (e.g., focus and tracking servo information).

As described above, the embodiments are substantially achromatic over the range of wavelength variation of conventional laser light sources. Thus, the lateral position of the focused light beam on the optical medium 5-191 is not significantly affected by a wavelength variation of the incident light.

The simulated calculations for the performance of the different wavelength prism systems 5-170 from 780nm to 785nm are shown in the table below. Phi is the angle of incidence on the correcting prism (35 deg. 26' in this example) with a deviation estimated to be + -0.5 deg.. The wavelength shift is shown in one column and the corresponding shift in the focused spot from the prism system is shown in each column for an angle of incidence in the range Phi 0.5 deg.. For example, as shown in the first row of the table, for a wavelength shift of the incident beam from 780nm to 781.5nm, the focused spot shift is-0.2 nm at the incident angle Phi, 2.6nm for an incident angle Phi-0.5 deg., and 2.5 nm for Phi +0.5 deg.

The wavelength shift Phi-0.5 DEG Phi +/-0.5 DEG

780-781.5nm 2.6nm -0.2nm -2.9nm

780-783nm 5.2nm -0.2nm -5.6nm

780-785nm 9.0nm -0.1nm -9.0nm

As shown in the table above, for wavelength shifts from 780 to 783nm, the lateral shift is less than 1nm at the angle of incidence Phi. Whereas in an embodiment similar to that described above, but without color correction, the lateral shift is about 200nm for a wavelength shift of 3 nm. Indicating that this is essentially an achromatic system.

FIG. 73 illustrates prism systems 5-339 as another embodiment of the present invention. This embodiment has correction prisms 5-340, flat plate prisms 5-342, and quadrangular prisms 5-344. The correcting prisms 5-340 and the plate prisms 5-342 are substantially the same as the correcting prisms 5-176 and the plate prisms 5-172, respectively, of the prism systems 5-170 shown in fig. 69. However, the quadrangular prisms 5 to 344 and the trapezoidal prisms 5 to 174 are different.

Details of the quadrilateral prisms 5-344 of FIG. 73 are shown in FIGS. 74, 74A and 74B. Quadrangular prisms 5 to 344 have surfaces S135 to 346, surfaces S145 to 348, surfaces S155 to 350, and surfaces S165 to 352. Surfaces S135-346, S145-348, S155-350 and S165-352 are similar in shape but differ from surfaces S65-240, S75-242, S85-244 and S95-246 of trapezoidal prisms 5-174. Surfaces S135-346 and S145-348 intersect at edges 5-353 at an angle of 5-354; surfaces S145-348 and S155-350 intersect at edge 5-355 at an angle of 5-356; surfaces S155-350 and S165-352 intersect at edges 5-357, at angles 5-358, as shown in FIG. 74. Finally, surfaces S165-352 and S135-346 intersect at edges 5-359. In one embodiment, the angle 5-354 is 49 ° 40 ', 5-356 is 135 °, 5-358 is 50 ° 21'. The distance between edges 5-353, 5-355, referred to in FIG. 74 as 5-360, is measured perpendicular to surfaces S155-350. In one embodiment, the distance 5-360 is 8.0 mm. In addition, the distance between edges 5-353, 5-359 is labeled 5-362, and in one embodiment, distance 5-362 is 8.9mm, measured parallel to S155-350. Finally, the distance between edges 5-353, 5-355 is labeled 5-364, measured along a plane parallel to S155-350. In one embodiment, the distance 5-364 is preferably 8.0 mm.

FIG. 74A is a plan view of surfaces S135-346, which also shows surfaces S165-352. FIG. 74A shows the thickness of prisms 5-344, numbered 5-368. In one embodiment, the thickness is 5-368 is 8.0 mm. Prisms 5-344 preferably have clear apertures 5-370 defined along surfaces S135-346 and clear apertures 5-372 defined along surfaces S165-352, as shown in FIG. 74A. In this embodiment, the clear aperture 5-370 is a circular aperture located in the center of the surface with the center of the circle being 5-374 mm from the edge, and in one embodiment, the clear aperture 5-370 is a circular aperture with a minimum diameter of 6.5mm and a distance of 5-374 of 4.0 mm. The surfaces S165-352 preferably also have clear pore sizes 5-372, centered on the surface. In one embodiment, the clear aperture 5-372 is a 6.5mm by 8.5mm oval aperture centered on the surface S165-352, as shown in FIG. 74A.

FIG. 74B is a plan view of surfaces S145-348, which also shows surfaces S155-350. The prism 5-344, having a full length from edge 5-353 to edge 5-357, is labeled 5-380 and is measured along a plane parallel to S155-350. In one embodiment, the length is 5-380 mm 16.13 mm. As shown in FIG. 74B, surfaces S145-348 have clear aperture 5-382 at the center of the surface, and surfaces S155-350 also have clear aperture 5-384 at the center of the surface. In one embodiment, the clear pore size of 5-382 is 6.5mm by 9.2mm, and the clear pore size of 5-384 is 6.5mm by 6.7 mm.

The quadrangular prisms 5-344 are also preferably coated on some of their surfaces. In one embodiment, surfaces S135-346 have a coating with a reflectivity ≦ 0.2% for internally incident light at an angle of incidence of 4 ° 40 ± 5' with respect to normal. In the same embodiment, surfaces S155-350 have a coating with a reflectivity ≦ 0.5% for incident internal light at an angle of incidence of 10.7 ° ± 0.5 ° with respect to normal. Finally, the surfaces S165-352 preferably have a thin film coating with Rs > 90% and Rp 12.5% at an angle of incidence of 39' ± 0.5 ° to the normal. This thin film coating also preferably has a phase shift of less than 8 deg. for all operating optical conditions.

With the configuration of fig. 74, the total deflection angle from the incoming beam to the outgoing beam is preferably 90 °. This facilitates manufacture, since a 90 ° deflection angle mounting element is easier to manufacture than the 87 ° deflection angle mounting element as in the embodiment of fig. 69. The prisms are not completely achromatic for the plating and dimensions determined for the embodiment of fig. 73. However, the prism system shown in FIG. 73 is substantially achromatic within an acceptable range around the design wavelength.

Simulated calculations of the performance of the prism systems 5-339 of FIG. 73 are shown in the following table, with the wavelength being varied from 780nm to 785 nm. In this embodiment, Phi is also 35 ° 26'.

Wavelength shift Phi-0.5 deg. Phi +0.5 deg

780-781.5nm 12.5nm 9.8nm 7.1nm

780-783nm 25.1nm 19.6nm 14.3nm

780-785nm 42.0nm 32.9nm 24.0nm

As can be seen from the above table, the design of fig. 73 is not as good as the achromatization of the design of fig. 69. However, for a shift of wavelength 780 to 783nm, the lateral displacement of the focused spot is only 19.6 nm. Whereas an embodiment similar to the above but without achromatic correction has a lateral shift of about 200nm for a wavelength shift of 3 nm.

Data retrieval-conversion detection

A detailed system for retrieving and storing data from magneto-optical devices is provided in the related application No. 07/964,518, filed 1993 at 25/1, which is hereby incorporated by reference as if fully set forth herein.

Figure 75 is a block diagram of an exemplary magneto-optical system that can have both a read mode and a write mode. During the write mode, the data source 6-10 supplies data to the encoder 6-12. The encoders 6-12 convert the data into binary code bits. The binary code bits are transmitted to the laser pulse generator 6-14 where the code bits can be converted into excitation pulses for switching the laser 6-16 on and off. In one embodiment, for example, a code bit of "1" indicates that the laser will emit a train of pulses at fixed intervals regardless of the code bit pattern. And a code bit of "0" indicates that the laser is not pulsed during this interval. Performance may be enhanced by adjusting the relative number of occurrences of laser pulses or by extending the otherwise uniform pulse duration, depending on the particular laser and type of optical media used, in response to which pulses are emitted, the lasers 6-16 heat localized regions of the optical media 6-18, thereby exposing localized regions of the optical media 6-18 to magnetic flux and thereby fixing the polarity of the magnetic material on the optical media 6-18. These localized regions, commonly referred to as "pits," store encoded data in magnetic form until erased.

During the reading mode, a laser beam or other light source is reflected from the surface of the optical media 6-18. The reflected laser beam is polarized according to the polarity of the magnetic surface of the optical medium 6-18. The reflected laser beam is sent to an optical reader 6-20 which sends an input signal or read signal to a waveform processor 6-22 for processing the input signal and recovering the encoded data. The output of the waveform processor 6-22 may be provided to a decoder 6-24. The decoder 6-24 converts the encoded data back to its original form and sends the decoded data to a data output port 6-26 for transmission or other processing as required.

FIG. 76 shows in more detail the process of data storage and retrieval processing using the GCR 8/9 code format. For the GCR 8/9 code, one cell (ce-ll)6-28 is specified as one channel bit, as shown in FIG. 76A. Each clock cycle 6-42 corresponds to a channel bit; thus, each of the units 6-30 to 6-41 corresponds to one clock cycle 6-42 of the clock waveform 6-45. As an example of a clock speed, for a 3.5 "optical disc with a storage capacity of 256M rotating at 2400 rpm, the clock period is typically 63ns or the frequency is 15.879 MHz. The GCR input waveforms 6-47 are the encoded data outputs from the encoders 6-12 of FIG. 75. The GCR input waveforms 6-47 correspond to a representative channel sequence "010001110101". Laser pulse generators 6-14 use the GCR data waveforms 6-47 to derive pulsed GCR waveforms 6-65 (which have not been adjusted in time or duration to reflect performance enhancement for a particular data pattern in fig. 76). Generally speaking, GCR pulses 6-67 through 6-78 occur during the clock period when the GCR data waveform 6-47 is high. Pulsed GCR waveforms 6-65 are fed to lasers 6-16. The previous magnetic properties of the optical medium have been erased and the magnetization polarity of the medium is reversed when an external magnetic field of opposite polarity to the erased medium is present and when the laser emits sufficient energy to exceed the curie temperature of the medium, the laser pulses generated by GCR pulses 6-68, 6-69, 6-70, etc. form a pattern of pits 6-80 on optical medium 6-18. Thus, pits 6-82 to 6-88 correspond to pulses 6-68, 6-69, 6-70, 6-71, 6-73, 6-76, and 6-77, respectively. Successive pits 6-82 to 6-85 may merge together to actually form one long pit. The long pit has a leading edge corresponding to the leading edge of the first pit 6-82 and a trailing edge corresponding to the trailing edge of the last pit 6-85.

Reading the pits with an optical device, e.g. a laser, results in a playback signal 6-90. The playback signal 6-90 is low where no pit is present. At the leading edge of a pit 6-86 the playback signal 6-90 rises and stays high until the trailing edge of the pit 6-86, after which it falls until the next pit 6-87 stays low.

The above process may be referred to as Pulse Width Modulation (PWM) because the pulse widths in the playback signals 6-90 represent the distance between the 1-bits. Thus the edges of the pits 6-80 defining the pulse length in the playback signal contain the appropriate data information. If the playback signal 6-90 is differentiated, the signal peaks of the first derivative signal correspond to the edges of the pits 6-80. The signal spikes of the first derivative of the playback signal may be slightly offset from the edges of the pits 6-80, since the playback signal 6-90 is represented as an ideal playback signal. These signal spikes need to be detected in order to recover the pit edge information from the first derivative. This process is described in detail herein below.

In contrast, most existing RLL2, 7 coding systems are used in conjunction with Pulse Position Modulation (PPM). In the PPM system, each pit represents "1", and when there is no pit, it is "0". The distance between pits represents the distance between respective 1 bits. The center of each pit corresponds to the position of data. To find the center of the pit, the playback signal is differentiated and the first derivative is subjected to zero crossing detection. This technique can be quite different from the PWM system described above, where the signal spikes of the first derivative contain the appropriate pulse width information.

However, it is possible to use a PWM system with an RLL system, such as the RLL2, 7 coding system, instead of the PPM system. Each channel bit may correspond to one clock cycle of the clock waveform. As with the GCR system described above using PWM, a "1" can be represented by a change in the input waveform. Thus, the PLL2, 7 input waveform can remain in the same state when a "0" occurs. And when a "1" occurs, a change from high to low or low to high occurs.

In the RLL and GCR codes, as in the other codes, the input signals generated by the optical readers 6-20 are often asymmetric when reading the data pattern. When an asymmetric signal is AC coupled between the circuits, the averaged DC value will be off the peak-to-peak midpoint. Such unintended deviations from the midpoint may cause shifts in the apparent location of the data, adversely affect the accuracy with which the location of the data is determined, and reduce timing margins or render the recorded data unrecoverable.

This phenomenon can be explained with reference to fig. 77A and 77B, which represent an ideal input signal S derived from a symmetrical data pattern₁. Normally, the change between 1 and 0 in the data is detected at the midpoint between the high and low peaks of the input signal. As can be seen from FIG. 77A, at the input signal S ₁Peak to peak midpoint M_p1Upper and lower area A of₁And A₂Are equal. The change between 1 and 0 corresponds exactly (in an ideal system) to the input signal S₁And the midpoint M of the peak-to-peak_P1The intersection point of (a).

In contrast, fig. 77B shows an input signal S2 resulting from an asymmetric data pattern. It can be seen that the peak-to-peak midpoint M_p2Area A above_1′Area A greater than or equal to_2′. Thus, the input signal S₂Having a direct current component such that the DC reference line DC_BASEShifted to the mid-point M of the peak-to-peak_p2The above. When the input signal S is AC-coupled by determining₂May occur because the dc level is not equal to the peak-to-peak midpoint M_p2And (5) the consistency is achieved. The DC level does not remain constant but rises or falls according to the nature of the input signal. The larger the DC component is established, the larger the deviation of the detected transformation point from the true transformation point. As such, the DC component may cause the timing margin to decrease or the data to be unrecoverable.

FIG. 78 is a block diagram of read channels 6-200 for one embodiment for mitigating the effects of DC components in accordance with the present invention. The read channels 6-200 correspond generally to the waveform processors 6-22 of FIG. 75. It comprises a preamplifier stage 6-202, a differentiator stage 6-204, an equalizer stage 6-206, a partial integrator stage 6-208 and a data generator stage 6-210. Referring to the more detailed block diagram of FIG. 79, the waveform diagrams of FIGS. 84A-84D do not necessarily describe the operation of the read channels 6-200 with reference to other figures.

When the optical medium 6-18 is scanned for reading out data, the pre-amplifier stage 6-202 amplifies the input signal to a suitable level. The preamplifier stage 6-202 may comprise a preamplifier 6-203 as is well known in the art. As an alternative the preamplifier 6-203 may also be placed elsewhere, for example in the optical reader 6-20. FIG. 84A shows an exemplary amplified playback signal 6-220.

The output of the preamplifier stage 6-202 shown in fig. 79A is sent to the differentiator stage 6-204. The differentiating stage 6-204 may comprise a differential amplifier 6-212, for example a video differential amplifier constituted by capacitors 6-213 in a manner well known in the art. Fig. 80A shows a representative frequency response curve for differentiation stages 6-204. The differentiation stage 6-204 effectively increases the relative amplitude of the high frequency components of the amplified play signal 6-202. The output waveforms of the differentiation stages 6-204 are shown in fig. 84B.

The differentiation stage 6-204 is followed by an equalization stage 6-206, as shown in fig. 79A. The equalization stages 6-206 provide additional filtering to modify the overall channel transfer function and provide more reliable data detection. The equalization stages 6-206 shape the differentiated input signal so that equalizing the amplitudes of the high and low frequency components produces a smoother signal for subsequent processing. Equalization filters typically modify both the signal harmonics and the signal spectrum. Thus, an improvement in the differentiated input signal waveform (i.e., reduction in distortion) is generally accompanied by a reduction in the signal-to-noise ratio. Thus, the design of the equalization stages 6-206 involves a compromise between trying to minimize noise and providing a distortion-free signal at an acceptable hardware cost. In general, equalizer design depends on the amount of intersymbol interference to be compensated, the modulation code, the data recovery technique used, the signal-to-noise ratio, and the shape of the noise spectrum.

A substantial part of the linear intersymbol interference when reading data stored in a magneto-optical disc is caused by the limited analog read channel bandwidth and the roll-off of the input signal amplitude due to the increased storage density. Thus, the equalization stages 6-206 may include one or several linear filters that modify the transfer function of the read channel, thereby providing more reliable data detection. The equalization stage is typically implemented as part of the read channel, but under certain conditions, part of the equalization filtering may also be implemented as part of the write channel.

For analysis purposes, the playback signal may be considered as a train of bipolar rectangular pulses having a unit amplitude and duration T. Alternatively, the playback signal may be thought of as a series of bi-directional step functions at each location where the magnetic flux reverses direction. Wherein the step amplitude and the pulse amplitude are identical. When an input signal is applied to the equalization stages 6-206, clock information and the polarity of the pulses for each clock unit or binary bit (bit) can be derived from the output signals of the equalization stages 6-206. In theory, clock and polarity information can be derived using an ideal waveform recovery equalizer that provides an output signal having values similar to the mid-bit (mid-bit) and bit boundary (bit boundary) values of the input signal. The zero-crossing points of the output signal occur at the bit boundaries in order to accurately regenerate the clock. If the zero-crossing time and direction are known, the data of the clock can be extracted from the signal zero-crossings.

In one embodiment, the equalization stages 6-206 include an equalizer selected from a set of waveform recovery equalizers. Waveform recovery equalizers typically produce a signal that is similar to a binary sequence of the input waveform or the playback waveform. The principle of the resulting signal is that the corners of the rectangular pulse are rounded because the signal harmonics are attenuated in the channel. The resulting signal may also exhibit some change in the amplitude of the output signal.

The equalizer that produces the minimum bandwidth output signal is an ideal low pass filter with a response of one to the minimum cut-off frequency and zero to higher frequencies. Although such an ideal low-pass filter cannot be realized in practice, Nyquist theory about residual symmetry (vestigial symmetry) suggests that the sharp cut-off minimum bandwidth filter can be modified while still keeping the output pulse zero-crossing at all bit-middle cell times. To achieve this result, the high frequency roll-off of the equalized channel is preferably symmetric and has the half-amplitude (halfampieitude) point at the minimum bandwidth filter cutoff frequency.

One type of roll-off characteristic that may be exhibited by the filters in equalization stages 6-206 is a raised cosine roll-off, and is therefore referred to as a raised cosine equalizer. The raised cosine roll-off transfer function can be implemented approximately and has an improved response over minimum bandwidth filters. The output pulse has a zero value at time nT, but the amplitude of the side lobe (sidelobe) ringing is reduced. The output zero crossings of the raised cosine filter are more uniform than those of the minimum bandwidth filter and the linear phase characteristic is more easily achieved due to a gradual roll-off, for example due to a relatively gradual roll-off of the raised cosine filter. However, these advantages are generally achieved at the expense of increased bandwidth. The ratio of bandwidth extension to minimum bandwidth fm is sometimes referred to as "α" of the raised cosine channel. Thus, in the case of using a modulation code with d-0, α -0 is the minimum bandwidth, but it represents a rectangular transfer function that cannot be achieved, and α -1 represents a filter using twice the minimum bandwidth.

The pulse transfer function of the raised cosine equalization channel (including the analog channel plus the equalizer, but not including the input filter) is as follows:

h (f) ═ 1, for 0 < f < (1-alpha) & fm

H(f)＝1/2{1+Cos[(f-(1-α)·fm)/(2·α·fm)]}，

Suitable for (1-alpha) fm < f < (1+ alpha) fm

H (f) ═ 0, applies to f > (1+ α) · fm where * (f) ═ k · f is the phase and k is a constant. One type of equalizer described above may be referred to as an alpha waveform recovery equalizer. The α -1 channel has a characteristic of being zero at a half-bit interval and a full-bit interval. Such a channel results in no intersymbol interference signals at the bit middle or bit boundary instants (these instants are the signal zero crossing and sampling instants) so that the clock and data can be accurately recovered. For such full bandwidth equalizers, the roll-off starts at zero frequency and extends to the cut-off frequency fc.

Given a sufficient signal-to-noise ratio, a raised cosine equalizer can correct a large amount of linear intersymbol interference. A large amount of high frequency boosting may be required to compensate for the resolution of the magneto-optical medium and the optical system. Preferably, an equalizer with a bandwidth equal to at least twice the minimum bandwidth is used to eliminate linear intersymbol interference, assuming a physically realizable channel using a modulation code with d-0. Such a wide bandwidth generally causes a reduction in the signal-to-noise ratio. The equalizer bandwidth is chosen such that an optimal trade-off between interference distortion and noise is achieved. In some cases, it may be desirable to narrow the bandwidth by using an α < 1 transfer function to improve noise at the expense of increased distortion in the form of clock jitter.

Another type of waveform recovery equalizer is known as a cosine beta response equalizer. The impulse transfer function for the full bandwidth beta channel is as follows:

H(f)＝cos^β(π. f/(2. fc)) applies to 0 < f < fc

H (f) is 0, for f > fc

As with the alpha equalizer family, there are many beta equalizers. The full bandwidth beta equalizer has a cut-off frequency fc, so the clock jitter is reduced due to the relatively small amount of interference on the bit (bin) boundaries. Techniques are known in the art for optimizing these types of equalization filters to achieve a minimum probability of error under various noise conditions.

The use of an alpha equalizer generally causes a bandwidth narrowing, thus reducing noise at the expense of clock jitter or horizontal eye opening. The use of a beta equalizer generally improves the signal-to-noise ratio by reducing the boost of high frequencies without reducing the bandwidth. The use of a beta equalizer can reduce Vertical eye opening (Vertical eye opening) or reduce the effective amplitude. The α -1 and β -2 equalizer channels are identical from the eye pattern (eye pattern) point of view, both types of channels having a fairly open eye pattern.

The optimum equalizer channel bandwidth for a code with d > 0 does not necessarily depend on the minimum recording pulse width Tr as expected, But depends on the bit width Tm. This is because the data recovery circuit typically needs to be used to identify different pulses with a small difference of one bit width. The nominal bandwidth BW is required by the (0, k) code (k represents the maximum number of consecutive bits without flux reversal)_NOMFc to eliminate interference at the edges and center of each bit if there are no intersymbol interference brackets at the bit boundaries.

For codes with d > 0, interference can be substantially cancelled at bit edges using a reduced bandwidth BW of 1/(2 · Tm) of fc/2. In this case, all bit sense pulses have unity amplitude when the flux is reversed and the trailing edge of the sense pulse crosses zero when the flux transitions. The narrower bandwidth BW results in the output signal crossing zero at the non-interference point regardless of the center of the bit, but in the presence of channel impairments, a bandwidth reduction is generally obtained while also increasing the ambiguity of detection. A narrower bandwidth BW may also cause a decrease in the slope of the zero crossings of the signal, resulting in a possible increase in detection sensitivity to noise, disk speed variations, differences in analog channels, or improper equalization. For example, a half-bandwidth β ═ 2 equalization channel with an (l, k)2/3 rate modulation code may produce a signal without intersymbol interference at signal zero, but with some amplitude change between zero crossings. This bandwidth is smaller than that of the non-return-to-zero (NRZ1) modulation, although more information is recorded than with NRZ1 modulation. (e.g., bandwidth 0.75, bit rate 1.33 for NRZ 1). The reduced bandwidth compensates for the waste of the rate of the modulation code.

The alpha-1 and beta waveform recovery equalizers allow the zero-crossing of the output to occur at the same point as the input pulse edge. Data detection is then obtained by hard-limiting (hard-limiting) the equalized signal, typically producing an output signal similar to the originally played signal. However, this result only occurs when the equalizer should be extended to DC, which is not generally the case for magneto-optical disk channels, and the birefringence of the disk in the MO (magneto-optical) channel shifts the DC baseline up and down, producing output code bits that are stretched or shortened by the degree of zero crossing detector amplitude shift. This problem can be mitigated by using DC restoration as described herein. To achieve the nulled low frequency response of the waveform recovery equalizer, the low frequency signal may have to be amplified sufficiently, which may severely degrade the signal-to-noise ratio under certain conditions. If there is a significant amount of low frequency noise, the waveform restoration equalization technique may not be very satisfactory unless a modulation code without DC and very low frequency content is used or a DC restoration circuit is used.

In a preferred embodiment, the equalization stages 6-206 may include programmable filters and equalizers 6-207 located on an integrated chip, as shown in FIG. 79A. Such chips are currently available from various manufacturers. The filters and equalizers 6-207 may be of the equal ripple type and have a relatively constant group delay for frequencies up to approximately twice the cutoff frequency. A typical frequency response curve for the equalization stages 6-206 is shown in fig. 80B, and an example of an output waveform is shown in fig. 84C.

The signal peaks of the waveform in fig. 84C contain accurate information about the location of the read data after the signal is processed by the equalizer stages 6-206. Signal peaks may be detected by taking another derivative, but this may be detrimental to the signal-to-noise ratio of the system and may cause unwanted jitter. In the preferred embodiment of the invention described herein, a peak detection device is provided that does not take the second derivative by using local integration and a new data generation circuit.

After the signal is processed by the equalization stages 6-206, it is sent to the local integration stages 6-208 for waveform shaping. As shown in fig. 79A, the local integration stages 6-208 may include amplification stages 6-229, band pass filter stages 6-230, integrator and low pass filter stages 6-232, and subtractor and low pass filter stages 6-234. The amplification stage 6-229 receives the output of the equalization stage 6-206 and provides signals to the band-pass filtering stage 6-230 and to the integrator and low-pass filtering stage 6-232. The integrator and low pass filter stages 6-232 preferably attenuate selected ranges of high frequency components. A typical frequency response 6-260 for the integrator and low electrical filter stages 6-232 and a typical frequency response 6-261 for the bandpass filter stages are shown in fig. 80C.

The output of band-pass filtering stage 6-230 of fig. 79A is subtracted from the output of integrator and low-pass filtering stage 6-232 before being filtered by low-pass filtering stage 6-234. The overall frequency response curve of the local integration stages 6-208 including the low pass filters 6-234 is shown in fig. 80D. Exemplary output waveforms of the local integration stages 6-208 are shown in FIG. 84D.

A detailed circuit diagram of a particular embodiment of the local integration stages 6-208 is shown in fig. 79B. First, differential inputs 6-238, 6-239, for example from the equalization stages 6-206, are received. The differential inputs 6-238, 6-239 are fed to differential amplifiers 6-240 constructed as shown for differential summing. The differential amplifier 6-240 substantially corresponds to the amplifier stage 6-229 shown in fig. 79A.

The output of the differential amplifier 6-240 is connected to a pair of current generators 6-241 and 6-242. The first current generator 6-241 includes a resistor R77 and a PNP transistor Q61, which is configured as shown in fig. 79B. The second current generator 6-242 also includes a resistor R78 and a PNP transistor Q11, which is configured as shown.

The output of the current generator 6-241 is connected to a band pass filter 6-243. The band pass filters 6-243 include an inductor L3, a capacitor C72 and a resistor R10, formed in parallel as shown. The band-pass filters 6-243 correspond substantially to the band-pass filtering stages 6-230 of fig. 79A. The output of the current generator 6-242 is connected to the integrator 6-244. The integrator 6-244 includes a capacitor C81 and a resistor R66 connected in parallel as shown in fig. 79B.

The outputs of integrators 6-244 are coupled to NPN transistor Q31 through resistor R55. Transistor Q31 is connected as an emitter follower providing isolation from the output of the integrators 6-244 and as a voltage source. The emitter of transistor Q31 is connected to low pass filters 6-245. The low pass filters 6-245 include an inductor L6, a capacitor C66 and a resistor R49 in the form shown in fig. 79B. The integrator 6-244 comprises an emitter follower of a transistor Q31 and the pass filter 6-245 is substantially equivalent to the integrator and low pass filter stage 6-232 shown in fig. 79A. The frequency response of the integrator 6-244 substantially corresponds to the frequency response 6-260 shown in fig. 80C, while the frequency response of the band-pass filter 6-243 substantially corresponds to the frequency response 6-261 shown in fig. 80C.

The outputs of the low pass filters 6-245 and the outputs of the band pass filters 6-243 are coupled to differential amplifiers 6-246 as shown in fig. 79B. The differential amplifier 6-246 sums the difference of its inputs and provides a differential output to a low pass filter 6-247. The differential amplifier 6-246 and the low-pass filter 6-247 substantially correspond to the subtractor and the low-pass filtering stage 6-234 of fig. 79A.

Examples of waveforms of the circuit of fig. 79B are shown in fig. 80G (1) to 80G (4). Fig. 80G (1) shows first exemplary input waveforms 6-256 that may be provided to differential amplifiers 6-240 from, for example, equalizers 6-206. The next waveform 6-257 in fig. 80G (2) corresponds to the output of the bandpass filter 6-243 of fig. 79B in response to the circuit receiving the input waveform 6-256. The next waveform 6-258 in fig. 80G (3) corresponds to the output from low pass filters 6-245 after the circuit receiving the input waveforms 6-256 in response to fig. 79B. Waveforms 6-258 represent the results of the operation of integrators 6-244. The function of the low pass filters 6-245 is primarily to provide a lag so that the output of the band pass filters 6-243 and the output of the integrators 6-244 coincide in time at the input of the differential amplifier 246. Thus, the low pass filters 6-245 match the lag at each input of the differential amplifiers 6-246 before the differential summing.

The final waveform 6-259 of fig. 80G (4) corresponds to the output from the second low pass filter 6-247 after the signals output from the band pass filter 6-243 and low pass filter 6-245 have been combined and filtered. Waveforms 6-259 exhibit significantly improved resolution over the original signal read from the magnetic medium.

It should be noted that the partial integration function described with reference to fig. 79A, 79B is implemented using differential amplifiers (e.g., differential amplifiers 6-240 and 6-246), thus providing common mode rejection, equivalent to rejection of the DC component of the input signals 6-238, 6-239. Another feature of the embodiment shown in fig. 79A and 79B is that the partial integration stage exhibits a fairly good frequency response characteristic. In particular, by combining the integrated signal with a high pass filtered signal (e.g., at the subtractor and low pass filter block 6-234 or at the difference amplifier 6-246), noise may be removed from the differentiated and equalized playback signal while maintaining a relatively fast response time due in part to the high pass frequency boost provided by the band pass filter.

The main function of the combination of the differential stage 6-204, the equalization stage 6-206 and the local integration stage 6-208 is to shape the playback signal 6-220 in a suitable way to facilitate data recovery. Comparing fig. 84A and 84D, it can be seen that the final signal shown in fig. 84D is similar to the playback signals 6-220 of fig. 84A (from which the former is derived), but differs in that the magnitudes of its high and low frequency components have been equalized and the sharp noise-like characteristics have been removed. The overall frequency response curve for the combination of the differential stage 6-204, the equalization stage 6-206, and the partial integration stage 6-208 is shown in fig. 80E. The total group delay response curve for the same element chain is shown in fig. 80F.

It may be noted that there are tape drive systems that now use equalization and integration of the playback signal to assist in data recovery. However, these systems do not have the problem of a DC component because they typically utilize DC-free codes. As described above, the DC-free code has a disadvantage of low density ratio and thus low efficiency. The present invention allows for a more efficient coding system to be used in different embodiments by providing means to eliminate the effects of DC component build up without having to use DC-free codes.

The output of the local integration stage 6-208 (e.g., the waveform in fig. 84D) is fed into the data generation stage 6-210 of fig. 79. A block diagram of the data generation stages 6-210 is shown in figure 81. It includes a positive peak detector 6-300, a negative peak detector 6-302, a voltage divider 6-304, a comparator 6-306, and a double edge circuit 6-308. The operation of the circuit shown in fig. 81 can be explained with reference to fig. 83. In fig. 83 it is assumed that the recorded bit sequence 6-320 has been read out in the manner described above and finally caused to produce a preprocessed signal 6-322 output from the local integration stage 6-208. It should be noted that the preprocessed signals 6-322 and other waveforms shown herein have been somewhat idealized for ease of illustration, and those skilled in the art will appreciate that the actual waveforms may differ somewhat in shape and size from those shown in FIG. 83 and elsewhere.

The pre-processed signal 6-322 is fed to a positive peak detector 6-300 and a negative peak detector 6-302, which measure and track the positive and negative peaks of the pre-processed signal 6-322, respectively. The positive peak output signals 6-330 of the positive peak detectors 6-300 and the negative peak output signals 6-332 of the negative peak detectors 6-302 are shown in fig. 83. The positive peak output signal 6-330 and the negative peak output signal 6-332 are averaged by a voltage divider 6-304 formed by a pair of resistors 6-341 and 6-342. The output of the voltage divider 6-304 is used as the threshold signal 6-334 of fig. 81-83 and represents approximately the peak-to-peak midpoint of the preprocessed signal 6-322. The output of the voltage divider 6-304 is supplied to a comparator 6-306 which compares the divided voltage with the preprocessed signal 6-322. When the pre-processed signal 6-322 exceeds the threshold signal 6-334, the comparator 6-306 changes state, indicating a transition of the read data from 1 to 0 or from 0 to 1. The outputs of comparators 6-306 are shown in FIG. 83 as output data waveforms 6-362. As explained in detail below, the output data waveforms 6-362 are fed back to the positive peak detectors 6-300 and negative peak detectors 6-302 to allow tracking of the DC envelope. The outputs of the comparators 6-306 are also fed to a dual edge circuit 6-308 which generates a fixed width unipolar pulse whenever the state of the comparators 6-306 changes.

The outputs of the two edge circuits 6-308 provide clock and data information from which the data can be recovered straightforwardly. For example, in a Pulse Width Modulation (PWM) technique such as the aforementioned GCR8/9 modulation code, each data pulse output from a two-edge circuit 6-308 represents a flux transition (i.e., a recorded 1 bit), while the absence of a data pulse at a clock interval indicates no flux transition (i.e., a recorded 0 bit). The sequence of recording bits may then be decoded by decoders 6-24 (fig. 75) in a manner well known in the art to determine the original data.

In order to correctly track the envelope caused by the DC part of the pre-processed signal 6-322, the preferred embodiment feeds back the duty cycle information from the output signal 6-362 to the peak detector. Thus, the output of the comparator 6-306 is fed back to the positive peak detector 6-300 and the negative peak detector 6-302. This process is further illustrated with reference to fig. 82, where a more detailed circuit diagram of the data generator stages 6-210 is given. As shown in fig. 82, the preprocessed signals 6-322 are sent to the bases of transistors Q2 and Q5. Transistor Q2 is associated with the positive peak detector 6-300 and transistor Q5 is associated with the negative peak detector 6-302. Since the positive peak detectors 6-300 and the negative peak detectors 6-302 operate in a similar manner, the duty cycle feedback operation will be described with reference to the positive peak detectors 6-300 only, and similar operation of the negative peak detectors 6-302 will be apparent to those skilled in the art with reference to fig. 82.

When the magnitude of the pre-conditioned signal 6-322 exceeds the stored voltage of capacitor C1 (and the positive bias of transistor Q2), transistor Q2 charges capacitor C1. In fig. 83, it can be seen that the positive peak output signal 6-330 quickly fills the peak of the signal 6-322. By feedback, the output signal 6-362 maintains a positive charge on capacitor C1 when it is high and discharges capacitor C1 when it is low. Thus, if the output signals 6-362 are high, the positive charge on capacitor C1 is maintained by transistor Q1 through resistor R2. The resistors R1, R2 are preferably chosen to be of the same value so that the charge applied to the capacitor through resistor R2 is at the same rate as the charge discharged through resistor R1, thereby maintaining a constant static charge on the capacitor C1. On the other hand, if the output signal 6-362 is low, transistor Q1 is off and capacitor C1 discharges through resistor R1. The values of capacitor C1 and resistor R1 are preferably chosen so that the time is often slightly faster than the rate at which the desired DC component builds, so that capacitor C1 can track the change in DC level as the DC component changes.

The output of capacitor C1 is fed to the base of transistor Q3. The voltage level of the emitter of Q3 is greater than the bias level of capacitor C1. The current flowing through resistor R3 causes the emitter of transistor Q3 to follow the voltage of capacitor C1 (minus the emitter-base bias). Thus, the emitter of transistor Q3 produces positive peak output signals 6-330. It should be noted that the transistors Q1 and Q2 are NPN type transistors and Q3 is a PNP type transistor. Thus, the NPN-PNP structure largely cancels out the adverse effects of thermal effects on Q1, Q2, and Q3, and also cancels out the bias voltages associated with their operation.

The negative peak detector 6-302 operates in a similar manner to the positive peak detector 6-300 and will therefore not be explained in detail. The emitter of transistor Q6 produces negative peak output signals 6-332.

As described above, the positive peak output signal 6-330 and the negative peak output signal 6-332 are averaged by a voltage divider 6-304 formed by a pair of resistors R4, 6-341 and 6-342, as shown in FIGS. 81 and 82, to form a threshold signal 6-334. The threshold signal 6-334 thus constitutes the peak-to-peak midpoint of the pre-processed signal 6-322 and tracks the DC envelope of the pre-processed signal 6-322 by duty cycle feedback compensation.

Although duty cycle feedback has been shown by the outputs of comparators 6-306 in the preferred embodiment, it is observed that other feedback paths may be used. For example, if a flip-flop or other memory element is placed at the output of the dual edge circuit 6-308, a similar feedback path may be taken from the output of the dual edge circuit 6-308. Other means for measuring the duty cycle and adjusting the threshold signal to track the DC envelope may be used.

The preferred technique as described in fig. 78 and 79B includes the step of differentiating the feedback signal prior to partial integration; this is followed by a DC tracking step. The optimal method is particularly suitable for systems that play back signals with a relatively poor resolution and may advantageously be applied for reading information stored in the GCR format. In one aspect of the preferred method, the initial differencing step reduces low frequency components in the input playback signal. In another aspect of the preferred method, the local integration stage recovers or partially recovers the playback signal while providing fast response through high-pass boosting (e.g., from a band-pass filtering stage). The best method is to be contrasted with the method in which integration of the playback signal is performed from the beginning (i.e. before differencing), which latter method may lead to an increase in the DC component and thus make it more difficult to track the DC component in time.

It will be appreciated that the various circuits and methods described herein are not limited to magneto-optical systems, but may be used for the reading of data stored in systems such as magnetic tape systems or other types of disks, and in a broader sense, in any system for processing electrical signals (whether it be a data storage system or not), where it is desirable to mitigate the effects of a DC component.

Other aspects of data retrieval and data storage

In FIG. 85, during a write mode, a data source 7-10 transmits data to an encoder 7-12. The encoders 7-12 convert binary data into binary code bits. The code bits are then sent to the laser pulse generator 7-14 where they are converted into an excitation pulse which switches the laser 7-16 on or off. In the preferred embodiment, the code bit "1" indicates that the laser should be pulsed for a fixed duration regardless of the code bit form. However, depending on the laser and optical medium used, performance can be improved by adjusting the timing of the laser pulses or by extending the duration of the pulses. The output of the laser 7-16 heats a localized region of the optical medium 7-18 that is being exposed to a magnetic flux that establishes the polarity of the magnetic material on the optical medium 7-18. During reading of the optical media 7-18 a laser beam is directed onto the surface of the media, the polarization of the reflected laser beam depending on the polarity of the magnetic surface of the optical media.

During the read mode, the reflected laser beam is then input to the optical reader 7-20 and the read code is sent to the waveform processor 7-22. The processed read code is sent to the decoder 7-24 and the output data is sent to the data output port 7-26 for transmission.

FIG. 86 illustrates the difference between laser pulses in the GCR8/9 and RLL2, 7-code formats. In GCR8/9, cells 7-28 are defined as code bits as shown in FIG. 86A. For GCR8/9, 9 cells or code bits equal 8 data bits. Thus, each of the units 7-30 to 7-41 corresponds to one clock cycle 7-42 of the clock waveform 7-45. For a 3.5 "disc with a storage capacity of 256Mbytes and a rotational speed of 2400 Revolutions Per Minute (RPM), the clock period 7-42 is typically 63ns or a clock frequency of 15.879 MHz. The GCR data waveforms 7-47 are the encoded data output by the encoders 7-12, and a typical data sequence is shown in FIG. 86A. The coded data sequence "010001110101" is represented by GCR data 7-50 through 7-61, where GCR data 7-50 is low and GCR data 7-51 is high. GCR data 7-52 is high, GCR data 7-53 through 7-61, and so on. Pulse GCR waveforms 7-65 are the outputs of laser pulse generators 7-14 and are input to lasers 7-16. In the practice of the invention, a non-return-to-zero drive signal is used to actuate the magnetic recording head. Thus, because the laser emits sufficient pulse energy to cause the medium to exceed the curie temperature, the magnetization of the erased optical medium reverses polarity in the presence of an external magnetic field of opposite polarity to that of the erase. The illustrated pulse GCR waveforms 7-65 are not adjusted for a time or duration interval to reflect the performance enhancement for a particular dataform. Pulses GCR7-67 through 7-78 appear as no pulses when the corresponding GCR data 7-47 is low and as pulses when GCR data 7-47 is high, e.g., pulses GCR7-67 are no pulses because data 7-50 are low. In contrast, pulses GCR7-68, 7-70, and 7-71 appear to have pulses because GCR data 7-51 through 7-54 are each high, similarly for pulses GCR7-72 through 7-78. In the uniform case described, the pulse widths of pulses GCR7-65 are uniform for pulses GCR7-68, 7-69, 7-70, 7-71, 7-73, 7-76, and 7-77. In the preferred embodiment, this pulse width is 28 ns. Each laser pulse corresponding to a pulse GCR waveform 7-65 forms a pit 7-80 on the optical medium 7-18. The pits 7-82 correspond to the pulses GCR 7-68. The pits 7 to 83 correspond to the pulses GCR7 to 69. Similarly, the pits 7-84 to 7-88 correspond to the pulses GCR7-70, 7-71, 7-73, 7-76, and 7-77, respectively.

The recording pits 7-80 are wider than the pulses GCR7-65 because of thermal diffusion and spot size on the optical medium 7-18. The successive pits 7-80 are joined together to actually form one larger pit. Thus, the lengthened pit has a leading edge corresponding to the first pit, and a trailing edge corresponding to the last pit. For example, the pit formed by the pits 7-82 to 7-85 has a leading edge from the pit 7-82 and a trailing edge from the pit 7-85. In the GCR8/9 data format, the leading edge goes high corresponding to GCR data 7-47 and the trailing edge goes low corresponding to GCR data 7-47. Thus, for the data form "10001" represented by GCR data 7-51 to 7-55, the leading edge occurs at the first "1" (GCR data 7-47 goes high) as shown by pit 7-82, and the trailing edge occurs at the end of GCR data 7-54 as shown by pit 7-85 because GCR data 7-55 is low.

The playback signal 7-90 is low when the recording pits 7-80 appear to be without pits. At the leading edge of a pit, the playback signal rises and then remains high until the trailing edge of the pit is reached. The signal goes low and stays low until the next pit. For example, the playback signal 7-91 is low because the GCR data 7-50 is low and no pit is generated. At the leading edge of the pit 7-82 the playback signal 7-90 has a leading edge as shown in the playback signal 7-92. The playback signal 7-90 will then remain unchanged until the trailing edge of a pit. For example, the playback signals 7-93, 7-94 remain high because the pits 7-83, 7-84 have no trailing edges. The signal remains high during playback of signal 7-95 because of the presence of pits 7-85. However, since the GCR data 7-55 is low, the recording pits 7-85 produce trailing edges. In this way the playback signal 7-96 is attenuated. The signal will fade to "0" until a pit occurs, forming a leading edge. Thus, due to the presence of the pits 7-86, which correspond to the GCR data 7-56 being high, the playback signal 7-97 rises. Since there is no immediate successor to the recording pits 7-86 when the GCR data 7-57 is low, the playback signal 7-98 falls. The playback signal 7-99 remains low because there are no pits recorded when the GCR data 7-58 is low. As the GCR data 7-59 and 7-60 become higher, the recording pits 7-87 and 7-88 overlap to form one large pit. Thus, the playback signal 7-100 rises and the playback signal 7-101 remains high. The playback signal 7-102 falls at the trailing edge of the pit 7-88 when the GCR data 7-61 is low.

For RLL2, 7 cells include two bits of data, corresponding to two clock cycles 7-121 of the 2F clock waveforms 7-120 of FIG. 86B. For a 256M disc, the RLL2, 7 encoding format requires a 2F clock pulse width of 35.4ns or a clock frequency of 28.23 MHz. This value is calculated directly. In order to maintain the same disc density, the GCR8/9 and RLL2, 7 encoding formats must contain the same amount of information in the same recording time. Because each data bit in RLL2, 7 lattices requires two code bits, the required clock frequency is 2- (8/9) of the GCR format. The GCR data format records 9 code bits per 8 data bits. Thus, the GCR data bit is clocked at 9/8 of clock cycles 7-42. Thus, for a GCR clock period of 63ns, RLL2, 7 pulse widths 7-121 must be 35.4ns in order to maintain the same disc density.

RLL2, 7 data waveforms 7-122 reflect two code bits per cell. For example, RLL2, 7 Data 7-124 represents dataform "00", and RLL2, 7 Data 7-125 represents dataform "10". In this data format, "1" represents a data conversion. Thus, RLL2, 7 data 7-125 go high when a "1" appears in the data form. Similarly, RLL2, 7 data 7-126 goes low when a "1" appears in the data format. While RLL2, 7 data 7-122 remain in the same state when a "0" occurs. The 2, 7 waveforms 7-137 of the pulses reflect the pulses of the lasers 7-16 corresponding to RLL2, 7 data 7-122. Thus, for RLL2, 7 data 7-125 and 7-126, the 2, 7 waveforms 7-140 and 7-141 of the pulses are high during the time that the signal is high. Because of the thermal elongation of the pits, the 2, 7 waveform 7-141 of the pulse goes low before RLL2, 7 data 7-126. For longer dataforms of "0", the pulse must be maintained. For example, during the data form "10001", as shown by RLL2, 7 Data 7-128, 7-129, the 2, 7 waveforms 7-143, 7-144 of the pulses remain high for a longer period of time than the 2, 7 waveforms 7-140, 7-141 of the pulses. For a data form that is "0" in succession, the 2, 7 waveforms 7-137 of the pulses may be individual pulses. For example, for the data form "1000001", RLL2, 7 data 7-132, 7-133, and 7-134 may appear as two separate pulses, as shown by pulses 2, 77-147, 7-148, and 7-149.

The recorded pits 7-160 exhibit thermal elongation when using the GCR8/9 format. For example, pits 7-162 are wider than the 2, 7 waveforms 7-140, 7-141 of the pulse, with similar results for pits 7-163. Further, the playback signal 7-167, illustrated by playback signals 7-168 to 7-174, becomes high at the leading edge of the pit 7-160, decreases at the trailing edge of the pit 7-160, and remains unchanged during the non-pit or pit-present period.

Pulsed GCR codes can be improved by correcting predictable position offsets. FIG. 87 is a timing diagram showing write compensation for laser pulse generators 7-14. Practical tests have shown that early recording improves performance when the laser 7-16 is off for two bits or more. Clock waveforms 7-176 are the code bit clocks used to clock in data 7-177, 7-203, and 7-229, which represent the worst-case data forms for improved performance. Other forms can be corrected but suffer in signal amplitude. The data 7-180 to 7-184 correspond to the data sequence "10100". The uncompensated pulse waveforms 7-188 to 7-192 correspond to this data form without write compensation. The uncompensated pulse waveforms 7-189, 7-191 occur during the second half of the clock cycle. After write compensation, the output of the laser pulse generator 7-14 corresponds to the compensation pulse shape 7-195, wherein the compensation pulse shapes 7-197, 7-198 remain unchanged, while the shortened off-interval of the compensation pulse shape 7-199 provides the earlier compensation pulse shape 7-200. During the compensated pulses 7-201, the laser 7-16 remains off for a longer time than the uncompensated pulses 7-192. Similarly, for data 7-206 through 7-209, corresponding to data form "1100", the uncompensated pulse waveform 7-211 would be two pulses after the cut-off uncompensated pulse waveform 7-213, i.e., uncompensated pulse waveforms 7-214 and 7-216. The write compensation circuit again adjusts the compensated pulse waveform 7-220 such that the compensated pulse waveform 7-225 occurs closer in time to the compensated pulse waveform 7-223 such that the compensated pulse waveform 7-224 is shorter than the uncompensated pulse waveform 7-215. Finally, data 7-231 through 7-235, equivalent to "00100", have uncompensated pulse shapes 7-237 appearing at uncompensated pulse shapes 7-240. The write compensation will move the compensated pulse shape 7-243 forward into the compensation pulse shape 7-246 that occurs earlier.

FIG. 88 is a schematic diagram of a write compensation circuit. Which comprises the following steps: a dataform monitor 7-248, a write compensation form detector 7-249 and a delay circuit 7-269. The dataform monitor 7-248 is a serial shift register that sequentially shifts the encoded data from the encoder 7-12 in clock. The last shifted 5 of the data bits are sent to the write compensation pattern detectors 7-249 where they are analyzed to determine whether to pulse the laser earlier than normal.

The dataform detector 7-248 is composed of a data sequence D flip-flop 7-250 to 7-256, the encoded data being input to the D port of the data sequence D flip-flop 7-250, the Q output WD1 of which flip-flop becomes the input to the D port of the data sequence D flip-flop 7-251. This clock-in continues through the data sequence D flip-flops 7-252 to 7-256, the Q output WD7 of flip-flops 7-256 being the data sequence delayed by 7 clock cycles since it was first input to the dataform monitor 7-248. The Q outputs WD1, WD2, WD3, WD4 and WD5 of the data series D flip-flops 7-250 through 7-254 represent the last 5 bits of the last 7 bits of data of the input dataform monitor 7-248, respectively. These 5 bits of data are sent to a write compensation pattern detector 7-149 where they are compared with a predetermined data pattern; if this is the case, the start-up write signal is sent to the delay circuit 7-269, indicating that the laser should be pulsed earlier than normal.

The first data form is detected by inverting the Q data WD1, WD2, WD4 and WD5 from the data sequences D flip-flops 7-250, 7-251, 7-253 and 7-254, respectively, via the data inverters 7-282, 7-283, 7-284, respectively. These inverter outputs are anded with the outputs from the data series D flip-flops 7-252 in sense and gates 7-264. Thus, when the sequence "00100" occurs, the outputs of the detection and gates 7-264 go high, indicating that detection of the data format has occurred. Similarly, the second dataform is tested by inverting the Q outputs WD1, WD2, and WD4 from the data series D flip-flops 7-250, 7-251, and 7-253, respectively, through the data inverters 7-282, 7-283, 7-284, respectively, and comparing these inverted outputs with the outputs WD3 and WD5 of the data series D flip-flops 7-252 and 7-254, respectively, in the sense AND gates 7-286. Thus, the dataform "10100" will be triggered high by the sense and gate 7-286, indicating a sense. The third data sequence is checked by inverting the Q outputs WD1 and WD2 from the data sequence D flip-flops 7-250 and 7-251, respectively, through the data inverters 7-287, 7-288, and then anding these inverted outputs with the Q outputs WD3, WD4 from the data sequence D flip-flops 7-252, 7-253 in the data detection and gates 7-289, respectively. Thus, the data form "1100" will be detected by the detection and gate 7-289, indicating that the data is present. The dataform sense outputs of the sense and gates 7-264, 7-286, 7-289 are or 'ed' in sense form or gates 7-266, the output of or gates 7-266 going high when one of the three dataforms is sensed. The sense pattern output is clocked into a start write D flip-flop 7-268, the Q output of which, i.e., the start write signal, is provided to a delay circuit 7-269.

Delay circuit 7-269 receives the data output from data sequence D flip-flop 7-253 and passes it simultaneously to delay circuit 7-276 and non-delayed select and gate 7-274. The delayed outputs of delay circuits 7-276 are provided to delay select and gates 7-272. The enable write signal from the write compensation pattern detector 7-249 will enable the delayed select and gate 7-272 or the non-delayed select and gate 7-274. When the enable write signal is low, indicating that one of the three data is not occurring, it is inverted by enable write inverters 7-270. This causes the delayed data output from the delay circuits 7-276 to have to be clocked in (tobe clocked). On the other hand, if the initiate write is high, indicating that one of the three dataforms has occurred, non-delayed select and gate 7-274 allows transmission of undelayed data from data sequence D flip-flops 7-253. The outputs from the delay select and gates 7-272 and the non-delay select and gates 7-274 are or' ed at data or gates 7-278, where they are output from delay circuits 7-269. Although the above discussion of write compensation circuitry or timing is for three dataforms, indicating that the write pulse should occur 10ns earlier, in actual implementations the delay is 10ns for all data that is not three dataforms. The delay of delay circuit 7-276 is set to be between 7 and 12ns for the frequency of the preferred embodiment.

The rise time of the last magneto-optical signal is longer than the fall time when recording lower frequency data forms. This causes the final output of the waveform processor 7-22 to deteriorate in amplitude at positive peaks, which can be corrected by recording at the leading edge of the dataform with a higher effective power. In the preferred embodiment, dataform "000111" will trigger a wide write signal during its second "1" period, thereby pulsing the laser during its normally off period.

In FIG. 89, clock waveforms 7-301 are driven into data waveforms 7-303 of data form "000111" by laser pulse generators 7-14. As shown by data 7-305 through 7-310, when data waveform 7-303 is a "1", laser pulse generator 7-14 generates pulse waveform 7-312 having pulses 7-314, 7-315, and 7-316. During the second "1" of this dataform, laser pulse generator 7-14 will operate for an increased power waveform 7-318 and generate pulses 7-320. The output laser pulse waveform 7-322 is an OR of pulse 7-312 and the increased power waveform 7-318, producing laser pulses 7-323, 7-324, and 7-325. Under normal operation, laser pulses 7-324 should be off during the first half of the clock cycle. However, in the first particular dataform, keeping the laser on for laser pulses 7-323 and 7-324 effectively increases the power by 50% during this time interval.

In fig. 90, the amplitude asymmetry correction circuit 7-291 produces a wide write (write-wide) pulse 7-292 (corresponding to the increased power waveform 7-318 of fig. 89) that will be or' ed with the laser pulse output of the delay circuit 7-269 (corresponding to the pulse waveform 7-312 of fig. 89) in the or gate of the laser pulse producing the output laser pulse waveform 7-322. The operation of the dataform monitor 7-248 is shown in fig. 88. The Q outputs WD2 through WD7 of the data sequence D flip-flops 7-251 through 7-256 are input to the amplitude asymmetry correction circuits 7-291, respectively. Wherein the outputs WD5, WD6, WD7 of the data sequence D flip-flops 7-254, 7-255, and 7-256 are inverted in the data inverters 7-293, 7-294, 7-295, respectively. The outputs of the data inverters 7-293, 7-294, 7-295 and the outputs of the data sequence D flip-flops 7-251, 7-252, 7-253 are and 'D' in the detection and gate 7-296. The output of the sense and gate 7-296 indicates the detected form "000111" which will clock out the next clock 7-301 from the wide D flip-flop 7-297.

The waveform output of the optical reader 7-20 will degrade depending on the frequency and data format. The amplitude and timing can be improved by processing the signals by the waveform processors 7-22. The asymmetry of the rise and fall times of the arc onset pulses can be improved by summing the equalized differential signal with its derivative. In fig. 91 the magneto-optical signal 7-327 is differentiated by a differential amplifier 7-329. The differentiated signal is sent to an equalizer 7-331 where in this embodiment 5dB equalization is achieved and the amplitude is equalized according to frequency. The derivative of the equalized signal is taken by the processor 7-333 and the derivative and the equalized signal are summed in an adder 7-335, the output of the adder 7-335 being the read-out signal 7-337.

FIG. 92 is a timing diagram of the dynamic threshold circuit of FIG. 93. The read-out signal 7-337 contains an overshoot generated by a pulse tapering (slimming). Since such an overshoot is predictable, the threshold value of the sensing circuit may be increased during the overshoot to avoid reading the data of the error code during the positive 7-339, 7-340, 7-341, 7-342 and negative 7-343, 7-344, 7-345 peaks of the sensing signal 7-337. During the positive peak, the threshold waveforms 7-348 transition high. During the positive peaks 7-339, 7-340, and 7-341, the threshold waveforms 7-349, 7-350, 7-351 are high, respectively. During the negative peaks 7-343, 7-344, 7-345, the threshold waveforms 7-352, 7-353, 7-354 are low, respectively. Each peak of the read signal 7-337, positive or negative, produces a peak waveform 7-356, which is a short clock pulse, that occurs after the peak of the read signal 7-337. Peaks 7-339, 7-343, 7-340, 7-344, 7-341, 7-345, and 7-342 of the read signal 7-337 generate peak waveforms 7-358 through 7-364, respectively.

As shown in FIG. 93, threshold waveforms 7-348 are fed into the D port of threshold delay D flip-flops 7-366. The peak waveform 7-356 serves as a clock to clock the synchronization threshold waveform 7-348 through the flip-flop 7-366. The delayed threshold waveform 7-368 is the Q output of the threshold delay D flip-flop 7-366 which is xored with the threshold waveform 7-348 at the threshold xor gate 7-370. The exclusive or signal 7-372 is the output of the threshold exclusive or gate 7-370. The frequency of the exclusive or signal 7-372 is twice the original threshold waveform 7-348. The exclusive-or signal 7-372 is fed into the D port of exclusive-or D flip-flop 7-374 where it is clocked in by read clock 7-375. Waveforms 7-376 of F1 are the Q outputs of XOR D flip-flops 7-374. Read clock waveforms 7-375 have rising edges during the high pulse of xor-signal 7-372, except when xor-signal 7-372 is low during more than one read clock waveform 7-275. Thus, the F1 waveforms 7-376 are high, except for the time between the first read clock 7-375 pulse after the EXOR signal 7-372 is low at more than one read clock 7-375 and the next (encountered) EXOR signal 7-372 (high read clock) pulse.

The F1 waveforms 7-376 are OR'd in the envelope OR gates 7-378 with the EXOR signals 7-372. The output of the envelope or-gate 7-378 is high except for the time from the first read clock 7-375 after the EXOR signal 7-372 has been low for more than one clock cycle until the signal 7-372 goes high again. The output of envelope or gate 7-378 is driven in with read clock 7-375 via the D input of envelope D flip-flop 7-379. The Q outputs of envelope D flip-flops 7-379 are F2 waveforms 7-381. F2 waveforms 7-381 are high, except for the time from the second read clock 7-375, after the EXOR signal 7-372 goes low, until the EXOR signal 7-372 is high, which is asserted at the read clock 7-375 again. The F2 waveforms 7-381 are inverted by the F2 inverters 7-383 and negated with the EXOR signal 7-372 in the dynamic threshold NOR gates 7-385, thereby generating the dynamic threshold waveforms 7-387. The dynamic threshold waveforms 7-387 are high whenever the EXOR signal 7-372 is low, except when the F2 waveforms 7-381 are low. Thus, the time that the dynamic threshold waveform 7-387 is high is less than half a read clock 7-375 cycle, except that the EXOR signal 7-372 is low at the next read clock 7-375 cycle. This exception is from the end of EXOR signal 7-372 going high until the second read clock 7-375 pulse, during which dynamic threshold waveform 7-387 remains high.

Dynamic threshold waveforms 7-387 are used to forward bias or reverse bias biased diodes 7-389. When the dynamic threshold 7-387 is high, the biased diode 7-389 is reverse biased. Conversely, when the dynamic threshold waveform 7-387 is low, the biased diode 7-389 is forward biased.

When the dynamic threshold waveform 7-387 forward biases (i.e., is low) the bias diode 7-389, the potential of the filter bias signal 7-390 is above the dynamic threshold voltage by a value equal to the junction voltage of the bias diode 7-389. This potential is 0.6V for standard devices. The 5V supply voltage is stepped down across the current limiting resistor 7-393 to the potential of the filter bias signal 7-390 because the voltage across the charging capacitor 7-394 is the difference between the filter bias signal 7-390 and ground potential. The charging capacitor 7-394 charges to this potential, which is also the bias voltage of the transistor 7-395. This turns on transistors 7-395, which brings the voltage at the emitter of transistors 7-395 to 1.4 volts. Because the emitters of transistors 7-395 and 8-396 are connected, the emitter voltage of transistors 7-396 is less than the 2.5V base voltage of transistors 7-396. Thus, transistor 396 is turned off, thereby causing the collector voltage across the collector resistance to produce an increasing threshold waveform 7-399 of 0 volts (ground). The increase threshold waveform 7-399 is a signal that increases the threshold of the read signal 7-377 detector during overshoot.

When the dynamic threshold waveform 7-387 is high, the biasing diode 7-389 is reverse biased, thus no longer bringing the base of transistor 7-395 to 0.6 volts. When the dynamic threshold waveform 7-387 goes high, the charging capacitor 7-394 begins to charge, creating a potential at the transistor 7-395 and base that rises exponentially to the supply voltage of 5 volts. As the voltage of filter bias signal 7-390 rises, the voltage at the emitter of transistor 7-395 increases, which likewise increases the emitter voltage of transistor 7-396. Transistors 7-396 turn on when the emitter voltage exceeds the base voltage due to the junction potential of the emitter-base junction of transistors 7-396. The conduction of transistors 7-396 causes the increasing threshold waveform 7-399 to go high.

Under normal operation, dynamic threshold waveform 7-387 is a pulse as described above. During a normal read signal, the time when dynamic threshold 7-387 is high is equivalent to the time when read clock 7-375 is high. The charging time to charge the voltage across the charging capacitors 7-394 to 2.5 volts above the base voltage is longer than half a clock cycle. Thus, under normal conditions, the increase threshold waveform 7-399 remains low. However, during overshoot, dynamic threshold waveform 7-387 is high for a longer time, charging capacitor 7-394 to a voltage exceeding 2.5V, thus causing the increasing threshold waveform 7-399 to go high.

In FIG. 94, host computers 7-410 serve as sources and users of digital data, which interface circuits 7-412 connect to data buses 7-414. The host computer 7-410 processes data and needs to read and write the external memory frequently, and thus establishes a connection with the data bus 7-414 through the interface circuit 7-412. The data bus 7-414 is connected to the inputs of the write encoder 7-416 and the write decoder 7-418. Write encoders 7-416 preferably encode data from buses 7-414 in a low density (i.e., ANSI) format; while write encoders 7-418 encode data from data buses 7-414 in a high density format. Reference is made herein to The Draft Proposalinfor 90 MM Rewritable optical disc cards for Information exchange, published 1991, 1.1.D., which illustrates The ANSI format. The outputs of the write encoders 7-416 and 7-418 are alternately connected to the write input of a magneto-optical disk read/write head 7-420 via a switch 7-422. The read outputs of the heads 7-420 are alternately connected to the inputs of read decoders 7-426, 7-428 via switches 7-424. The read decoder 7-426 decodes the data in the same format as the write decoder 7-416, i.e., ANSI format; read decoders 7-428 decode data in the same format as write decoders 7-418. The write encoders 7-418 and read decoders 7-428 are preferably implemented using the encoding and decoding techniques disclosed above. The outputs of decoders 7-426 and 7-428 are coupled to data bus 7-414.

In response to the mode selection signal, the switch control circuit 7-430 sets the states of the switches 7-422 and 7-424 to the first mode or the second mode. In the first mode, the write encoder 7-418 and the read decoder 7-428 are connected between the data bus 7-414 and the read/write head 7-420. In the second approach, the write encoder 7-416 and the read decoder 7-426 are connected between the data bus 7-414 and the read/write head 7-420. The read/write head 7-420 reads and writes encoded data on a 90mm optical disc received by a replaceable optical drive 7-432 controlled by a disc drive circuit 7-434. The read/write head 7-420 is controlled by the position control circuit 7-436 to move radially over the surface of the disk received by the disk drive 7-432.

The mode select signal sets the system in a first way when a 90mm high density format disc is received by the disc drive 7-432. As a result, data from the host 7-410 to be stored on the disk is organized by the interface circuit 7-412 and encoded by the write encoder 7-418. Data read from the disc is decoded by the read decoder 7-428, reorganized by the interface circuit 7-412, and passed to the host 7-410 for processing.

When a 90mm low density disc in ANSI format is received by the disc drive 7-432, the mode select signal sets the system to the second mode. As a result, data from the host 7-410 to be stored on the disk is organized by the interface circuit 7-412 and encoded by the write encoder 7-416. The data read from the disc is decoded by the read decoder 7-426, reorganized by the interface circuit 7-412 and transmitted to the host 7-410 for processing.

Regardless of the format used to store the data, it is preferable to store a format selection signal, such as the low-density ANSI format, on each disk, with the system also defaulting to the corresponding format, such as the second format. This way the selection signal can be recorded in the control track area in ANSI format. When a disc is loaded in the disc drive 7-432, the disc drive circuit 7-434 initially controls the position control circuit 7-436 to read the area of the disc on which the mode selection signal is stored. The read decoder 7-426 reproduces the mode selective signal applied to the switch control circuit 7-430. If the installed disc has a low density ANSI format, the system remains unchanged from the second mode when the mode select signal is read. If the mounted disc has a high density format, the system switches to the first mode when reading the mode selection signal.

In some cases, it may be desirable to modify the lasers used in the first and second modes. For example, different laser frequencies or different focusing lens systems may be used for different modes. In this case the mode selection signal is also connected to the read/write head 7-420 to control the switching between the frequency or optical lens focusing system depending on the situation.

Preferably, the stored data is organized in two formats so that there are the same number of bytes per sector, 512 bytes under ANSI. In this case the same interface circuits 7-412 may be used to organize the data stored or retrieved in both formats.

The same read/write head 7-420, position control circuit 7-436, optical disc drive 7-432, disc drive circuit 7-434, interface circuit 7-412, and data bus 7-414 may be used in accordance with the present invention to store or retrieve data on an optical disc in different formats. As a result, downward compatibility from the high density format, which is being developed as an advanced technology, to the industry standard ANSI format can be achieved using the same equipment.

Referring now to fig. 95, 96 and 98, the optimum format of the high density optical disc will be described. There are 10000 tracks, i.e., tracks 0 to 9999, arranged in 21 zones. Each track is divided into several sectors. There are different numbers of sectors in each region, the number increasing from the inside out. The frequency of data recorded in each area is also different and also increases from the inside to the outside. (see figures 95, 98 for an explanation of the number of tracks in each zone, the number of sectors in each zone, and the recording frequency in each zone). In contrast to the low-density disc, the format mark is erasable recorded on the disc, preferably a magneto-optical disc, using the same technique as that used for recording data. These format flags include sector fields, header fields for each sector, and control tracks. In contrast to the header field and data, the sector fields of all areas are recorded at the same frequency. A preferred embodiment of the sector format is described below.

Sector format

The sector includes a sector flag, a header, and a recording field in which 512 user data can be recorded. The record field may be empty or written by the user. The total length of a sector is the header and record fields whose frequencies differ from region to region, 721 bytes (one byte corresponds to 9 channel bits), plus 80 channel bits of the sector label of fixed frequency, i.e., the same frequency for each region. The tolerance is borne by the buffer, i.e. the last field of the sector. The header field is 48 bytes in length. The length of the record field is 673 bytes.

Sector Mark (SM)

The sector mark is made up of a form that does not occur in the data, which allows the drive to identify the beginning of a sector without relying on a phase-locked loop. The sector mark is recorded with a fixed frequency of 11.6MHz for all sectors. The sector mark is 80 channel bits in length. The following figure shows the format in NRZI format.

1111 1111 1100 0000

1111 1100 0000 0000

0000 1111 1100 0000

1111 1100 0000 1111

1111 1100 1001 0010

VFO field

There are 4 fields, or called VFO1, one of two VFOs 2, or called VFO3, that are used to phase lock the vco of the phase locked loop of the read channel. The information in the VFO field, VFO1 and VFO3, is identical in form and has the same length of 108 bits. Two fields called VFOs 2 are each 72 bits in length.

Address Mark (AM)

The address mark is made of a form that does not occur in the data. This field, which is used to synchronize the drive bytes for the disc drive to the following ID field, has a length of 9 bits and is of the form:

110000101ID field

The three ID fields each contain a sector address, i.e., a track number and a sector number of the sector, and a CRC (cyclic redundancy check) byte. Each field comprises 5 bytes, the content of which is as follows:

first byte-track most significant byte

Second byte-track least significant byte

Third byte-

Bits 7 and 6

00-ID field 0

01-ID field 1

10-ID field 2

11-not allow

Bit 5-zero

Bit 4 in bit 0-binary sector number

Byte 4 and 5-CRC field

The CRC byte contains CRC information, calculated over the first three bytes as shown in equations 1, 2, and 3 in table 99. Accordingly, the 16 check bits of the CRC of the ID field should of course be calculated over the first three bytes in this field. The generator polynomial is equation (1) of fig. 99. The remaining polynomial is defined by equation (2) where bi represents the first three byte bits and bi is the inverted bit, b₂₃Is the highest order bit of the first byte. 16 check bits C of CRC_kIs defined by equation (3) of FIG. 99, where C₁₅Is the highest order bit of the fourth byte in the ID field.

End mark (PA)

The end-marker fields are equal in length and all have 9 bits. There is an end-marker following LD3 and an end-marker following the data field. The end flag allows the last byte of the CRC or data field preceding it to be terminated. The end marker has 9 bits of the form:

100010001

clearance (Gaps)

CAP1 is a field of nominal length with 9 channel bits and CAP2 has 54 channel bits. CAP1 should be zero and GAP2 is not specified. CAP2 is the first field of the record field and gives the disc drive some time to process after the disc drive has finished reading the title and before it has to write or read the VFO3 field.

Sync

The Sync field enables the driver to obtain byte synchronization for subsequent data fields. It has a length of 27 bits and is recorded in the following bit form:

101000111 110110001 111000111

data field

The data field is used to record user data. It has 639 bytes (1 byte-9 lane bits) and includes:

512 bytes of user data;

4 bytes, the contents of which are not specified by this standard, which should be ignored when swapping;

a 4-byte CRC parity bit (parity);

80 bytes of ECC parity bits; and

39 bytes for resynchronization;

user data byte

The user data bytes are used by the user to record information.

CRC and ECC bytes

The CRC (Cyclic Redundancy check) byte and the ECC (Error Correct-ion Code) byte are used in an Error detection and correction system to Correct erroneous data. The ECC is a Reed-Solomon code with a rank (hierarchy) of 16.

Resynchronization byte

The resync byte is used to resynchronize the drive after a large defect in the data field. It has a length of 9 bits and is of the form:

100010001

the contents and positions thereof in the data field are as follows. The resynchronization field is inserted between bytes A15n and A15+1, where 1 ≦ n ≦ 39.

Buffer field

The length of the buffer field is 108 channel bits.

Except for the resynchronization byte, each 8-bit byte in the data field and the three address fields is converted to channel bits on the disk as per fig. 100A and 100B. All other fields in the sector are represented by channel bits as specified above. The recording Code used to record all data in the information area on the disc is the Group-Code (GCR 8/9).

In FIG. 97, write data for low-volume 128M (low-density) is decoded using RLL2, 7 encoder/decoder (ENDEC) 7-502. In the high capacity, 256M (high density) mode, GCR encoder/decoder (ENDEC) 7-504 is used. The write pulse generators 7-506 generate pulses with a pulse width of 86ns, the write power of which for the low capacity mode varies from 7.0mW to 8.5mW from the inner area to the outer area. For the high capacity mode, the write pulse generator 7-507 reduces the pulse width to 28ns, but the write power is increased from the inner area to the outer area to from 9.0mW to 10.0 mW. The selection circuit 7-509 connects either one of the pulse generators 7-506 or 7-507 to the laser diode driver of the magneto-optical read/write head depending on the state of the applied control bit HC. The control bit HC is equal to zero in the low capacity mode and equal to 1 in the high capacity mode. The appropriate output is selected to drive the laser diode driver. The write clock is generated by the frequency synthesizer of the data splitter 7-508. The frequency is set to 11.6MHz for the low capacity mode and 10.59MHz to 15.95MHz for the high capacity mode from the inner zone to the outer zone.

During playback, the preamplifiers 7-510 input by the photodiodes in the magneto-optical read/write head can be selected for either the sum mode (A + B) or the difference mode (A-B). For sum mode, the preamplifier 7-510 reads the change in reflection due to the pre-formatted pits. These pits are printed with RLL2, 7 code, which identifies the sector marks, VFO fields and track sector data. 512 user bytes of data are recorded in each pre-formatted sector. There are 10000 tracks, which are divided into 25 sectors, and 128Mbytes of data is shared for the low capacity mode. In the high capacity mode, the disc is formatted with GCR code. There are 40 sectors in the inner region (i.e., region 1) and the number of sectors gradually increases to 60 sectors in the outer region (i.e., region 21). 512 bytes of user data, for a total of 256Mbytes of data, are recorded in each sector.

Data written in the RLL2, 7 mode is also recorded in the form of pits. When the pits are read out in the difference mode (a-B), the waveform presented at the preamplifier output and the preformatted pits when read in the sum mode (a + B) are the same. This signal only needs to be differentiated once by the dv/dt amplifier 7-512. The pulse approximately corresponding to the center of each pit is generated by means of digitizing the nominal output (VNOMP, VNOM N) of the programmable filter. For the low capacity mode, the filter cutoff frequency is set to 5.4MHz in response to the HC control bit. The filtered signal is digitized and passed through glitch (de-glitch) logic 7-518. The resulting signal, known as HYSTOUT (hysteresis), is sent to a data splitter 7-508. The signal is also coupled to the system controller for detecting sector markers. In response to the HC control bit, the plotter of the PLO of the frequency synthesizer in data separator 7-508 is set to 3 and the synthesizer is set to 11.6 MHz. In synchronization, the data is the same as the data originally encoded by RLL ENDEC 7-502. This data is coupled to RLL ENDEC 7-502 for decoding and then sent to the data bus for utilization.

In the high capacity mode, the differential mode of the preamplifier is selected. The playback signal appearing at the preamplifier output is in the form of NR2 (non return to zero), which requires both edges to be detected. This is achieved by differentiating twice by the dv/dt amplifier and by a differentiator in the programmable filter chip 7-514 after the AGC amplifier 7-516. The differentiator, high frequency cutoff filter and equalizer on chips 7-514 are enabled by the HC control bit. The cut-off frequency of the filter is adjusted according to zone identification bits (zone bits) imposed on the chip 7-514 (in the low capacity mode the differentiator and equalizer in the chip 7-514 are not used). The output signals (VDIFF P, VDIFF N) from the chips 7-514 are digitized and de-faked in the de-faking logic 7-518. The circuit suppresses noise at low signal levels. The threshold value is set by the HYST control signal applied to the demosaicing logic 7-518. The DATA P output is input to the DATA separator. In response to the HC control bit, the PLO multiplier-divider is set to 2 and the synthesizer is also set to the appropriate frequency determined by the application area number bits provided from the system controller. The cut-off frequency of the programmable filter also depends on the region bit, but only in the high capacity mode. The synchronization data is identical to the original GCR encoded data. This data is coupled to GCR ENDEC 7-504 for decoding and then to a data bus for use. The entire read function is shared between the low capacity and high capacity modes.

RLL2, 7ENDEC7-502 and write pulse generators 7-506 are represented in FIG. 94 by write encoders 7-416 and read decoders 7-426. GCR ENDEC 7-504 and write pulse generator 7-507 are represented in FIG. 94 by write encoders 7-418 and read decoders 7-428. The selection circuit 7-509 in fig. 94 is represented by a switch 7-422. In FIG. 94, the internal control of the ENEDCs 7-502 and 7-504, which alternately enable the ENDECs 7-502 and 7-504 according to the HC control bits, is represented by switches 7-424. The pre-amplifier 7-510, the amplifier 7-512, the AGC amplifier 7-516, the chip 7-514, the debounce logic circuit 7-518 and the data separator 7-508 are used in both high capacity and low capacity modes. Thus, they are represented in part by both read decoders 7-426 and read decoders 7-428.

Mechanical isolator

Referring now to fig. 120 and 121, two embodiments of the mechanical isolator of the present invention are shown, designated by reference numerals 9-10 and 9-12, respectively. The mechanical isolators 9-10 and 9-12 are ideal for use in optical drives such as CD discs, laser discs or magneto-optical players/recorders. However, the mechanical isolators 9-10 and 9-12 are also applicable to any similar system. Two embodiments of the invention are envisioned: the first embodiment 9-10 is shown in fig. 120 and the second embodiment 9-12 is shown in fig. 121. The mechanical isolator 9-12 has compression ribs 9-14 to absorb the compression of the present invention. Mechanical isolators 9-10, 9-12 may be mounted at the ends of the pole shoe members 9-16. The stoppers 9-18 serve to prevent the moving disc holder from hitting solid metal. The shoes 9-20 are mounted at one end of the pole pieces 9-16 and help provide vibration isolation and help accommodate thermal expansion.

The mechanical isolators 9-10, 9-12 should be made of a material that exhibits minimal creep, such as silicone rubber, polyurethane or cast plastic. In this case the material MS40G 14H-4RED was chosen.

It will be appreciated by those skilled in the art that the mechanical isolators 9-10 and 9-12 are alternative embodiments suitable for particular applications, as they each generally comprise first means for mitigating the effects of unwanted mechanical forces on the movable disk drive component, and second means for supporting the first means between the component and the source of unwanted mechanical forces, thereby providing mechanical isolation of the component. In each of the spacers 9-10, 9-12, the first means is realized as a shock-absorbing or impact-blocking element 9-18, which may comprise at least one compression rib 9-14. Several compression ribs 9-14 are shown in fig. 121 to absorb the compression force. The second means preferably comprises a housing as shown in figures 120 and 121 which is adapted to be mounted on the ends of the pole pieces 9-16. The first means is made of a material exhibiting minimal creep, preferably selected from the group consisting of silicone rubber, polyurethane, and injection molded plastic. The mechanical isolators 9-10, 9-12 and the first means provide impact absorption and mechanical isolation for preventing the movable carriage from striking a solid surface in the form of impact stops 9-18.

Firmware

Appendix A, attached and incorporated by reference herein, includes hex executable code in firmware. The following sections provide detailed functional and structural definitions of hexadecimal code in appendix a. As described in more detail in the following sections, the 80C188 firmware controls the SCSI interface to or from the host to the SCSI interface. The firmware includes code necessary for the interface with the digital signal processor to enable and complete reading, writing and searching, and also includes a driver command module directly interfaced with a plurality of hardware components.

The firmware includes a core and a SCSI monitor task module. The core and the SCSI monitor task module receive SCSI commands from the host. Since these functions do not require media access, the SCSI monitor module can perform these functions as well as direct a lower level task monitor module to perform these functions. For all other functions, the SCSI monitor module requests the driver task layer for the function to execute and waits for a reply from the driver task layer to indicate that the function is complete.

The driver task layer alternately directs any of several modules to perform the required functions. These modules include: the device comprises a drive command module, a drive maintenance module and a format module. The modules are mutually matched,

These functions are accomplished with a fault management module, an exception handling module, and a digital signal processor.

The drive command module directs the digital signal processor or directs the hardware device itself to control the motion of the hardware device. The format module directs the drive command module to format the media. All defects found in the medium during processing are stored in a defect management module and may also be placed in random access memory.

Feedback from the digital signal processor and hardware devices appears in the form of command execution signals and is passed to the driver attention module interrupt. In addition, the drive attention module allows other modules to record attention so that when an interrupt occurs, the recording module receives notification of the interrupt.

When a drive attention interrupt signals a fault or exception, the drive attention module retrieves information related to the status of the media and drive from the drive command module and the exception handling module uses the information to attempt to recover from the fault. Instead of returning to the drive task layer and SCSI interface with the host via a failure state, the exception handling module may direct the drive control module or format module to try the function again. The drive attention module may direct multiple retries before failing and returning to the drive task layer in the failed state. Various drive functions, such as look-up, exit, magnetic bias, and temperature, may be exception-handling. In addition to the fault condition, a detection code qualifier is sent to the drive task layer. The detection code qualifier specifies exactly the fault that occurred, causing the SCSI interface to specify the information to the host. Those skilled in the art will recognize that: the exception handling module may be included within the drive attention module.

In operation with respect to magnetic biasing, the bias magnet is turned on and the bias is monitored by a series analog-to-digital converter. The bias is monitored until it is brought within the desired range, or until 5 milliseconds have elapsed, in which case the fault condition is passed to the drive task layer.

In operation, the temperature of the motherboard is monitored. The properties of the medium may change due to the temperature increase. At high information densities, the constant density writing beam creates a cover layer over the recorded information as a function of temperature and media characteristics. Thus, by monitoring the ambient temperature in the room, the firmware can adjust the power of the write beam according to the temperature sensitive characteristics of the medium, i.e. recalibration can be achieved.

The properties of the writing beam also vary with position on the medium. The medium is divided into a plurality of concentric zones. The number of areas is determined by the density of information recorded on the medium. For double density recording the medium is divided into 16 zones. For quad-density recording, the medium is divided into 32 or 34 zones. The power of the writing beam varies approximately linearly between the zones.

In addition, the characteristics of the write beam and the read beam vary with the medium itself. Different media manufactured by different manufacturers have different optical characteristics. The identification code is read from the medium when the medium is at the desired rotational speed. The optical characteristic information related to the medium is added to a non-volatile random access memory (NVRAM) at the same time as the drive is manufactured, and information corresponding to the current medium is added to a digital signal processor when the identification code is read out. If the identification code cannot be read, the power of the read beam is set to a low power and slowly increased until the identification code becomes readable.

In monitoring and varying the power of the read and write beams, a number of digital-to-analog converters may be used. The monitoring and variation of power may include one or more digital-to-analog converters.

The invention also includes a method of changing the spin rate of a storage medium from an initial spin rate to a desired spin rate having an allowable lower limit and an allowable upper limit. The method comprises the following steps: applying a force to the storage medium to change the rotation rate of the storage medium from an initial rotation rate to a first upper limit, the first upper limit being between the initial rotation rate and a desired rotation rate, generating a first signal when the rotation rate of the storage medium exceeds the first upper limit during the step of applying the force, generating a second signal when the rotation rate of the storage medium exceeds an allowable lower limit during the step of applying the force and after the step of generating the first signal, and then terminating the force applied to the storage medium. In a particular embodiment of the method, the defining step may include setting a second upper limit on an allowable upper limit of the desired rotation rate, setting a lower limit at an allowable lower limit of the desired rotation rate, and terminating the application of the force to the storage medium when the rotation rate of the storage medium is greater than the lower limit. The allowable upper limit of the required rotation rate is preferably larger than the allowable lower limit of the required rotation rate. In addition, the allowable upper limit is greater than fifty percent of the desired rotation rate and the allowable lower limit is less than fifty percent of the desired rotation rate.

Another method according to the invention comprises changing the rotation rate of the storage medium from an initial rotation rate to a desired rotation rate having a first allowed limit and a second allowed limit. The method comprises the following steps: applying a force to the storage medium to change the rate of rotation of the storage medium from an initial rate of rotation to a first intermediate limit between the initial rate of rotation and a desired rate of rotation, generating a first signal when the rate of rotation of the storage medium passes the first intermediate limit during the step of applying the force, generating a second signal when the rate of rotation of the storage medium passes a first allowable limit after the step of applying the force and generating the first signal, and then terminating the force applied to the storage medium. In a particular implementation of the method, the defining step further comprises: the first operational limit is set at a first allowable limit for the desired rate of rotation, the second operational limit is set at a second allowable limit for the desired rate of rotation, and the force applied to the storage medium is terminated when the rate of rotation of the storage medium is between the two operational limits. The difference between the first operating limit and the desired spin rate is preferably fifty percent of the desired spin rate, and the difference between the second operating limit and the desired spin rate is also preferably fifty percent of the desired spin rate.

When the spindle motor rotates from a stationary or slow rotation state, the drive command module writes an upper rotational speed limit into the digital signal processor. The upper limit is slower than desired. When the spindle speed exceeds the upper limit, the digital signal processor generates an interrupt. The drive command module writes another upper limit to the digital signal processor. The new upper limit is lower than the allowable lower limit for normal operation. When the spindle speed exceeds the new upper limit, the last upper and lower limits are written into the digital signal processor. These two final limits determine the working range of the spindle speed and can be about 1% offset.

During initial spin-up, the media is first rotated to the lowest rotational speed for proper operation of the drive, according to the process described above. At this point, the identification code is read. If the identification code cannot be read, the medium is rotated at the next highest rotational speed relative to normal operation and an attempt is made to read the identification code again. This process is repeated until the identification code cannot be read at the highest speed of normal operation (in which case a malfunction occurs), or is successfully read.

There may be several types of memory storage in the drive. First, there may be a flash Electrically Erasable Programmable Read Only Memory (EEPROM). Implementations of the present invention may include 256 kbytes of flash EEPROM. Second, there may be SRAM, and the implementation of the present invention may include 256K bytes of SRAM. Finally, there may be non-volatile random access memory NVRAM, and the implementation of the present invention may include 2K bytes of NVRAM.

The information part in the following sections is represented by "TBD": disc Drive SCSI Firmware, Drive Exceptions, Read Ahead Cache, and Disc Drive Firmware Architecture, indicate that the execution of a module is not decided in advance, and that some parameters (not primary functions or operations) relating to optimization or the surrounding environment need to be decided. It is also shown that some modules become unnecessary according to the execution of other modules as represented in the executable code in appendix a and as described in the following paragraphs. Each "TBD" case is a design consideration that does not affect the practice of the invention by those skilled in the art. A module whose execution process is not decided in advance may be executed in the following manner.

While the medium is being formatted, the defect management module will create a defect table and write the defect table to a portion of the medium. When a previously formatted medium is loaded into the drive, the defect management module will read the defect table from the medium and load it into memory. The defect management module can consult the defect table to ensure that the digital signal processor or hardware device does not directly attempt to access the defective portion of the medium.

Command SEEK COMP ON and SEEK COMP OFF activates and deactivates, respectively, an algorithm that optimizes SEEK time to a point ON the media. The command may directly generate the algorithm, may set a flag to indicate another module to generate the algorithm, or may generate an interrupt directing another module to generate the algorithm. In addition, other implementations will be known to those skilled in the art.

The commands NORMAL PLL BWIDTH, HGH PLL BWIDTH, ANDVHGHPLL BWIDTH may read values from memory and store the values in the read chip memory. Alternatively, the command may calculate a value and store the value in the read chip memory.

A similar implementation may be had for 2X Write Power Calibration and 4X Write Power Cali-corporation. During manufacture, the value from the digital-to-analog converter controls the write power of the transmission energy source. So that the write power can be measured for different digital-to-analog converter values and the detection value can be determined. These detection values may be stored in a memory of the drive. In use of the drive, the value from the digital-to-analog converter controls the write power of the transmission energy source and the detected value is measured. These detection values are compared to stored detection values until they are within allowable limits. More than one digital-to-analog converter may be used for this process. In addition, the process may calibrate the write power according to the temperature, as described above.

As described above, recalibration may be performed based on temperature, media type, and other factors. In addition, recalibration of the servomechanism may be accomplished by directing the digital signal processor to set the servomechanism according to certain variable factors.

The manufacturing requirements show that: the above information determined at the time of manufacture of the drive is recorded and stored in a memory associated with the drive.

The Front Panel Eject Request function generates a drive attention interrupt. The Front panel object Request function can determine the driving status and, based on its information, cause the current command to complete or stop the command.

The firmware performance result is an optimization result. When a command is queued in firmware, the modules in firmware will determine certain criteria, including: the time to complete the present command, the distance between the present position of the carriage and the position required by the queued command, the rotational speed of the media, and the circumferential position of the carriage relative to the position required by the queued command. From this and other information, the firmware determines the time to move the carriage at that time relative to the position required by the queued command and the circumferential position of the carriage. If the carriage is required to wait some time for the media to rotate to the position required to go to the carriage for the queued command, the firmware will direct the drive to continue processing the present command until there is little or no waiting time after moving the carriage.

The SCSI Eject Command may be disabled by an optical switch, which may be implemented in the form of a DIP switch.

As performed in part by the Pown-on Self Test, External ENDECtest and GlueLogic Test include read and write information under certain conditions to ensure proper functional execution of the External ENDEC and GlueLogic.

The following paragraphs describe the system firmware in more detail. The specification describes the best mode presently contemplated for carrying out the present invention as of the filing date of the present application. As known to those skilled in the art, the following sections include certain defined regions identified as "TBD" indicating where the above-described implementation will apply.

Disk drive SCSI firmware

The purpose of the following paragraphs is to illustrate the functional characteristics of the SCSI firmware for Jupiter-15.25 inch MO disk drives. The SCSI firmware is the controller code portion executed by the 80C188 CPU. This description does not account for the functional nature of the controller code executed by the DSP.

Firmware Requirements for this object of the present invention that have been utilized are included in this discussion and can be found under the subheading of a.firmware Requirements, below. The following related documents are cited herein for reference: 1) cirrus Logic CL-SM330, Optical Disk ENDEC/ECC, April1991, 2) Cirrus Logic CL-SM331, SCSI Optical Disk Controller, April1991, 3) MOST Manufacturing, Inc., 1, 7 ENDEC/FORMATTER, August 2, 1994, 4) MOST Manufacturing-training, Inc., Jupiter-1 Product Specification, September15, 1994, and 5) MOST Manufacturing, Inc., 80C188/TMS320C5XCommunications, Rev. XH, August 25, 1994.

SCSI SUPPORT: SCSI Commands (SCSI Commands): SCSI Commands supported by Jupiter firmware are listed in tables 1-5 below. In addition to listing the supported command set, when a 1X, CCW, O-ROM or P-ROM media is installed, the commands identified in tables 1-5 are invalid when issued to a drive. The P-ROM column indicates the commands issued for the block that is in the read-only group of the P-ROM media. Table 1-group 0, 6-byte command code command name IX CCW P-ROM00h sense Unit preparation 01h zeroing Unit 03h request sense 04h Format Unit NO TBD TBD07h Re-specify Block NO TBD No08h read 09h Erase 0Ah write No0Bh look-up 0Ch Erase No No12h Inquiry 15h way select 16h Retention Unit 17h Release Unit 1h Start stop Unit 1Ch receive diagnose 1Dh Send diagnose 1Eh prevent allow media from excluding Table 2-group 1, 10-byte command code command name 1x CCW P-ROM25h read Capacity 28h read 2Ah write No2Bh look-up 2Ch Erase No2Eh write and verify No2Fh check 35h synchronize cache No36h Lock unlock cache 37h read Defect data 3Bh write buffer 3Ch Read buffer 3Eh Long-time read 3Fh Long-time write No Table 3-group 2, 10-byte Command code Command name 1x CCW P-ROM40h Change definition 41h write identical content No55h mode selection 5Ah mode detection Table 4-group 5, 12-byte Command code Command name 1x CCW P-ROMA8h read Aah write No NoAch Erase No NoAEh write and check No NoAfh check B7h read Defect data Table 5-group 7, provider unique Command code Command name 1x CW P-ROME0h Peek/Poke CPU memory

E1h read drive attention count

E5h read track buffer

E7h read/write ESDI

Read specially for E8h

EAh special writing No

ECh Absolute Erase No No No

FAh manufacturing test

TBD cleaning of optical components

As referred to herein, a full description of the supported SCSI command set is provided in Jupiter-1Product Specification Se-connection 9, SCSISupport. It is important to note that: jupiter firmware will not support the Log Select and Log Sense commands.

SCSI Messages (SCSI information): the SCSI information supported by Jupiter firmware is listed in Table 6 below.

TABLE 6 SCSI information supported

Code information name

00h Command completion

01h extension information

00 h-modified data pointer

01 h-synchronous data transfer request

02h save data pointer

03h resume pointer

04h break off

05h starter detection error

06h abort

07h message revocation

08h off

09h information parity error checking

0Ah Link Command completion

0Bh Link Command complete (with sign)

0Ch bus device reset

0Eh clear queue

80h + mark

It is important to note that: will not support Terminate 1/0 Message.

SCSI Mode Pages SCSI Mode Page: the Mode Pages supported by Jupiter firmware are listed in table 7.

TABLE 7 supported modes Page

Code information name

00h cell parameter

01h read/write error recovery parameter

02h disconnect/reconnect control parameter

07h check error recovery parameter

08h cache parameter pages

Parameters for 0Bh supported media types

0Ch labeling and differentiation parameters

30h vendor uniqueness parameter

3Bh MOST engineering feature control

3Ch error retry limit parameter

3Dh vendor's uniqueness query data page

3Eh vendor unique manufacturing data sheet

The Jupiter firmware will not support save pages. It is important to note that: ModePages 20h and 21h will not be supported.

Reset: the Reset will be performed by the drive according to a SCSI Bus Reset, an Autochanger Reset, or a 12V power failure. The functions performed by the driver for each of these types of resets are described below.

(SCSI Bus Reset): when the SCSI Bus RESET signal is set, an INT3 is generated for 80C 188. The use of INT3 will allow the driver to respond flexibly to resets such as Hard or SoftReset. However, the use of INT3 assumes: the interrupt vector for INT3 is still valid. If the firmware has accidentally overwritten that entry of the Interrupt Vector Table (IVT), the reset will not restore the drive and the user will take the option of simply turning off the power to the drive and then turning it on again.

INT3(Interrupt Serial route (ISR) (Interrupt service subroutine) must be determined by the selection switch whether a Hard or Soft Reset must be performed.

Hard SCSI Reset: when the SCSI Bus Reset is detected by the driver and the HardReset (Hard Reset) select switch is turned on (denoted as Hard Reset), the driver will: (1) no attempt is made to process any command in progress; (2) no data in buffer ram (i.e., in Wirte Cache) is written to the media; (3) no SCSI device condition is saved; (4) removing all pending commands from the queue; (5) performing the following steps in the Powerup Sequence for Hard Reset; (6) setting the value of each Mode Pages to a default value; (7) the cell attention condition is set.

There is no hardware reset line to reset the various chips on the board and the firmware must use the software reset feature of a chip having such a feature. Firmware must also initialize registers as described in the specification of hard and soft resets for chips on pages 36 and 47 of the Cirrus Logic SM330 Manual and the Cirruslogic SM331 Manual.

Soft SCSI Reset (SCSI Soft Reset): when the SCSI Bus Reset is detected by the driver and the Hard Reset select switch is disabled (denoted as Soft Reset), the driver will: (1) no attempt is made to process various commands in progress; (2) any data in the Bu-buffer RAM (i.e., in the Wirte Cache) is not written to the media; (3) no SCSI device condition is saved; (4) removing all pending commands from the queue; (5) performing the following steps in Powerup Sequence for SoftSeset; (6) setting the value of each ModePages to a default value; (7) the cell attention condition is set.

Autochanger Reset: if the Autochanger sets an auto-ochrgerreset in the power supply program, the drive must: (1) ignore autocohanger EJECT, and (2) wait for the autocohanger RESET to be released before performing SCSI initialization. The Autoch-anger can set Autochanger RESET at any time to change the SCSIID of the drive.

12V Power Failure (12V Power Failure): when the 12V power supply subsides below (TBD), a hardware reset is generated for 80C188, SM330, SM331, and RLL (1, 7) External ENDEC. Once ENDEC is Reset, this will drive the Servo Reset to the initialized state, which will in turn Reset the DSP and the servomechanism.

Uncleavable Conditions (non-erasable state): the unclearable condition occurs when the drive detects a fatal error (listed in table 8 below). The non-clear state forces the drive to respond to the Request SenseCommand with the Sense Key of HARDWARE ERROR, the ERROR Code of INTERNALCONTROLER ERROR, and the Additional SenseCommand Qualifier specific to ERRORs. The Send Diagnostic SC-SI command may remove the source of the hardware error and clear the non-clear state. If the SendDiagnostic command fails to successfully clear the hardware error, a SCSIBUS reset will be required to clear the non-clear state. A SCSI Bus Reset received during the time the driver has a non-purgeable state will force the driver to perform a Hard Reset and perform a full set of its diagnostics. In this manner, any fatal error discovered during the performance of one operation will first cause the current operation to abort and then prevent the drive from attempting to change media during a subsequent operation.

TABLE 8 Severe errors

Description of symbol names

ASCQ _ NO _ TCS _ AVAIL No-valid information Block

error/SFP during reading of control track for ASCQ _ CZ _ RD _ ERR

ASCQ _ UNDEF _ UNIT _ ATTN undefined cell attention

ASCQ _ CPU _ FAILURE CPU FAILURE

ASCQ _ BUFF _ RAM _ FAILURE buffer RAM FAIL

ASCQ _ SM330_ FAILURE Cirrus Logic SM330 FAILURE

ASCQ _ SM331_ FAILURE Cirrus Logic SM331 Fault

ASCQ _ WCS1_ FAILURE Cirrus Logic write control storage test #1

Fault of

ASCQ _ WCS2_ FAILURE Cirrus Logic write control storage test #2

Fault of

ASCQ _ EXT _ ENDEC _ FAILURE RLL (1, 7) ENDEC Fault

ASCQ _ UNDEF _ REALLOC undetermined real address

FAILURE of ASCQ _ LOAD _ SEQ _ FAILURE during Add Format sequencer

Attention to excessive driving of ASCQ _ TOO _ MANY _ ATTNS

ASCQ _ DSP _ CMD _ CHECKSUM DSP instruction checking and failure

ASCQ _ LASER _ FAIL LASER power control failure

ASCQ _ HRDWR _ FAIL hardware Fault

UNKNOWN interrupts of ASCQ _ UNKNOWN _ READ _ ERROR during READ

ASCQ _ UNKNOWN _ WRITE _ ERROR UNKNOWN interruption during WRITE

ASCQ _ DRV _ INIT _ FAIL driver initialization fault

ASCQ _ INV _ OP invalidate DSP instruction

ASCQ _ RELOC _ LIMIT _ RCHD attempts to use excessive reallocation in the same sector

ASCQ _ DRV _ SELECT _ FAIL drive SELECT Fault

ASCQ _ MAGNET _ FAILED bias fault

Multi-initiator Support: support for multiple boot-up procedures will be provided by the Jupit-er firmware. A queue pair disconnect instruction for an incoming request is maintained by firmware for sequential requests from multiple boot programs. Initially the Tagged queue command is not supported. However, firmware design does not preclude the later addition of this feature.

When a non-media access command is received while the drive is processing a disconnected media access command, the firmware must be able to use the new command while the connection is maintained. The exact method of providing this capability is not certain. The commands supported in this non-disconnect mode are listed in table 9 below.

TABLE 9 non-disconnect SCSI Command

Code information name

00h test cell preparation

03h request detection

12h query

16h reservation unit

17h Release Unit

1Ah mode detection

1Ch reception diagnostics

1Eh prevents/allows media movement

25h read capacity

5Ah mode detection

E0h Peer/Poke CPU memory

E1h read drive attention count

E5h read track buffer

E7h read/write ESDI

SCSI REQ/ACK Response: the Cirrus SM331 chip only receives the first six bytes of the SCSI Co-mmandedscriptor Block (CDB) and then generates an interrupt. The firmware must use Programmed I/O (P10) to transfer all remaining bytes. If the firmware is delayed, the command stays between the sixth and seventh bytes. The drive latency in response to a cirrus scsi interrupt must be in the following range: 20 mus is a suitable number, 40 mus is a bad time period, 150 mus is not allowed.

SCSI Inquiry Command: the driver will respond to the scsiinqinquiry Command which returns the firmware revision level (version level) of the SCSI firmware and DSP firmware, the checksum of the SCSI firmware flash memory PROM and DSP PROM, and a bit indicating whether the Hard Reset or Soft Reset function is being supported.

INITIALIZATION: diagnoslics (diagnosis): the diagnostics performed by the driver are performed during the Power-On SelfTest (POST) according to SCSI Send diagnostic-nonstick Command or when the driver detects that a serial feature interface cable is connected.

Power-On Self Test (POST): during POST, the driver will perform the tests listed below. A detailed description of each test is provided below b.post Definition at the beginning of the following paragraph.

These tests include: 1)80C188 Register and Flag Test, 2) CPRURAM Test, 3)80C188 Interrupt Vector Test, 4) ROM Checksum Test, 5) SM331 Register Test, 6) SM331 sequence Test, 7) SM330 ENDEC Test, 8) External ENDEC Test, 9) Glue Logic Test, 10) Buffer RAM Test, 11) DSP POST, and 12) Bias Magnettest.

If it is determined that some Buffer RAM is bad when the Buffer RAM Test is executed, the drive is considered unusable. The driver responds to the SCSI command but only reports a hardware failure. The BufferRAM test will be completed in two phases. The first phase only tests the 64 kbytes of the buffer. During this time, the drive can cause Busy to respond to SCSI commands. After driver initialization, the remainder of the Buffer RAM will be tested in a background mode. (see Powerup Sequence section below for details). If a portion of the Buff-er RAM is determined to be bad during background testing, the drive will declare that a non-clear state exists.

Send Diagnostic Command: when the driver receives a SCSI SendDiagnostic Command, the driver will perform the following diagnostics (1) ROM Chenksum Test, (2) SM331 Sequencer Test, (3) SM331 SCSIInterface Test, (4) SM330 ENDECtest, (5) External ENDEC Te-st, (6) Glue Logic Test, (7) Buffer RAM Test, and (8) Bias Mag-net Test. As described above, each test performed according to the Send Diagnostic Command will be the same as the test performed by the driver when the POST is executed.

Serial Diagnostic Interface: when the driver powers up, it will perform the diagnostics numbers 1 to 4 in the Power-On Self Test (POST) section above and then check if a serial interface cable is being connected. If no cable is detected, the drive continues to execute Post; if a cable is detected, the driver will interrupt the execution of the POST and prepare to receive diagnostic commands through the serial diagnostic interface. Diagnostic commands and their formats are beyond the scope of the present discussion.

Chip Initialization (Chip Initialization): SM330 initiation: this section describes the initialization of Cirrus Logic 330. The mnemonic for the SM330register is listed in table 31 provided by the c.sm330registers section below. The steps taken to initialize the Cirrus LogicSM330 are listed below:

1) The current value of the General Purpose Output (EDC _ GPO) register is retained.

2) The CHIP is RESET by setting the EPC CHIP RESET, EDCOPER HALT and EDC ERROR RESET fields in EDC _ CFG _ REG 1.

3) EDC _ VU _ PTR _ SRC _ MODE, EDC _130MM _ MODE, and EDC _1_ speed fields are set in EDC _ CFG _ REG 2.

4) The EDC _ SPT register is set to the default number of sectors PER track, SECT _ PER _ TRK _ RLL _1X _512_ 1.

5) EDC _ SM _ WIN _ POS, EDC _ SMM (shift left 3) and EDC _ SMs regions are set in the EDC _ SMC register.

6) The EDC _ RMC record is set to a default value of 2.

7) The EDC _ ID _ FLD _ SYN _ CTL register is set to a default value of 2 out of 3IDs and a default value of 9 out of 12Data Sync Marks.

8) The EDC _ WIN _ CTL record is initialized to Ox 00.

9) The chip is brought out of reset by writing Ox00 to the EDC _ CFG _ REG1 register.

10) The value retained by the EDC _ GPO register is written back to the register.

11) The EDC _ CFG _ REG3 register is initialized to Ox 00.

12) All chip interrupts are cleared by writing OXFF to the EDC _ INT _ STAT and EDC _ MED _ ERR _ STAT registers.

13) All chip interrupts are blocked by writing 0x00 into the EDC _ INT _ EN _ REG and EDC _ MED _ ERR _ EN registers.

14) The sequencer SYNC byte count is initialized by writing 40 into the SF _ SYNC _ DYTE _ CNT _ LMT register.

15) The Data buffer Address pointer is initialized to zero (EDC _ DAT _ BUF _ ADR _ L, EDC _ DAT _ BUF _ ADR _ M, and EDC _ DAT _ BUF _ ADR _ H records).

16) The EDC _ TOF _ WIN _ CTL register is cleared to 0x 00.

17) The EDC _ SM _ ALPC _ LEN register is cleared to 0x 00.

18) The EDC _ PLL _ LOCK _ CTL register is initialized to 0xE 0.

19) The EDC _ PLL _ RELOCK _ CTL register is cleared to 0x 00.

20) The EDC _ LFLD _ WIN _ CTL register is cleared to 0x 00.

21) ECC Corrector RAM addresses 0x00 and 0x01 are set to zero.

22) ECC Corrector RAM addresses 0x0F and 0x016 are set to zero.

23) ECC Corrector RAM addresses 0x20 and 0x027 are set to zero.

24) The ECC CorrectorRAM threshold for sector correction is initialized to 0x 0F.

25) The ECC Corrector RAM threshold for cross correction is initialized to 0x 03.

26) The EDC _ GPO register is initialized by clearing the DSP _ DIR, BIAS _ EN, BIAS _ E _ W, SCLK, SDO, and MIRROR _ TX _ bits.

27) The LED for the driver is switched off.

SM331 initiation: this section describes the initialization of Cirrus Logic SM 331. The memory notation for the SM331 register is listed in table 32 provided in the sm331 Registers section below.

The initialization of the SM331 includes the initialization of the read select switch and portions of the SCSI, Buffer Manag-er, and Format sequence of the chip. To read the tri-state select switch on the SCSI Bus, the firmware performs the following steps:

1) SM331 is placed on RESET by setting BM _ SW _ RESET in the BM _ MODE _ CTL register.

2) SM331 is taken out of RESET by clearing BM _ SW _ RESET in the BM _ MODE _ CTL register.

3) The SF _ LOCAL _ HINT _ EN, SF _ LOCAL _ DINT _ EN, and SF _ SCSI _ ID _4047H fields are set in the SF _ MODE _ CTL register.

4) The BM _ MOE _ DISABLE bit is set in the BM _ MODE _ CTL register.

5) The BM _ SCHED _ DATA record is read twice. (the first read causes an effective transfer of data from the buffer fetched during the second read).

6) The read value is supplemented and retained as the value of the option switch.

7) The BM _ MOE _ DISABLE bit is cleared in the BM _ MODE _ CTL register.

The steps taken to initialize the SCSI portion of SM331 are listed below:

1) the SCSI ID for the drive is read out of the 20-pin connector through the GLIC _ JB _ INP _ REG register and placed in the variable target-ID.

2) SCSI Parity Enable SCSI Parity allows the option to be read out of the 20-pin connector through the GLIC _ JB _ INP _ REG register.

3) The SCSI _ MODE _ CTL register established with the SCSI ID, SCSI partition Enable and CLK _ PRESCALE fields of the driver is set.

4) The phase control register SCSI _ PHA _ CTL is cleared with 0x 00.

5) The synchronous control register SCSI _ SYNC _ CTL is initialized with the value (0x0F-1) · 0x 10.

6) BufferManagerF1F0 is cleared by writing 0x10 into the BM _ STAT _ CTL register.

7) The BM SCSI _ DATA _2T and BM _ DRAM _ BURST _ EN fields are set in a buffer manager Control register BM _ STAT _ CTL.

8) The Buffer Manager Transfer control register BM _ XFER _ CTL is initialized to 0x 00.

9) The SCSI Reselection ID register SCSI _ SEL _ REG is set to the driver's SCSIID.

10) SCSI _ RESET, SCSI _ ATTN, SCSI _ OFST _ OVERRVN, SCSI _ BUS _ FREE, SCSI _ BFR _ PTY _ ERR, SCSI _ BUS _ PTY _ ERR bits are set in SCSISstatus register SCSI _ STAT _ 1.

11) The SCSI _ STAT _2 register is initialized to 0 xFF.

12) SCSI interrupts are blocked by writing 0x00 to the SCSI _ NT _ EN _2 register.

The steps taken to initialize the Buffer Manager part of SM331 are as follows:

1) the BM _ SCSI _ ATA _2T and BM _ DRAM _ BURST _ EN fields are set in the buffer manager Control register BM _ TAT _ TL.

2) The Buffer Manager Transfer control register BM _ XFER _ CTL is initialized to 0x 00.

3) BM _ DRAM, BM _256K _ RAM, BM _ PTY _ EN and BM _ NO _ WS fields are set in the Buffer Manager Mode Control register BM _ MODE _ CTL.

4) DRAM timing is initialized in BM _ TIME _ CTL and BM _ DRAM _ REF _ PER registers.

5) The SIZE of the Buffer RAM is encoded into the BM _ BUFF _ SIZE register.

6) Disk Address Pointer is initialized to 0x000000 in the BM _ DAPL, BM _ DAPM, and BM _ DAPH registers.

7) The Host Address Pointer is initialized to 0x000000 in the BM _ HAPL, BM _ HAPM, and BM _ HAPH registers.

8) Stop Address Pointer is initialized to 0x000000 in BM _ SAPL, BM _ SAPM, and BM _ SAPH registers.

The steps taken to initialize the Format sequence part of SM331 are determined as follows:

1) the Format sequence is stopped by writing 0x1F (stop address) to the sequencing Start Address register SF _ SEQ _ STRT _ ADR.

2) A default sector SIZE of 512 bytes is established in the sector SIZE register SF _ SECT _ SIZE by writing 0x 00.

3) The SYNC BYTE count is initialized by writing X028 to the SF _ SYNC _ BYTE _ CNT _ LMT register.

4) The operation control register SF _ OP _ CTL is initialized by setting the SF _ DATA _ BR _ FLD _ EN field.

5) The BRANCH address register SF _ BRANCH _ ADR is initialized to 0x 00.

6) Sequencer interrupts are blocked by writing 0x00 into the SF _ INT _ EN register.

7) The default Write Control Store (WCS) program is loaded into the Format sequence-cer.

RLL(1，7)External ENDEC Initialization：(TBD)。

Glue Logic IC (GLIC) initiation: the initialization of the GLIC includes the following steps: (1) set the Read Gate override-de bit in the GLIC _ JB _ CTRL _ REG register, and (2) allow all interrupts in the GLIC _ INT _ EN _ REG register.

SCSI Initialization (SCSI Initialization): the SCSI Initialization firmware will use the 20 pin connector as the signal source for the SCSI ID and SCSI partition Enable of the driver. When the cable is connected, the signal will be driven by a "Ju-box" (Ju-box). When the cable is disconnected, the same pin is jumpered to indicate that the SCSIID and SCSI partition Enable are to be used.

The Termination of SCSI Bus in the driver is selected by a selection switch. There will be no firmware interaction required to support SCSI Termination.

Powerup Sequence (power-up Sequence): table 10 below lists the steps of the power up sequence one by one in the order performed. The Power On, Soft Reset and Hard Reset entries mark the execution steps of Power On condition, Soft Reset or Hard Reset described below. If the non-clear state occurs when a Reset is received that generates a SoftReset, the Reset will instead generate a Hard Reset to cause the drive to complete its full diagnostic settings.

Watch 10

Powerhard Soft Specification

On Reset Reset

Y (1) is held by ENDEC for the Servo Reset signal. SCSI (small computer system interface)

The chip does not (cannot) respond to a selection.

Y Y (2)80C188 initialize Peri-

A personal Control Block and an external chip selection switch.

Y Y (3)80C188 block the timer.

Y Y (4)80C188 initializes the interrupt controller.

Y Y (5)80C188 performs a CPU flag test.

Y Y (6)80C188 performs a CPU register ripple test.

At this point, 80C188 checks to see if a full Hard Reset is to be performed or a change called a Firm Reset can be used instead. The Firm Reset will not Reset the DSP. This method saves time by not forcibly unloading the DSP code nor re-initializing all its servo loops without the DSP. The Firm Reset will check for a valid RAM flag (TBD) in the 80C188 CPU memory: the unclonable state does not exist and checks: the DSP can respond appropriately to a Get Status command. If either of these adjustments is not true, the driver will perform a HardReset. The following description is given with the sequence numbers in table 11.

TABLE 11

Power On Hard Firm Soft description

Y Y (7)80C188 External ENDEC reset, set

Servo Reset signal.

Y Y Y (8)80C188 performs a CPURAM test.

Y Y Y (9)80C188 performs a CPU interrupt test.

Y Y Y (10)80C188 initializes the full interrupt vector.

Y Y Y (11)80C188 performs a CPUROM checksum.

Y Y Y (12)80C188 initializes all chips and timers.

Y Y Y (13)80C188 tests Cirrns Logic SM 331. Y Y Y (14)80C188 tests Cirrns Logic SM 330. Y Y Y (15)80C188 test RLL (1, 7) External ENDEC. Y Y Y (16)80C188 performs a Buffer RAM test. Only by

The first 64 kbytes of BufferRAM are tested. Y Y Y (17)80C188 performs a Bias Magnet test. Y (18) system firmware initializes itself (i.e., core initialization). The Y Y Y Y (19) driver initializes the Sense Data structure. The Y Y Y (20) driver initializes the host request block information structure. Interruption of SCSI and Drive affinities by Y Y Y (21)

Is allowed. Y Y Y (22) SCSI interface is initialized and the driver pair is any

SCSI commands have the ability to respond to Busy. Y Y (23)80C188 does not set a Servo Reset. Y Y (24) offload DSP code from SCSI ROM. Y Y Y (25) DSP starting execution and completing a diagnosis

Setting (TBD). Y Y (26)80C1288 request for an address of a Velocity Table

And load the default (low rate table). Y Y (27)80C188 confirmation (TBD): the DSP is running properly.

If not, Sevo Reset is set, Reset and synchronize steps

(23) The treatments were repeated together and tried twice more. Y Y Y (28)80C188 enables all interrupts from GLIC. The Y Y Y Y (29) driver initializes the Mode Page structure. The Y Y Y Y (30) driver initializes the Inquiry Data structure. Y (31) DSP confirmation: the Eject Limit switch is in the correct position. Otherwise notify (TBD)80C188 (TBD). The Y Y Y (32) drive checks the presence of the carriage and spins it up. The Y Y Y (33) DSP is instructed to turn off the focus and tracking loops.

If the DSP reports: when the disc cartridge is initialized to fail, the disc cartridge is reported

Two additional retries are performed before the shelf initialization failure ". Y Y (34) drive implementation of the media type determination described in paragraph 5.1

And (5) determining an algorithm. Type one is determined and media parameters are initialized. Velocity Table of current media contained in Y Y (35) is

Loading into the DSP. Y Y Y (36) drive reads out Defect table and creates Defect Mana-

A get data structure. Starting the Y Y (37) driver to test in background mode

The remainder of the Buffer RAM. Y Y Y (38) SCSI interface forms all work (i.e., it is no longer back to

BUSY back).

DRIVE ATTENTIONS: drive Attention Interrupts: DriveAttention interruption is surfaced: an abnormal state exists within the drive. Interrupts are generated by hardware attached to the GlueLogic IC (GLIC) or by a DSP. The combined form of the DSP interrupt forming the interrupt (on INT 2) is sent through the GLIC to 80C 188. The following paragraphs describe interrupts generated by the DSP. The GLIC Interrupts section describes Interrupts generated by other hardware connected to the GLIC. The firmware can determine the source of the interrupt by analyzing the GLICInteruptStatus Register (Base Addr +05 h).

DSP Interrupts: the source of a DSP interrupt may be split into two classes including abort interrupts and non-abort interrupts. An abort interrupt is generated by the DSP when an accident occurs requiring immediate disabling of the drive's writes. When the DSP is in an abort Interrupt, the driver hardware will not set the Write Gate, turn off the laser, and generate a Drive Attention Interrupt to 80C 188. When the DSP is a non-abort interrupt, only one Drive AttentionInterrupt is generated for 80C 188.

Aborting DSP interrupts: the state of generating a DSP to report an abort interrupt is shown in table 12.

TABLE 12 abort DSP interrupts

Error of focus

Off track error

Laser power control error

Spindle not at correct speed

When the Focus Error signal exceeds the programmable threshold set by 80C188, a Focus Error is reported by the DSP. When the Off-Track Error signal exceeds the programmable threshold set by 80C188, an Off-Track Error is reported by the DSP. When the output of the Laser can no longer be controlled by the DSP within the threshold set by 80C188, the DSP reports a Laser Power control error. When the Spindle Speed falls below the minimum RPM established by 80C188 or rises above the maximum RPM established by 80C188, a Spindle Not At Speed Error is reported by the DSP.

Non-Aborting DSP Interrupts: the state in which the DSP is generated to report a non-abort interrupt is shown in table 13 below.

TABLE 13 non-abort DSP interrupts

10 second timer event

Bad instruction checksum

Unknown instruction

Bad track finding error

Cartridge eject failure error

The 10-Second Timer Event interrupts the signal returned by the DSP that the internal clock has reached 10 seconds. 80C188 is responsible for managing the running clock for the total power up hours and minutes. Each 10-SecondTimer Event interrupts the propel power hour clock. When its computation for the Checksum of the command does not conform to the contents of the Checksum byte within the command received by 80C188, a BadCommand Checksum is reported by the DSP. When the contents of the command byte received by 80C188 is not a valid DSP command, an Unknown Comm-and is reported by the DSP.

A Bad Seek Error is reported by the DSP when (a) the first entry in the Seek Velocity Table is empty, or (b) the Focus Loop is not closed (which occurs only with the first instruction before the DSP is commanded to initialize). The Seek setting Errors will be exposed as Off-Track Errors. The DSP will block Off-TrackErrors (TBD) μ s after TrackingLoop closing to prevent false Off-TrackErrors during the set time. When the DSP does not detect the Eject Limit signal within (TBD) μ s, a Cartidge EjectFailedError is reported by the DSP.

GLIC Interrupts: GLIC (glue Logic IC) provides an interface to the various input and output signals that 80C188 must manage.

The input signals that have been defined for generating interrupts by the GLIC are shown in table 14:

TABLE 14 other drive attention interrupts

Automatic converter reset

Automatic converter power down request

Automatic converter exit

Front panel exit

Cartridge insertion (at entry) (to be)

Disc cartridge present (sitting on hub)

An Autochanger Reset interrupt is generated by the GLIC whenever a rising edge is detected on the Autochanger Reset input signal on the Jukebox 20-pin connector. An Autochanger Power Down Request interrupt is generated by the GLIC whenever a rising edge is detected on the Autochanger Power Down Request input signal on the Jukebox20 pin connector. An Autochanger Eject interrupt is generated by the GLIC whenever a rising edge is detected on the Autochanger Eject input signal on the Jukebox20 pin connector. A FrontPanel Eject interrupt is generated by the GLIC whenever a rising edge is detected on the signal from the ForntPanelEject Switch. A cart-edge Inserted interrupt (Cartridge detected in the drive's entry) is generated by the GLIC whenever a rising or falling edge is detected on the signal from the card Inserted Switch. Interrupts can be generated by the GLIC hardware, but there is no switch to generate the interrupt. At this point, no firmware will be written to support the feature. A cartidpresentation interrupt (a cartridge is mounted on the drive hub) is generated by the GLIC whenever a leading or trailing edge is detected on the signal from the cartidseated Switch.

Drive Attention Recovery: the Drive authorization code must serve all Drive authorization and return the Drive to a secure, well-known state. To do this, the Drive Attention code must be split into an Intercept Service Route (ISR) and a Handler. The driveAttentention ISR must perform like the highest priority maskable ISR to enable it to preempt the SCSIISR and/or Disk ISR and to disable all operations in progress, bringing the drive to a safe state. Once the operation is disabled, the SCSI ISR or Disk ISR is allowed to run to completion and exit. The processor portion of the driveattentionhandle becomes idle and attempts to bring the drive to a known state. Typically, there are multiple Drive Attention Interrupts that cause the Handler to interrupt itself as the drives are chained through a series of faults.

When the DSP detects a Drive Attention, an interrupt supply 80C188 is generated by the GLIC (on INT 2). When the interrupt is an abort interrupt, the GLIC also deactivates the WriteGate and turns off the laser. The Drive Attentention ISR will stop all ongoing Drive operations by terminating SM331 FormatSequencer, SM330 and External ENDEC. A line relay (hook) will be provided to invoke an application specific termination routine. The Drive AttentionNotification section below further provides information related thereto.

The Drive Attention Handler is responsible for: identifying the cause of the Drive Attention interrupt, clearing the interrupt source initiates a recovery process to bring the Drive to a known state, and verifies: the original error state has been cleared. The source of the DriveAttention Interrupt can be determined by analyzing GLIC Interrupt Status registers-ter (Base Addr +05h) and by requesting the current DSP Status. The relative priority of possible errors is addressed below. If the DSP is the interrupt source, the Drive AttentHandler will send a command to the DSP to reset the Attention state and clear the status bit. The error recovery process for each of the various error states is described below.

Drive Attention Error Priorities: this paragraph lists the various DriveAttention error states that are recognized by the Jupiter driver and given relative priority to each type of error. The following table shows table 15-Drive Attention Pri-orders, with a corresponding queue for each error.

TABLE 15-Driving attention priority

Laser power error

Focus failure

Off-track, including:

making track setting errors

Tracking error

Write termination

Write fault (write gate set and bias OK not yet set)

Magnetic bias fault (TBD)

Spindle speed failure

An exit request comprising:

front panel exit request

Auto-converter exit request

Automatic converter power down request

Automatic converter reset

Disc cartridge rack detection (disc cartridge in entrance switch)

Media conversion (current switch of disk box)

Cartridge unload failure (cartridge in place after exit cycle)

Disk reject (not for Jupiter)

A command failure comprising:

bad command check and invalid command

Drive Attenttion Error Recovery: this paragraph describes the various Drive Attention error states recognized by the Jupiter driver. Each small segment will describe the case bits used for error state classification and also include pseudo code to illustrate how the error state is handled.

The pseudo-code listed in each paragraph has been redesigned from the Drive Attention Handler currently in use with the RMD-5300 product and serves as only a guide. The implementation code uses multiple flags to further refine the priority of Drive Attention.

The variables SuggSenseKey, SuggSense, and SuggSense-CodeQ indicated in the pseudo Code represent SCSI Sense Data field Sense Key, Error Code, and Addi-functional SenseCode Qualifier (ASCQ), respectively. The variable unclr _ cond _ flag is used to indicate when an unclonable condition exists within the drive. The unclearable state forces the driver to respond to the RequestSense Command with the current ASCQ value in SenseKey of HARDWARE ERROR, Error Code of INTERNAL CONTROL ERROR, and unclr _ cond _ flag. By having the driver perform all of its Diagnostic settings, the reset or execution of one SCSISend Diagnostic command can clear one non-clear state. In this manner, any catastrophic error discovered during the performance of an operation will prevent the drive from replacing the media.

The following items were used for each subsection: s is the Standard Status of the drive, O is the Optical Status of the drive, D is the DSP Status, and G is GLIC Inter-rupt Status. StandardStatus and Optical Status are modified ESDI Status words of the driver. The lower Drive Command Status provides information under ESDI Status. The next DSP Status Definitions provides information under DSP Status. At the beginning of each small segment, the status bits that are used to determine whether a particular error state exists are listed. The pseudo code describes how to handle the state.

Command failure:

a state bit:

S＝ESDI_CMD_PTY_FLT|ESDI_INVALID_CMD；

pseudo code:

SuggSenseKey＝HARDWARE_ERROR；

SuggSenseCode＝INTERNAL_CONTROLLER_ERR；

if S ═ ESDI _ CMD _ PTY _ FLT

SuggSenseCodeQ＝ASCQ_CMD_PRTY；

If S ═ ESDI _ INVALID _ CMD

SuggSenseCodeQ＝ASCQ_INV_OP；

unclr_cond_flag＝SuggSenseCodeQ；

Command failure may occur if a bad command check is detected by the DSP or if an invalid command is received by the DSP. According to the present invention, none of these errors occur in the final product being manufactured. Thus, if they occur, they may indicate another type of error, such as a memory error, which will be detected during a reset process that requires the unclearable state to be cleared.

Disc reject:

a state bit:

O＝CARTRIDGE_REJECTED

pseudo code:

send RESET _ ATTN command

Get REQ _ STD _ STAT

Getting REQ _ OPT _ STAT;

if (ANY _ ATTN _ PENDING)

Returning (ATTN _ DIDNT _ CLEAR);

sends out the Bias Magnet command to turn off the Magnet

If a medium exists

Send STOP _ SPINDLE command

Wait_for_cmd_cmplt

If the DSP fails to successfully close the focus and/or tracking loop after three attempts, a diskreiied error will be reported.

Cartridge unloading failure:

a state bit:

O＝CART_LOAD_FAILURE

pseudo code:

if three attempts fail

GLIC_JB_CTRL_REG&＝～JB_ERROR；//Assert.

SuggSenseKey＝HARDWARE_ERROR；

SuggSenseCode＝INTERNAL_CONTROLLER_ERR；

SuggSenseCodeQ＝ASCQ_CANT_UNLD；

Otherwise

Send RESET _ ATTN command

Get REQ _ STD _ STAT

Getting REQ _ OPT _ STAT;

GLIC_JB_CTRL_REG|＝JB_CART_LOADED；//Deassert.

if (ANY _ ATTN _ PENDING)

Returning (ATTN _ DIDNT _ CLEAR);

if a medium exists

Eject _ CART command

Wait_for_cmd_cmplt()；

If the Eject Limit signal is not asserted after three seconds, the DSP will monitor the cartridge Eject sequence and generate an interrupt. The recovery process will be attempted three times to eject the cartridge. If the ERROR is still present, a failure is reported on the SCSI and 20 pin Autochanger connector signal ERROR (active low).

An exit request:

a state bit:

O＝EJECT_REQUEST

pseudo code:

SuggSenseKey＝MEDIUM ERROR；

SuggSenseCode＝MEDIUM_OUT

SuggSenseCodeQ＝NO_SENSE_CODE_QUAL；

REQ _ STD _ STAT is taken;

if a medium exists

Sends out the Bias Magnet command to turn off the Magnet

Send STOP SPINDLE command

GLIC_JB_CTRL_REG|＝JB_CART LOADED；//Deassert.

Eject _ CART command

Wait_for_cmd_cmplt()；

Send RESET _ ATTN command

REQ _ STD _ STAT is taken;

if (ANY _ ATTN _ PENDING)

Returning (ATTN _ DIDNT _ CLEAR);

eject Request can come from either Autochanger or FrontBranl. If a cartridge is present, the spindle will stop and the Autochanger CART _ load signal is deasserted (active low). After waiting for the SPINDLE to STOP (STOP spin, described in the following paragraph), the cartridge is ejected.

Replacing the medium:

a state bit:

O＝CARTRIDGE_CHANGED

pseudo code:

SuggSenseKey＝MEDIUM ERROR；

SuggSenseCode＝MEDIUM_OUT；

SuggSenseCodeQ＝NO_SENSE_CODE_QUAL；

Set_not_rdy mchg_attn()；

send RESET _ ATTN command

REQ _ STD _ STAT is taken;

getting REQ _ OPT _ STAT;

if (ANY _ ATTN _ PENDING)

Returning (ATTN _ DIDNT _ CLEAR);

send STOP _ SPINDLE command

Send START _ SPINDLE command to 4xRPM

Wait_for_cmd_cmplt()；

GLIC_JB_CTRI_REG&＝～JB_CART_LOADED；//Assert.

This condition exists when the Cartridge is on the hub and the cartidge Present switch is closed. The autoconger signal CART _ load is set (active low).

Main shaft speed failure:

a state bit:

O＝SPINDLE_SPEED_FAILURE

pseudo code:

send RESET _ ATTN command

REQ _ STD _ STAT is taken;

getting REQ _ OPT _ STAT;

GLIC_JB_CTRL_REG1＝JB_CART_LOADED；//Deassert.

if (ANY _ ATTN _ PENDING)

Returning (ATTN _ DIDNT _ CLEAR);

if a medium is present

START SPINDLE command to current medium

Wait_for_cmd_cmplt()；

GLIC_JB_CTRL_REG&＝～JB_CART_LOADED；//Assert.

For a particular type of media, the DSP will monitor the spindle speed according to an acceptable speed range. The minimum and maximum speeds are identified to the DSP by 80C 188. If the spindle speed is detected as being outside a certain range, the DSP will generate an interrupt.

Laser power failure:

a state bit:

O＝LASER_DRIVE_FAILURE

pseudo code:

send RESET _ ATTN command

Send RECAL _ DRIVE command

REQ _ STD _ STAT is taken;

getting REQ _ OPT _ STAT;

if O ═ LASER _ DRIVE _ FAILURE

SuggSenseKey＝HARDWARE_ERROR；

SuggSenseCode＝INTERNAL_CONTROLLER_ERR；

SuggSSenseCodeQ＝ASCQ_CASER_FAIL；

unclr_cond_rlag＝SuggSenseCodeQ；

Returning (ATTN _ DIDNT _ CLEAR);

if (ANY _ ATTN _ PENDING)

Returning (ATTN _ DIDNT _ CLEAR);

return (ALL _ DONE);

an abort interrupt is generated when a LaserReadPower threshold is exceeded and detected by the DSP. If the laser fault is not cleared after the drive performs a recalibration, a non-cleared state is declared to exist.

Focus failure:

a state bit:

O＝FOCUS_SERVO_FAILURE

pseudo code:

CLIC_JB_CTRL_REG|＝JB_CART_LOADED；//Deassert.

send RESET _ ATTN command

REQ _ STD _ STAT is taken;

getting REQ _ OPT _ STAT;

if (ANY _ ATTN _ PENDING)

Returning (ATTN _ DIDNT _ CLEAR);

GLID_JB_CTRL_REG&＝～JB_CART_LOADED；//Assert.

the threshold for Out of Focus errors may be programmed by 80C 188. When the focus signal exceeds a specified threshold. The DSP will generate an abort interrupt to 80C 188.

Write failure:

a state bit:

S＝WRITE_FAULT_ERROR

pseudo code:

if the medium is write-free

Set_not_rdy_mchg_attn()；

SuggSenseKey＝NOT_READY；

SuggSenseCode＝DRIVE_NOT_READY；

SuggSenseCodeQ＝NO_SENSE_CODE_QUAL；

Otherwise

SuggSenseKey＝MEDIUM_ERROR；

SuggSenseCode＝WRITE_PROTECTED；

SuggSenseCodeQ＝NO_SENSE_CODE_QUAL；

Send RESET _ ATTN command

Get REQ _ STD _ STAT

Getting REQ _ OPT _ STAT;

if (ANY _ ATTN _ PENDING)

Returning (ATTN _ DIDNT _ CLEAR);

not on the track:

a state bit:

O＝NOT_ON_TRACK|WRITE_TERMINATED；

S＝SEEK_FAULT；

pseudo code:

get DSP status

If Bad Seek and Focus Loop NOT Closed

Downloading lookup tables (seek tables) to DSP

Send RESET _ ATTN command

Otherwise

Send RESET _ ATTN command

If (S ═ SEEK _ FAULT) or (O ═ WRITE _ TERMINATED)

Send RECAL _ DRIVE command

Get REQ _ STD _ STAT

Getting REQ _ OPT _ STAT;

if (ANY _ ATTN _ PENDING)

Returning (ATTN _ DIDNT _ CLEAR);

the Drive Attention Handler will request status from the DSP when a Bad Seek is reported by the DSP to determine if a Seek error occurred or if the Velocity Table was lost. If the Bad Seek status bit is set and the "Focus Loop Not Closed" status bit is Not set, this means that the lookup table is Not properly initialized. If only the SeekFault status bit is set, the Drive AttentHandler will send a "Reset Att-entry" command to the DSP indicating: the Seek Fault status bit is to be cleared. Then, 80C188 seek code will need to restart from the Drive Attention recording point.

The threshold for Off-Track Errors may be programmed by 80C 188. If the write process needs to have a higher constraint, the threshold can be set separately for reading or writing. When an Off-Track is detected, the DSP will end the drive operation using a "catastrophic" interrupt. The Drive Attention Handler will send a "Reset Attention" to the DSP.

Open Issue. The recovery mechanism is to cause the firmware to issue another seek command (thereby allowing the DSP to seek and re-implement tracking). One method that may be used is to open a TrackingLoop and command the DSP to re-track. When no stop is found and the head is slipping across the disc, the method does not work for a failure mode. Thus, the best recovery mechanism is an attempt to re-search. A specific code will be needed to handle the case when the last look-up fails due to the Off-Track Error. The re-lookup should be the best recovery attempt.

Failure of the bias magnet:

a state bit:

S＝MAGNET_BIAS_FAILURE

pseudo code:

SuggSenseKey＝HARDWARE_ERROR；

SuggSenseCode＝INTERNAL_CONTROLLER_ERR；

SuggSenseCodeQ＝ASCQ_MAGNET_FAILED；

send RESET _ ATTN command

Get REQ _ STD _ STAT

Getting REQ _ OPT _ STAT;

if (ANY _ ATTN _ PENDING)

Returning (ATTN _ DIDNT _ CLEAR);

helical Mode: when all error conditions have been cleared, the DriveAttentionHandler must return the drive to the original state of the spiral (also called track following or jump back prohibited). This is done by saving the initial state at the ingress and executing the following code at the egress.

If ((wassizing ═ 0) & & | (S & MEDIUM _ NOT _ PRESENT) & & & &

！(S&SPINDLE_STOPPED))

SpiralMode(FALSE)；

Drive Attention Notification: the Drive Attentention generates an interrupt to a Drive Attentention Handler that takes the Drive into a known state. It is then the responsibility of this Handler to inform the part of the firmware responsible for managing the current operation that attention states exist and what to do to clear the state. Two mechanisms are used to notify the firmware. They include informational notifications and direct notifications.

When a task has initiated an operation and is waiting for the SCSI ISR or DiskISR to send a message, the Drive Attention Handler sends a message to the task's queue indicating: a Drive Attention occurs. The task currently responsible for an operation is maintained in a path variable (a routing variable). A task queue that continuously polls for information takes too much overhead processing when a portion of the firmware is executing and can generate a Drive Attenti-on at any time (e.g., when seeking a track code). The second mechanism for reporting Drive Attention uses a "long jump" feature to return code execution to where the firmware knows how to restart an algorithm or attempt a retry. The process of identifying where a long hop is called registration. Multiple levels of registration may be performed, each new level retaining in its stack the previous registration information at that level. When a portion of the code registers itself, the code can also identify the routine (Context sensitive abort) that the Drive Attentention ISR will call to perform a Context-dependent abort.

MEDIA FORMATS (MEDIA format): media Type Determination: the following sequence of events is used to identify the type of media.

a) When the drive is powered, the cartridge is inserted or already present.

b)80C188 issues a 4x speed spin-up command to the spindle motor.

c) When the RPM is greater than 60 RPM, 80C188 issues a DSP command to notify.

d) When the DSP interrupts at an RPM greater than 60, 80C188 issues a DSP command to notify when the RPM is greater than 4x the minimum RPM.

e) Then, 80C188 issues a DSP command to initialize:

(1) the DSP slowly looks for an internal emergency stop.

(2) The DSP looks up to the OD of The (TBD) track.

(3) The default value is that Jump Backs is allowed and the direction is 4 x.

(4) If during the initial seek the DSP encounters an error, the error will be reported to 80C 188. 80C188 will reset the DSP and then reinitialize.

f)80C188 attempts to read from Inner Diameter the ID of a 4x zone (TBD) corresponding to The (TBD) track.

g) If no ID can be read, 80C188 attempts to read the ID using the neighbor frequencies of the add and subtract (TBD) region.

h) If no ID can be read, 80C188 issues a 2x speed command to the spindle motor.

i) When the RPM is greater than 2x minimum, 80C188 issues a DSP command to notify.

j) When the DSP interrupts at greater than 2x minimum RPM, 80C188 issues an initialization command to the DSP and then attempts to read an ID in the zone (TBD) corresponding to The (TBD) track.

k) If no ID can be read, 80C188 attempts to read the ID using the frequency of the adjacent region of the add-and-subtract (TBD) region.

l) if no ID can be read, steps (h) to (k) are 1 x.

m) if no ID can be read, 80C188 issues a 2x speed command via the spindle motor.

n) when the RPM is less than 2x max, 80C188 issues a DSP command to notify.

o) when the DSP interrupts at less than 2x minimum RPM, 80C188 attempts to read an ID by performing a frequency sweep (sweep). The scanning mode will be: lack of region, region-1, region +1, region-2, region +2, etc., until all frequencies are tried out.

p) if no ID can be read, 80C188 issues a 4x speed command to the spindle motor.

q) when the RPM is less than 4x max, 80C188 issues a DSP command to notify.

r) 80C188 attempts to read an ID by performing a frequency sweep when the DSP interrupts at an RPM less than 4x maximum. The scanning mode will be: lack of region, region-1, region +1, region-2, region +2, etc., until all frequencies are tried out.

AN ID HAS BEEN READ (one ID HAS BEEN READ):

s)80C188 issues a seek command to determine a location within the SFP area.

t)80C188 attempts to read out 512 byte sectors of SFP data. If the sector is not successfully read, 80C188 attempts to read 1024 byte sectors of SFP data.

u)80C188 initializes the media parameters of the drive according to the media type and SFP information. A pre-write test flag is set to indicate: the pre-write test must be performed prior to writing to the medium.

v)80C188 starts initialization of the cartridge (i.e., reading out Defect management areas, creating a group table, etc.). If any DMA must be rewritten to make it consistent with other DMAs, the drive must check whether the pre-write check should be performed first.

CCW (Pseudo-WORM) Support: the Blankcheck function of Cirrus Logic SM330 will be used to decide whether 1x and 2x cartridges are unrecorded. The DMP field will not be used. The Blank Check function of ExternalENDEC will be used to decide if a 4x cartridge is not recorded. The DMP field will not be used.

Whenever a CCW cartridge is inserted in the drive, the drive will automatically disable WriteCache and clear the WCE (WriteCache Enable) field in the Mode Page 08h, Caching Parameters. By issuing a CHECK CONDITION, all starters will be notified of the change on the next command from each initiator. The SenseKev/Sense Code combination returned according to the request-st Sense Command will be UNIT ATTENTION/MODE SELECTPARAMETERS CHANGED (06h/29 h).

P-ROM Support: open Issue. For P-ROM media, the PREFMT signal must be set when the header is beyond or in three tracks of one ROM area of the cartridge. The seek algorithm needs to consider where the P-ROM area is located on the cartridge and may need to go through them. The DSP is required to make a seek over a P-ROM area during initialization. The initial seek is performed at a low rate to minimize the change in the Off-Track Error.

Retry Strategy (Retry Strategy): when a drive attempts to access a medium for a read, erase, write or verify operation, a media error, a correction error or other error may be encountered. The sources of media errors are: sector Mark (SM), Sector IDS, Data Syncs (DS), or Resyns (RS). The sources of correction errors are: cyclic Redundancy Check (CRC) or Error Checking and recording (ECC). Other errors that the drive can encounter are: format sequence errors, DriveAttentions, or Buffer RAM parity errors. For each media or correction error, the drive validates the error against thresholds for the error type and the operation type. The thresholds are maintained in various Mode Pages that can be modified by the host (host). Table 16 shows the default thresholds used by the drive.

TABLE 16 Default Thresholds 1x, 2x 1x, 2x 4x

512BPS 1024BPS 512BPS 1024BPS sector mark 4/5 Marks 4/5 Marks

3/4 Spaces 3/4 Spaces 4/5 Segments 4/5 Segments IDs read 2/32/32/32/3 erase, write 2/32/32/32/3 modify 3/33/33/33/3 Data Sync 9/129/123/43/4

(DS) Groups Groups Groups GroupsResync(RS) 3 6 3 6

Per sector error 15301530

Middle ECC byte

Error 3636 per alternate

Middle ECC byte

When a media or correction error is encountered that exceeds the current threshold or any other error defined above, the drive will attempt a retry operation as described in the remainder of this paragraph. Retry is performed unless a fatal error is encountered during the attempt to access the data that results in an unclonable state or other abort state. In addition, if an internal debug flag, drvRe-try Disable, is set, no retry is performed. The drvRetry Disable flag is set or cleared via SCSI Read/Write ESDI Comm-and (E7 h).

When the drive is performing a Read operation, it will perform the maximum number of retries as indicated in the Mode Page01h, Read/Write error recovery Parameters, Read Retry Count (Byte 3). When the drive is performing an erase or Write operation, it will perform the maximum number of retries as indicated in the Mode Page01h, Read/Write Error Recov-Ery Parameters, Write Retry Count (Byte 8). When the driver is performing a Verify operation, it will perform the maximum number of retries as shown by Mode Page 07h, Verify Error Recovery Parameters, Verify RetryCount (Byte 3).

If a sector cannot be read within the current threshold, the drive will attempt to recover the sector using a larger than physical approach (Heroic means) as described in the following paragraph of Heroic Reco-veryStrategies. If the sector is recovered, it is reallocated as described in the following paragraph-completion burst.

Error Checking and Correction (ECC); error Checking for read or verify operations is performed in hardware in the Cirrus LogicSM 330. An update vector for correcting all bytes in the error is generated by the SM330 and transmitted to the SM330 over a dedicated serial line between the two chips. The CRC and ECC codes for the write operation are generated by the SM 330.

When the Disable Correction (DCR) bit is set in the Mode Page 01h, Read/Writeerror Recovery Parameters, no Correction is added to the sector for the Read operation. When the Enableearly Correction (ECC) bit is not set in ModePage 01h, Read/Write error recovery Parameters, ECC is not added to the sector for the Read operation either. If the EEC bit is not set, the drive will automatically apply a correction on the last retry after all retries have failed except one, if the DCR is not set. It is important to note that with the DCR bit set, ECC errors are still detected, but not corrected.

Heroic Recovery Strategies: the term Meroic Recovery is used to describe the process of recovering data from a medium using all possible methods. This countermeasure is to selectively relax each threshold and finally restore the original state of the data. The absolute criterion for deciding whether a sector has been recovered is whether the data can be corrected within a maximum threshold established by the correction hardware. To minimize error correction, the media threshold is relaxed in a progressive order (TBD).

If a sector cannot be Read within the current threshold, Heroic Recovery is enabled and either the Transfer Block (TB) bit or the Automatic Read Responsive Enabled (ARRE) bit is set in the Mode Page 01h, Read/Write Error Recovery Parameters. If the sector's data is fully recovered and ARRE is allowed, the sector is reallocated as described in the following paragraph.

The drive parameters that can be changed in attempting to recover data are: (1) PLL bandwidth-dth (normal, high and extremely high), (2) Frequency Zone (expectation Zone-1, expectation Zone +1), (3) Pseudo SectorMark, (4) Pseudo Pata Sync, (5) Lockon First Sync (sector not suitable for reallocation, only sent to host), (6) (TBD).

Reaction Strategy: reallocation is the process of relocating data of a logical sector to a new physical sector. A sector reallocation (1) according to a host request (SCSI realssignblock Command, 07 h); (2) when a sector cannot be read out within the current threshold, the sector is fully recovered, and the ARRE bit is set; (3) the sector cannot be erased or written using the current threshold and the Automatic Write Read-station Enabled (AWRE) bit is set at the Mode Page 01h, Read/Write error recovery Parameters; or (4) the sector cannot be verified as part of a SCSI Write and Verify Command within the current threshold.

Read reaction: when the Data for the sector exceeding the read threshold has been fully recovered and the AREE bit is set, if the threshold is exceeded because of a Data Sync Resync or ECC corrected error, the drive will attempt to rewrite the Data to the same physical sector. If the same sector's data can now be verified within the threshold determined in the Moed Page 07h Verify error recovery Parameters, the sector will not be reallocated. Sectors that are erroneous or that cannot be properly verified due to an error in the SectorMark in the ID field will be reassigned to a new physical sector.

When a new physical sector is needed to relocate a logical sector, the drive will write data (using the write threshold) to a spare sector and then verify that sector (using the verify threshold). If the sector cannot be written or verified using the current threshold, another physical sector will be recognized as spare and the process repeated. The largest of the three spare sectors will be used to attempt to reallocate a single logical sector.

Write Reallocation: if the Automatic Write Reallocation Enabled (AWRE) bit is set, a Sector will be reassigned that fails to meet the SectorMark threshold or the threshold for the number of valid Sector IDSs as determined by the Mode Page 01h, Read/Write Error Recovery Parameters.

When a new physical sector is needed to relocate a logical sector, the drive will write data (using the write threshold) to a spare sector and then verify that sector (using the verify threshold). If the sector cannot be written or verified using the current threshold, another physical sector will be identified as spare and the process repeated. The largest of the three spare sectors will be used to attempt to reallocate a single logical sector.

Verify Write Reallocation (Verify-After-Write Reallocation): a sector will be reallocated that cannot meet the verification threshold as defined by the Mode Page 07h, Verify Error RecoveryParameters, as part of a SCSI Write and Verify Command. The ARRE and AWRE bits do not affect the decision: a sector that cannot be verified within the current threshold as part of the SCSI Write and verify Command is reallocated.

When a new physical sector is needed to relocate a logical sector, the drive will write data (using the write threshold) to a spare sector and then verify that sector (using the verify sector). If the sector cannot be written or verified using the current threshold, another physical sector will be identified as spare and the process repeated. The largest of the three spare sectors will be used to attempt to reallocate a single logical sector.

SCSI Error Codes Returned: the following paragraphs describe the SCSI Sense Key/SenseCode/Additional Sense Code Qualifier (ASCQ) rendezvous for each state described in the previous and later paragraphs. The control bits that affect the response of the drive and the SCSI Sense Key/Sense Code/ASCQ combination returned to the host are listed in Table 17 below-Mode Page01h, Error Recovery Parameters.

TABLE 17 Mode Page 01h, Error Recovery Parameters

(mode page 01h, error recovery parameter) bit name indicates that the AWRE auto-write allows the drive to effect detection during write operations

Automatic reassignment of defective blocks. ARRE auto-read allows the drive to effect detection during read operations

Automatic reassignment of defective blocks. TB transmission block driver will transmit to host one recovered outside threshold

And (5) repeating the blocks. RC read continuous driver will transfer data without delay to realize error

And (5) recovering by mistake. Data may be generated to maintain the number of connections

And (4) according to the stream. ECC allows an early correction drive to use error correction before retries. The PER post-error driver will report a Check Conclusion to

Blocks recovered by retry, correction or reallocation. Inhibiting when an error is encountered during a DTE error that the drive will terminate the data

And (5) transmitting. DCR inhibits error correction that the correction drive will not use data error recovery

Is positive. The drive will still detect ECC errors.

Errors While reallocting (Errors in redistribution): in an attempt to reassign a logical sector to a new physical sector, the sensing (sense) combinations in table 18 will be reported by the drive if the indicated error condition is encountered.

TABLE 18 Error Codes Reported While addressing to

Reallocate a Sector (in an attempt to reassign a fan)

Error Code reported by zone time) error state Sense Key/Code/ASCQ data returns an unavailable spare area 03/32/00 Yes automatic reallocation failure 04/81/00 Yes over attempts to reallocate 04/44/a6 Yes defect table error 03/32/01 Yes

Automatic reaction is considered to fail when a hardware error or other fatal error renders the drive incapable of performing a reallocation. During the execution of the reallocation, the drive will make only three attempts to allocate a logical sector to a new physical sector. If more than three attempts are required, the drive considers that a hardware error has occurred. This approach limits the number of attempts to reallocate sectors, thereby greatly reducing the time taken to reallocate and greatly reducing the consumption of active spare area. If the drive can only write and verify a single Defect Management Area (DMA) on the disc, the drive will report a Defect List Error.

Read Error Codes (Read Error code): this segment shows the conditions that enable the drive to report back to the host state during the execution of a read operation. Whether the status is actually reported depends on whether the host issues a SCSI Request Sense Command.

The above conditions can be divided into five main types, including: (1) attempting to locate a desired sector, (2) attempting to read the sector, (3) attempting to recover the sector using a greater than physical method (heroics), (4) attempting to reallocate the sector, and (5) Drive attributes and other fatal errors. Table 18 provides the sensing combinations reported when a reassignment failed, while table 8 above provides the sensing combinations reported for a fatal error.

When attempting to locate the desired sector, the sensing combination in table 19 is reported by the driver if the indicated error type is encountered.

TABLE 19 Error Codes Reported While Locating the Desired

Sector (error Code reported when locating the desired Sector) error status sensor Key/Code/ASCQ data returns a Sector tag threshold 03/01/00 No [ ID threshold (bad CRC) ] 03/10/00 No [ ID threshold (non-address tag) ] 03/12/00 No

During an attempt to read the sector, if the indicated error type is encountered, the ARR is not set, and data cannot be recovered within the threshold while performing a retry, the sense combination in table 20 will be reported by the drive. If all retries are used and the data has not been recovered, the drive will perform a heroic recovery if the TB bit is set. However, whether or not the data is fully recovered, the data will be returned to the host. If fully recovered, the data is not reallocated to a new sector.

Table 20-Error Codes Reported While testing to Read,

ARRE is Not Set (reported when ARRE is Not Set when read is attempted

Reported error Code) error status Sense Key/Code/ASCQ data return data sync threshold 03/13/00 if TB 1 resynchronization threshold 03/11/07 if TB 1ECC error threshold 03/11/0C if TB 1 uncorrectable ECC error 03/11/02 if TB 1 uncorrectable

During an attempt to read out the sector, if the DCR is set and data can be recovered within the threshold when performing a retry or heroics, the status will be reported by the drive to the sense combination in table 21. If the data cannot be recovered by heroics, the error codes returned are those listed in table 20 above. If the data is fully recovered and ARRE is set, the drive will attempt to reassign the logical sector to a new physical sector.

TABLE 21 Error Codes Reported While Performing reading

Retries, DCR is Set (when report read retry, DCR is Set

Error Code reported at set time) error state Sense Key/Code/ASCQ Data return does not need to retry, ECC is not used. 00/00/00 Yes requires a retry. ECC is not used. 01/17/01 Yes needs to be exaggerated. ECC is not used. 01/17/06 Yes performs automatic reassignment. The (ARRE ═ 1) needs to be exaggerated. ECC is not used. 01/17/07 recommend automatic reassignment if TB is 1. (ARRE ═ 0) needs to be exaggerated. ECC is not used. 01/17/09 Yes the rewrite for automatic reassignment was successful

When attempting to read out a sector, if the DCR is not set and data can be recovered within the threshold when performing a retry or heroics, the combination of senses in table 22 will be reported by the drive for that status. If the data cannot be recovered by heroics, the error codes returned are those listed in table 20. If the data is fully recovered and ARRE is set, the drive will attempt to reassign the logical sector to a new physical sector.

TABLE 22 Error Codes Reported While Performing reading

Retries, DCR Not Set (when a read retry is performed, DCR has Not yet been Set)

Error Code reported at setup) error state Sense Key/Code/ASCQ Data return does not need to retry. ECC is not used. 00/00/00 Yes does not need to retry. ECC 01/18/00 Yes (within threshold) is required. A retry is required. ECC 01/18/01 Yes (within threshold) is required. Hermics is required. Hermics is required to perform 01/18/02 Yes automatic reassignment (ARRE ═ 1). It is recommended 01/18/05 that heroics be required if TB 1 automatic reallocation (ARRE 0). The rewrite for the 01/18/07 Yes automatic reassignment was successful

Read Error Reporting: this paragraph describes: logic used by the firmware to determine when to set a particular detection combination, when to report errors via a Check Condition, and when to return data.

Read operation

　　Do_seek：<dp n="d147"/>seek to desired sector if seek error bit error abort with 04/15 (random positioning error) init read count from Mode Page 01h if DCR is set or EEC is set set to desired ECC error bit count if RC is set if 1x or 2x Mode set RC in SM330 else RC set RC in SM330set to align ID errors, RS errors, and DS errors (note: Wait hardware to indicate sector read or error present) Wait _ for _ msg: wait for msg from ISR if not repeated from the repetition if PER is set set Check Condition if DCR is set set sense to 01/17/01 (recovery data with error correction and retry) if DTE set set to return all blocks read Do not have a behind the rest of the block request data for SCSI new seek required go Do _ seek if not move Do<dp n="d148"/>The auto Wait _ for _ msgelse return to cal retrieve return read return complete no more than three copies if (TB is Set or ARRE is Set, and not physical access, and not read going) the performance of the form of the great recipient update Set of the Condition of sending DCR Set set Set 01/17/07 (Recovery data without ECC, recommendation re-assignment) if TB is Set to return complete received block Set of not more than one Set of sending DCR Set set Set to send copy return of sample sector Wait Set 01/17/09 (Recovery data, recommendation re-assignment) if TB is Set to return complete received block Set of not more than one Set of sending Report _ error ARRE Set of sending copy return update Set of write request of sample sector update Set of sending data of sending sector update Set 01/17/09 or PER re-send data with re-retry 52, rewriting of data is successful) else <dp n="d149"/>set sense to 01/18/07 (with retry and ECC recovery data, the rewriting of data is successful) else if reallocation is performed PER is set Check Condition if DCR is set sense to 01/17/06 (recovery data without ECC, automatic reallocation is performed) else set sense to 01/18/02 (recovery data without ECC, automatic reallocation is performed) else set Check Condition no available set sense to 03/32 (no available defect spare storage unit) if automatic reallocation is performedsense to 04/81 if to manual attributes to relocation set sense to 04/44/A6 (reaching relocation Limit) if Defect List core not be write set sense to 03/32/01 (Defect List update failure) else set Check Condition TB is set to return partial retrieved block to Report _ error<dp n="d150"/>do not return block set correction to Report _ error if PER set set correction DCR set set sense to 01/17/01 (data recovered by retries) else set sense to 01/18/01 (data recovered by error correction and retries) prepare to repeat the block if laser repeat and EEC is set set to use ECC correction to set _ for _ readReport _ error: if-Sector Mark Threshold set sense to 01/01 (no INDEX/SECTOR signal) if-ID CRC set sense to 03/10 (ID CRC or ECC error) if-ID Threshold set sense to 03/12 (no address tag found for ID field) if-Data Sync Threshold set sense to 03/13 (no address tag found for Data field) if-response Threshold set sense to 03/11/07 <dp n="d151"/>(data resynchronization error) if ECC Threshold error set sense to 03/11/0C (unrecovered read error, it is recommended to rewrite this data) if Uncorrrected ECC Threshold set sense to 03/22/02 (error too long to correct) return to caller

Verify Error Codes: this section shows the case where the driver is enabled to report a status back to the host as the SCSI Verify Command performs the Verify operation. Whether this condition is actually reported depends on whether a SCSI Requ-est Sense Command occurs by the host.

These cases can be divided into three main types, including: (1) attempt to allocate the required sector, (2) attempt to verify the sector, and (3) Drive attributes and other fatal errors. The above table 8-Severerror provides the combination of sensing reported for severe errors.

During an attempt to allocate the desired sector, the sensing combinations listed in table 19 will be reported by the drive if the indicated error type is encountered. During an attempt to verify the sector, the sensing combinations listed in table 20 will be reported by the drive if the indicated error type is encountered. But with the verify operation, no data will actually be returned to the host. By way of determination, heroics is never executed during the verify operation. The purpose is to Verify that data can be read using the (possibly) more accurate thresholds of the model Page 07h, Verify Error recovery parameters. Automatic reassignment of sectors is not performed for sectors that cannot be verified at the current threshold (note that automatic reassignment may be performed during a verification after a write operation initiated by a completely different SCSI command).

Verify Error Reporting: this paragraph describes: the firmware uses logic that determines when to set a particular detection combination, when to report errors via a Check Condition, and when to return data.

Inspection operations

seek to desired sector if seek error abort with 04/15 (random positioning error) Setup _ for _ verify:<dp n="d152"/>wait vertical retry count from Mode Page 07h if DCR is set to detect ECC errors but not count register (note: Wait hardware indicates sector has been read or has error) Wait for msg: wait for msg from ISR if no error if recovered from recovery if PER is Set set Check Condition DCR is Set set Set sense to 01/17/01 (recovery data with retry), else Set sense to 01/18/01 (recovery data with error correction added) if DTE is Set donot connected after this block if new seek required to get Setup _ for _ verify else if more than do to get Wait _ for msg else return to be to a controller else default response if more than do so set Check Condition to Report _ error (same as read operation) else if PFR set <dp n="d153"/>set Check condition DCR is set set sense to 01/17/01 (recovery data with retry), else set sense to 01/18/01 (recovery data with error correction added) prepare to retry the block to Setup _ for _ verify

Write Error Codes: this field indicates the conditions that enable the driver to report a status back to the host during the execution of a write operation, depending on whether the host issues a SCSI Request Sense Command.

This condition can be divided into four main types, including: (1) attempt to locate the desired sector, (2) attempt to write to the sector, (3) attempt to reallocate the sector, (4) Drive attention-tion and other fatal errors. The above table 18-Error Codes Reported While testing to Reallocate a Sector provides the combination of senses Reported when a redistribution failed, While the table 8-sensor Errors represents the Reported combination of dgkn measurements for a fatal Error.

During the attempt to locate the desired sector, the sensing combinations listed in table 19 are reported by the drive if the indicated error type is encountered. Upon attempting to write to the sector, the sense combinations listed in table 23 are reported by the drive if the indicated error type is encountered.

TABLE 23 Error Codes Reported While Performance

Write Operations (error codes reported when performing Write Operations) error condition Sense Key/Code/ASCQ no retry 00/00/00 requires a retry 01/0C/00 to perform automatic reassignment. 01/0C/01(ARRE 1) recommends automatic reassignment. 03/0C/00(ARRE 0)

Write Error Reporting: this paragraph describes: logic used by the firmware to determine when a particular combination of tests is set, when errors are reported through a Check Condition, and when data is returned.

Write operation

seek to desired sector if seek error abort with 04/15 (random positioning error) (note: set up section) Setup _ for _ write: init write retry count from Mode Page 01h (note: Wait hardware to indicate sector has been written or has an error.) Wait for msg: wait for msg from ISR if no error if corrected from the redundancy if set of Check condition set sense to 01/0C/00 (recovered write error) if DTE is set do not complete connection if block if new seek required to get set _ for _ write else if more than do <dp n="d155"/>Auto Wait _ for _ msg else return to cause decrease in write request if more requests is set, not physical access, not write close update if more requests is set, not read close update set detect 01/0C/01 (write error recovered by automatic reassignment) else set Check update if more requests are set detect 03/32 (no defect spare storage unit available) if more automatic reassignment failed set detect 04/81 (automatic reassignment failed)realate set sense to 04/44/A6 (reaching relocation Limit) if Defect List core not be write set sense to 03/32/01 (Defect List update failure) else set Check Condition to Report _ error<dp n="d156"/>it PER is set set Check Condition set sense to 01/0C/00 (recovered Write error) prepare to retry the block go Setup _ for _ Write 

Verify After Write Error Codes: this section shows the case where the driver is enabled to report back to the host when a verification is performed after the write operation. Whether this condition is actually reported depends on whether the host issues a SCSI Request Sense Command.

This situation can be divided into four main types, including: (1) attempting to locate the desired sector, (2) attempting to verify the sector, (3) attempting to reallocate the sector, and (4) Drive attributes and other fatal errors. The table above l8-Error Codes Reported While attachment to realmate a Sector shows the Reported sense combinations when a redistribution fails, While the table 8-segment Errors provide the Reported sense combinations for a fatal Error.

During the attempt to allocate the desired sector, if the indicated error type is encountered, the sensing combination listed in table 19 is reported by the drive. During an attempt to verify the sector, the sense combinations listed in table 20 will be reported by the drive if the indicated error type is encountered.

Verify Write Error Reporting (Verify Error report After Write): this section describes the logic used by the firmware to decide when to set a particular sensing combination, when to report an error via a CheckCondition, and when to return data.

Verification after a write-store operation

seek to desired sector if seek error abort with 04/15 (note: establish section) Setup _ for _ verify: init verify recovery count from Mode Page 07h if DCR is set to detect ECC errors but not count register (note: wait for hardware to indicate that sector has been read or has errors)<dp n="d157"/>Wait for msg: the Wait for msg from ISR if no error if recovered from retry set set Check set to 01/17/01 (recovery data with retry) else set sense to 01/18/01 (recovery data with ECC and retry added) if DTE is set do not connect to the later but block if new seek to set _ for _ verify if move to do get set _ for _ msg else return to clock else repeat request if no move retry is present if write again to write again set of strategy result set 01/17/09 (recovery data with retry and retry) is write data with recovery data of ECC or recovery data 01/18/07. <dp n="d158"/>Else if reallocation of recovery data with retry and ECC succeeds, else if reallocation of recovery data with ECC is performed, else set sense to 01/18/02 (recovery data with ECC is performed, automatic reallocation is performed) else set Check Condition set sense to 03/32 (no Defect spare storage unit available) if automatic reallocation failed set sense 04/81 (automatic reallocation failed) if too manual allocation to reallocation set sense to 04/44/A6 (relocation limit reached)set sense to 03/32/01 (failure of defect table update) else if PER is set Check Condition DCR is set set sense to 01/17/01 (with renewed resume data)<dp n="d159"/>else Set sense to 01/18/01 (recovery data if ECC and retry exist) prepare to retry the block go Set for verify 

Defect Management Areas: this segment is the TBD. The following are notes and questions that will be used during this definition. Reading DMAS: which threshold to use is a design consideration. How many retries. Comparing/Vprating DMAs: what is good. When they are rewritten. "applying End of Life" and "End of Life" are announced. Each of these matters is a design consideration that does not affect the practice of the invention by those skilled in the art. The DMA data structure is built to support: sector Slipp-ing, Linear Replacement.

Seek Tables for Different Media: the firmware will be downloaded to the DSP with the appropriate speedometer based on the type of media being detected as installed in the drive. A default (i.e., fixed) velocity table will be used until the media type has been determined.

DRIVE COMMAND INTERFACE: a Drive Command Interface is a software Interface that provides a hardware platform to access drivers. Access to SCSI interfaces, Format sequence, ENDEC, and External ENDEC is performed as direct access to those components without going through a DriveCommand Interface. All other components are accessed using the Drive Comman-ds defined in the next paragraph.

Drive Commands: the DriveCommands used by Jupiter firmware are listed in table 24 below. The Type column defines whether the Drive Command is immediate (I), executed by 80C188 (188), or executed by the DSP (DSP). An Immediate Command results in a flag or bit being set and does not require any CPU time to process or monitor the operation. An Immediate Command indicates that the Command is completed immediately. The lower Drive CommandCompletion provides further details regarding this. The 188 Command type indicates that 80C188 requires additional processing to meet its requirements. Additional monitoring is required to verify that the hardware has reached the desired state. The command is indicated as complete when processing or monitoring has been completed. The DSP Command type indicates that a Command must be sent to the DSP to satisfy the Drive Command requirement. When the DSP returns to the state of its command, the command is indicated as complete. Table 24-Drive Commands code name Specification type 0x0000 SET EE _ ADDR SET EEPROM Address I0x0100 READ _ EEPROM READ EEPROM (at present Address) 1880x0200 SET JUMP BACK _ IN SET JUMP BACK to OD DSP0x0300 SET JUMP _ BACK _ OUT SET JUMP BACK to OD DSP0x0400 JUMP _ BACK _ ENABLE SET JUMP BACK to I0x0500 JUMP _ BACK _ ENABLE allow JUMP BACK to I0x06000x0700 JUMP _ EABLE DISABLE EEPROM WRITE function (DSP) 0x0800 REQ _ STATUS request DSP state 0x SET _ LASER THOLD SET LASER readout power threshold DSP0x 00 SET THOSS _ SOLD SET DSP FOCUS threshold DSP0x 00 SET DSP SET THREAD _ SET THOSD SET DSP0x DSP SET THREAD _ SET THOD _ SET 19 _ SET TPS _ SET 19 _ EEPROM TEST threshold DSP0x DSP _ SET TPS _ SET 19 _ SET 0x _ TEX _ TED SET DSP TEX _ TEWR _ TEX _ TEWRITES _ ADD WRITE TEST DSP STATUS 0 (DSP STATUS) SET DSP STATUS WRITE threshold SET DSP0X DSM _ STAT _ EEPROM TEST Format 0 The evaluation status 188, the DSP0x2900 REQ _ OPT _ STAT request selection status 188, the DSP0x4400 SET _ MAG _ READ setting the bias frequency for reading 1880x4800 SET _ MAG ERASE setting the bias frequency for erasing 1880x4C00 SET _ MAG _ WRITE setting the bias frequency for writing 1880x5000 RESET _ ATTN RESET Drive Attestation DSP0x5100 RECAL _ DRIVE recalibration Drive (TBD)0x5200 STOP _ SPINDLE STOP SPINDLE 188, the DSP0x5300 START _ SPINDLE START SPINDLE 188, the DSP0x5400 LOCK _ CART LOCK I0x5500 UNLO _ T unlock cartridge I0x5600 EJET cartridge exit SPINDLE 188, the DSP0x5B 539 _ COMP _ ON (TBD) SET the NORMAL PLL 0x SALT _ SALT WRITE frequency for reading the DSP0x 670X _ SALT WRITE Drive (DDS 0x SALT _ SALT) reading bandwidth 6700 Setting to high I0x6A02 VHGH _ PLL _ BWIDTH SETs PLL bandwidth to extremely high I0x7000 SET _ LWP _ RAM SETs laser power DSP0x8000 SEEK _ BACKWARD SEEK to ID DSP0xC000 SEEK _ FORWARD SEEK to OD I

Drive Commands are one or two word Commands that are requested to be either passed to the DSP or to perform some function with 80C188 or passed to the DSP. The Drive Command code is responsible for maintaining the DSP protocol and determining when commands have been completed. In some cases, the command is immediately recognized as completed when 80C188 is performing its function. In other cases, a delay is required when the hardware is allowed to settle (as in the case of a switched-on bias). In the case where 80C188 instructs the PSP to perform a function, 80X188 must wait for the DSP to indicate that the command has completed. See the following driven command Completion, which is a more detailed discussion of the Completion command. The high word of the command for two words is placed in the variable esdi _ cmd. The low word is placed in the variable esdi _ cmd 2. Commands that use only one word still use the esdi _ cmd. These variables are synthetic variables and must be established before calling to the Drive _ cmd function.

Drive Command Descriptions (driver Command description): these small sections below provide a more detailed description of the Drive Command.

SET _ EE _ ADDR: the Set EEPROM Address command is used to identify the Address for the next NVRAM operation. As described below, the address is set first, followed by a READ _ EEPROM or a WRITE _ EEPROM command.

READ _ EEPROM: the Read EEPROM command reads the data currently stored in the NVRAM from the location previously identified by the SET _ EE _ ADDR command.

SET _ JUMP _ BACK _ IN: set Jumpbacks In Command identifies the DSP to make the media spiral face the ID and thus a jump back should perform a seek against the ID once. A jump back is performed every revolution to maintain the optics above the same physical track.

SET _ JUMP _ BACK _ OUT: set Jumpbacks Out Command recognizes the DSP to make the media spiral face the OD, whereby a jump back should perform a seek against the OD once. A jump back is performed every revolution to maintain the optics above the same physical track.

JUMP _ BACK _ ENABLE: a Jumpback Enable Command informs the DSP to perform a jump back in order to maintain the current head position on the medium.

JUMP _ BACK _ DISABLE: the Jumpback Disable Command informs the DSP not to perform a jump back and allows the head to follow the spiral of the medium.

DISABLE _ EEWB: this moiety is TBD.

REQ _ STATUS: the Request status Command requests the current status from the DSP.

SET _ LASER _ THOLD: a Set Laser Read Threshold Command sets an allowable range of a Laser Read power signal. If the read power exceeds the threshold, the DSP issues an abort interrupt.

SET _ FOCUS _ THOLD: a Set Focus Threshold Command sets an allowable range of the Focus error signal. If the focus error signal exceeds the threshold, the DSP issues an abort interrupt.

SET _ TRACK _ THOLD: a Set Tracking Threshold Command sets an allowable range of the Tracking error signal. If the tracking error signal exceeds the threshold, the DSP issues an abort interrupt.

SET _ SEEK _ THOLD: this moiety is TBD.

SET _ SPIN _ THOLD: spindle speed is monitored to ensure that data is written to the media and later recovered. The spindle speed is monitored by the DSP depending on the minimum and maximum RPM specified by the command. If the spindle speed falls below a minimum or exceeds a maximum, the DSP generates an abort interrupt.

The monitor function enables the Drive Command interface to detect when the cartridge reaches normal speed and when the cartridge fails to maintain the correct speed. By setting the minimum RPM to zero and the maximum to the lower RPM of the media rating range, the DSP will interrupt 80C188 when the cartridge actually reaches normal speed. Once normal speed is reached, 80C188 issues a new range to the DSP to specify the maximum and minimum RPM of the media rating range. A minimum RPM of zero indicates that no detection will be performed at the minimum RPM.

BLAS _ TEST: the Bias Test Command requests a Test Bias. The actual steps taken in the Test are described in the next paragraph b.post Definition, Bias Magnet Test.

READ _ DSP _ REV: the Read DSP Firmware Revision Command requests a Firmware Revision level from the DSP.

WRITE _ EEPROM: the Write EEPROM command writes a byte of data to the NVRAM at the location identified above using the SET _ EE _ ADDR command.

REQ _ STD _ STAT: the Request Standard Status Command requests ESDIStandard Status. The provided states include the condition of the driver and the state from the DSP.

REQ _ OPT _ STAT: the Request Standard Status Command requests ESDIOpticalStatus. The provided states include the state of the driver and the state from the DSP.

SET _ MAG _ READ: the Set Magnet Read Command prepares the drive for a Read operation. The Bias command is described in the next paragraphs Magnet Bias, Laser Power and PLL frequency command.

SET _ MAG _ ERASE: the Set magnetic Erase Command prepares the drive for an Erase operation. The Bias command is described in the next paragraphs Magnet Bias, Laser Power and PLL frequency command.

SET _ MAG _ WRITE: a Set magnetic Write Command prepares the drive for a Write operation. The Bias command is described in the next paragraphs Magnet Bias, Laser Power and PLL frequency command.

RESET ATTN: the Reset Attention Command instructs the DSP to unset a status bit that has been set to indicate an error state that generated a DriveAttention interrupt to 80C 188.

Record _ DRIVE: this fraction is the TBD.

STOP _ SPINDLE: stop spin commands open the servo loop and slow down the cartridge speed. The Drive Command code first instructs the DSP to open the servo loop for laser, focus and tracking. The spindle PRM is then set to zero and the brake is applied. After a few seconds (TBD), the brake is removed and the firmware verifies that the spindle is completely slow To (TBD) RPM. Once the spindle slows down, the firmware will again apply the brake and extend (TBD) for a few milliseconds to stop the cartridge. The time to wait for the start of the deceleration and the time to wait for the spindle to stop will depend on whether the cartridge is plastic or glass. The firmware will monitor the spindle ramp-up time in order to determine the type of media loaded. The SET _ SPIN _ THOLD command described above will be used to monitor spindle RPM rate.

START _ spin: the Start spin Command is responsible for speeding up the cartridge, confirming that the cartridge has the correct PRM, and requesting the DSP to perform initialization with the cartridge. As described above, the SET _ SPIN _ THOLD command is used to monitor the spindle RPM achieved.

The ramp-up is a two-step process comprising: (1) a spindle threshold is set to monitor the RPM until the disc cartridge reaches a minimum RPM for a particular media type, (2) a spindle threshold is set to monitor the RPM for the range of the media's rated RPM. If the cartridge up takes too long, the firmware will slow down the cartridge and return an error code (TBD). The drive does not have to exit the cartridge.

A timer will be used to measure the amount of time required to bring the medium up to 4x (default) RPM. The time required to accelerate the cartridge will depend on whether the media is plastic or glass. When recognized, the STOP _ SPINDLE command will use the appropriate pause depending on the cartridge type.

Once the cartridge reaches the desired RPM, the firmware will issue an initialization command to the DSP. At this point, the DSP will attempt to close all of its servo loops.

LOCK _ CART: the Lock card Command sets a flag that generates a series of requests to reject the Cartridge from exiting.

UNLOCK _ CART: an Unlock Cartridge Command clears a flag and allows a series of requests to allow the Cartridge to be ejected.

EJECT _ CART: the Eject card Command slows down the cartridge if it is currently spinning and exits the cartridge. The steps taken to slow down the cartridge are the same as those described above for STOP spin. Once its speed has dropped, the firmware will issue an eject cartridge command to the DSP.

SEEK _ COMP _ OFF: this fraction is the TBD.

SEE _ COMP _ ON: this fraction is the TBD.

SLCT _ FRO _ SET: select Frequency Set Command selects a Set of frequencies. Each media format requires a corresponding set of frequencies for media recording. The Bias Magnet Command described below is used to select a frequency from the group identified by the instruction.

ALLOW _ ATTN _ CLEAR: this fraction is the TBD.

READ _ DRV _ RAM: this fraction is the TBD.

NORMAL _ PLL _ BWIDTH: this fraction is the TBD.

HGH _ PLL _ BWIDTH: this fraction is the TBD.

VHGH _ PLL _ BWIDTH: this fraction is the TBD.

SET _ LWP _ RAM: the Set Laser Write Power RAM Command sets a Laser Write Power value of a specific Laser Power region. The command allows the drive to modify the write power to be used during the diagnostic period during the next erase or write operation performed within a particular power region.

SEEK _ BACKWARD: the format for the Seek Backward Command is represented in the next paragraph Seek Command.

SEEK _ BOEWARD: the format for the Seek Forward Command is represented in the next paragraph Seek Command.

SeeK Command: the format for the two word seek command is shown in table 25 below.

Table 25-Seek Command

hi _ wd (bit) bit 15 seek command being 1

Bit 14 direction bit (1 ═ OD ", O ═ ID")

Bit 13-0 is unused

lo _ wd (bit) bit 15-0 is the number of tracks to look up for

For Seelk Command, "OD" is defined as the direction toward the OD, i.e., away from the spindle motor. "ID" is defined as the direction toward the ID, i.e., toward the spindle motor. The threshold used by the DSP in the seek must be set separately before the seek command is issued. The SET _ SEEK _ THOLD command is used to SET the SEEK threshold.

Magnet Bias, Laser Power and RLL Frequency Command: the BiasCommand is responsible for establishing hardware that enables the drive to read, erase or write at a particular location on the media. The format for the single word BiasCommand is shown in table 26 below.

TABLE 26-Bias, Laser Power, and Frequency Command

(bias, laser power and frequency commands)

hi _ wd (bit) bit 15-12: 0100 for offset command

Bit 11-10: MO bias 01 ═ sensing

10 ═ erase

11 ═ writing

(bit) bit 9: "find way to below" ═ 1

(bit) bit 8-0: zone (laser power and frequency)

lo _ wd (bit) bit 15-0: is not used

In order to read, erase or write at a specific location on the media, the DriveCommand code must establish the magnetic bias, laser write power level (for 2x and 4x only), PLL frequency and DSP focus and tracking threshold. When the Command is ready for an erase or write operation, the Drve Command code must also verify that: the bias magnet is inducing a current between (TBD) V and (TBD) V within a few milliseconds of (TBD). A serial ADC would be used to sample the current that the bias magnet is inducing. The DSP used during read, erase or write operations must be set to focus and tracking thresholds, respectively, prior to this operation. SET _ FOCUS _ THOLD and SET _ TRACK _ THOLD commands are used to SET these thresholds.

There is only one band for 1x media, and there is no Laser Power WriteZone because writes are not supported by 1 x. The number of Laser Power Write Zon-es for 2x will equal the number of bands (i.e., 16 zones). The number of Laser power writes Zones for 4x would equal the number of bands (i.e., 512 bytes formatted media sectors 30 bands and 1024 bytes formatted media sectors 34 bands).

Drive Command Status (Drive Command Status): the valid status from Drive Commandinterface is based on a modified ESDL interface. It can be used together with RAM-5000 series products. The status bits reflect the actual state of the hardware, an error state from the DSP, or a state being managed by firmware. This state has two 16-bit words, commonly referred to as the Standard Status and the Optical Status. The definitions of the Status words and the Status sources are listed in Table 27-ESDI Standard Status and Table 28-ESDI OpticalStatus below. Table 27-ESDI Standard Status Standard Status bit Status source (reserved) 15 (unused) MEDIUM _ NOT _ PRESENT 14 FW maintaining WRITE _ PROTECT 13 FW maintaining OROM _ MEDIA 12 FW maintaining (reserved) 11 (unused) (reserved) 10 (unused) SPINDLE _ STOPPED 9 FW maintaining POWER _ ON _ CONDITION 8 (unused) ESDI _ CMD _ PTY _ FIT 7 from DSPESDI _ INTERFACE _ FLT 6 FW maintaining ESDI _ INVALID _ CMD 5 from DSPSEEK _ FAULT 4 from DSPMAGNET _ BIAS _ FAILURE 3 FW maintaining MAX _ LASER _ POWER _ EXCEEDED 2 (unused) DES _ INVALID _ FAILER 1 (TBD) 360 from ESDI Standard Status source 28-ESDI Standard Status bit Status from PFET _ FORE _ NOTCE 13 (unused) maintaining PFO _ FOUR _ NOTCE _ NOT 12 Status bit Status source (unused) Use) (reserved) 9 (unused) LASER _ DRIVE _ FAILURE 8 from DSPCARTRIDGE _ REJECTED 7 (unused) CARTRIDGE _ INIT _ FAILURE 6 from DSPDRIVE _ HARDWARE _ FAILURE 5 (unused) WRITE _ TERMINATED 4 (TBD) EJECT _ REQUEST 3 from GLICERASE _ BLAS _ IS _ ON 2 FW maintenance WRITE _ BIAS _ IS _ ON 1 FW maintenance DC _ POWER _ FAILURE 0 (unused)

Serial Drive Control Interface: drive Command interface provides a common mechanism to program a range of devices in Jupiter hardware. Selected serial devices for spindle motor control, ADC, read channel components and NVRAM. The serial interface is transparent to the firmware. The Drve Command firmware is responsible for the following tasks: it is understood how to talk to each device to start the spindle, read the bias current on the ADC, or read or write data at a location in NVRAM, etc. It is important that the Drive Command firmware not select all serial chip selects to abort all previous operations still in progress.

Open Issue: all interrupts must be disabled during the execution of the continuous access. Interrupts need to be disabled for 100 mus to 1 ms.

80C188/DSP Communication Interface: instructions to the DSP and their functions are specified in 80C1188/TMS320C-5 XCcommunication document (DSP _ COMM. DOC), Rev XGH-1994, 8.25. For convenience, these commands are listed in Table 29-DSPCommands. Table 29-DSP Commands (DSP Commands)

TABLE 29-DSP commands

DSP_REQ_STAT 0x00DSP_INIT_DRV 0x01DSP_LSR_ON 0x02DSP_CAP_FOCUS 0x03DSP_CAP_FTRK 0x04DSP_CAP_CTRK 0x05DSP_CLOSE_PIN 0x06DSP_JB_EN_IN 0x07DSP_JB_EN_OUT 0x08DSP_SEEK_IN 0x0ADSP_SEEK_OUT 0x0BDSP_OPEN_LOOPS 0x0CDSP_CLR_INT 0x0DDSP_RD_VEL 0x0EDSP_RD_CLOCK 0x0FDSP_EJECT_CART 0x11DSP_GET_REV 0x80DSP_RD_MEM 0x81DSP_WR_MEM 0x82

DSP states Definitions (DSP state definition): table 30 lists the bit definitions for the DSP status bytes. Table 30 also shows how each bit is converted to one bit in the ESDI Standard-ard Status or ESDIOptical Status definitions.

TABLE 30 transition of DSP State to ESDI State

DSP status byte 0 bit ESDI equivalent value status bit DSP _ CMD _ COMPLETE 7DSP _ BAD _ CHECKSUM 6 ESDI _ CMD _ PTY _ FLT Standard 7DSP _ INVALID _ CMD 5 ESDI _ INVALID _ CMD Standard 5DSP _ TRACKING _ ERR4 NOT _ ON _ TRACK OPTICAL 14DSP _ TIMER _ EVENT 3DSP _ FOCUS _ ERR 2 FOCUS _ SERVO _ FAILURE OPTICAL 11
	DSP _ LASER _ POWER _ ERR 1 LASER _ DRIVE _ FAILURE OPTICAL 8DSP _ FOCUS _ LP _ CLOSED 0DSP STATE Byte 1DSP _ FINE _ LP _ CLOSED 7DSP _ COARSE _ LP _ CLOSED 6DSP _ PINNING _ LP _ CLOSED5DSP _ SPINDLE _ SPEED _ ERR4 SPINDLE _ SPEED _ FAILURE OPTICAL 12DSP _ LASER _ ON 3DSP _ JUMPBACK _ IN 2DSP _ EJECT _ FAIL 1 CART _ LOAD _ FAIL OPTICAL 13DSP _ BAD _ SEEK 0 SEEK _ FAULT Standard 4

Drive Command Completion: the command and status phases of the driveCommand are separated in order to provide flexible sequential processing to the 80C188 firmware during execution of commands by the DSP. At this latter point, the 80C188 firmware can specifically wait for the command to complete. Generally, all that is required is: two consecutive commands do not exceed normal limits. Thus, at the beginning of each Drive Command, the firmware must check that the previous Command has completed and, if not, wait a certain Time (TBP) before timing ends.

The commands to the DSP are divided into different types requiring different pauses. One memory access should be completed within 500 mus. The short seek should be completed in 2 milliseconds and the long seek should be completed in 100 milliseconds. Initialization of the DSP takes up to 2 seconds.

The Drive Command firmware must also monitor the suspension of hardware that is responsible for managing components such as biasing and Read Channal. It may take as long as 4.5 milliseconds for the bias to achieve the required field strength. The delay during the Read channel process is (TBD) μ s.

JuKEBOX 20-PIN CONNECTOR SUPPORT: this paragraph describes that various actions taken by the Jupiter driver based on various signals on the 20-pin Jukebox connector (jubuox) will not be checked in the firmware to determine if a Jukebox cable is attached. All signals will be asserted/disabled at the jukebox interface whether or not the cable is connected.

AC Eject: when the AC EJECT signal is asserted on the 20-pin connector, the driver will abort all current operations and transfer all data in the Write Cache to the media. If the cartridge is spinning, the firmware will send out a Drive Command to slow down the cartridge. Once the Drive has verified that the cartridge has stopped rotating (DTB method), the Drive will issue a Drive Command to eject the cartridge.

AC Reset: open Issue. When the AC RESET signal is set on the 20-pin connector, the driver will no longer accept any new commands. While those commands on the current queue will be completed. All data currently in the Write Cache will be placed on the media. Once the driver completes the above function, it will wait for the Autochanger Reset signal to override ACReset before completing the SCSI initialization, as described above.

Cartidge in Drive: the CART IN DRIVE (AKA cartridge present) signal on the 20 pin connector will be maintained IN the withdrawn state regardless of whether the cartridge is IN the DRIVE or not. No firmware support will be provided for this signal. The interrupt may come from External ENDEC. However, no sensor sends a cartridge i entry signal.

Cartidge Loaded: the CART _ load (AKA cartridge present) signal on the 20-pin connector will be set when the cartridge is present, placed in the hub, rotated, and the DSP has completed its initialization including focus and tracking.

Error: the ERROR signal on the 20 pin connector will be set whenever the cartridge ejection sequence fails. There is currently no way for firmware to detect cartridge loading and unloading failures without a cartridge in the access sensor.

LED pipe: the LED _ PIPE signal on the 20-pin connector will be set whenever the LED of the driver is illuminated.

Power Down Request: when the PWRDNREQ signal on the 20-pin connector is set, the drive will complete all Write commands already in progress and then transfer all data in the Write Cac-he/Write buffer to the media.

Power Down Acknowledgeage: when the Write Cache has filled in response to a PWRDNREQ signal, the driver will set the PWRDNACK signal on the 20-pin connector.

Slandalone/AC: the driver may determine whether the 20-pin connector has been connected by detecting the level of the signal on the juke-box (juke-box) interface. If the signal is high, the driver is in a stand-alone mode. If the signal is low, the driver has a 20-pin connector to the jukebox.

DRIVE OPERATION: Non-Volatile RAM (NVRAM): NVRAM will be used in Jupiter driver. Some of the drive parameters (e.g., laser power settings and OEM product information) will be customized and stored in NVRAM. These parameters will be stored in Flash if NVRAM is later removed from the design.

Power Supply Failues: any failure of the 5V or 12V power supply will result in a hardware reset to 80C 188.

Focus Offset Calibration for 1x and 2 x: the DSP will perform the FocusOffset Calibration of 1x and 2x media, optimizing the optimal Radial Push Pull (RPP) signal. Focus offset calibration for 4 x: this fraction is the TBD. The following are the points and issues that will be used during the definition of this section. The Focus Offset Calibra-tion for 4x is executed in two parts. The first part of the calibration is performed by the DSP, where it will be optimized to the best RPP signal, as is done for lx and 2x Focus offset calibration. The second part of the Focus Offset Calibration for 4x will be performed to optimize to the best carrier-to-noise ratio (CNR). This requires 80C188 to write the read data pattern, select the optimum bias and enter the bias into the DSP.

80C188 will command the DSP to use a particular focus bias and then write a ZT data pattern to a sector. The sector is read out and the serial ADC must be read out to obtain the "sample and hold" value within about 100 mus. This process is repeated using various focus offsets until an optimum value is determined. The specific algorithm is TBD. The final value then goes to the DSP.

Write Power Calibration for 2 ×: this fraction is the TBD. The following are the points and issues used during the definition of this section. Open Issue. 80C188 will perform the write power calibration using the following (TBD) algorithm.

Write Power Calibration for 4x (Prewrite testing): this part is the TDB. The following are the points and issues used during this section of the definition. OpenIssue. When the pre-write test is to be performed, we need to discern: (1) initial temperature, all zones examined; (2) the starting temperature, only if that zone is used at the next time; (3) one new area is written at a time; (4) some other algorithm. Also, the pre-written test value has a header. Each of these matters does not affect the design of the present invention as implemented herein by those skilled in the art.

The process of 4x write power calibration is similar to the process of determining 4x focus bias. 80C188 is responsible for writing a series of sectors when changing the write power level of WR 1. One or two sectors must be skipped when performing the next write setup. Once a range of values has been used, the 80C188 reads the same sector and uses a serial ADC to determine the number of readback signals. On the basis of an algorithm (TBD), the optimum write power level is determined.

It is important to note that: the sequence needs to be interruptible and restartable. If a new SCSI command is received in the middle of the algorithm, the driver needs to respond to the command in a timed manner and return to the pre-write test at a later time.

Open Issue. If the drive is performing the pre-write test and a new SCSI write command is received. What the driver needs to do is: (1) abort the pre-write test and execute the write command using the old write power level, or (2) continue to use the pre-write test to determine the new write power level, thereby increasing the overhead of the command. Each of these matters is a matter of design that does not affect the ability of one of ordinary skill in the art to practice the invention as described herein.

Recalibration: this fraction is the TBD. The following are the points and issues used during this section of the definition. When, what to do, temperature monitoring, how long, when the temperature rises, a recalibration needs to be initiated.

What to do is checked against the recalibration. When the drive is recalibrated. Whether the calibration and the recalibration should be the same. Whether a recalibration should be made with a laser current change. These matters are not matters of design that would not affect the practice of the invention as described herein by one of ordinary skill in the art.

DSP calibration includes establishing Focus Offset and RPE Offset. There are two algorithms for calibrating focus. That algorithm to be used has not been determined. The recalibration will be performed as a function of temperature or error recovery procedures. Each 5-10 ℃ rise in temperature, Focus Offset, RPE Offset, and Write Laser Power will be recalibrated. The redaction should be performed when "nothirg else" is processed. If the double correction is in process, the SCSI command it inputs must be interruptible. If the system is still busy for an extended period. Final reduplication must be performed with priority. For each variation in laser readout power, a double correction will not occur.

Flash EEPROM Support: the Write Buffer SCSI Command will be used to add new SCSI firmware to the drive. The drive will not be able to withstand reset or power cycling that may occur during an update of the flasheprom. Very important is that: these factors are cleared so that the end user can attempt to implement the firmware modification: they can never cycle or produce a reset during the disassembly process. If this happens, the drive will need to be sent back to the manufacturer for repair.

The manufacturing requirements are as follows: this fraction is the TBD. The following are comments and questions to be used when defining this section. Trace Buffer Support (whether it is the same as RMA-5300 or not may be considered at design time).

Read Ahead Cache (Read look Ahead Cache): this fraction is the TBD. The following are comments and questions to be used in defining this section: the amount of storage in the cache memory assigned to the read and write sections is set by ModePages hereinafter.

Write Cache (Write Cache): this fraction is the TBD. The following are comments and questions to be used in defining this section. The amount of storage in the cache memory assigned to the read and write sections is set by ModePages. The design takes into account the problems of timed flush (flush) support, Immediate Reporting (Immediate Reporting), Write recording (Write Reordering), etc., which do not prevent one skilled in the art from implementing the present invention in light of the description.

SCSI command execution: this fraction is the TBD. The following are comments and questions to be used in defining this section. Multiple SCSI commands are combined into one media request. One Seek (Seek) is divided into a pre-Seek and a final Seek. The bus occupation algorithm is as follows: buffer Empty Ratio for writing, Buffer fullness Ratio for reading (Buffer full Ratio). These problems need to be considered in the design. Power-ON Hours (number of electrical Hours): the number of hours that the drive has been powered is saved in non-volatile RAM. To accumulate the hours of power supply, the DSP interrupts the 80C188 approximately every 10 seconds (2 '(19'). times.20. mu.s), updates the power supply hours every 2 '(19'). times.20. mu.s passed by the 80C188, and stores the points in the non-volatile RAM. If the driver encounters an error, 80C188 can request the current value of the DSP clock. Only the lower 19 bits are used and added to the number of power hours to provide an associated time stamp for the error event. Note that: 1) the time spent during initialization before releasing the DSP from the reset state is not included. This time can be added each time the driver is powered on. 2) Each time the driver is powered on, a duration of up to the next 10 (about 5 seconds) may be added.

Clean Lens (Lens Cleaning): once it is determined that the lens needs cleaning, the drive should then eject the cartridge and move the actuator into position. The ejection of the cartridge causes a brush to sweep across the lens. When the cartridge clears the throat, the actuator is moved to its normal position. The following is the problem of opening: 1) whether the disc cartridge is held at the throat. 2) When it is safe to move the actuator back to its normal position. 3) If the actuator is moved at the "wrong" time in the process, it will cause any damage to the lens. These matters are to be considered in the design, but do not prevent one skilled in the art from implementing the invention in light of the description.

Firmware Performance: this fraction is the TBD. The following are comments and questions to be used in defining this section. A minimum sector multiple is identified for the medium RPM. A policy for the use of multiple sectors per interrupt. A time limit range for an Interrupt Service Routine (ISR) is identified.

Front Panel Eject Request (Front Panel Exit Request): this fraction is the TBD. The following are comments and questions to be used in defining this section. Whether or not to abort the current command. Whether the contents of the cache memory have been written to the medium first. These are design considerations and do not affect the ability of those skilled in the art to practice the invention as described herein.

SCSI Eject Command (SCSI Exit Command): this fraction is the TBD. The following are comments and questions to be used in defining this section. Whether or not the ejection is performed when the cartidge PresentSwitch indicates that there is no Cartridge. Whether this should be inhibited by a selection switch. The jukebox may or may not want the owner to be able to directly eject the cartridge. These matters are considered in the design, but do not affect the ability of those skilled in the art to practice the invention in light of the description.

OPtion Switches: this fraction is the TBD. The following are comments and questions to be used in defining this section. The hardware reset is enabled (Enable)/disabled (Disable) according to the SCSI bus reset signal (hardware reset is required to be sent for enabling). The SCSI terminal is enabled/disabled. The enable/disable is automatically recognized after writing. Flash memory programming is enabled/disabled for updating SCSI firmware. Enable/disable Exit in SCSI commands. Reserved (Reserved) (TBD number).

FIRMWARE REQUIREMENTS (firmware request): this section contains the Firmware requirements for obtaining a Firmware Functional specification. Diagnostics

1) Serial communication for diagnostics is supported.

2) Serial communication supports access to new firmware.

3) Power On Self Test (POST) diagnostics was developed for new chips and hardware: RLL (1, 7) ENDEC, GLIC (Glue Logic IC), non-volatile RAM, read channel, spindle motor, serial A/D converter, parallel D/A converter.

4) The motor spindle speed should be able to be changed by SCSI commands.

Firmware updates

1) Flash EEPROM for SCSI firmware is supported.

2) The new firmware (SCSI and/or DSP) should be able to be loaded (downloadable) through SCSI.

3) The load operation on the firmware must be recoverable.

DSP Support (digital signal processor Support)

1) It must be possible to load DSP code from the SCSI EEPROM.

2) Communication interfaces for providing command, status and data exchange must be supported.

3) It must be able to support ROM (roadable) DSPs.

4) Different speedometers must be supported for different media formats.

4.20 Pin connector (20 pin connector)

1) The firmware must be able to detect when the 20-pin plug is connected.

2) The firmware should be able to read the lock value of the following 20 pin plug-in signals, Autochang-ERRESET, Autochanger Power Down Request, AutochangderEject, SCSI ID, SCSIPArity Enabled.

3) The firmware must be able to read the current state of Autochanger RESET (unlocked).

4) The firmware must receive an interrupt when the following signals on the 20 pin plug-in are set: autochanger RESET, Power Down Request, AutochangerEject.

5) The firmware must be able to set/deassert the following signals on the 20 pin plug-in: CART _ IN _ DIRVE, CART _ LORDED, ERROR, PWRDNACK (Power Down acknowledged-ge).

6) When setting PWRDNREQ on a 20 pin plug-in, 1) the Write Cache is flushed, then, 2) PWRDNACK is set.

SCSI initialization

1) The SCSI initialization firmware uses a 20-pin plug-in as the SCSI ID source for the driver. If a cable is connected, the signal may be driven by a jukebox. If no cables are attached, a jumper may be installed on the same pin, indicating the SCSI ID to be used.

2) The SCSI initialization firmware uses a 20-pin plug-in as the source of SCSI allowed odd/even Parity (Parity Enable) for the driver. If a cable is connected, the signal may be driven by a jukebox. If no cable is connected, a jumper may be installed on the same pin to indicate whether SCSI odd/even checking should be allowed.

3) The driver must support the user to select the power supply of the terminal.

Reset (Reset)

1) If the SCSI bus reset signal is set, interrupt 3(INT3) is generated for 80C 188.

2) If the Autochanger reset signal is set, an 80C188 interrupt is generated.

3) If the SCSI bus reset is set, the interrupt 3 interrupt service routine must determine from the selection switch whether a hardware or software reset must be performed. If a software reset is performed, the interrupt 3 interrupt service routine reports to the Monitor Task (Monitor Task) that a reset has occurred and the contents of the write cache must be flushed.

4) If the autocohanger sets the autocohanger reset signal during power-on, the driver a) must ignore the autocohanger detect and b) must wait for the autocohanger reset signal to be deasserted before performing SCSI initialization.

5) The autocohanger may set the autocohanger reset signal at any time, thereby changing the SCSI ID of the drive.

Read Channel Support (Read Channel Support)

1) The firmware must set the read channel for the current read operation type.

Write Channel Support 1) firmware must initiate processing of the sampled signal from the Read Channel for the pre-written test sector.

2) The firmware must be able to determine the optimum Write Power Level (Write Power Level) for the current frequency range and current drive temperature.

3) The firmware must transmit the Focus Offset to the DSP for 4x media.

Drive Command Support:

1) the drive command interface must be built on top of the interface for HC 11.

2) The drive command status word definition must be the same as the status word for CP.

3) Jump Back should be enabled/disabled via GLIC register for DSP to read.

4) The direction of Jump Back must be specified for the DSP.

5) The drive command firmware must set the spindle speed appropriate for the media type.

The 6 drive command firmware should be able to verify that the spindle speed is reached.

7) The drive command firmware should be able to sample the temperature of the drive.

8) The Reset Interface Command (Reset Interface Command) then deasserts the SERVO Reset signal (SERVO RESET) every 1 microsecond.

9) The Seek Command must provide a range of physical tracks corresponding to logical tracks in the range from-3355 to + 76724.

10) The drive command firmware may enable/disable biasing and select magnetic polarities.

11) The Bias/Laser/Freq command must fit up to 34 frequencies and Laser power regions.

12) The drive command firmware will notify the DSP to eject the cartridge.

13) When the cartridge has write protection, the drive command firmware should be detectable.

14) The drive command firmware may control chip selection for the serial interface.

15) The drive command firmware uses non-volatile RAM to record events and other drive parameters (e.g., laser power level) to be saved.

10. Processing program of driver Attention signal

1) The drive Attention signal handler must do this to detect the cartridge insertion and arrival at the center. And then the disc cartridge is rotated.

2) After the cartridge is inserted, LOADED, rotated and the DSP is "locked", CART _ load must be set.

3) If the Autochanger EJECT switch is set or the front panel EJECT switch is pressed, the drive a) transfers all queued write operations (flushing the write cache) to the medium, stops rotation of the cartridge, and c) EJECTs the cartridge.

4) The CART _ LOADED should be removed when the cartridge is stopped.

5) During the disk cartridge unloading process, if the DSP reports an eject failure, the Auto-changerERROR signal is set.

6) The driver Attention signal handler must handle and clear the following types of errors: seek Fault, Off Track, Bias Mag-net Fault, Laser Fault, Load/Unload Fault, spindle stall, Write Fault.

Functional enhancements Required

1) Non-media access commands are additionally supported when the drive satisfies the media access command but the media is currently unconnected. (this is often referred to as multi-originator support).

2) The commands are modified to support various command sets (TBD _ HP, IBM, DEC, AppleFujitsu, etc.).

3) The supported command set is increased. (TBD)

4) And adding a combination of Vendor unique detection Data (Vendor Uniqne sensor Data) and detection Key/Code (sensor Key/Code). (TBD)

5) Adding programmable-ROM support.

6) CCW (pseudo write-once ROM-WORM) support is added.

7) A Read look Ahead Cache (Read Ahead Cache) is added.

8) Write Cache (Write Cache) is added, including flushing the flush function of the Cache after a user-selectable delay.

Performance Requirements (Performance Requirements)

1) The interrupt service routine must be able to handle the following minimum sector multiple: 1x 538 microseconds at 3600RPM, 2x 368 microseconds at 3320 RPM, and 4x 272 microseconds at 1900 RPM.

13. Other requirements

1) The firmware should be able to set/deactivate the front panel Light Emitting Diodes (LEDs).

2) The firmware should support a power on time recorder.

3) The firmware should support the cartridge loading recorder.

4) If either the 5V or 12V power fails, the driver will fail (TBD).

Interrupt Sources (Interrupt Sources).

1) The interrupt sources of Jupiter are: i) interrupt 0(INTO), Cirrus Logic SM331(DINT), Cirrus Logic SM330, RLL (1, 7) ENDEC; ii) interrupt 1(INT1), Cirrus LogicSM331 (HINT); iii) interrupt 2(INT2), DSP, GLIC (GlueLogic IC); iv) interrupt 3(INT3), SCSI bus reset signal.

2) DSP interrupt sources are as follows; i) non-abort (Non _ abort) interrupt, seek error, 10 second clock event, command checksum error, unknown command, cartridge exit failure; ii) abnormal termination of the interruption, misconvergence, off-tracking, laser power control, spindle stall error.

3) GLIC disruption sources are as follows: autochanger Reset, Autochanger PowerDownrequest, Autochanger Eject, Front Panel Eject, Cartr-idle Inserted (in the throat), Cartidge Present (centrally located). 4) Cartidge Inserted is not supported by firmware. Error Recovery (Error Recovery)

1) A heroic error Recovery is attempted for each sector after a user specified number of retries and a user specified threshold.

2) Error Recovery should include Recovery using the following Error Recovery scheme. (TBD)

Post deinition: this section contains a description of the tests performed during (Power-on self test) Power-ONSelftest (POST).

1.80C188 register and flag testing

The 80C188 CPU sign, parity, carry and zero flags are checked to ensure that their settings are correct and then reset. The test is performed in two parts. The value OxC5 is first placed in the AH register and then flagged with the SAHF instruction. The reset status of the flag is tested (i.e., JNS, JNP, JNC, and JNZ). And then complement its value and store it in the flag. The status of the flag is tested (i.e., JS, JP, JC, and JZ). Any error condition of the flag will fail the test and force the driver to signal a CPU fault with the LED.

The register test is a ripple test that passes the value OxFFFF through all registers (i.e., AX, BX, EX, CX, DS, DX, SS, BP, SI, DI, and SP). The value 0x0000 is then passed through these registers. If the expected value does not appear in the end of the series, this indicates a test failure and forces the driver to signal a CPU fault with the LED.

Measurement of CPURAM

The CPU RAM test writes an incremental byte pattern (pattern) in two passes to all locations of the static RAM (sram). The near 128 byte block alternating pattern overwrites. The first block pattern during the first pass is Ox00, Ox01, Ox 02. The next pattern is Ox01, Ox02, Ox 03. During the second pass, the pattern is reversed. If at the end of each pass the value contained in a certain SRAM cell read back is incorrect, this indicates a test failure and forces the driver to signal a RAM failure with the LED.

3.80C188 interrupt vector test

Interrupt vector testing the dispatch capability of 80188 is tested using software interrupts. An entry of an Interrupt Vector Table (IVT) is initialized to point to a test Interrupt Service Routine (ISR). The AX register is initialized to Ox 0000. Interrupts are dispatched using INT instructions. The AX register is decremented and the ISR is exited. The value in AX is detected at the time of interruption return. If its value is not OxFFFF, it indicates that the test failed and forces the driver to signal a CPU fault with the LED.

ROM checksum test

The ROM checksum test checks the flash PROM contents with a 16-time basis polynomial. If the calculated checksum is not zero, this indicates a test failure and forces the driver and LED to signal a ROM fault.

For each 16-bit word in the PROM, the lower byte enters the BH register through an XOR gate and BX is multiplied by 2. If the carry flag is set after multiplication (shift), the polynomial Ox38CB passes through the exclusive or gate into BX. The upper byte of PROM enters BH register through XOR gate and multiplies BX by 2. If the carry flag is set after multiplication (shift), the polynomial Ox38CB passes through the exclusive or gate into BX.

SM331 register test

The Cirrus Logic CL-SM331 register test resets SM331 and checks the correctness of the register values after reset. If any of the registers fail the test, the driver reports an inedible status and issues (TBD) error signals with the LED.

The method comprises the following specific steps: 1) setting SM331 chip reset, 2) canceling SM331 chip reset, 3) clearing the Disk Access Pointer (DAP), 4) detecting whether the registers Ox57(BM _ DAPL) to Ox5F are zero, 5) detecting whether the register Ox41(SCSI _ SEL _ REG) is zero, 6) detecting whether the registers Ox43(SCSI _ SYNC _ CTL) to Ox45 are zero, 7) detecting whether the registers Ox48(SCSI _ STAT _2) to Ox49 are zero, 8) detecting whether the registers Ox50(BM _ SCHED _ DATA) to Ox52 are zero.

SM331 Sequencer (Sequencer) test

The Crirrus Logic Cl-SM331 sequencer tests the write control memory (WCS) that writes a pattern to the sequencer and confirms the writing of the pattern. If any of the test sites fail, the driver reports an unclear status and issues a (TBD) error signal with the LED.

The method comprises the following specific steps:

1) the sequencer is stopped. (writing the value Ox1F to the start address)

2) An incremental pattern is written in WCS at each of the 31 locations for the Next Address, Control, Count, and Branch fields.

3) The incremental pattern is verified.

4) A decreasing pattern is written in WCS at each of the 31 locations for the Next Address, Control, Count, and Branch fields.

5) The decreasing pattern is verified.

SM330 ENDEC testing

The Cirrus Logic CL-SM330 ENDEC test resets SM330, clears the GPO register, clears the Corrector RAM, verifies the Corrector RAM, and raises the SectorTransfer countequols Zero interrupt. If any part of the test fails, the driver reports an unclear status and issues a (TBD) error signal using an LED.

The method comprises the following specific steps:

1) the set SM330 chip resets.

2) The SM330 chip reset is undone.

3) Delaying for at least 10 microseconds for the chip to perform the reset.

4) The General Purpose Output (GPO) register is initialized to Ox 00.

5) The corector RAM locations Ox00 and Ox01 are zeroed.

6) The corector RAM locations Ox00 and Ox16 are zeroed.

7) The corector RAM locations Ox20 and Ox27 are zeroed.

8) It is checked whether the corector RAM positions Ox00 and Ox01 are zero.

9) It is checked whether the corector RAM positions Ox0F and Ox16 are zero.

10) It is checked whether the corector RAM locations 0 x20 and 0 x27 are zero.

11) Standard chip initialization is performed as described above.

12) The interrupt vector of SM330 is initialized to point to the test interrupt service routine.

13) A Zero is written in the Sector Transfer Count Register as the Transfer Count, forcing a "Sector Transfer Count equal zeros Zero" interrupt.

14) The firmware waits for the maximum count OxFFFF to decrement an initial register for the interrupt.

8. External ENDEC Test (TBD)

GLue Logic Test (TBD)

10. Buffer RAM testing

The buffer RAM test writes an incremental address pattern to all locations in the buffer RAM and then verifies the pattern. The incremental patterns used are Ox00, Ox01, Ox 02. The test then writes an inverted address pattern to all addresses of the buffer RAM and verifies the pattern. The pattern of reversal used Ox00, OxFF, OxFE. Finally, the test writes Ox00 at all locations in the buffer RAM. If any location in buffer RAM fails, the driver reports an unclear status, but does not signal an error with an LED.

11.DSP POST

The basic function of the DSP is validated by the 80C188 issuing a Read Code review command to the DSP. This command can test the interface between 80C188 and the DSP, access a location in DSP memory, and test the ability to return to a valid state.

Bias Magnet Test (Bias Test)

The Bias Magnet for the write function will be turned on. (to prevent accidental data loss, the laser write power digital-to-analog converter (DAC) may be maintained at the read power level). The effect of the DriveCommand code is to turn on the bias, set the laser write power, and then read the analog-to-digital converter (ADC) to verify the bias line profile (TBD) of the flowing current. The Drive Command code will wait (TBD) for several milliseconds before reading the ADC. If the current is not within The (TBD) range, the driver reports an unclear condition but does not signal an occurrence with an LED.

Register of sm330: this section contains a description of the Ci-rrus LogicSM330, optical disc ENDEC/ECC register, as shown in Table 31 below.

Watch 31

Name of register	Offset of	Description of the invention		R read/write states
					EDC_CFG_REG1	10h	Configuration register		R/W
EDC_CFG_REG2	11h	Configuration register		R/W
					EDC_CFG_REG3	12h	Configuration register		R/W
EDC_SPT	13h	Sector/track		R/W
					EDC_ID_TARG_SEC	14h	ID target sector		R/W
EDC_ID_TARG_TRK_LSB	15h	ID target track LSB		R/W
					EDC_ID_TARG_TRK_MSB	16h	ID target track HSB		R/W
EDC_ID_CMP_SEC	17h	ID comparison sector		R/W
					EDC_ID_CMP_TRK_LSB	18h	ID parity track LSB		R/W
EDC_ID_CMP_TRK_MSB	19h	ID comparison track MSB		R/W
					EDC_SEC_XFR_CNT	1Ah	Sector transfer count		R/W
EDC_SEC_COR_CNT	1Bh	Sector correction count		R/W
					EDC_DAT_BUF_ADR_L	1Ch	Data buffer address high		R/W
EDC_DAT_BUF_ADR_M	1Dh	In the data buffer address		R/W
					EDC_DAT_BUF_ADR_H	1Eh	Data buffer address low		R/W
EDC_REV_NUMBER	1Fh	CL-SH8530 version number		R/W
					EDC_INT_EN_REG	20h	Interrupt enable register		R/W
EDC_MED_ERR_EN	21h	Media error allowance		R/W
					EDC_INT_STAT	22h	Interrupt state		R/W
EDC_MED_ERR_STAT	23h	Media error condition		R/W
					EDC_SMC	24h	Sector mark control		R/W
EDC_RMC	25h	Resynchronization marker control		R/W
					EDC_ID_FLD_SYN_CTL	26h	ID field/sync control		R/W
EDC_ID_ERR_STAT	27h	ID error status		R/W
					EDC_WIN_CTL	28h	Window control		R/W
EDC_TOF_WIN_CTL	29h	TOF window control		R/W
					EDC_SM_ALPC_LEN	2Ah	Sector mark/ALPC		R/W
EDC_LFLD_ALPC	2Bh	LFLD/ALPC		R/W
					EDC_PLL_LOCK_CTL	2Ch	Phase locked loop lock control		R/W

Table 31 shows the sequence

EDC_PLL_RELOCK_CTL	2Dh	Relocking control	R/W
				EDC_LFLD_WIN_CTL	2Eh	LFLD window control	R/W
EDC_RESV2	2Fh	Retained	R/W
				EDC_ECC_COR_STAT	30h	ECC correction status	R/W
EDC_ECC_RAM_ADR	31h	ECC RAM address	R/W
				EDC_ECC_RAM_ACC	32h	ECC RAM access	R/W
EDC_RESV3	33h	Retained	--
				EDC_VU_1	34h	Vendor unique byte	R/W
EDC_VU_2	35h	Vendor unique byte	R/W
				EDC_VU_3	36h	Vendor unique byte	R/W
EDC_VU_4	37h	Vendor unique byte	R/W
				EDC_GPI	38h	Universal input	R--
EDC_GPO	39h	General purpose output	R/W
				EDC_RESV4	3Ah	Retained	--
EDC_TEST_REG	3Fh	Test register	R/W

SM331 REGISTERS: this section contains a description of the Cirrus Loqic SM331, SCSI disk controller registers shown in Table 32.

Watch 32

Name of register	Offset of	Description of the invention	Read/write state
				SCSI_ACC_REG	40h	Specifying SCSI access	R/W
SCSI_SEL_REG	41h	Selection/reselection ID	R/W
				SCSI_PHA_CTL	42h	SCSI phase control register	R/W
SCSI_SYNC_CTL	43h	SCSI Sync	R/W
				SCSI_MODE_CTL	44h	SCSI mode control register	R/W
SCSI_OP_CTL	45h	SCSI operation control register	R/W
				SCSI_STAT_1	46h	SCSI status register 1	R/W
SCSI_INT_EN_1	47h	SCSI interruption permission register	R/W
				SCSI_STAT_2	48h	SCSI status register 2	R/W
SCSI_INT_EN_2	49h	SCSI interrupt enable register 2	R/W
				SCSI_FIFO	4Ah	SCSI MPU FIFO access port	R/W
SF_SECT_SIZE	4Eh	Sector size	R/W
				SF_MODE_CTL	4Fh	Mode control	R/W
BM_SCHED_DATA	50h	Scheduled buffered data	R/W
				BM_STAT_CTL	51h	Buffer status/control	R/W
BM_XFER_CTL	52h	Transfer control register	R/W
				BM_MODE_CTL	53h	Buffer mode control	R/W
BM_TIME_CTL	54h	Buffer timing control	R/W
				BM_DRAM_REF_PER	55h	DRAM refresh cycle	R/W
BM_BUFF_SIZE	56h	Buffer size	R/W
				BM_DAPL	57h	Disk address pointer low	R/W
BM_DAPM	58h	In the disk address pointer	R/W
				BM_DAPH	59h	Disc address pointer high	R/W
BM_HAPL	5Ah	Host address pointer low	R/W
				BM_HAPM	5Bh	In the host address pointer	R/W
BM_HAPH	5Ch	Host address pointer high	R/W
				BM_SAPL	5Dh	Stop address pointer low	R/W
BM_SAPM	5Eh	In the stop address pointer	R/W
				BM_SAPH	5Fh	Stop address pointer high	R/W

Table 32 sequence

SF_SYNC_BYTE_CNT_LMT	70h	Sync byte count limit	R/W
				SF_OP_CTL	77h	Operation control register	R/W
SF_NXT_SEQ_ADR	78h	Next formatting sequence control	R
				SF_BRANCH_ADR	78h	Branch address	W
SF_SEQ_STAT_REG1	79h	Sequencer status register 1	R
				SF_SEQ_STRT_ADR	79h	Sequencer starting Address	W
SF_SEQ_STAT_REG2	7Ah	Sequencer status register 2	R
				SF_INT	7Dh	Interrupt register	R/W
SF_INT_EN	7Eh	Interrupt enable register	R/W
				SF_STACK	7Fh	Stack	R

E.glic REGISTERS: this section is illustrative of MOST Manufacturing, Inc. glue _ Logic Integrated Circuit (GLIC) registers, as shown in Table 33 below.

Watch 33

Name of register	Offset of	Description of the invention	Read/write state
				GLIC_DSP_REG	00h	Common register for DSP	R/W
GLIC_JB_CTRL_REG	01h	Coin-feed gramophone control register	R/W
				GLIC_INT_EN_REG	02h	Interrupt enable register	R/W
GLIC_MIO_REG	03h	Hybrid control registerDevice for cleaning the skin	R/W
				GLIC_JB_INP_REG	04h	Input register of coin-feed gramophone	R
GLIC_WPR_DAC0	04h	Write power DAC0	W
				GLIC_INT_INS_REG	05h	Service interrupt register	R
GLIC_WPR_DAC1	05h	Write power DAC1	W
				GLIC_WPR_DAC2	06h	Write power DAC2	W
GLIC_WPR_DAC3	07h	Write power DAC2	W

Except for driving abnormality: status and error handling problems

Tables 33-43 below summarize the "exception" handling problems related to the firmware of the present invention, which are specific to such firmware.

The next goal is to discuss the missing items/changes, the data integrity assurance issues, and the scheme of what function the drive performs (considering the logical, cost, and human impact).

Comments and preconditions:

1) The purpose of this directory is to include all drive exception handling conditions.

2) The best mode presently contemplated by the present invention is disclosed at the time of filing this application, in which power regulation, laser feedback, and media readout level damage thresholds are considered. From this point of view, focus detection at all read levels should occur during drive initialization in the inner radius region, so that a safe way of starting drive operation is taken (read power and focus detection never occur in the data area, just sustain).

3) The recovery section refers to the drive stopping and non-volatile error recording due to recovery failure. These failures are identified and recorded, but do not prevent the user from attempting to execute the command again. This is dangerous for the integrity of the user data, and some compensation is provided by the non-volatile error logging.

4) Assume that there is more than one initiator (initiator) on the SCSI bus.

5) Error detection cannot be disabled (although interrupts may be masked).

6) Exception handling priority is 1) data integrity, 2) cost issues, 3) system performance, 4) error logging capability.

7) Some of the drive tool design methods and the specific exception handling timing are determined by the market we are facing. A highly contaminated environment and a highly vibrating environment may require different performance for a particular embodiment.

8) The DSP does not provide a plan to accomplish the additional capabilities for the communication tests currently supported and the reset tests beyond the error condition described.

9) For correctness of the supply polarity, bits 2 and 5 of the GPO register need to be checked. There are no other exceptions in the table:

1) "Power On", "Hard Reset" and "Soft Reset" have been mentioned above.

2) Exception processing of "Invalid SCSI Command" illegal SCSI commands "and" ImpoperSCSICommand "is described in conjunction with SCSI processing.

3) The "Power Failure" (5V and 15V) will typically trigger a Power-on reset, as described above. However, a power failure for the different processes (only 12V interrupt to DSP, no 5V in the design) is discussed here. This is not disclosed at the time of filing this application. However, the details of this problem are merely further elaborated and do not affect the operability of the invention described herein.

4) The "Laser Write Power Error" is reserved for monitoring the Laser Write Power level during periods when no writing is performed or is ongoing.

5) The erroneous Write state of the "Write Fault" flag inside 188 is triggered by a rotation Fault (or the like). This flag was originally triggered by real-time measurement of bias current. Real-time measurement of bias current is a next step problem. The problems that appear in the following list are design considerations and do not affect the implementation of the invention as described in the specification by those skilled in the art.

Watch 34

Error detection
							Signal	Read power	Rotate	Focusing	Tracking	Finding	Pop-up
State filter	Whether or not	Whether or not	Is that	Is that	Whether or not	Whether or not
							Critical time (accuracy)	No (not tried)	Is that	Is that	Is that	Whether or not	Whether or not
Sampling rate/error time	TBD to 1msec + TBD	16.7 to 31.6msec (1 rev + TBD)	50Khz80usec	50Khz80usec	TBD+TBD	5sec
							Write interrupt abort/non-abort	Abnormal termination	Abnormal termination	Abnormal termination	Abnormal termination	Non-abnormal termination	Non-abnormal termination
188 shielding capability	No-yes?	Is that	Is that	Is that	Is that	Is that

Watch 35

Error determination
							Signal	Read power	Rotate	Focusing	Tracking	Seek path	Quit
Decision filter	Is that	Is that	Is that	Is that	Whether or not	Whether or not
							Critical in time	Is that	Whether or not	Whether or not	Whether or not	Whether or not	Whether or not
Sampling rate/error time	ASAP	TBD＞100msec	y msec	y msec	10msec	TBD＞100
							Description of the determination	The initialization process and focus detection require 100 ms recovery and verification periods	Detecting 100 ms normal state in 1 second, if unsuccessful, recovering	Moving the state threshold to the read level, detecting the x millisecond normal state in the y millisecond period, and if not successful, recovering	Moving the state threshold to the read level, detecting the x millisecond normal state in the y millisecond period, and if not successful, recovering	Recovery is performed directly	Recovery is performed directly

Watch 36

Error recovery
							Signal	Read power	Rotate	Focusing	Tracking	Finding way	Quit
Priority	1	5	2	3	4	12
							Statement of recovery	1) Turn off the laser and open the loop completely	1) Resetting the rotation to the correct speed	1) All open loop and perform initialization drive on DSP	1) The fine and coarse tracking loops are opened, the fine tracking loop is closed, and the coarse tracking loop is closed. (can send out a seek	1) Open fine and coarse tracking loops and send initialization drives to the DSP	1) Reissuing the exit instruction
	2) Reinitializing power (initialization drive) in non-data area 3) monitoring power state for 100 msec	2) A 100 ms normal state 3) in which the rotation state is monitored within 1 second opens the loop and stops rotating all together if it fails,retry for 3 times	2) Success in monitoring the initialization drive status 3) if it fails, all open loops and 3 initialization drives are issued	2) Monitor tracking state 3) if failed, a third error will cause the fine and coarse tracking loops to open and send out the initialization drive to the DSP	2) Failure of the initialization drive may result in full open loop and the initialization drive (full drive) 3) if failure, a third failure of the full initialization drive may result in drive stop (non-volatile error log)	2) Three complete exit failures can result in drive stalls (non-volatile error log)
								4) The second error will force the drive to stop (non-volatile error log)	4) A third error can cause the drive to stop (non-volatile error recording)	4) A third error can cause the drive to stop (non-volatile error recording)	4) Failure of the initialization drive results in full open loop and initialization drive (full initialization)
				5) A third failure of the full initialization drive will result in a drive stop (non-volatile error log)

Watch 37

Source of abnormality
							Signal	Read power	Rotate	Focusing	Tracking	Finding way	Quit
	Laser feedback, media reflectivity, and drive errors.	Shaking, vibration, media imbalance, thermal shutdown, and drive error.	Shaking, vibration, media damage, media change, thermal shutdown, and drive error.	Shaking, vibration, media damage, media change, thermal shutdown, and drive error.	Shaking, vibration, media damage, scale changes and drive errors.	Mechanical squeezing of the medium is faulty and driven.

Watch 38

Signal	Read power	Rotate	Focusing	Tracking	Finding way	Quit
									Non-volatile error logging for all recovery attempts.	Non-volatile error logging for all recovery attempts. Whether the drive can support focus capture (laser feedback, etc.) in the data area.	Non-volatile error logging for all recovery attempts. And (4) PROM function. Item "1" is to test pattern/verify. A mode is initially requested for identifying that the focus ring is open.	Non-volatile error logging for all recovery attempts. Recovery problems in accident conditions.	Non-volatile error logging for all recovery attempts. Whether the DSP can detect the cam position. Whether the exit motor can sustain the stall current without burning out.

Watch 39

Error detection
							Signal	ID of wrong track finding	Magnetic bias	Sector mark	Track-sector ID	Data read ECC level	Internal parity error
State filter	Is that	Whether or not	Is that	Is that	Is that	Whether or not

Critical time (accuracy)	Whether or not	Is that	Is that	Is that	Is that	Is that
							Sampling rate/error time	2/header	1/write operation	1/header	2/header	1/sector	TBD
Pre-WriteCondAbort／Non-Abort	Pre-Abort	Pre-Abort	Pre-Abort	Pre-Abort	N/A	Abort
							Shielding capability	Is that	Is that	Is that	？	Is that	Is that
Description of the Filter	Reading: writing: checking: to successfully read a track and sector ID, the two header track numbers must match.		Reading: writing:checking: the four fifths and three quarters symbols must coincide.	Reading: writing: checking: the two track and sector numbers must coincide.	Reading: the threshold is set to the TBD voltage to support reading and detection of reassignments.
												Checking: the threshold is set to the TBD level (below the read level) to support checksum relocation.

Watch 40

Error determination

Signal	ID of wrong track finding	Magnetic bias	Sector mark	Track-sector ID	Data read ECC level	Internal parity error
							Decision filter	Whether or not	Whether or not	Is that	Whether or not	Whether or not	Whether or not
Critical in time	Whether or not	Is that	Is that	Is that	Is that	Is that
							Sampling rate/error time	1/header	1/write operation	1/header	2/header	1/sector	TBD

Table 41

MistakesError recovery
							Signal	ID of wrong track finding	Magnetic bias	Sector mark	Track-sector ID	Data read ECC level	Internal parity error
Priority	6	7	8	9	10	11
							Statement of recovery	Reading: writing: checking: the track is found 3 times again to obtain a match of track numbers. If it fails, an error is reported to the host and the non-volatile memory.	Writing: an unclear magnetic failure bit is set and no writing is performed. Recorded in a non-volatile memory.	Writing: checking: 1) a failure to verify any SM will result in a band scan for a given medium (see "media format") 2) a failure of a given sector will result in a sector relocation.	Writing: checking: 1) failure to verify either ID results in a band scan that must match both track and sector numbers for a given medium (see "media format") 2), or else results in sector relocation.	Reading: the ECC level is maximized and the data is restored. Read again 3 times. If above the TBDECC level, it is relocated. Checking: if the ECC level is higher than the TBD, the sector is relocated.	Reading: writing: checking: the operation was retried 3 times. Errors are recorded with the host and the non-volatile memory.

Reading: 1) failure to verify any SM will result in a band scan given the media (see "media Format") 2) failure of the designated sector will result in excessive recovery, including reducing the required SM from 3 to 0 (using the resultant sector mark)

Reading: 1) a failure to check any ID will result in a band scan of a given medium (see "media format") 2) retries 3 times. The over-restoration includes a match of one of the two tracks and sector numbers.

Watch 42

Source of abnormality
							Signal	ID of wrong track finding	Magnetic bias	Sector mark	Track-sector ID	Data read ECC level	Internal parity error
	Media damage, media change, and drive error	Thermal shutdown and drive error.	Media damage, media change, and drive error	Media damage, media change, and drive error	Media damage, media change, and drive error	Drive error

Watch 43

Problem(s)
							Signal	ID of wrong track finding	Magnetic bias	Sector mark	Track-sector ID	Data read ECC level	Internal parity error
	The error is recorded in a non-volatile memory.	Do it after writing? Data integrity related to bias failure during writing.	Record too big recovered error? High error sector relocation.		It is a problem that sectors written at a predetermined time are relocated.
									The thermal shutdown is automatically reset. Hardware current limits need to be identified.

Read Ahead Cache (Read Ahead Cache)

This section describes the Read Ahead Cache original operation for the RMD-5200-SD drive. First, an overview of the cache memory will be briefly described, and then, each cache memory component will be described. This section also illustrates the testing of operations for the Read Ahead Cache.

256 cache codes are based on 128 cache codes. There are only two differences in the two modes of operation (except for the invocation of the media specific function). First, the 256-cache ISR contains delayed error handling. (delayed errors are media errors detected before error correction of the previous sector is complete.) the second difference is that the 256 mode does not diagnose "sequencer stop" errors. These differences are not important to the operation of the cache. Thus the description herein does not distinguish between 256 and 128 caches.

The look-ahead cache code is generated before this. The present invention includes modifications to the original code. These changes are to improve data integrity and to add 256-mode functionality. The changed features are not described here in focus, but the rules of the currently best mode of the code are described.

Cache Overview: cache Enable Conditions: the cache is enabled only if the following conditions are met, 1) the RCD bit of mode page 8 is set to zero, 2) the current SCSI command is Read _6 or Read _10 in LBA mode addressed, or 3) the current SCSI Read command is completed without any error. This includes the stages of the CheckCondition state and relocation. If any relocation is performed in order for the SDL to be updated without delay, no caching is performed. Cache Prefetch Operation: the prefetch operation begins at a logical block immediately following the last logical block of the previous READ command. Errors that occur during prefetch operations are not reported to the originator unless the target fails to correctly execute subsequent commands due to the effect of the error. An error may be reported in a subsequent command.

Cache Termination: the caching is terminated when either of the following conditions occur, 1) the last LBA being cached is read, 2) an unrecoverable read error has occurred and retry has been applied, 3) a Bus Device Reset has occurred, 4) a conflicting SCSI command is received (a "conflicting" SCSI command is one that requires Drive seek, access to the buffer, or changes Drive parameters (spindle speed, media fetch block status, etc., see below), or 5) a Drive Attention occurs.

Cache Components: mode Page 8: mode Page 8 defines the parameters that affect read-ahead caching. However, only the RCD bit (byte 2 bit 0) has a practical impact on read-look-ahead caching in RMD-5200-SD. This bit is the Read Cache Disa-ble bit. Implicit in this name, when the bit is set, caching is disabled.

The other fields in the Mode Page 8 cannot be executed and cannot change their default values.

Drive Structure Cache Parameters: the cache parameters indicating read-ahead cache status are stored in the drive structure drv _ cfg:

1)Cache_ctrl(UINT)

the various bits represent the current state of the cache:

Ox0001：CACHE ENABLED

set when mode page 8 allows caching, in LBA mode

The last READ command from the host is either Read _6 or Read _10, and

and has blocks that can be cached.

Ox0002：CACHE_IN_PROG

Indicating that the hardware is performing a cache read. In the high speed buffer

Set on start of read from cache, and when cache is started

The ISR is reset when tcs is queued in the cache queue.

Ox0004：CACHE_STOP

Set by the Cache Monitor task to notify the Cache

The memory ISR finishes caching.

Ox0008：CACHE_TCS_ON_Q

Indicating ISR from Cache tcs at Cache

Monitor queuing. After another cache is started

This tcs should be handled before reading.

Ox0010：CACHE_START_SCSI_XFER

By RdDataInCache upon a cache hit

The function is set. The bit indicates that the read processor can start immediately

SCSI transfer.

Ox0020：CACHE_ABORT_READ_TASK

Set by Cache Monitor to indicate that control should return to SCSI

Monitor Task。

Ox0040：CACHE_MORM_IN_PROG

Indicating that the current read operation is for the desired data.

2)cache_start_lba(ULONG)

The first LBA is cached.

3)cache_cur_lba(ULONG)

LBAs after the last LBA are cached.

4)cache_buff_addr(ULONG)

Corresponding to the buffer address of cache _ start _ lba.

5)cache_xfer_len(UINT)

The number of blocks left to the cache.

6)cache_blks_rd(UINT)

Number of blocks of cache.

7)cache_free_space(UTNI)

Free space available for caching data.

8)cache_free_space_predict(UINT)

Free space for caching data is desired.

Cache Functions: the functions that are called when caching is enabled, the order in which they are called during a simple caching sequence is described briefly below.

CheckQueurouting (Old Task, New Task): both SCSI MonitorTask and CacheMonitor Task can handle TCSs from SCSI selection ISRs. Only one of the two jobs executes the role at a time. The variable SCSI-mon-task is used to indicate which job is used to receive any further SCSI select TCS. CheckQue-u routing will specify scsi _ mon _ Task as New _ Task. In addition, OLd _ Task queued for filtering. Any TCS from the Drive Attentention ISR or from the SCSI select ISR is transferred to the New _ Task queue. The other TCSs are relocated.

CheckQueurouting is called by both SCSI control when switching between SCSI Monitor Task and CacheMonitorTask.

Computer _ cache _ rng (): this function is an assembler that is invoked before normal read operations begin, after which caching can be performed. This is done by calculating the first LBA to be cached and the maximum number of blocks that can be cached (cache _ xfer _ len). The transfer length of the cache is truncated according to the maximum available free space and the maximum LBA. Computer _ cache rng () also initializes drv _ cfg. cache _ blks _ rd to 0. Enable bit in drv _ cfg. cache _ ctrl is set if transfer length is valid.

Prep _ Cache (): this function is an assembler that functions to determine whether a normal read has been completed. If so, the following cache parameters are initialized: 1) drv _ cfg, cache _ free _ space, 2) drv _ cfg, cache _ free _ space _ predict, 3) drv _ cfg, cache _ buff _ addr. Prep _ Cache () returns TRUE when the Cache can be started, otherwise returns FALSE.

Cache ISR (RA _ Cache _ ISR or gcrraC _ ISR): the cache ISR is a simplified version of the normal read ISR, which is simplified to the extent that: 1) upon completion of ECC, the ISR only checks for the availability of free space and the end of the burst. Unlike normal reads, cache is independent of SCSI transfers, so there is no need to check SCSI notification status; 2) the cache ISR does not identify the type of error, other than the sequencer stall error, and the cache does not modify any error thresholds on retries, so it is not necessary to determine the particular type of error; 3) the CACHE ISR checks the CACHE _ STOP bit in drv _ cfg. CACHE _ ctrl each time ECC is completed. If this bit is set, the ISR stalls further caching.

Because of this simplification, the Cache ISR returns only three Cache states: 1) return RA _ XFER _ CMPLT when the cache block has been successfully read and a new seek requires the cache to continue; 2) returning to RA _ RD _ ERROR when any other ERROR occurs except for the ERROR caused by the sequencer stopping; 3) RA _ SEQ _ STOPPED. Such errors are treated separately because the act of correcting requires restarting the sequencer.

REQUEST _ task (new task): the Request _ Task sets the state of the calling Task to SLEEP, and simultaneously activates New _ Task. The Request _ task also holds the instruction pointer value in the calling function. New _ Task will start execution (indicated by the saved instruction pointer) at the point where it last called Request _ Task.

Cache Monitor Tas k: activation of Cache Monitor Task: and activating the Cache monitor Task by the Read Task at the moment when the last transmission data is returned to the host. Once activated, it processes TCSs from the SCSI select ISR, the Drive Atten-tion ISR, and from the Cache ISR.

Cache Monitor Task is not activated by just placing a TCS in its queue, and from this point of view it is not a real Task. In contrast to this. As described above, it is called in by the Read Task by calling in the REQUEST _ TASK (New _ Task). Initially, the Cache Monitor Task is to be executed starting from the outermost Sleep () statement. The Cache Monitor TASK returns control to the Read TASK by another call to REQUEST _ TASK.

It should be particularly noted that while the Cache Monitor Task is active, the Read Task is using a TCS and has not yet returned to the system. When control returns to SCSI MonitorTack, the SCSIMonitor Task is still waiting for this particular TCS.

SCSI Monitor Functions: part of the role of the Cache Monitor Task is to process the TCR from the SCSI selected ISR. When the SCSI Monitor Task receives a READ command and the Modepage 8 has not yet disabled caching, the Cache Monitor Task receives the TCS from the SCSI select ISR. At this point, the SCSI Monitor Task rearranges its TCS by calling CheckQueurouting (SCSI _ MONITOR _ TASK, CACHE _ MONITOR _ TASK).

The Cache Monitor Tack organizes the SCSI commands into three levels, including 1) conflicting commands, 2) simultaneous commands, and 3) sequential commands. Based on the classification of the command, the Cache Monitor Task may abort the Cache, execute the command, or stop and restore the Cache.

Conflicting Command (Conflicting Command):

conflicting commands are those that require the drive to seek, access the buffer or change drive parameters (change spindle speed, media fetch inhibit status, etc.). Upon receiving a conflicting SCSI command, the Cache Monitor Task closes and terminates the Cache abnormally. The SCSI Monitor Task is relocated. The following commands are defined as conflicting commands: rezero Unit, previous/AllowMedia Removal, Format, Write _10, Reassign Block, Seek _10, Erase _6, Erase _10, Write _6, Write/Verify, Seek _6, Verify, Mode Select, Read Defect Data, Reserve Unit, Write Buffer, Release Unit Read Buffer, ModeSense, Read Long, Start/Stop, Write Long, Send diagnostic-cs, All vector Unit command.

Current Command: concurrent commands are those that can be executed without affecting the state of the cache. The following instructions are defined as simultaneous commands: TestUnit Ready, Inquiry, Request Sense, ReadCapacity.

Continuity Commands: consecutive commands are read commands that may require cached data and initiate additional cache reads. Only two commands are divided into consecutive commands. Namely Read _6 and Read _ 10.

Processing Cache ISR TCS: the Cache Monitor Task receives the TCS from CacheISR and then calls RaCacheIsrProc () to process the TCS.

Cache Monitor Task Deactivation: if any SCSI READ command is received that requires non-cached data, control returns READ Task. If the cache is finished due to a SCSI Reset, Bus Device Reset Message, conflicting SCSI commands, or Drive Attenttion, control returns to SCSI monitor-or Task.

When the Cache Monitor Task is deactivated, control returns Read Task, which may then return control to the SCSI Monitor Task. The control flow is determined by the cache Task state set by the CacheMonitor Task. When the Read Tack is relocated by calling REQUEST _ TASK, it can evaluate the cache TASK state. Three cache task states are described next. 1) RAC _ TERM: this state indicates that the cache has been aborted. The Read Task will return to the SCSI Monitor, which immediately returns the READCS and fetches the next TCS from the queue. It is worth noting that the SCSIMonitor Task does not proceed to the STATUS phase as it normally would, because all of the STATUS and commands have been sent out as part of the transfer to the CacheMon-iter Task. 2) RAC _ CONT: this state indicates that a new READ command has been entered and that all or part of the requested data has been cached. The Cache Monitor task has already initiated the SCSI transfer and the Read Processor needs to wait for the arrival of the SCSI TCS. 3) RAC _ NEW _ REQ: this state indicates that a new READ command has come and that the requested data has not yet been cached. The Read Processor needs to initiate a "normal" Read and then wait for the TCS from the Read ISR.

RaCacheIsrProc (): this program is called by the Cache Monitor Task and functions to perform the function of Read Task with respect to disk transfers. It processes the TCS from CacheISR, updates the appropriate parameters in the drive structure, and initiates additional read operations as required.

StopCacheinprog (): this procedure is called when the Cache Monitor Task receives a "continuous" READ command. Its purpose is to completely end the current caching process. It checks the CACHE _ IN _ PROG bit to see if the CACHE is IN progress. If so, the CACHE _ STOP bit is set to notify the CACHE ISR to end the CACHE. The delay of 5ms enables the CACHE to finish and then the CACHE _ IN _ PROG bit is checked again to see if the ISR has stopped caching. If the bit is not cleared, it is assumed that the cache is shut down by some other device. IN this case, the CACHE _ STOP and CACHE _ IN _ PROG bits are cleared.

Rddatalncache (): this procedure is called by the Cache Monitor Task when it starts processing a "continuous" READ command. Its role is to determine if the cache required for the new read hits. CACHE _ START _ SCSI XFER bit is set in drv-cfg CACHE _ ctrl if CACHE hit. Rddatalncache also modifies drv _ cfg. rw _ scsi _ blks to reflect how many required blocks have been cached.

If the cache has hit, but not all required data has completed the cache, the RdDataInCache modifies the drive structure data to indicate how many blocks have been read, how many blocks are to be read, and where the read should be resumed.

Read Ahead Cache Performance Test: test Description: a cache test program called ct.c is programmed. This cache test program operates in conjunction with the SDS-3(F) host adapter. This procedure was modified slightly to obtain the ctt.c.ctt.exe of the read-look-ahead cache that was originally used to verify the RMD-5200-SD.

CTT tested the cache in the first 64K LBAs. A unique pattern is written in each of these LBAs. This pattern consists entirely of 0X5A, with the first four bytes being overwritten by the block's hexadecimal LBA address (except for LBAO, which is set to 0 XFF). The CTT first checks the LBAO and if no expected pattern is found, the CTT initializes the disc. If the LBAO matches, the disc is considered to have been initialized.

After disc initialization, the CTT performs sequential reading of 64K blocks multiple times. The same transfer length is used in each time. The transmission length is doubled in the next time. Due to the limited buffer size of the host adapter, the maximum transfer length used is 64 blocks. A comparison is performed on each read data to verify the integrity of the data.

Test Options: logging Results to a File (Co-mmand LineOption): the user can, by executing command line C: ex. If a log file is designated, any result normally copied on the screen is also copied into the log file.

Target ID: the CTT can test various target IDs, although it cannot be done in one execution.

Number of Ltertiary: the user may specify the number of times the CTT performs the entire test.

Initial Transfer Length (Initial Transfer Length): the user may specify the initial transfer length. The transfer length is doubled in each subsequent pass until the transfer length exceeds 64 blocks.

Pause Between Reads): the CTT always executes one pass between reads without interruption. Alternatively, however, the CTT may be paused between reads of one pass. This choice ensures that the driver has time to complete all or part of the cache, depending on the latency. A partial cache is tested to ensure that the drive can reliably stop the cache. All caches are tested to ensure that the drive stops caching when the buffer is full.

Pause Length: the user may also be asked for a pause duration in milliseconds if a pause selection is selected.

Halt on Errors (go out of outage): the CTT also asks whether the test should be stopped when it encounters a false state (e.g., data mismatch or check condition status). Downtime is useful when the user is not filing results in execution, such as when testing frequently fails.

Disc Drive Firmware Architecture

This section explains the structural changes required when using the disk controller chipset of Cirrus Logic and implementing Jupiter-1 using RMD-5200-SD firmware as the basis.

The Jupiter-1 architecture may reduce the number of tasks required in the system. SCSI Monitor-or Task (referred to herein as Monitor Task) can control all functions of a driver. ReadStask and Write Task may be incorporated into a Drive Task. The function of Read Ahead cacheMoritor Task can be decomposed: duplicate monitor functions may be omitted and cache functions may be moved to the Drive Task. Particular variations of the (SCSI) monitor Task and Drive Task are described above.

Interrupts: the interrupts for Jupiter-1 are divided into four classes. These include non-masked interrupts (NMI), SCSI interrupts, Drive interrupts, and Drive Attention interrupts.

The NMI is generated when the SCSI Bus RESET signal is set, when the 20-pin plug ACRESENT is set (TBD), or when PWRDNREQ (auto changer power off request) is set.

When the first six bytes of a command are received, a SCSI interrupt is generated when a SCSI Bus Att-entry signal is set, when a SCSI parity error occurs, when a buffer parity error occurs, or when SCSI transfer is completed.

Driver interrupts may be generated by three chips: namely SM331, SM330 or external ENDEC. The SM331 interrupt occurs when the format sequencer stops or when an ECC correction vector parity error is detected. The time when the SM330 interrupt in 1x or 2x mode occurs is: when a valid ID is read, a media error occurs, an ECC error occurs, a Sector Transfer Count register is decremented to zero when a corrupted Sector is encountered, or an interrupt occurs when an Operation is generated. The SM330 interruption in 4x mode occurs when an ECC error occurs or an Operation Complete interruption is generated. The time that the external ENDEC interrupt occurs in 4x mode is: when a valid ID is read, a media error occurs, a corrupted Sector is encountered, the Sector Transfer Count register is decremented to zero, the end of an erase or write exception, or when an index pulse is generated.

The driver Attention interrupt is generated by a DSP or a Glue Logic IC (GLIC). The DSP generates a Drive Attention interrupt in the following cases; when the system can not be initialized correctly and track finding faults occur, the speed of the spindle motor is normal and the speed of the spindle motor is abnormal when a state of being separated from tracking is detected. The GLIC generates a DriveAttention interrupt in the following cases: when the AC Eject is set, when the front panel Eject button is pressed, when the Eject Limit signal is set, when the carriage Sensor signal is toggled, and when the carriage sensed Sensor signal is toggled.

Multi-Tasking Kemel (multitask core): identification message types (identification information type): current architectures provide a means of identifying the particular type of information received. A popular way is to query the information source and sometimes use the "status" of the information as its category. Integer variables of TCS ID, TCS Source ID, and TCS Destination ID are converted into byte variables. Adding a new byte variable for the information category maintains the additional bytes remaining in the TCS header. The information category variable serves as an identification field in a different (Vari-ant) record.

Current Processing (simultaneous Processing): jupiter-1 requires concurrent processing to enable the Drive to a) perform command queuing and b) respond to a non-media access instruction in a multi-originator environment when issuing a read or write request to a Drive Task. This structure causes the SCSI Monitor Task to block execution until the Read Task or Write Task completes processing the current request.

Simultaneous processing in Jupiter-1 can be achieved by: 1) disallow Monitor Task blocking after a request is sent to a Drive Task, 2) incorporate all tasks into the round-robin schedule to "co-cache" CPU resources, and 3) allow the Monitor Task to take priority of either the Drive Task or the Low-Level Task when a non-disconnect command is received. To achieve 1) above, the Monitor Task may use a new core service to send the request to the DriveTask. When a Drive Attention occurs, the task receives information from the task registers, the existing way of which needs to be changed. The Dri-ve Attention information path is discussed in detail below. Project 2) implementation of round-robin scheduling is described in the following paragraph. Item 3) the preferred embodiment will be described later in the next paragraph. It should be noted that if preemption is not used, a signal (Semaphore) is required to manage the SCSI interface. The new core service requires testing, testing and setup, as well as clearing the SCSI-in-use signal.

Round-Robin Scheduling: in order for each task to have "equal" access to the CPU resources, each task must release the CPU at periodic intervals. The blocking of the execution of a task while it waits for the next message to arrive in its queue has achieved the above requirements to some extent. According to the requirement of simultaneous processing, the waiting time caused by the running time required by the Monitor Task and the time of surrounding the CPU by the Drive Task should be as small as possible. The issue that preemption can sometimes involve latency is discussed in the next paragraph.

If preferred possession is not required, the CPU is automatically shared between jobs. The current task is blocked when the core calls for waiting for the next message, while the core is searching for a ready task. When the core performs such a search, the scheduling latency may be minimized by: 1) reducing the number of tasks that need to be checked, 2) reducing the possible states in which one task is located. Eliminating a Read Ahead Task and merging separate tasks for reading and writing to various media types into one Task can reduce the number of tasks. Details of task merging are described in further detail below.

Possible states set in one task include a state of "waiting for specified information". This state should be discarded as needed for simultaneous processing, and should therefore be removed from the system. There should be only three possible states: active, waiting for information, and dormant. The core code for tasks checking for dormancy and tasks checking for waiting information has been highly optimized. The Ready List of tasks does not significantly increase the execution process. The core needs an additional 11 seconds to test two additional jobs before returning to the check on the original task.

Preemption (Preemption): the Jupiter-1 structure needs to be prioritized to such an extent that one non-disconnect command received during a disconnected media access command can make the Monitor Task take precedence of the Drive Task or the Low-Level Task. Up to now, the Drive Task is not required to have priority to Monitor Task or Low-Level Task. It is proposed herein that the Drive Task should be caused to restart some part of its processing, rather than delaying the non-disconnect command by ten or tens of milliseconds.

Inside the Drive Task and Low-Level Task, a part of code (in particular the heroic recovery program) is needed to identify the part where the process needs to be restarted if the Task is preempted. The DriveTask and Low-Level Task will record themselves at the beginning of these parts to identify the start of the restart. This is similar to the record of Drive Attention. If a Drive Task or Low-level Task is an active Task but has no records, it is considered that the Task can be fully preempted. That is, the task may be interrupted and resumed from the same point thereafter without harmful effects.

When the SCSI ISR receives a new command, a new core call is made at the exit of the ISR to determine if preemption is required and if so, dispatch. If the Task being executed before running the SCSI ISR is a Monitor Task, there is no need for preemptions. If the current Task is a Drive Task or a Low-Level Task, the Task is preempted.

If a new non-disconnect command is received by the SCSI ISR while the drive is processing a disconnect media access command, the ISR calls the new core service at the exit to detect if a task is itself logged. If not, the Task is preempted by the Monitor Task and resumes from the point where it was interrupted when the round-robin scheduling resumes. If the Task is recorded, the kernel will a) turn off the Drive, b) take the Drive out of the Spiral Mode (a Drive Task comm-and to the DSP), c) direct the Drive Task or Low-Level Task to restart from the recorded address, and d) transfer execution to the Monitor Task. After the Monitor Task has processed the new command, it will make a core call to wait for the next message. The core will then enter an idle loop looking for a ready task. The Drive Task or Low-LevelTask is still ready and the core will dispatch to this Task and resume execution from the recorded address with the value in AX indicating the occurrence of a restart.

If it is pre-empted by the Monitor Task, any media access will be destroyed while the CPU is monitoring some of the disc's contents in real time (i.e., waiting for sector markers). This portion of the code needs to be managed by logging for restart in the event of preemption.

Once a Drive Task or Low Level Task initiates media access, the hardware and disk ISR will continue the burst, causing the Task to end completely, and send a message to the Task indicating that the burst has completed. The task then responds, dequeues the message, and starts the next burst. The preempting after the hardware has been started does not cause any problem with the drive control.

During an implicit seek for media access, the seek code disables the SCSI interrupt, attempts to read the ID, and waits 16 milliseconds for an ISR to read the locked ID. During this 16 millisecond period, the SCSI ISR is not operational, which means that the SCSI bus is temporarily occupied in the middle of the Commandphase (after the first six bytes have been read by the SM 331). In the event of a successful seek, the SCSI interrupt remains disabled after all registers are set, and after the sequencer is enabled, during the time the ID is read from the seek code until the seek code returns to the set code (i.e., gcr _ StartDrvf). To better address this issue, the new structure will allow the Monitor Task to take the seek first. This may be done by recording the seek code and then allowing the SCSI interrupt for preemptive use. If a SCSI interrupt occurs while the seek is in progress (requiring preemptive engagement), the DSP ends the seek and sets the drive to Jump Back. (assume here that the DSP can queue the Disable Spiral command while ending the seek). If a SCSI interruption (requiring preemptive ownership) occurs after the end of the seek but before the hardware boot, the code should restart from its recorded address and eventually perform the seek anew. If a SCSI interrupt occurs after hardware startup, media access may be fully preempted and thus no recording is required.

Stack Size: the stack size of each task is currently set to 512 bytes. For Jupiter-1 to expect increased modularity and for additional layers to manage command queuing and caching, etc., it may be necessary to increase the size of the stack to 1024 bytes. If the number of tasks is reduced to 3, the memory allocated to the stack is actually reduced.

Drive configuration structure (Drive configuration structure): identi-location of MediaType (media type identification): the firmware needs to determine the type of media inserted into the drive in order to assign the appropriate program for each media type. Independent bits in the Drive Con-configuration variable "input" are used for various media types: 1x, 2x, and 4 x.

Drive State Variable: as required by the above described simultaneous processing, the Monitor Task must be able to determine the current state of the drive and issue appropriate information corresponding to newly arrived events. This can be achieved by introducing a new "drive state" that is independently maintained by the Mon-itorTask. Table 44 lists possible drive states. Table 44-Drive status power up, phase 1 (no select) power up, phase 2 (busy) power down soft reset hard reset load cartridge spindle accelerate spindle decelerate exit tape cartridge interleave seek Read buffered Read unbuffered Read cache write cache clear cache, then power down clear write cache, then exit disk cartridge clear write cache, then reset Drive Task can change status from "Read" to "Read, Connected" or "Read, Disconnected".

Power On Self Test (Power On Self Test): ROM Checksum: (ROM detected sum): ROMTest typically calculates the sum of detections of a single EPROM. According to the two-chip design of Jupiter-1, the ROM sense sum range must include the address range of both chips. The address range of the two chips is 0xC0000 to 0 xFFFFF.

Buffer RAM Diagnostic (Buffer RAM Diagnostic): in the case of 4MB Buffer RAM, the Buffer RAM diagnostic takes a much longer time. Jupiter-1 is required to be able to process a SCSI selection after 250 milliseconds. Such firmware typically has a two-phase initialization. PhaseI initialization is the disallowing of a selection during the driver's execution of self-diagnostics, which typically includes Buffer RAM diagnostics. Once it is established that the drive is substantially complete, the drive enters Phase II initialization, at which point it may process a selection and respond only to test Unit Ready or InquiryCommand. During PhaseII, the drive reads the EEPROM, initializes Inquiry Data, ModePageData, and other various Data structures. The Jupiter-14 BM Buffer RAM test should be performed during Phase II initialization.

RAM Diagnostic: if the RAM diagnostic time for both SRAM chips is too long, the test can be split and the remainder of the Buffer RAM test performed during Phase II initialization in the manner described above.

Autochanger Reset (auto changer Reset): if the drive detects that the Auto changerReset has been Reset, the drive must wait for the Auto-changer Reset to be cancelled before attempting to read the used SCSI ID from the 20-pin plug-in and whether SCSI Parity is allowed. The Jupiter-1 driver may perform all of its Phase I initialization while the AutochangerReset is reset. When the driver is ready to initialize the SCSI portion of SM331, it checks the GLIC chip to see if a 20 pin plug is connected. If there is no connection, a select jumper is used to determine the SCSIID and whether SCSI Party is allowed. If a 20 pin plug is connected, the driver queries the GLIC chip to monitor the actual level of the Autochanger Reset. When the Autochan-ger Reset is deactivated, the signal from the 20-pin plug-in will determine the SCSI ID and whether SCSIParity is enabled.

Boot Task: initialization Code (Initialization Code): the code for Phase II initialization is contained within the Boot Task. The Boot Task performs initialization, generates other driver tasks, and then replaces itself with the code of the Monitor Task. It takes a certain amount of time to cover the Boot Task with the Monitor Task. Jupirter-1, in turn, loads the Phase II initialization code into a program that is first executed in Monitor Task. After initialization is performed, the Monitor Task goes to the code it normally executes. Due to the control loop of each task, the execution of a task never leaves its control loop. The initialization code is set before the task ring, so the initialization code is only executed once when the core initially generates the task.

Single Read and Write Task (Single Read and Write Task): existing architectures provide separate tasks for 1x read, 2x read, 1x write, and 2x write. It is never possible to install more than one type of media at the same time. Only one read or write function can be performed at a time. Thus only one media access session is required, Read/Write Task.

Phase II initialization code generates only a single read/write task, referred to as DriveTask in this discussion. The next few paragraphs provide further details.

Cartidge initialization (Cartridge initialization): the initialization of the disc cartridge is performed when the disc cartridge is powered on already in the drive or when the disc cartridge is inserted after power-on. Current architectures perform initialization as part of the Boot Task when powered on. If the cartridge is inserted after power-on, initialization is performed as part of a Drive Attention Handler, which is an Interrupt Service Routine (ISR). Based on the new interrupt structure and timeout information from the DSP, the cartidge initialization function must be performed by the task in order for the task to receive the information in its queue (only the task has a queue). The Phase II initialization code now transmits a message to the Drive Task to perform cartridge initialization at power-on and when the cartridge is inserted. Details of cartridge initialization are discussed below.

(SCSI) Monitor Task: current Process-ing (Simultaneous processing):

drive State Management and Control: the MonitorTask can respond at this time to maintain the "driver state" variable. The following subsections illustrate the relationship between each SCSI command received, the status of the drive, and various information used throughout the drive architecture. As described above, table 44 provides a list of drive states.

Non-Media Access Command: monitor Ta-sk remains responsive to the execution of non-media-access commands, such as Test UnitReady, Inquiry, and Mode Sense.

Start/Stop Spindle Command: in the existing architecture, SCSI Monitor Task implements Start/Stop Spindle Co-mmand. In order to achieve simultaneous processing when executing the command, this command must be executed by a separate task. When the initialization of the disc cartridge is performed, the drive state is "Spinning Down" for structural compatibility. Please see the following about LOW-Level Task.

SCSI Seek: the SCSI Seek Command will be processed by the Drive Task. This is needed to enable the Monitor Task to support simultaneous processing when a new command is received. The Monitor Task changes the driver state to "Seek" and sends a Seek execution message to the Drive Task. The Drive Task will send a "Seek Status" message back to the MonitorTask indicating that the request has been satisfied.

Media Access Commands (Media Access Commands): the Monitor Task is responsible for transmitting a message to the Drive Ta-sk for each read, verify, delete, write/verify and format instruction. The Monitor Task may set the driver state to "Read", "Write", or "Format" as required. The Monitor Task does not stop its execution while waiting for the Drive Task to meet its requirements. The Drive Task will go to Monitor Task. A status message is returned indicating that the request has been satisfied.

Read State and Caching: when the Monitor Task receives a read request from one of the initiators, it checks whether the current Mode Pa-ge 08h allows reading of the cache. If allowed and there are no other commands in the queue, the Monitor Task will transfer a message to the Drive Task, start processing the Read request, and then start the Read Ahead Cache. At this point, the drive state changes to "Read, With Caching". If there are additional commands in the queue, Monitortask determines whether the next command excludes the cache. If so, the information is passed to the Drive Task, the Read request is started to process, and then the Read AheadCache is started. The drive state at that time will change to "Read With Caching". If there are other commands in the queue, the Monitor Task determines whether the next command excludes the cache. If not, the information passed to the Drive Task indicates that caching should not begin and will set the Drive state to "Read, WithoutCaching".

If the Read cache is allowed and started, and another command is received thereafter, the Monitor Task (executing concurrently) determines whether the Read ahead cache should be stopped. For example, if the received command is a write request, the monitor Task may send a message to the Drive Task to abort the Read Ahead Cache and discard all data in the Cache. If the received command is a Read request, the Monitor Task transfers a message to the Drive Task, stops the Read Aheadcache, and retains the cache data. The following will relate to the related problem of handling the DriveAttention information.

Write State and Caching: when the MonitorTask receives a write request from an originator, it checks whether the current Mode Pa-ge 08h votes to allow caching. If allowed, and there are no other commands in the queue, the Monitor Task will send a message to the Drivetask to process the write request as required. The state of the drive at this time becomes "WriteRequest, With Ca-chip". If there are other commands in the queue, the Monitor Task determines if the next command is blocking the cache. If so, the information passed to the Drive Task indicates that caching should not be performed and sets the Drive state to "Write request WithoutCaching".

If Write Cache is allowed and another command is received, the Moni-tor Task (executing concurrently) will determine if the Write Cache should be stopped. If the received command is, for example, a read request, the Monitor Task should transfer a message to the Drive Task to stop the Write Cache and inject all the data in the Cache to the media. If the received command is a write request, the Monitor Task does not act, but simply queues the command until the current request is satisfied before processing. The following will discuss the relevant issues of handling Drive Attention information.

Catastrophic Events: catasterophilic Events are defined as SCSI BUS Reset or Power Down Request from the auto changer. When one of these events occurs, an NMI ISR (unmasked interrupt service routine) is caused to send a message to the Monitor Task. As described below, the Monitor Task takes corrective action based on the driver status.

When a "SCSI BUS Reset" command is received, the Monitor Task checks the current drive status. If the current Drive state is the "Write" state, then the "Flush Write Cache" information is transferred to the Drive Task and the Drive state is changed to "Flush Write Cache, the thenReset". When the Drive Task returns a "Flush Status" message, the Monitor Task checks the Reset Bit in byte 14 of VendorUnique Mode Page 21 h. If a hardware Reset is configured, Monitor Task sets the drive status to "Hard Reset" and then jumps to the boot address (OFFFFOh) to initiate the hardware Reset. If a software Reset is configured, the Moni-tor Task sets the driver state to "Soft Reset" and then initiates the software Reset. If a "SCSI Bus Reset" message is received while the drive is in the "Read" state, the Monitor Task checks the Reset Bit in byte 14 of the vector Unique Mode Page 21h and initiates a hardware or software Reset as instructed.

Upon receiving the "Power Down Request" message, the Monitor Task checks the current drive status. If the current Drive state is the "Write" state, a "Flush Write Cache" message is sent to the Drive Task and the Drive state is changed to "Flush Write Cache, the then Power Down". When the Drivetask returns an "F1 ushStatus" message, the Monitor Task changes the driver state to "Power Down" and sets the PWRDNACK signal on the 20 pin plug-in. When the "Power Down Request" information is received and the drive is in the "Read" state, the Monitor Task sets the drive state to "Power Down" and sets the RWDNACK signal on the 20-pin plug. Note: take other action or remain unchanged after PWRDNACK is set.

Command queuing: note: connected (tagged) or disconnected queuing. These matters are matters of design that do not affect the ability of those skilled in the art to practice the present invention as permitted and disclosed herein.

Drive Task: the Drive Task is used to perform cartridge initialization, SCSI seek, and all media access and caching functions. Since only one type of media access can occur at a time, and only one type of cache is supported at a time, the task should be single. The Monitor Task will send a message to the Drivetask requesting the appropriate service.

Service SCSI Commands (SCSI service Commands): when the Drive Task receives a request to service a SCSI command (seek, read/verify, erase/write, or format), the Drive Task firmware branches to the appropriate path for read, write, or format, and then to the path for 1x, 2x, or 4x media format. The code for each media type may also be stored as a separate set of modules, as previously described for maintainability and stability.

Cartidge Initialization (Cartridge Initialization): the cartridge initialization function will be performed by the time the Drive Task receives a message from the Monitor Task at power-on. If the cartridge is inserted after power is turned on, the Drive Attention Handler transmits a "cartidginous inserted" message to the Monitor Task. The Monitor Task will select the driver state as "LoadingCarddge" and send the "Initialize Cartidge Request" information to the Drive Task. The Drivetask then transmits "spin Start/Stop Request" information to the LOW-Level Task, see below. Once the cartridge is successfully loaded and reaches rotational speed, the DriveTask determines the cartridge type and media format, reads the four Defect Management Areas (DMAs), rewrites any DMAs as required, and initializes the management structure for the failure. When the initialization is completed, the DriveTask will transmit an information of "Initialize card Status" back to the Monitor Task. The drive state may then become "idle".

Read and Read Ahead Cache: the Read code in the Drive Task is responsible for managing the Read process, Read Ahead Cache, determining the time when the hit occurs, or determining the access of the medium. Information from the MonitorTask controls the read, cache, or non-cache actions of the Drive Task.

When the Drive Task receives a read request, the read request indicates whether caching should begin after the read completes. The "Read Request, Widthont Ca-ing" information indicates that the DriveTask should not intend to cache any data. The "Read Request, with caching" information indicates that the Drive Task should plan to extend the Read to the cache. When the Drive Task receives one of these messages, the Monitor Task has set the Drive state to the appropriate read state.

The Drive Task may receive other information in performing the non-cache read, ignoring the original cache and not extending the read. If "Stop Re-ad Cache" information is received, the Drive Task will only satisfy the non-cached portion of the read. If the cache has not started, the DriveTask does not start a look-ahead read. If the cache has already started, the read-ahead is turned off and all cached data is retained. The Read Mode state diagram is shown in FIG. 122. If the "Abort Read Cache" information is received, the Drive Task will only satisfy the non-cached part of the Read. If the cache has not started, the Drive Task will not start a look ahead read. If the cache has started, the look-ahead is turned off and all cached data is discarded.

The Read Ahead Cache will Cache each sector from the last LBA, ABA, or Cache tracking sectors until 1) the "Stop Read Cache" or "Abort Re-ad Cache" information is received, 2) the maximum prefetch requirement is met, 3) there is no free space in the buffer RAM, or 4) a sector cannot be recovered within the current threshold.

The Drive Task must necessarily maintain the Drive Attention Router (DAR) flag (token). If Drive Attenttion occurs while performing advanced reading, Srive Task must be made aware of the Attention status, take appropriate action to clear the status, and begin recovery operations. The management of DAR flags is discussed below.

Write Cache: a discussion of this problem is illustrated with reference to fig. 123. The task of writing code within a DriveTask is to decide when to access the media, manage WriteCache, manage Write Cache buffer latency, and flush the Write Cache. The information from the Monitor Task controls the action of the write process. When the Drive Task receives a request to write, the information indicates whether the data can be cached. The "Write Request, With Caching" information indicates that the Drive Task may Cache data based on the Immedia Flag in the CDB and the current contents of the Write Cache. The "Write Request, withholding" information indicates that the Drive Task is not possible to cache data in any case.

The Drive Task may receive other information while performing a Write of the Cache to inject the contents of the Write Cache. If "Stop Write Cache" information is received, the Drive Task will satisfy the current Write request and then inject all cached data to the media. If the "Flush Write Cache" information is received, the Drive Task will satisfy the current Write request and then inject all cached data onto the medium if the Write request is in progress, or inject all cached data onto the medium if there is no ongoing Write request.

The function of the Write Cache is to take advantage of the dependency of data from multiple SCSI Write requests. Consecutive sectors from multiple requests can be combined into one medium access with less processing overhead. Consecutive sectors may be cached. Non-contiguous sectors may cause sectors already in the cache to take the longest time to transfer to the medium.

The Maximum time allowed for data to remain in Buffer RAM is specified in Maximum Buffer Latency in the Mode Page 21 h. When a write request is cached, the Drive Task requests the Timer Service to send a message after the end of the time specified in the Maximum Buffer Latency. If the Drive Task receives timeout information before the data is transferred to the medium (due to the non-continuity of successive requests), the Drive Task starts transferring the data (and all successive data) to the medium. If the sector forces a data transfer to the medium because it is not connected, the Drive Task requests the Timer Service to not send the previously requested timeout.

Only one timeout is needed each time the buffer delay time is monitored. This timeout is for the first write request that is cached. If subsequent requests are consecutive, this request should be cached with the first one, and when the first request is to be written to the medium, the latter request is also written to the medium with the first one, so that the timeout is single. If the latter request is not continuous, the first request is written to the medium, its timeout is cancelled, and a new timeout is requested for the latter request. Only one timeout is required.

The Drive Task must necessarily save the Drive Attention Router (DAR) flag. If Drive Attenttion occurs while the Write Cache is executing, the Drive task should be made aware of the Attenttion state, take appropriate action to clear this state, and begin recovery operations. The management of DAR flags is discussed below.

Low-Level Task: the responsibility of the Low-Level Task in this design is to handle system requests for read, verify, erase, write, or extensive recovery of sectors. The use of these requests is during the read of Defect Management Areas, during the rearrangement of a sector, during the automatic relocation of sectors, during the recovery of write errors, and during the extensive recovery of read errors. The new responsibilities of the Low-Level Task also include processing Spindle Start/Stop Requests and EjectCarddge Requests.

According to the requirement of simultaneous processing, the Monitor Task can not inquire the main shaft or exit event any more when waiting for a new SCSI command or waiting for timeout. Accordingly, these functions are moved to the Low-Level Task. The Low-Level Task has its own Task queue and can be blocked while waiting for various events to occur.

When the Low-Level Task receives the "Spindle Start/Stop Request", it will send out a Drive Command to Start or Stop the Spindle, and then monitor for timeout. Upon receiving a Drive Command to start the spindle, the Drive Command firmware will issue an appropriate speed Command to the spindle motor control chip. A command is also issued to the DSP to monitor spindle speed and to issue an interrupt when the spindle reaches the required minimum speed.

In order to monitor the time required by the spindle start function, the Low-Level Task sends a request to the TimerService for receiving information in units of (pending) seconds. The Low-Level Task then waits for one of two messages. The Drive AttentionHandler receives a request when the DSP issues an interrupt that the spindle reaches speed. Low-Level Task, a registered recipient of Drive Attention information, will receive "SpindLeAt Speed" information. Timer Service receives notification that the Spindle timeout is no longer needed and sends a "Spindle Start/StopStat-us" message back to Monitor Task. If the spindle timeout information is received, the spindle motor has not reached the prescribed speed. A Drive Command is issued to Stop the Spindle and a "spin Start/Stop Status" message is returned to the Morn-iter Task. Proposals have been made to monitor the function of the stopped spindle.

Timer service: one new active service of Jupiter-1 is the System TimerService.

The Timer Service has a dedicated Timer 1 and Timer 2 (as prescalers). Timer 0 is available to the firmware at any time. It is the responsibility of the Timer Service to transmit a message to the requester after a specified time has elapsed. If there are multiple overlapping requests, the Timer Service is responsible for managing each request and generating information at the correct time.

The Timer Service may accept two types of requests: insert Timer Event and Remo-ve TimerEvent. When an Insert Timer Event request is received and there are no other outstanding requests, the Timer Service starts timers that specify the total number of clock signals (clocks), allows the timers to interrupt, places the request in the header of its timed Event table, and returns a handle (handle) of the timed Event to the caller. If a Timer interrupt occurs, the Timer Service removes the request from the header of the timed event table and sends a message to the requester. If the Timer Service receives a timed event request when one or more requests are outstanding, the Timer Service places the requests in the timed event table in the proper order, queued for a small to large delay period. All timed events in the table are managed by delta time. If a new request for a timed event is queued before an original request, the delta time for the original request and subsequent events in the table are recalculated. If the timeout for a newly received request is shorter than the timeout for the event currently at the head of the queue, the timers are reprogrammed and the event list is sorted in new increments.

If a Remove Timer Event request is received, the Timer Service identifies the timed Event using the handle returned from the Inserttimer Event request and removes it from the timed Event table. If the removed event is originally on the head of the timed event table, the timers reprogram the next event in the table for the remaining time and drop the table in new increments. If the removed event is originally in the middle of the table, the increment of the removed event causes the table of events to be sorted down.

NMI ISR (unmasked interrupt service routine): an NMIISR may be invoked if a SCSI Bus Base or Power Down Request from an auto changer event occurs. The ISR will query the Glue Logic IC (GLIC) to determine the source of the interrupt, and then transmit the information to the Monitor Task. The Monitor Task takes the corrective action described above based on the received information.

If the SCSI Bus Reset bit in the GLIC (TBD) register is set, the setting of the SCSIBus Reset line results in NMI and a "SCSI Bus Reset" message is passed to the MonitorTask. If the Au-changer Reset bit in the GLIC (pending) register is set, the setting of the Autochanger Reset line has caused NMI and a "Autochanger Reset" message is sent to the Monitor Task. If the AutochangerPower Down Request in the GLIC (pending) register is set, the setting of the Autochanger PWRDNREQ line results in NMI, and an "Autoch-anger Power Down Request" message is sent to the Monitor Task.

Drive events: drive Attention is an exception event with respect to events such as out of track, seek fault, or exit request. This section of this document explains the process that needs to be reported to the firmware when a DriveAttention occurs, and in this case what information will be generated.

Drive Attention Notification: when a Drive Attention occurs, a different recovery procedure may be required depending on what the Drive is doing when the event occurs. For example, if the drive is idle and happens to be off track at this time, recovery is not required. On the other hand, if a read is being performed, the drive needs to seek again and then continue with the read operation.

The task with the current interface to the drive knows the appropriate measures for recovery based on what the task has done. Therefore, a notification of the occurrence of Drive Attention must be communicated to the task that is currently interfacing with the Drive. Since the task is not always the task currently being executed, each task must identify the time it incurs the Drive attachment. Thus, the first notification mechanism is to transmit a message to the task responsible for it when a Drive Attention occurs. This responsible task is demarcated by a variable task-id-router, which is managed by all tasks in common.

The first mechanism relies on each task waiting to receive information, one of which may be Drive Attention information. Stopping queries to the queue can significantly reduce computing power if the firmware does not intend for information. A second notification mechanism may also be employed that does not rely on tasks to query DriveAttention information. At a critical point in the firmware, if Drive Attention occurs, the task may record a piece of code to point to. If Drive Attention does not occur, additional time other than recording/non-recording is not required.

Drive Attention Handling and Concurrentness: the Drive Atten-tion Handler performs like an ISR, first a short ISR with interrupts disabled, and then a larger Handler with interrupts enabled. The following example 1 provides an illustrative protocol.

Example 1

The seek is ongoing and SCSI interrupts are disabled. A Drive Attention occurs due to a track finding failure of the Drive. The Drive Attention Handler operates like an ISR. If another SCSI command is intended, the first six bytes will be processed by hardware. The other remaining bytes need to wait for PIO processing in the SCSI ISR until after the Drive Attentention re-enables the interrupt. The SCSI interrupt is still masked because the drive was previously seeking. Thus, the intermediate SCSI bus for a command may be occupied during the entire recovery time performed by the DriveAttentHandler (including recalls if necessary).

Drive Attention Events and Messages：

The Attention source is determined.

The information is transmitted to the recipient of the current record of Drive Attention information.

Information for AC Eject Request, Front Panel Eject Request, Spindle AtSpecd, and Eject Limit is transmitted.

The automatic spin-up and initialization are not performed when the disc cartridge is inserted.

Drive Attention Routing and Caching: when the Drive AttentTransuter flag is needed, the Monitor Task transmits TCS to terminate the Read AheadCache.

The record of Drive Task must be maintained as that Task for receiving Drive Attention information when executing the Read Ahead Cache. If a Drive Attention is ready to occur (e.g., out of tracking), then the Drive Task needs to take corrective action. The Monitor Task should send a message to the Drive Task informing it of the abnormal termination and return a Drive Attention Router flag.

SCSI Transfer: PIO Mode: if the transfer size is greater than (pending) bytes, the data is copied to Buffer RAM and then DMA'd away therefrom.

SCSI Messages：Bus Device Reset，Terminate I/O，and

Abort.

Events：List of Events.

Message Types：

Current TCS Sources Types

SCSI_TCS Pass request from Monitor Task to Drive Task

ATTN_TCS From Drive Attention Handler

LL_RD_TCS Request for Low-Level Read

LL_WR_TCS Request for Low-Level Write

ERCVRY_TCS Request for Sector Error Recovery

Will be replaced by:

Messages

SCSI Bus Reset

Autochanger Reset

Autochanger power Down Request

Drive Attention TCSs

Error(Seek Fault，Off Track，Cartridge Not At Speed，etc.)

Cartridge in Throat

Cartridge on Hub

electric Request (automatic converter or front panel)

Eject Limit

spindle At Speed

Timer Event Request

Timer Event Occurred

Spindle Start/Stop Request

Spindle Start/Stop Status(OK，Fail)

Elect Cartridge Request

Eject Cartridge Status(OK，Fail)

Initialize Cartridge Request

Initialize cartidge Status (OK, Fail; Cartridge type)

Drive Attention Router(DAR)Token

Return Drive Attention Router(DAR)Token

DAR Returned

Seek Request

Seek Status (DAR Token return)

Read Request，with caching

Read Request，without caching

Read Status

Stop Read Cache (to send Read Request)

Abort Read Cache，flush Read Cache

Write Request，with caching

Write Request，without caching

Write Status

Stop Write Cache (flush to complete Write to Write Cache)

Timed Write Request (Write selected Write Cache part to media)

Flush Write Cache (Reset or Power Down Request)

Flush Status

Hardware requirements: 1)2K RAM to mirror the non-volatile RAM to meet fast access to the stored data. This helps to meet the requirements of the non-disconnect commands (i.e., Mode Sense and LogSense). 2) Elapsed Time Counter for power on hour count.

An electronic circuit:

the driver electronics is made up of three circuit components: an integrated spindle motor circuit, as shown in FIGS. 101A-101G; a flexible (flex) circuit with preamplifier, as shown in fig. 102 and 105; and a main circuit board including a main driving function, as shown in fig. 106A to 119.

Integrated spindle motor circuit

The spindle motor plate has three functions: one function is to receive the actuator signal on connector J2 in FIG. 101A and pass it to the motherboard via connector J1 in FIG. 101G. Other functions of the board are a brushless spindle motor driver and a coarse position sensor preamplifier. These functions will be described in detail below.

With continued reference to FIGS. 101A-G, the circuit shows a drive for the spindle motor. The spindle motor driver circuit contains U1 in FIG. 101F, which is a brushless motor driver, and various elements for stabilizing the spindle motor (motor not shown). U1 is programmable and uses a 1MHz clock provided by the motherboard. U1 sends positioning pulses to the motherboard on the FCOM signal terminals, enabling the motherboard to monitor spindle speed.

The circuits of fig. 101A-G are also used to generate a coarse position error. The error signals are generated by operational amplifiers U2 and U3. U2 and U3 use a 12 volt power supply and a +5 volt power supply. The +5 volt supply is used as a reference. The reference signal passes through the ferrite bead to input pins 3 and 5 of U3, U3 has 487K feedback resistors R18 and R19 in parallel with 47 picofarad capacitors C19 and C20. Two transimpedance (transimpedance) amplifiers U3A and U3B receive inputs from position sensitive detectors located on actuators (not shown). The detector resembles a split detector photodiode. The amplifier U2A has a gain of 2 for differentially amplifying the outputs from U3A and U3B. The output of U2A is sent to the main circuit board as a coarse position error.

The reference level of the other operational amplifier U2B is generated on input pin 6 by resistors R23 and R17. This reference level requires the sum output of the transimpedance amplifiers U3A and U3B, the sum of which appears at node 5 of U2B, which should be the same voltage from the voltage divider resistors R23 and R17 at node 6. Feedback capacitor C21 causes U2B to form an integrator, driving transistor Q3 through resistor R21. Q3 drives an LED whose light impinges on a photodiode (neither shown). This essentially forms a closed loop system that ensures certain voltage levels output from the transimpedance amplifiers U3A and U3B.

Referring to fig. 101A-G, another function of the plate is that the motor exits the drive. The motor driver is a darlington Q1, see fig. 101E, with current limited by transistor Q2 and dependent on resistor R7. The diodes D1 and C11 are used to suppress noise of the motor (not shown). The cartridge eject mechanism position is detected by the hall effect sensor U4, see fig. 101D, and is used to determine the position of the gear train until the cartridge is ejected. There are also three switches WP-SW, CP-SW and FP-SW on the board for detecting whether the cartridge is in a write-protected state, whether a cartridge is present, and whether the front panel switch requests the main processor to eject the cartridge.

Pre-amplifier

There are two embodiments of preamplifiers. The general elements are shown in FIGS. 102A-D and 103A-D. The elements that differ between the two embodiments are shown in fig. 104A-105B.

The optical module flex lead(s) shown in fig. 102A-105B have three primary functions. One is a servo transimpedance amplifier part; second, read channel read preamplifier; third is a laser driver.

Connector J4 and signals from U1 are shown in FIG. 102A, as shown in FIG. 102B, which are transimpedance signals. TD and RD are two four-wire detectors for servo signals. During the initial alignment, X1 is not connected to X2, so four lines can be aligned individually. Then, pin 1X 1 is connected to pin 1X 2, pin 2X 1 is connected to pin 2X 2, and so on. The sum of the currents of the two four-core wires is then transimpedance amplified by amplifiers U1A through U1D. The servo signals on the main board are generated from four-wire signals. The transimpedance amplifier U1A-U1D is formed by connecting 100K ohm resistors RP1A, RP1B, RP1C and RP1D in parallel with 1 pico farad capacitors C101-C104.

The photodiode FS in fig. 102A is a forward sense diode. Its positive sense current indicates the power from the laser and is connected to the motherboard by pin 15 of connector J4.

Referring to fig. 102B, U106 is shown connected to J103. J103 is another four-wire detector, two of its four wires being used to generate a differential MO (magneto-optical) signal and a sum signal. U106 is a VM8101, which is a preamplifier made specifically for MO drivers, and is also a transimpedance amplifier. The read +/-signal from U106 can be switched between the difference and sum signals by the preformatted signal from pin 6 of connector J103.

FIGS. 103A-D show level shifters U7B, U7C, and U7D for write levels. U7B, U7C and U7D are three differential operational amplifiers, which are also compensated and can stably bear large capacitive loads. The resistors and capacitors at the periphery of U7B, U7C, and U7D perform the task of stability. The differential amplifiers U7B, U7C, and U7D have a gain of 1/2 for establishing the write level for the transistor bases Q301, Q302, Q303, Q304, Q305, and Q306 shown in FIGS. 104A-B. The write levels are three: write level 1, write level 2, and write level 3, which allows the present invention to provide different write levels for different pulses in the pulse train needed to write the MO signal.

The fourth operational amplifier U7A in fig. 103C sets the read current level. U7A drives Q12 and mirrors current into transistors Q7, Q8, and Q9. The mirror currents in Q7 and Q8 are the actual readout currents flowing to the laser.

The combination of the optical disk system of the present invention includes a laser, a first means for delivering a current to the laser, and a digital logic means for switching a power supply of the first means to drive the laser, thereby consuming electric power only when the laser is excited, and obtaining a switching characteristic capable of enhancing a rise and a fall. In a preferred embodiment, as shown in fig. 104A and 104B, the digital logic device includes CMOS buffers U301 and U302, which may be connected between a supply ground and a full supply voltage. In addition, the first means is preferably implemented with pass transistors (passtransistors) Q301-Q306, see FIGS. 104A-B.

The optical disc system is of the type having a focusing mechanism and a tracking mechanism, a lens, and an optical disc to be read, the mechanism in this example being controlled by a feedback loop according to another aspect thereof. One of the preferred embodiments of this feedback loop includes an electronic circuit for generating servo signals to effect calibration of the focusing and tracking mechanisms, a first means for delivering current to the laser, and a digital logic means for switching the power supply to the first means to drive the laser, whereby electrical power is only consumed when the laser is energized and enhanced up and down switching characteristics are obtained. In this embodiment, the digital logic device includes CMOS buffers, which are preferably connected between the supply ground and the full supply voltage. As described above, the first means may be implemented with a pass transistor.

Fig. 104A-B further illustrate the actual pulse driver and the enable pin that turns on the laser LD 1. The laser is actually protected by the CMOS gates U301 and U302A to ensure that the laser is not affected by any current spikes as the voltage level rises. The U302A asserts a logic low from the LaserON signal and the U302A can keep the current mirror image, as shown in FIG. 103A, not allowed until the read enable line of U302A, i.e., pins 1, 2, and 3, is allowed by a high logic level on pins 20, 21, 22, and 23 of U302A. It also provides a signal that allows the laser to be driven with write pulses only after the laser is activated. Activation is performed by pin 4 of U302A, which pin 4 controls the inputs of 301A, 301B and 302B.

The enable pins of U302 and U301, i.e., pins 13 and 24, and pin 24 of U301A are independent write signals that correspond to write strobe 1, write strobe 2, and write strobe 3. The three write levels can be generated by turning on the current sources generated by the independent transistors Q301 through Q306. The ferrite beads 301 and 302 in FIG. 104B act to isolate the read and write currents and prevent the RF modulation from being emitted back out of the cable due to EMI requirements.

Referring to fig. 105A-B, U303 is a custom integrated circuit IDZ3 manufactured by Hewlett Packard, which functions to generate a current of approximately 460 MHz. This current is introduced into the laser for RF modulation, thereby reducing laser noise. The output of which is coupled through C307. There is an enable pin 1 on U303 for turning modulation on and off.

The present invention comprises an improved Colpitts type oscillator in which pulse ringing is reduced. The oscillator includes a resonant circuit for raising the impedance of the oscillator. The resonant circuit may also include an inductor. One aspect of the present invention is to increase the supply voltage of the oscillator to facilitate increased RF modulation amplitude and reduced ringing. As described in detail below, a preferred embodiment of the improved Colpitts oscillator circuit comprises a transistor having an emitter, a base, and a collector; a voltage source; and a load resistor connected in series between the collector and the voltage source to mitigate ringing of the oscillator when the write pulse is supplied to the oscillator. A load inductor may also advantageously be used in series with the load resistor. In this embodiment, the write pulse is applied to the junction of the load resistance and the load inductance, and a tank circuit of a split capacitor may be connected between the collector across the emitter and collector and ground.

An improved Colpitts oscillator circuit of another preferred embodiment of the present invention comprises a transistor having an emitter, a substrate, and a collector; a split capacitor connected between the collector and ground across the emitter and collector; a voltage source; and a load inductor and a load resistor connected in series between the collector and the voltage source, whereby ringing of the oscillator can be relaxed when the write pulse is applied to a connection point between the load inductor and the load resistor. This embodiment also has an increased supply voltage to increase the RF modulation amplitude and reduce ringing. This Colpitts oscillator has a load circuit of increasing resistance, which can advantageously be provided in combination with the laser and the write pulse source. In a preferred embodiment, the load circuit further comprises an inductor.

The combination is modified to include a laser, a write pulse source, a voltage source, a Colpitts oscillator having a transistor with an emitter, a base, and a collector, and a load resistor connected in series between the collector and the voltage source to mitigate ringing of the oscillator when the write pulse is provided to the oscillator. It may comprise a tank inductance in series with the load resistance, the write pulse being applied at the junction between the load resistance and the resonant inductance, and/or a split capacitor tank connected between the collector and ground, across the emitter and collector.

Another embodiment of this combination for use in the optical disc system of the present invention comprises a laser, a write pulse source, a Colpitts oscillator having a transistor with an emitter, a base and a collector, and a split capacitor tank connected between the collector and ground across the emitter and collector, a voltage source, and a load inductance and load resistance connected in series between the collector and the voltage source, such that ringing of the oscillator is mitigated when the write pulse is applied to the junction between the load resistance and the load inductance. This embodiment also has an increased load impedance and increased voltage in order to increase the RF modulation amplitude and reduce ringing. Methods of reducing ringing in Colpitts oscillators include increasing the load resistance of the oscillator and increasing the voltage supplied to the oscillator.

As described above, the optical disc system comprises a focusing mechanism and a tracking mechanism, which are advantageously controlled by a feedback loop comprising electronic circuitry for generating a servo error signal for effecting a correction of the focusing mechanism and the tracking mechanism, a laser, a write pulse source, a Col-pitts oscillator having a transistor with an emitter, a base, and a collector, and a split capacitor tank connected between the collector and ground across the emitter and the collector, a voltage source, and a tank inductance and a load resistance connected in series between the collector and the voltage source, such that when a write pulse is applied to the connection between the load resistance and the resonant inductance, ringing of the oscillator is mitigated.

In fig. 104, the second embodiment uses a Colpitts oscillator constructed around a single transistor Q400, see fig. 104B, comprising a split capacitor bank C403, and C402, and an inductor L400. The bias voltage of this circuit is 12 volts and the load resistor R400 is 2K, thereby ensuring that the write pulse from ferrite bead FB301 does not cause any ringing of the oscillator circuit. The oscillator can be disabled by a base signal formed by grounding R402 if disabling is desired.

In previous designs, the Colpitts oscillator included a 5 volt power supply and an inductor instead of R400. This different design provides sufficient modulation amplitude for the laser to reduce noise. However, this prior design configuration may ring when the write pulse is provided. Since the inductance is replaced by resistor R400, the write pulse no longer induces ringing in the tank circuit. To clear the ringing and maintain sufficient peak-to-peak current in the RF modulation continuously, the oscillator power supply needs to be changed from 5 volts to 12 volts and all resistances changed appropriately.

Main circuit board

Fig. 106A to 119C show the main circuit board. The main circuit board includes drive functions not included in the spindle motor board or preamplifier. Including a SCSI controller, encoder/decoders for reading and writing, a read channel, a servo device, a power amplifier, and a servo error generator.

FIG. 106A shows the connection of flex circuit J1 from the preamplifier. As shown in fig. 102A, pin 15 of the preamplifier flex circuit J1 is the forward sense current from the preamplifier flex circuit board, see fig. 102A. Resistor R2 in fig. 106A provides a reference voltage that is negative in the sense output. The op-amp U23B buffers this signal, which is measured by the ADCU11 (FIGS. 110C-D).

The two resistors R58, R59 in fig. 106A implement a resistive voltage division function for achieving a more accurate resolution of the laser readout current level. The output of the digital-to-analog converter U3 shown in FIG. 110D sets the read current of the laser. The DSP U4 in fig. 110A-B controls the converter.

FIG. 106E shows an Eval connector J6, also referred to as a test connector. The Eval connector J6 provides a serial communication link to the processor U38 (FIGS. 109A-B) through the I/O port of U43 shown in FIGS. 108A (1) -A (3) in the test mode. The comparator U29A in FIG. 106F generates a SCSI reset signal for the processor.

The power monitor U45 in FIG. 106G monitors the system power and keeps the system in a reset state until the 5 volt power supply and the 12 volt power supply are within the tolerance range.

The connector J3A in fig. 106H connects the main circuit board to the main power supply. The power filters F1 and F2 filter the main circuit board.

Referring to fig. 106I, capacitively coupled chassis MT1, MT2 are used for capacitive grounding of the main circuit board to the chassis, forming an AC ground to the chassis.

U32 in FIGS. 107A-C represents a SCSI buffer manager/controller circuit. The U32 performs buffering functions and command processing for the SCSI bus. The U19A expands the length of the detected ID signal from U43 of fig. 108A. In FIG. 107C, U41, U42, and U44 are 1Mbx9 buffer RAMs used as SCSI buffers. Fig. 107B shows an eight-bit dip switch S2. Switch S2 is a general DIP switch for selecting SCSI bus parameters such as reset and termination.

FIG. 108A shows an encoding/decoding circuit U43, which is part of the SCSI controller. The encode/decode circuit U43 performs RLL2, 7 encoding/decoding of data and provides all required signals as well as decoding of sector formats of the ISO standard disc format for 1x and 2x 5-1/4 inch discs. The circuit also has a universal input/output that performs a variety of functions including communicating with various serial devices, enabling the bias coil driver, and determining the polarity of the bias coil.

A small non-volatile RAM U34, FIG. 108A (3), stores drive specific parameters. These parameters are parameters set at the time of verification and manufacture of the drive.

The SCSI active termination components U50, U51 shown in fig. 108B may be accessed by the switch S2 in fig. 107B.

The encoding/decoding circuit 43 in fig. 108A has a special mode that when used in a driver, an NRZ bit mode can be allowed for input and output. The subscription GLENDEC U100 in fig. 115A-C can be used for RLL1, 7 encoding/decoding of 4x optical discs when enabled. In this manner of encoding/decoding, the circuit U43 may allow the use of many other encoding/decoding systems for other optical disc sizes.

Fig. 109 shows an 80C188 system control processor U38. The operating frequency of the 80C188 system control processor U38 is 20 mhz with 256 kbytes of program memory U35, U36, and 256 kbytes of RAM U39, U40, see fig. 109C-D. The 80C188 system control processor U38 controls the functions of the driver. The 80C188 system control processor U38 is a general purpose processor and can be programmed to handle different formats and different user requirements. Different optical disc formats may be handled by appropriate supporting equipment and encoding/decoding systems.

Fig. 110 shows a TI TMS320C50 DSP servo controller U4, a multiple input analog-to-digital converter U11 for converting servo error signals, and an 8 channel/8 bit digital-to-analog converter U3 for providing servo drive signals and level settings. The DSP servo controller U4 receives signals from the analog-to-digital converter U11 and outputs signals to the digital-to-analog converter U3.

One of the control functions of the DSP servo controller U4 is to monitor the spindle speed via an indicator signal on pin 40 of the DSP servo controller U4. The DSP servo controller U4 determines the write drive or the read drive via control signals on pin 45. The DSP servo controller U4 communicates with the system control processor U38 through a GLENDEC U100 shown in FIGS. 115A-C. The DSP servo controller U4 performs fine tracking servo, coarse tracking servo, focus servo, laser read power control, and cartridge eject control. The DSP servo controller U4 also monitors the spindle speed for verifying that the disc is rotating within a speed tolerance. The analog-to-digital converter U11 performs the conversion of the focus, tracking, and coarse position signals. The focus and tracking conversion is done using +/-references on pins 17 and 18 from analog-to-digital converter U11, which is generated from four wires and signals. The four-wire sum signal is the sum of the servo signals. Normalization of the error signal is performed with a +/-four wire sum reference, using a +/-voltage reference to convert coarse position, four wire signal and forward sense.

The output of the digital-to-analog converter U3 in FIG. 110D includes the fine drive signal, the coarse drive signal, the focus drive, the LS and MS signals. These signals are servo signals used to drive the power amplifiers (U9 and U11 in FIGS. 111A-B, and U8 in FIG. 112B) and to close the servo loop. Focusing includes FOCUSDRYLS and FOCUSDRYMS drive signals. The FOCUS-DRYLS signal causes the FOCUS motor to fine tune the steps in an open loop fashion to achieve the disc with very small steps. The focussryms signal is used as a servo loop driver. Pin 7 of the digital-to-analog converter U3 in FIG. 110D includes the signal READ _ LEVEL _ MS. Pin 9 of the digital-to-analog converter U3 includes a signal READ LEVEL LS. These signals from pins 7, 9 of the digital-to-analog converter U2 are used to control the laser read power. Pin 3 of the digital-to-analog converter U3 is a threshold offset used in 4x read channel error recovery to introduce an offset into the read channel to achieve error recovery.

The optical disc system of the invention generally comprises a lens and an optical disc to be read, and the invention also relates to an improved method of focus capture comprising the steps of: directing light onto the disc to be read, initially retracting the lens to the bottom of its stroke, scanning to the top of the lens stroke while searching for the maximum Quad Sum signal on leg 25 of U11 in fig. 110D, moving the lens away from the disc, monitoring the total amount of light reflected back from the disc, determining the total amount of light during the monitoring, searching for the first zero crossing when the total amount of light reaches more than half of the measured peak, determining when the Quad Sum signal exceeds half of the peak, and stopping focus adjustment at that point. Another embodiment of this method of the invention comprises the steps of: the method includes the steps of directing light onto an optical disc to be read, moving a lens to a first position, monitoring a Quad Sum signal, moving the lens away from the first position toward the optical disc to be read while looking for a maximum Quad Sum signal, moving the lens away from the optical disc, monitoring a total amount of light received from the optical disc, determining when the total amount of light reaches more than half of a measured peak value in monitoring the light, searching for a first zero crossing, determining when the Quad Sum signal exceeds half of the peak value, and ceasing focusing when the Quad Sum signal exceeds half of the peak value. In both embodiments of this method, the illumination light may be from a laser.

The improved focus capture system of the present invention comprises means for directing light onto an optical disc to be read, moving means for initially retracting the lens to the bottom of its stroke, successively scanning all the way to the top of the lens stroke while searching for the largest Quad Sum signal and then moving the lens back away from the disc in reverse, monitoring means for monitoring the total amount of light returned from the disc and during the monitoring determining when the total amount of light reaches more than half of the measured peak value, means for searching for the first zero crossing, and means for determining when the Quad Sum signal exceeds half of the peak value and stopping focus at that point.

Another embodiment of the focus pull system of the present invention comprises means for directing light onto an optical disc to be read, means for monitoring the Quad Sum signal, moving means for moving the lens to a first position, moving the lens away from the first position toward the optical disc to be read, and moving the lens away from the optical disc in reverse, means for monitoring the total amount of light received from the optical disc, means for determining when the total amount of light reaches more than half of the measured peak value during the monitoring of the light, means for searching for a first zero crossing, means for determining when the Quad Sum signal exceeds half of the peak value, and means for ceasing focusing when the Quad Sum signal exceeds half of the peak value. In this example, the means for directing light onto the disc to be read comprises a laser.

Another aspect of the invention includes a feedback loop for use with such an optical disc system having a focusing mechanism, a tracking mechanism, a lens, and an optical disc to be read, wherein the mechanism is controlled by the feedback loop. One embodiment of such a feedback loop comprises electronic circuitry for generating servo signals used to effect calibration of the focus and tracking mechanisms, means for directing light onto the disc to be read, moving means for initially retracting the lens to the bottom of its travel, successively scanning to the top of the lens travel while searching for the largest Quad Sum signal, and then moving the lens back away from the disc, means for monitoring the total light returning from the disc, and for determining when the total light reaches more than half the measured peak during the monitoring process, means for searching for the first zero crossing, and means for determining when the Quad Sum signal exceeds half the peak and stopping focus at that point, thus improving the focus collection capability.

Fig. 110D also shows a 2.5 volt reference U24, which is amplified by a factor of 2 by amplifier U23D to a 5 volt reference. The 2.5 volt reference U24 is used by comparator U29. The comparator U29 compares the AC component of the tracking error signal to zero voltage to determine the zero crossing points for tracking. The tracking error signal is digitized and sent to the GLENDEC U100 shown in fig. 115A-C for determining tracking zero crossings used in the seek operation.

The analog-to-digital converter U11 in fig. 110C-D performs conversion of focus and tracking errors using four lines of sum signals. The error signal can be automatically corrected for the column four wires and the signal using the four wires and as a reference on pins 17 and 18 of the analog-to-digital converter U11. The analog-to-digital converter U11 divides the error signal by the sum signal and provides a normalized error signal that is input into the servo loop. This has the advantage that the number of variables to be processed in such a servo loop can be reduced. This normalization function may be performed by an external analog divider. Analog dividers have inherent accuracy and speed problems. This function may also be performed by the DSP servo controller U4 in fig. 110A-B, digitally dividing the error signal by the four-wire sum signal. The division operation in the DSP servo controller U4 requires a significant amount of time. When the sampling rate is 50KHz, it may not be time to divide and digitally process the error signal within the servo loop. Since the four-line sum is used as a reference, the error signal can be automatically normalized without division.

Referring to fig. 110 and 113, the analog-to-digital reference signals on pins 17, 18 of the analog-to-digital converter U11 in fig. 110C-D are sent by the operational amplifiers U17A, U17B of fig. 113. The operational amplifiers U17A, U17B generate reference +/-voltages. The switches U27A, U27B select the input reference for the operational amplifiers U17A, U17B. The operational amplifiers U17A, U17B function to generate a 1 volt reference and a 4 volt reference (2.5 volts +/-1.5 volts reference) when switch 27B is active, or a reference from a four wire sum when switch U27A is active. Switches U27A and U27B are switched at the servo sample rate of 50 KHz. This allows the focus and tracking samples to be obtained using the Quad Sum in each servo sample, and the Quad Sum, forward sense and coarse position are obtained with a reference of 2.5 volts +/-1.5 volts. By multiplexing the reference values, an automatic normalization of the servo errors can be achieved in a single analog-to-digital conversion.

In summary, the switching system in fig. 113 performs multiplexing of two different reference levels. The switching system enables true reference level analog-to-digital conversion for laser power and the total amount of detected signal from the disc, and corrects for servo error signals when four lines and references are used. For signals such as laser power, four lines and levels, focus error signals, and tracking signals, these signals can be converted in real time by switching between two reference levels at a rate of 50 kHz.

Fig. 111 shows a circuit having the focus power amplifier U9 in fig. 111A and the trimming drive power amplifier U10 in fig. 111B. The pins 10 of the power amplifiers U9, U10 are digital enable lines, which are controlled by a processor. One of the advantages of using microprocessor control is that the power amplifier is disabled during the switching on of the drive power supply in order to prevent damage and uncontrolled movement of the respective focusing and drive components during this time. Both power amplifiers U9, U10 use a 2.5 volt reference as an analog reference and are powered by a 5 volt power supply. The power amplifiers U9, U10 accept digital-to-analog inputs from the DSP servo controller U4 to control the output of the current. The focus power amplifier may drive a current of +/-250 milliamps and the trim power amplifier may drive a current of +/-200 milliamps.

Fig. 112 shows a circuit with power amplifiers U30 (fig. 112A) and U8 (fig. 112B) for drive and coarse drive of the MO bias coil. The power amplifiers U30, U8 are powered by a 12 volt power supply to provide a wide range of voltages across the motor. The bias coil (not shown) is digitally controlled so as to be enabled and set to either the erase polarity or the write polarity. The power amplifier U30 may output 1/3 amps of current to a 20 ohm coil. The coarse motor power amplifier U8 is designed to provide a current of up to 0.45 amps to a load of 13-1/2 ohms. A level shifter U23A is provided at one input of the power amplifier U8 to shift the voltage-driven reference from 2.5 volts to 5 volts.

The structures of the power amplifiers U9, U10, U30, U8 as shown in fig. 111 and 112 are similar and the compensated bandwidth range is greater than 30 KHz. The clamp diodes CR1, CR2, CR4, and CR5 provided on coarse power amplifier U8 in fig. 112B prevent the output voltage of power amplifier U8 from increasing too much due to the back electromotive force (EMF) of the coarse motor when the motor is rotating in reverse. The clamp diodes CR1, CR2, CR4, CR5 will not cause the power amplifier U8 to go into saturation for a long time, which makes the track finding difficult.

The output of the amplifier U26A in FIG. 112A and the voltage divider resistors R28/R30 feed back the bias current to the analog-to-digital converter U6 shown in FIG. 114A. Thereby enabling the processor U38 (fig. 109) to ensure that the bias coil is in the desired state before writing is performed.

Referring to fig. 113, the four-wire and reference converter is implemented by the circuits U27A, U27B, U17A and U17B as described above with reference to fig. 110. The spindle motor connector J2 transmits signals to other circuit elements.

The differential amplifier U23C converts the coarse position error to a reference of 2.5 volts. The coarse position error from the spindle motor board (J2) is referenced to Vcc. Transistor Q14 is a driver for front panel light emitting diode LED 1.

Referring to fig. 114, U6 is a serial a/D converter for converting signals from temperature sensor U20. The driver is calibrated in response to changes in the measured temperature. This is an important feature of the invention, especially in the case of 4x writing, where the write power is critical and may need to be adjusted as a function of the system temperature.

The signals on pin 2(PWCAL) and pin 6 of the analog-to-digital converter U6 are the servo differential amplifier signals sent by 84910 (fig. 117). These signals may be used to sample the read channel signal and are controlled by the digital signals on pins 27-30 of 84910 in FIG. 117B. In the present embodiment, the pins 27-30 are grounded, however, those skilled in the art will recognize that these pins may be driven by a variety of different signals, and thus may sample a variety of signals when calibration is required.

Pin 3 of U6 in fig. 114A is the AGC level, which is buffered by U21B and then divided by a resistor to the order of magnitude that it can be input to the a/D converter. This AGC level will be sampled in a known written sector. The resulting value will be written as a fixed AGC level on pin 19 of U16. The fixed AGC level is input to 84910 of fig. 117. 84910 sets the AGC level accordingly to inhibit the amplifier from operating at maximum gain during evaluation of the sector to determine if it is a blank sector.

The optical disc drive system of the present invention comprises the following combination of means: a disc-shaped storage medium having a plurality of data sectors, amplifying means for evaluating a particular sector to determine whether the sector is blank, and means for inhibiting the amplifier from operating in a maximum gain state during evaluation of the sector. In one embodiment of the present invention, the means for disabling the amplifying means comprises a microprocessor U38 shown in fig. 109A and B for setting the gain level of the amplifying means.

As will be described in further detail below, the optical disc system of the present invention is of the type having a focusing mechanism, and tracking mechanism, a lens, and an optical disc to be read, said mechanisms being controlled by a feedback loop comprising electronic circuitry for generating servo signals to effect effective calibration of the focusing mechanism and tracking mechanism, amplifying means for evaluating a particular sector of the optical disc to determine whether the sector is blank, and means for inhibiting the amplifying means from operating at maximum gain when the sector is evaluated. In another embodiment of the invention, the means for disabling the amplifier device comprises a microprocessor U38 shown in fig. 109A and B for setting the gain level of the amplifying device.

The bias current discussed above in connection with fig. 112 is monitored by pin 4 of the analog-to-digital converter U6 in fig. 114A as a further guard during write and erase operations to determine that the bias current has the correct magnitude and polarity.

The signals pwcalf and PWCALHF appear on pins 7 and 8 of U6 of a6 and a7, respectively, which are obtained by sample and hold circuits (see fig. 118) and can be controlled by a lap logic encoder/decoder (GLENDEC) via signals WTLF or WTHF, as shown in fig. 118B. These signals are employed within a sector to sample the high frequency written pattern and to sample the average DC component of the low frequency written pattern. The average values can be compared to obtain an offset that can be used to optimize the 4x write power.

Leg 11 of U6(A9) in FIG. 114A is coupled through U21A to a differential amplifier having INID + and INTD-inputs. These signals are the DC level of the data relative to the DC level of the recovered signal in the 4x read channel. The differential signal determines the threshold level used by the comparators in the 4x read channel. This DC shift can be cancelled using the DSP threshold on pin 3U 3 in the D/a converter (see fig. 110D). In addition, a shuffle may be introduced for error recovery in an effort to recover data that otherwise cannot be recovered. Thereby providing 4x read channel recovery and calibration functions.

Referring to FIGS. 114A-B, the signal Read DIFF appears on pin 12 of U6, A10, as the output of the differential amplifier U15B. Read DIFF is the DC component of MO (magneto optical) preamplifiers or preformat preamplifiers. The DC value of the read signal can then be determined and used to measure the DC value of the erased track in the first direction and the DC value of the erased track in the second direction to provide a difference signal for the peak-to-peak MO signal. The written data may also be averaged to produce an average DC value that is measured for the process being written. This value is also used for calibration of the 4x write power.

U16 in FIG. 114B is a D/A converter controlled by an 80C188 (FIGS. 109A-B; U38) processor. The output of U16 is several voltages for controlling the current level of the three write power levels WR1-V, WR2-V and WR 3-V. These signals determine the power of the various pulses. The fourth output is the fixed AGC level described above.

GLENDEC is shown in U100 in FIG. 115. Glue Logic ENcode/DECode/mainly uses a gate array to combine a plurality of different functions. The ENcode/DECode section is an RLL1, 7 ENcode/DECode function. The input to the ENCode function is NRZ on pin 70 of U43 (FIG. 108A), the output of which is encoded as RLL1, 7. And then written to the disk via legs 36, 37 and 38 of U100 (WR1, WR2, WR 3). The DECode function receives RLL1, 7 encoded data from the disk, decodes it and restores it to NRZ for transmission to U43 (fig. 108A). U16 in fig. 114B also includes a 4x sector format for timing. Of course, U16 is programmable and thus may have different sector formats defined therein.

Other functions performed by the GLENDEC U100 of FIG. 115 include the communication interface between the DSP (U4 of FIG. 110) and the host processor, i.e., 80C188 (U38; FIG. 109). Counters for track crossings and timers for measuring the time between track crossings are also provided, which are used by the DSP for the seek function.

Fig. 116 shows a servo error generation circuit. The signals QUADA, QUA-DB, QUADC and QUADD in FIG. 116A represent the outputs of the servo transimpedance amplifiers (FIG. 102B, U1A, -U1D) located on the preamplifier board. These signals are appropriately added and subtracted in the operational amplifiers U22A and U22B of fig. 116A-B to generate the tracking and focus error signals TE and FE at J4 of fig. 116A and U22C of fig. 116B, respectively. U22C of FIG. 116B adds QUADA, QUADB, QUADC and QUADD to form the four-line sum signal QS. The switches U28A, U28B, U28C, U28D, U27C, and U27D are allowed during writing, thereby reducing the circuit gain because the four-wire current during writing is increased. During writing QUADA, QUADB, QUADC and QUADD are attenuated by a factor of approximately 4.

The read channel is discussed below with reference to FIG. 118A. The read signals RFD +, RFD-are emitted by the preamplifier board (FIG. 102B, U106) and propagate through the gain switches U48A, U48B (FIG. 118A (1)) for normalizing the levels associated with the preformatted and MO signals. The gain switch switches between the preformat and MO areas of the optical disc under the control of U25B.

U48C and U48D are open during writing so the read signal does not saturate the input of the read channel. During a read operation, these switches are closed, causing a read signal to be sent through the switches to the differentiator U47, see fig. 118A (2). The minimum group delay error of U47 is compensated and can operate to 20 MHz. The output of U47 is AC coupled through C36 and C37 to SSI filter U1 and is fed through FRONTOUT + and FRONTOUT-to 84910 (FIG. 117). As shown in fig. 117C, the signal is attenuated by the resistors R75 and R48, and the signal reaches a signal level acceptable for 84910. FRONTOUT + and FRONTOUT-AC are then coupled to 84910 through C34 and C33, respectively.

At 84910, several functions are included to allow the read channel to function properly. The method comprises the steps of reading channel AGC, reading channel phase-locked loop, data detection, data separation and frequency synthesis. A servo error generator with the typical Winchester servo error generator function is also part of 84910. However, these functions are not used in the present embodiment.

The data split signals of fig. 117 and 84910(U13) are output from pins 14 and 15 and then connected to SM330, U43 (fig. 108A). These signals are used for the 1x and 2x read channel modes.

The preformat signal controls pin 31 of 84910 so that there are actually two independent AGC signals. One for reading the header or preformatted data and the other for MO data.

In the case of the 4 × read channel, the signals SSIFP and SSIFN (fig. 118A (2)) enter the buffer amplifier U49 (fig. 119A). The output of U49 is passed to Q3, Q4 and Q5 (FIGS. 119A-B), which function as a band-raised integrator. U5 in FIG. 119B is a buffer amplifier for integrating and boosting the signal. Thus, the 4x read channel involves SSI filtering, equalization, differentiation, and integration.

The output of U5 is buffered by amplifier U12 in fig. 119A and coupled to a circuit for determining the midpoint between the peak-to-peak levels, also known as a recovery circuit. As a result of the restoration, the signals INTD + and INTD-in fig. 118C are input to a comparator, the output of which provides a threshold level signal for data separation. The signals INT +, INT-, INTD + and INTD-are then input to U14 in FIG. 118C, a MRC1, for comparison, and the readout data is separated. The output of U14 is fed back to GLENDEC U100 (fig. 115) for encoding/decoding operations.

Digital signal processor firmware is disclosed in appendix B, which is attached hereto and is incorporated herein by reference.

Digital lead/lag compensation circuit

It is well known in the art to control a position system in which a motor is driven using a drive signal (e.g., the drive signal is a current) that is proportional to acceleration. There are some special concerns. Such position control systems require lead/lag compensation to substantially eliminate oscillations and stabilize the position control system or servo system.

The circuit of the present invention is a digital lead/lag compensation circuit that not only substantially eliminates ringing, but also provides a notch filter having a frequency equal to one-half the digital sampling frequency. The mathematical formula for the transfer function of the digital lead/lag circuit of the present invention, which is a single lead, synthetic lag compensation, is set forth in the following paragraph headed "transfer function". Several prior art digital lead/lag compensation circuits and an analog lead/lag compensation circuit for comparison are also listed. As will be seen hereinafter, the transfer function of the present invention is:

the transfer function formula for the S-domain, a suitable formula represented by Bode curves, is also listed in the following paragraphs. It can be seen from the Bode plot that the compensation circuit of the present invention has minimal effect on phase.

Although the prior art compensation circuit also has minimal phase effect, only the compensation circuit of the present invention has a notch filter at half the digital sampling frequency. By choosing the sampling frequency correctly, this notch filter can be used to notch spurious mechanical resonance frequencies such as those of the servo motor being compensated. In the drive 10 of fig. 1, and in some alternative embodiments thereof, such a single lead-synthetic-lag compensation circuit is used to suppress mechanical decoupling resonances of the fine tuning and focus servo motors, see the following paragraphs.

Transfer function

The following mathematical formula represents the transfer function of the digital lead/lag compensation circuit of the present invention. First the transfer function of the focus loop will be discussed. The details of the compensating transfer function are explained later.

Focus loop transfer function:

frequency shift at 23C

T_factor-1

ω₀Actuator model 2 · pi · 3000: decoupling frequency:parasitic resonance: omega₃＝T_factor·2·π·23·10³ ζ₃＝0.03ω₂＝T_factor·2·π·27·10³High Frequency (HF) phase loss:fundamental frequency: m_constant＝790 m/(s^2^*A)ω₅＝T_factor·2·π·36.9 ζ₅＝0.08The actuator responds: h_actuator(s)＝H₁(s)·H₂(s)·H₃(s)·H₄(s) DSP model: single lead synthetic lag circuit: sampling period T: 20. 10-^-6DSP S&H and processing delay:the DSP responds: h_dsp(s)：＝(ZOH(s)·H_delay(s)·H_leadlag(s)) antialiasing filter: Simplified focus power amplifier response:a DSP model: single lead synthetic lag circuit: sampling period T is 20.10^-6DSP S&H and processing delay:the DSP responds: h_dsp(s)＝(ZOH(s)·H_delay(s)·H_leadlag(s)) antialiasing filter:simplified focus power amplifier response:ω_pa2＝2·π·45000 ζ_pa2＝0.8 G_pa＝G_pa1·G_pa2 A/BITfocus error signal:filter response: h(s) ═ H_filt(s) Volts/voltpsd response: h(s) ═ H_dsp(s) Volts/Volt power amplifier response: h(s) ═ H_pa(s) Amps/bit actuator response: h(s) ═ H_actuator(s) m/a focus error response: h(s) ═ H_febit/m open loop response: h(s) ═ H_filt(s)·H_dsp(s)·H_pa(s)·H_actuator(s)·H_feGain factor:closed loop response:generate a Nyquist plot with "M-circle" (M-circle): magnitude of selected closed loop spike Mp:radius of M-circle:center of M-circle:n＝300 k＝1-n N_kdata in 1000 ÷ 100. kBode diagram:Magn(s)＝20·log(|G·H(s)|)φ(s)＝angle(Re(H(s))，lm(H(s)))360·degMagn₁(s)＝20·log(|H_cl(s)|)φ₁(s)＝angle(Re(H_cl(s))，lm(H_cl(s)))-360·deg

as shown in fig. 124, the Nyquist plot of the focus loop transfer function includes equal-peak trajectories (equal-peak-loci) that constitute M-circles 9-22, 9-24, 9-26, and 9-28. The respective Mp values were 4.0, 2.0, 1.5, 1.3, respectively. Fig. 124 also shows the loop curves 9-30 resulting from the open loop equations described above. Graph 125 represents the magnitude curves for open loop responses 9-32, and closed loop response magnitude curves 9-34. Fig. 126 shows the phase curves for the open loop responses 9-36 and the closed loop response phase curves 9-38.

Compensating the transfer function:

T：＝20·10^-6 ω₀＝2·π·i·3000

DSP S&h and processing delay:

a DSP model: triple lead/lag circuit

Bidirectional conversionDefinition of Z ═ e^s·TTriple lead-lag response:single lead-lag response:comprehensive lead-lag: omega_center：＝2·π·2200 Span＝1.0ω₂-ω_center-0.5·Span·ω_centerAnd (3) simulating Box compensation:τ_lp：＝330·10^-12·20.5·10³single lead integrated lag: omega₆：＝2·π·900 ω₇＝2·π·22000 ζ₇＝0.8Curve data:Magn(s)＝20·log(|H_Triple(s)|)φ(s)＝angle(Re(H_Triple(s))，lm(H_Triple(s)))-360·degMagn₁(s)＝20·log(|H_Single(s)|)φ₁(s)＝angle(Re(H_Single(s))，lm(H_Single(s)))-360·degMagn₂(s)＝20·log(|H_Complex(s)|)φ₂(s)＝angle(Re(H_Complex(s))，lm(H_Complex(s)))-360·degMagn₃(s)：＝20·log(|H_AnalogBox(s)|)φ₃(s)：＝angle(Re(H_AnalogBox(s))，lm(H_AnalogBox(s)))-360·degMagn₄(s)：＝20·log(｜H_slcl(s)｜)φ₄(s)：＝angle(Re(H_slcl(s))，lm(H_slcl(s)))-360·deg

fig. 127 shows the amplitude response curve of the focus compensation, transfer function, derived from the formula shown. FIG. 127 shows individual response curves for triple lead-lag, single lead-lag, combined lead-lag, simulated Box, and single lead-combined lag, identified by legend in the legend Box. While the graph 128 shows the phase response curve for the focus compensation transfer function derived from the corresponding formula. Fig. 128 shows graphically identified individual phase response curves for triple lead-lag, single lead-lag, combined lead-lag, simulated Box, and single lead combined lag.

Integrated lead/lagD₁=1Single lead integrated lag:ω₂·T²+2·T＝4.276·10^-5 2·ω₂·T²＝5.529·10^-6

not described herein, the following U.S. patents are incorporated by reference: US 5,155,633 to Grove et al; prikryl et al, US 5,245,174; and US 5,177,640 to Grass-ens.

Although the present invention has been described in detail with reference to certain preferred embodiments, it should be understood that the invention is not limited to these precise embodiments. Rather, based on the description herein of the presently preferred embodiment of the invention, many modifications and variations may be made by one of ordinary skill in the art without departing from the scope or spirit of the invention. The scope of the invention is, therefore, indicated by the following claims rather than by the foregoing description. All changes, modifications and variations that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims (5)

1. An optical disc system having a focusing mechanism and a tracking mechanism, a lens and a readable disc, said mechanisms being controlled by a feedback loop, said optical disc system comprising:

amplifier means for evaluating a predetermined sector of said disc to determine if said sector is blank;

means for preventing the amplifier means from operating at maximum gain when evaluating the sector;

a servo loop having a servo loop transfer function and an error signal, said servo loop being adapted for positioning applications, said error signal being sampled at a predetermined sampling frequency;

an actuator having a mechanical resonance frequency lower than said predetermined sampling frequency, said actuator being controlled by said servo loop; and

a digital lead/lag compensation circuit for stabilizing a servo loop, said compensation circuit having a compensation transfer function comprising a single lead and a complex lag for producing a notch filter having a notch, said compensation transfer function being formulated such that said notch of said notch filter occurs at about half said predetermined sampling frequency, thereby reducing the amplitude of said mechanical resonance frequency in the transfer function of the servo loop, thereby enabling a blank sector check to be performed in a system that reduces the amplitude of said mechanical resonance frequency.

2. The optical disc system of claim 1 wherein said means for disabling said amplifier means comprises a microprocessor for setting a gain level for said amplifier means.

3. The optical disc system of claim 1 or 2, wherein the compensating transfer function is

4. An optical disc system having a focusing mechanism and a tracking mechanism, a lens and a readable disc, said mechanisms being controlled by a feedback loop, said method comprising:

evaluating a predetermined sector of said disc by an amplifier to determine if said sector is blank;

preventing the amplifier device from operating at maximum gain while evaluating the sector;

providing a servo loop having a servo loop transfer function and an error signal, said servo loop being adapted for positioning applications, said error signal being sampled at a predetermined sampling frequency;

providing an actuator having a mechanical resonance frequency below said predetermined sampling frequency, said actuator being controlled by said servo loop; and

a digital lead/lag compensation circuit is connected to stabilize the servo loop, said compensation circuit having a compensation transfer function comprising a single lead and a complex lag to produce a notch filter having a notch, said compensation transfer function being formulated such that said notch of said notch filter occurs at about one-half of said predetermined sampling frequency, thereby reducing the amplitude of said mechanical resonance frequency in the transfer function of the servo loop, thereby enabling a blank sector check to be performed in a system that reduces the amplitude of said mechanical resonance frequency.

5. The method of claim 4, wherein the compensating transfer function is: