HK1022193B

HK1022193B - High impedance bias circuit for ac amplifiers

Info

Publication number: HK1022193B
Application number: HK00101102.3A
Authority: HK
Inventors: C‧M‧斯坦查克
Original assignee: 爱特梅尔公司
Priority date: 1997-09-23
Filing date: 1998-09-03
Publication date: 2003-12-05

Description

High impedance bias circuit for AC signal amplifier

Technical Field

The present invention relates to integrated circuits employing active devices to generate a high impedance node, and more particularly to the use of a high impedance node in a bias voltage generation circuit.

Background

There are many types of voltage amplifiers, but all share the same characteristics and the same limitations. For illustrative purposes, fig. 1 shows the internal structure of a basic amplifier 11. The exemplary amplifier 11 has an input signal Vin at an input node 15 and an output signal Vout at an output node 17.

Vout is V determined by the internal structure of the amplifier 11_INA function of (a). In this example, the input signal Vin is internally coupled to the control gate of an nmos transistor 13. The nmos transistor 13 is coupled between the constant current source 21 and ground, with its drain 18 connected to the output of the current source 21 and the output node 17. As Vin changes, the source 19 to drain 18 voltage drop responds by changing the phase of Vin by 180 ° and by having an amplitude gain determined by the constructive characteristics of transistor 13 and the load line of amplifier 11. The load line of the amplifier 11 is determined by the load at the drain 18 and the value of the VCC voltage, which is typically 3V to 5V. The usual control does not exceed the variation of the power supply Vcc, nor is it possible to change the constructional characteristics of the transistor 13 after the manufacture is completed. As shown, the only load coupled to the drain 18 is a current source 21. Therefore, being able to select and maintain an accurate current value for current source 21 is an important criterion for maintaining a stable, predetermined gain for amplifier 11.

Fig. 2 shows an amplifier 11 configured with a typical current source. In FIG. 2, the current source comprises pmos transistor 23 having its source 25 coupled to Vcc, its drain 27 coupled to drain 18 of transistor 13, and its gate 26 coupled to reference voltage V_REFAnd (4) coupling. Input signal V due to structural and layout constraints_INUsually also via an internal coupling capacitor 29 with the reference signal V_REFAnd (4) coupling. This can degrade the performance of the amplifier 11, as described below.

Referring to FIG. 3, an enhancement mode transistor, such as pmos transistor 23, is characterized by a source-drain current I_DSAnd voltage V_DSTypically with opposite polarity to that of the curves of the nmos transistor. For clarity, all I_DS、V_DSAnd V_GSThey are referred to only in terms of their magnitude and not their polarity, and thus the following discussion is equally applicable to pmos and nmos devices.

At a given source-gate voltage, at saturationAnd in-region, source-drain current I_DSVariation Δ i and source-drain voltage V_DSThe change in Δ v is relatively small in comparison. Such as I_DSTo V_GSWill be seen as the transistor action of one switching transistor in other applications. Due to I_DSCurrent at a large V_DSEnhancement MOS transistors that remain relatively stable in range and operate in the saturation region are well recognized in the art as good current sources. Saturation mode of MOS transistor and saturation current of MOS transistor is V_GSSelection, V_GSThe change occurs and the saturation current of transistor 23 will also change and transistor 23 will even lose saturation. Since the gain of the amplifier 11 in fig. 2 depends on the stable saturation current from the transistor 23, the reference voltage V is provided by a constant voltage source_REFI.e. V in FIG. 3_GSIs important.

Referring to fig. 4, a good constant voltage source, such as a battery, experiences small voltage fluctuations Δ v over a large current range Δ i. As described above in fig. 3, the transistor action of the switching MOS device in the saturation region has a performance opposite to the large voltage fluctuation Δ v over the small current variation Δ i. Therefore, such transistor action of MOS transistors has traditionally been unsuitable for generating a constant voltage source. However, no battery is possible in the integrated circuit. Therefore, when constructing a constant voltage source in an integrated circuit, it is limited to transistors, resistors and other integratable devices. To avoid some of the disadvantages of the transistor action described above, the transistor is usually connected as a diode.

Referring to fig. 5, a typical IC prior art circuit for a constant voltage source is shown. Transistor 24 acts as a diode with its gate 22 coupled to its drain 28, and thus its V_GSWith it V_DSAre equal. Diode connected transistor 24 is coupled in series with current drain 35 between Vcc and ground. Reference voltage output V_REFIs tapped at node 38 which connects drain 28 to current drain 35.

Line 39 in graph 37 illustrates I of diode-connected transistor 24_DSAnd V_GSThe relationship between, as shown, the device 24 follows a more diode-like curve; the current change Δ i causes the voltage change Δ v to be less severe than represented by the transistor action curve in fig. 3. Thus, I of the diode-connected transistor 24 is made_DSCurrent and V_DSThe relationship between the voltages is more gradual.

However, the use of a diode-connected transistor only provides a partial solution. As shown in the graph 37, V is much less sensitive than before_DSFor I_DSThe fluctuations in (a) are still very sensitive. Decrease V_DSFor I_DSOne common approach to varying sensitivity is to limit I_DSThe amount of current fluctuation Δ i, thereby limiting V_DSA fluctuation Δ v of (a). The current fluctuation Δ i is usually determined by the input signal V_INIntroduced via coupling capacitor 29.

Referring to fig. 6, the current fluctuation ai is conventionally limited by placing a large resistor 41 between the node 38 and the node 40, the resistor 41 being connected to the output signal V_REFAnd a coupling capacitor 29. The large resistance of resistor 41 reduces by V_INThe amount of current drawn thereby reduces the amount of current ripple Δ i through the diode-connected transistor 24. In order to make the resistor 41 sufficiently reduce V_REFMedium ripple, this resistor must be large and usually has a large megaohm value. Such large resistor structures in integrated circuits require a large area to be occupied. Furthermore, large resistors in ICs are often plagued by various problems, including leakage current and its inherent capacitance sharing problems. Both of these problems cause additional current fluctuations that reduce the effectiveness of the resistor. Furthermore, the circuit of FIG. 6 does not account for V due to Vcc power supply fluctuations_REFThe voltage changes.

Several attempts have been made to reduce the dependence on large resistors in IC constant voltage source structures. Tsukada, U.S. patent No. 5,467,052, discloses a reference voltage for a circuit that generates resistance to power fluctuations. Tsukada discloses the use of a first resistor in a first branch and a second resistor in a second branch, the current through the second branch being the ratio of the two resistors and the characteristics of some of the transistors used. Because the current depends on a ratio, a smaller resistor may be used. Similarly, Young, us patent No. 4,264,874, discloses two current mirrors coupled to each other, with a resistor connected between one of the branches of the current mirror and ground. Zimmer et al, U.S. patent No. 5,317,280, discloses a method of making a high impedance node using PFETs and smaller multi-way resistors. Zimmer et al disclose a method of forming a high impedance node using a PFET and a plurality of small resistors. They apply a bootstrapping technique to multiply the resistance of the bias impedance by the ratio of two small resistors.

These methods reduce the size of the required resistors without eliminating them. An integrated voltage source can be built by using only diode-connected transistors as shown in fig. 5, without using resistors. However, as noted above, such circuits are susceptible to the introduction of error currents and Vcc fluctuations.

It is an object of the present invention to provide a constant voltage source using only active devices that is immune to error currents introduced by this input signal or Vcc ripple.

It is another object of the invention to provide a circuit that can be used to simulate a high impedance node without using resistors.

It is a further object of the present invention to provide a constant voltage source that is insensitive to power supply, temperature and input signal variations, has a high impedance node that does not require resistors, and is suitable for IC circuits.

Summary of The Invention

According to an aspect of the present invention, there is provided a constant voltage source having an output voltage node, and further comprising:

a first electrical mains and a second electrical mains;

means for establishing a reference current;

an active nonlinear device having a first node, a second node, and a control input, said active nonlinear device characterized by a family of current-voltage (I-V) curves, each of said I-V curves relating device current through said first and second nodes to device voltage across said first and second nodes, said control input selecting one of said I-V curves, said active nonlinear device remaining in a saturated mode of operation;

said means for establishing a reference current is coupled in series with said active nonlinear device between said first and second power rails, thereby generating a predetermined voltage across said first and second nodes according to said reference current and a first I-V curve, said first node being said output voltage node;

current monitoring means for detecting an offset current through said first and second nodes, said offset current comprising the sum of said reference current and an error current;

feedback means responsive to said current sensing means and coupled to said control input, said feedback means modulating said control input to operate said active nonlinear device according to a second I-V curve via which said offset current corresponds to said predetermined voltage, whereby a substantially vertical load line is established at said predetermined voltage.

According to another aspect of the present invention, there is provided a constant voltage source having an output voltage node, and further comprising:

a first electrical mains and a second electrical mains;

means for establishing a reference current;

a first MOS transistor having a first source, a first drain, and a first gate coupled to the first power rail, the first MOS transistor characterized by a family I-V relationship, the first MOS transistor constantly maintained in a saturated mode of operation;

said means for establishing a reference current is coupled in series with said first MOS transistor between said first and second power rails, whereby said reference current establishes a predetermined voltage drop across the source and drain of said first MOS transistor according to a first I-V curve, said first drain being said output voltage node;

a monitoring device for detecting an error current through the first MOS transistor, the AC monitoring device being coupled to the first drain;

a profile control circuit responsive to the ac monitoring device and having a profile selection output coupled to the first control gate, the profile control circuit effective to adjust a channel conductance of the first MOS transistor to establish a second voltage across a source and a drain of the first MOS transistor according to a second I-V profile in response to a sum of the error current and the reference current through the first MOS transistor, the second voltage substantially equal to the predetermined voltage, thereby maintaining a substantially vertical load at the predetermined voltage drop; and

a coupling capacitor coupling an input signal to the output voltage node, the input signal effective to generate the error current.

a first electrical mains and a second electrical mains;

a current source generating a reference current;

a first MOS device having a first source, a first drain and a first gate coupled to the first power rail, the first MOS device characterized by a family of currents I_DSTo voltage V_DSThe first MOS device is constantly maintained in a saturation operating mode;

the current source is coupled in series with the first MOS device between the first and second power rails, thereby according to the reference current and I_DSTo V_DSEstablishing a predetermined voltage between the first source and the drain, the first drain being the output voltage node;

means for coupling an input signal to said output voltage node, said input signal effective to establish an offset current through said first MOS device, said offset current comprising a sum of said reference current and an error current;

a current monitoring device for detecting the offset current;

a profile control circuit responsive to the current monitoring device and having a profile selection output coupled to the first control gate, the profile control circuit effective to adjust a channel conductance of the first MOS transistor to a second I_DSTo V_GSCurve of said bias current flowing through said second I_DSTo V_GSThe curve is responsive to the predetermined voltage, thereby establishing a substantially vertical load line at the predetermined voltage.

The various objects of the present invention are achieved in a circuit that emulates a high impedance node to maintain a constant voltage output over a varying error current. The high-impedance node is simulated using an active nonlinear device (such as a BJT, JFET or MOS transistor) having a saturation region, and a constant current source is used to generate a steady-state current I through the nonlinear device_XYThereby establishing a quiescent voltage drop V across the nonlinear device_XY*. More preferably, I is generated by a constant current source_XYThe current is sufficient to place the active nonlinear device in its saturation region of operation. The active nonlinear device is characterized in that_XYAnd V_XYThe family of curves describes for a given control input the relationship between the current passing through it and the voltage across it. That is, control inputs to the non-linear device may be used to select any operating characteristic.

In operation, voltage fluctuations across the nonlinear device due to error currents through the nonlinear device are monitored by a characteristic curve selector circuit. When V is_XYWhen the voltage begins to change due to the introduction of an error current, the characteristic selector circuit sends a compensation signal to the control input of the nonlinear device. The compensation signal selects a new characteristic curve for the nonlinear device. The characteristic curve establishes I for the nonlinear device_XY' and V_XY' and the non-linear device takes into account the addition of an error current to the steady state current from the current source. The new characteristic curve is selected such that the new voltage drop across the non-linear device (corresponding to the steady state current plus the error current) is substantially equal to its initial quiescent voltage drop V_XYSame. Thus, the characteristic curve selector circuit will drop a new voltage V across the non-linear device despite the introduction of the error current_XY' Return to its V_XYInitial rest voltage value of x. In effect, the nonlinear device exhibits a vertical load line, maintaining a constant voltage output over a wide range of current values. Therefore, the output voltage can remain relatively stable, unaffected by fluctuations in the capacitively coupled input signal. Since the voltage output remains constant, the operation is efficient as if it were isolated from the input signal by a large resistor, thereby achieving simulation of the high impedance node.

In a preferred embodiment, the error current fluctuation is monitored indirectly by recording the resultant voltage fluctuation on one of the nodes of the nonlinear device. This makes the second effect of the present invention possible. This action allows it to compensate for Vcc fluctuations and maintain a constant voltage output. As described above, the present invention can maintain a constant V across its X and Y nodes over current fluctuations_XYVoltage drop. However, since the present invention cuts off power from Vcc and maintains V from Vcc_XYConstant voltage drop, so that, in situ, any voltage fluctuations in Vcc may be reflected on node X or node Y. Thus, the present invention monitors only one of node X and node Y, rather than by probing across node X and node YTo monitor V directly_XY. Since each node changes with changes in Vcc, this embodiment is able to detect changes in Vcc, and the profile selector will respond to a new operating point by modulating the control input of the non-linear device to change the vertical load line until a second V is found that will restore the voltage on the monitored one of nodes X and Y to its original value_XY"value".

Brief description of the drawings

Fig. 1 and 2 are prior art voltage amplifiers.

FIG. 3 is an illustration of current versus voltage characteristics of a prior art MOS transistor

Fig. 4 is an explanatory diagram of the characteristics of voltage and current of an actual voltage source.

Fig. 5 is a prior art constant voltage source.

Fig. 6 is a second embodiment of a prior art constant voltage source.

Figure 7 is a symbolic representation of a circuit according to the invention using sense resistors.

Fig. 8 is a circuit block of the first embodiment of the present invention.

Fig. 9 and 10 are graphical illustrations of the operation of one of the elements of fig. 8.

Fig. 11 is a circuit block of the second embodiment of the present invention.

Fig. 12 to 14 are graphical representations of a second function of one of the elements of fig. 8 and 11.

Fig. 15 is a circuit tool of the circuit block in fig. 8 and 11.

Fig. 16 is a voltage amplifier including the circuit configuration of fig. 15.

Implementation ofBest mode for carrying out the invention

The present invention does not employ the conventional approach of placing a resistor 41 between the voltage reference node 38 and the output node 40 coupled to the intrinsic capacitor 29, as shown in prior art fig. 6. Referring to fig. 7, the present invention is directed to introducing an inductive high impedance 44 between the output node 43 and the internal coupling capacitor 45. Since the input signal Vin is coupled to the constant voltage output signal V via the internal capacitor 45_BIASAre coupled, therefore, introduce V_BIASAnd a capacitor 45, the output signal V being effectively coupled by an inductive high impedance 44_BIASIsolated from the input signal Vin. However, the present invention discards the conventional structure of diode-connected transistor 47 in series with current drain 49 in order to create an induced high impedance 44 in an actual IC circuit.

The present invention creates a high impedance node that does not require the use of resistors, but rather only active devices. The present invention allows error current to flow freely rather than limiting the amount of error current that is capacitively coupled through the input signal to the voltage generating circuit. The present invention monitors all current fluctuations and adjusts the voltage generation circuitry to compensate for the current fluctuations.

Referring to fig. 8, the present invention includes an active nonlinear device 51 having a first node Y coupled to Vcc, a second node X coupled to a current sensing element 53, and a third node Z receiving a control signal. The active nonlinear device 51 is characterized by a family of curves that, at a given control input Z, relate the voltage V across nodes X and Y_XYWith current I through nodes X and Y_XYAnd (4) associating. Preferably, each of said curves is characterized by a linear ohmic region and a nonlinear saturation region, the active nonlinear device 51 may be one of a BJT, JFET or MOS transistor.

The active nonlinear device 51 is connected in series with a current drain 55 between Vcc and ground, the current drain 55 being represented by a resistive element, but it is understood that it may also be a constant current transducer insensitive to temperature and voltage variations. The purpose of the current drain 55 is to establish a current path from the active non-linear device 51 to ground through which a predetermined voltage can be applied across the active non-linear device 51.

By coupling capacitor 54, input signal Vin may be allowed to freely introduce error current Δ i to output node V_BIAS. At the output node V_BIASAnd the active nonlinear device 51, a current sensing element 53 is disposed therebetween to monitor the current passing therethrough. The current sensing element 53 has an output signal coupled to a characteristic control sub-circuit 57 which control sub-circuit 57 monitors the change in alternating current and selects one of the family of curves which will maintain the voltage across nodes X and Y constant at any given current through nodes X and Y. The output from the characteristic control 57 is applied to the control input node Z through a low pass filter 59. The low pass filter 59 stabilizes the control of the active nonlinear device 51 to filter out any off-time transients due to noise.

Referring to fig. 9, a first example of operation of the circuit of fig. 8 is shown. FIG. 9 is the current I through nodes X and Y for a given control signal Z_XYFor voltage V across nodes X and Y_XYThe relationship between them. In this example, Q at point 65 represents an initial I indicated by point 63_XYThe current and the initial control signal Z1 create a desired constant voltage drop across nodes X and Y. The quiescent voltage Q is determined at an initial operating point 61 at the intersection of the initial current point 63 and the initial control signal Z1. If the error current Δ I is to make the current I_XYFalling, the operating point along curve Z1 will tend to fall from point 61 to point 67. V_XYThis is typically reflected in a more severe drop from point 65 to point 69. To compensate for this voltage reduction, the characteristic curve control sub-circuit 57 in FIG. 8 will respond to the new operating position Z3 by adjusting Z. This operating position Z3 will effectively move the operating point of the active nonlinear device 51 from point 67 to point 71, thereby shifting the voltage V_XYFrom point 69 back to its original position at point 65. Due to this modulation of the control signal Z, the active nonlinear device 51 effectively exhibits a vertical load line 73. On the load line, pass throughThe voltages at nodes X and Y remain effectively stable over a wide range of current fluctuations Δ i through nodes X and Y.

Referring to fig. 10, a second example of operation of the circuit of fig. 8 is shown. In this example, the desired constant V at point 79_XYThe operating point of the voltage drop Q is indicated by operating point 76. As shown, the initial operating current I at operating point 76 and point 77_XYAnd the initial input control signal Z2. If an error current is introduced and the current I is made to be equal_XYIncrease Δ i, voltage V_XYWill correspond to the new operating point 81 tending to increase from point 79 to position 83 by Δ v. However, the characteristic curve control sub-circuit 57 shown in fig. 8 modulates the input control signal Z to a new operation position indicated by Z3. This will establish a new operating point 75 and thus the voltage V_XYReturning to its initial resting value Q at point 79. In addition, the device exhibits a vertical load line 85.

Since the voltage across nodes X and Y remains insensitive to variations in Vin, the present invention exhibits a high impedance node through the use of the transistor operating saturation region of device 51. In contrast to previous techniques that focused on limiting current ripple, the present invention modulates the voltage to the current relationship of the nonlinear device 51 to maintain a constant voltage drop over varying currents. In this way, large resistors are not required, thereby eliminating the introduction of resistor leakage currents and any additional internal distributed capacitance, which can limit the frequency response of the device.

Referring to fig. 11, a second embodiment of the present invention takes advantage of the non-linearity of the current versus voltage relationship in the saturation region of the active non-linear device 51. As shown above, the saturation region of the active nonlinear device 51 is characterized by large voltage fluctuations in response to small current changes. A second embodiment utilizes this transistor operation by monitoring V_XYThe voltage fluctuations are used to indirectly monitor the current changes through the active nonlinear device 51. While this can be done by monitoring the voltage drop across nodes X and Y, the second embodiment monitors only node Y, in contrast. This enables the second embodiment to access data not available in the previous embodimentsV subject to access_BIASA second source of voltage error.

A second source of voltage error results from variations in the power supply Vcc. As indicated above, the previous embodiments of the present invention maintain a relatively vertical load line for the active nonlinear device 51. This means that the voltage V across the active nonlinear device 51 is independent of current fluctuations_XYRemains relatively stable at some predetermined value Q. Due to V_XYIs Vcc minus the voltage V at node Y_XYRemains constant and therefore the voltage at node Y remains constant as the current fluctuates, as long as power supply Vcc remains constant. However, if the error voltage Δ Verr is introduced into the power supply Vcc, the same error voltage Δ Verr will be reflected on the node Y. Irrespective of V_XYIs held constant at Q, which will be at the output node V_BIASA voltage error Δ Verr is introduced. However, by monitoring the voltage at node Y, the second embodiment of the present invention addresses not only the problem of error current Δ i introduced by the input signal Vin, but also monitors and responds to voltage errors caused by power fluctuations Δ Verr.

In the present embodiment of fig. 11, the power drain as shown as resistor 5 in fig. 8 is replaced by a temperature and power insensitive current converter I_SINK56. Active nonlinear devices 51 and I_SINK56 are connected in series between Vcc and ground. As shown, the power supply Vcc of fig. 11 is susceptible to power fluctuations ± Δ Verr.

The input signal Vin is coupled to the output node V via the coupling capacitor 54_BIASAnd node Y. A voltage monitoring device 58 is coupled between node Y and ground. The voltage monitoring device 58 has an output signal coupled to the characteristic control 57. It monitors traffic fluctuations on node Y. Assuming Vcc is constant, voltage fluctuations on node Y will mean that active nonlinear device 51 is experiencing error current Δ i fluctuations. The characteristic control 57 will respond to ac voltage fluctuations by passing a control signal via low pass filter 59 to the input node Z of the active nonlinear device 51 to maintain the vertical load line applied to the device 51. As described above, the control signal Z is modulated to be onThe effective characteristic of device 51 is cycled through until voltage V_XYIs returned to its original position. In this case, V is used_XYIs indirectly monitored by recording voltage fluctuations on node Y, so the control signal Z is modulated until the voltage on node Y is returned to its original position. Assuming that Vcc is constant, this will drive the voltage V_XYAnd returns to the initial value of Q and the voltage on node Y to the initial value of Vcc-Q. Thus, the embodiment of FIG. 11 reproduces the response of the circuit of FIG. 8.

On the other hand, if it is assumed that no error current Δ i is 0 through the active nonlinear device 51, but Vcc instead experiences power fluctuation Δ Verr, then node Y will fluctuate with Δ Verr. The voltage monitoring device 58 in turn transmits this voltage fluctuation to the characteristic curve control 57, which in turn transmits a modulation control signal via the low-pass filter 59 to the control input Z. This selects a new characteristic curve for the active nonlinear device 51 to return the voltage on node Y to its original value, regardless of the power fluctuation Δ Verr. The resulting voltage across nodes X and Y may not necessarily be equal to the initial voltage drop Q. In effect, the vertical load line applied to the non-linear device 51 is switched to a new operating point, as will be described in detail below.

For example, assume the desired V of Q_XYThe voltage is maintained constant across nodes X and Y, V_BIASThe required bias voltage output is then defined as:

V_BIAS*＝Vcc-Q*

if a power fluctuation introduces an error voltage Δ Verr into Vcc, then a new bias voltage V_BIAS' will be:

V_BIAS’＝(Vcc±ΔVerr)-Q*

＝Vcc-Q*±ΔVerr

＝V_BIAS*±ΔVerr

thereby outputting the required output V_BIASWill reflect the error voltage Δ Verr and to compensate for this power voltage error, the characteristic control 57 moves the vertical load line of the active nonlinear device 51 to a new quiescent value Q' by an equal amount Δ Verr. For example, assume that a negative- Δ Verr is added to Vcc, thereby causing a new bias output V_BIAS' is:

V_BIAS’＝(Vcc-ΔVerr)-Q*

the characteristic control 57 will respond by shifting the vertical load line of the nonlinear device 51 from V via a quantity-Verr_XYQ is shifted to a new compensation value. In other words, the new rest value Q' is equal to the initial value of Q and the displacement of- Δ Verr, so that

V_BIAS’＝(Vcc-ΔVerr)-(Q*-ΔVerr)

＝(Vcc-ΔVerr-Q*+ΔVerr)

＝Vcc-Q*

＝V_BIAS*

As seen above, the new voltage drop of Q ═ Δ Verr is sufficient to reduce the voltage at node Y, i.e. the output bias voltage V_BIAS' Return to V_BIASInitial value of x.

FIG. 12 is a graphical depiction of how the second embodiment of the present invention addresses Vcc power fluctuations. Can be at a predetermined V which results in Q_XYA stationary operating point 62 is found at the intersection of the initial constant current Δ i of the voltage drop and the selected characteristic curve Z. The circuit of figure 11 can be more easily discussed separately for power, provided that no error current Δ I is introduced, and I is therefore kept constantError fluctuation ± Δ Verr. As shown, introducing a small modulation ± Z' into the control input Z can move the vertical load line 64 from the operating point 66 to the operating point 68 to the point 74 which results in a control voltage displacement over a wide range of Q ± Δ Q. Deviations in the power supply Vcc may be transient in nature or may be caused by gradual loss of power (e.g., natural aging of the battery). Due to large V_XYIn response to small Z modulation, the circuit can quickly respond to power transients and a gradual reduction in the power supply.

Referring to fig. 13, a first example of operation of the circuit of fig. 11 is shown in response to power fluctuations in Vcc. In fig. 13, it is assumed that no error current Δ i is introduced through the capacitively coupled input Vin, thereby keeping the current Δ i constant. Further assume that an initial control input of Z places device 51 at operating point 70 with a quiescent voltage drop of Q. Assuming that Vcc receives a negative power fluctuation of- Δ Verr, the characteristic control 57 of fig. 11 will respond by shifting the vertical load line 64 from an initial position at point Q x down to a new position Q' by an equal amount- Δ Verr. This is achieved by modulating the control input of the active nonlinear device 51 from Z to the new characteristic curve Z'. This switches the operating point from point 70 to point 72 and reduces the voltage drop across nodes X and Y by an amount- Δ Verr to a new Q'. As described above, this new value is sufficient to restore the voltage at node Y to its original value.

The new quiescent operating point of Q' remains constant as long as no new power fluctuations are experienced. In this manner, the vertical load line 64 is converted to a new orientation 64'. As described above with reference to fig. 8 to 10, that is, if the power supply is maintained at Vcc- Δ Verr and the input signal Vin will introduce current fluctuations Δ i, then the circuit in fig. 11 will respond to maintain the voltage drop across nodes X and Y at Q'.

Referring to FIG. 14, a second example of operation assumes that Vcc receives a positive voltage fluctuation of + Δ Verr. The circuit of fig. 11, in turn, responds by modulating the control input from Z to Z', moving the vertical load line 80 from operating point 74 to operating point 78 by an amount + Δ Verr. This generates a new quiescent operation value Q'. The operating value Q' is maintained constant as long as the power supply does not vary. If the power supply is to be returned to the initial value of Vcc, the circuit of figure 11 will return the voltage drop across nodes X and Y to the initial value of Q by returning the control input of non-linear device 51 to its initial characteristic curve Z.

As can be seen from the above, the present circuit responds to two different sources of error, and in the first case, the present invention is able to maintain a vertical load line across the nonlinear device, thereby making the voltage drop across it independent of current error fluctuations Δ i. Thus, it remains safe under current fluctuations introduced by a capacitively coupled input signal Vin. In the second case, the circuit can also correct for power fluctuations in Vcc by monitoring a node of the non-linear device 51 and compensating for power fluctuations by continuously diverting the desired voltage drop Q 'across the non-linear device 51 and maintaining a vertical load line at that new voltage drop Q'.

Referring to fig. 15, a CMOS implementation of the invention is shown. In this embodiment, the active nonlinear device 51 in fig. 8 and 11 is implemented by a pmos transistor 91 in fig. 15. The Pmos transistor 91 has a drain 92 coupled to a current transformer 93, whereby the Pmos transistor 91 is connected in series with the current transformer 93 between Vcc and ground. Constant bias voltage V_BIASTapped off from node 100 at the junction of drain 92 and current transformer 93. The input signal Vin is coupled to the node 100 via an internal capacitance 54. The Pmos transistor 91 operates in its saturation region and, as described above, at small I_DSExperiences a large V on the current fluctuation_DSThe voltage fluctuates. Because of this operation, transistors in the saturation region have traditionally been used as current sources without well-formed voltage sources. However, because of this increased sensitivity of the voltage to current variations, the present embodiment indirectly monitors current fluctuations through transistor 91 by recording the resultant voltage fluctuations at node 100. Thus, the circuit of FIG. 15 is in accordance with the second embodiment of the invention shown in FIG. 11In an embodiment, a voltage monitoring subcircuit 58 is used in place of the current sensing element 53 in FIG. 8.

Within subcircuit 58, a second pmos transistor 93 has a gate coupled to node 100 and a drain 94 coupled to drain 96 of nmos transistor 95. The Pmos transistor 93 and nmos transistor 95 are connected in series between Vcc and ground. The voltage fluctuation at the gate of pmos transistor 93 causes current fluctuation in transistor 93. The current through transistor 93 effectively becomes a measure of the current ripple through transistor 91. Transistor 95 has a control gate 97 coupled to its drain 96 so that it can again generate a gate voltage representative of the current through transistor 93. Thus, the gate voltage of the transistor 95 is reflected on the characteristic curve control 57.

The characteristic control 57 is implemented by a third pmos transistor 101 connected in series with a second nmos transistor 99, both connected in series between Vcc and ground. The drain 98 of the Pmos transistor 101 is coupled to its gate 104. Thus, a measure of the voltage at gate 97 of the current ripple through node 100 is communicated to characteristic control 57 and the current through transistors 99 and 101 is adjusted accordingly. Transistor 101 generates a compensation voltage at its gate and passes it to the gate of pmos transistor 91 via low pass filter 59 comprising capacitor 103.

The voltage polarity and current ripple of the non-linear device 51 will depend on the type of device (pmos, nmos, etc.) used to implement the element 51. For simplicity, the following discussion will refer only to the magnitude of the voltage and current fluctuations. Interpretation of the correct polarity for a given device type is considered to be within the ability of one of ordinary skill in the art.

Assuming Vcc is constant, the voltage increase at node 100 corresponds in magnitude to the source-drain voltage V across transistor 91_DSThe voltage drop of (c). Likewise, V of transistor 91_DSOne voltage drop in the voltage corresponds to its source-drain current I_DSOne voltage drop of (a). Similarly, the voltage drop at node 100 corresponds to V of transistor 91_DSVoltage ofIncreases in amplitude. Thus, a decrease in current through transistor 91 indicates an increase in voltage at node 100, while an increase in current through transistor 91 indicates a decrease in voltage at node 100.

Referring to fig. 9 and 15, it is assumed that the family of curves depicted in fig. 9 clearly represents the characteristic operation of the transistor 91. Further assume that the magnitude of the current I through transistor 91_DSIs represented as a current value I in FIG. 9_XYAmplitude of voltage V across transistor 91_DSIs represented as a voltage value V in FIG. 9_XY. Current I through transistor 91_XYIs the current I through the current transducer 93_SINKPlus the sum of any error current Δ i introduced by the capacitively coupled input signal Vin, as follows:

I_XY＝I_SINK±Δi

it is assumed that the input signal Vin is not added first, and thus, no error current Δ i is introduced as 0. If the characteristic control 57 applies an initial control voltage of Z1 to the gate of the transistor 91 and the constant current transformer 93 has a current magnitude as explicitly indicated by point 63, this will establish a quiescent voltage drop (V) of a value Q across the source to drain of the transistor 91_XY)。

If the input signal Vin is added and an error current Δ I is introduced at node 100, this will result in I of transistor 91_DSThe- Δ i in the current decreases. It V_DSThe voltage will tend to respond by decreasing toward point 69. As shown above, V of transistor 91_DSThe decrease in voltage will result in an increase in voltage at node 100.

Subcircuit 58 responds to the voltage increase at node 100 by reducing the current sourcing capability of transistor 93. Transistor 95 can pull down the potential at its gate because the current through transistor 93 is reduced. This low potential is reflected in transistor 99 of characteristic control 57. The reduced potential at the gate of transistor 99 causes it to reduce its current sourcing capability. Transistor 101 couples the pass-through transistor by raising the voltage at its control gate 104The reduced current of the transistor 99 responds. This voltage increase is passed to the control gate of transistor 91 via low pass filter 59. When the voltage at the control gate of transistor 91 increases, its source-gate voltage V_DSFalls to a new value Z3. While maintaining I_DS＝I_SINKLower V of Z3 at new current of Δ i_GSVoltage increase of V_DSThe voltage amplitude returns to the original value of Q.

Referring to fig. 10 and 15, if on the other hand, assume that the input signal Vin draws the error current Δ I from node 100, this will result in I of transistor 91_DSThe current increases by + Δ i. As a result, V of transistor 91_DSThe voltage will tend to respond by increasing from the initial value Q at point 79 to point 83. V across transistor 91 as described above_DSThe increase in amplitude will result in a voltage drop at node 100.

Subcircuit 58 responds to the voltage drop at node 100 by increasing the current sourcing capability of transistor 93. Thus, the transistor 93 pulls up the potential at the gate of the transistor 95. The comparatively high potential is reflected in transistor 99 of characteristic control 57. The higher potential at the gate of transistor 99 causes it to increase its current sourcing capability, pulling the potential down at the gate 104 of transistor 101. This voltage drop is passed to the control gate of transistor 91 via low pass filter 59. When the voltage at the control gate of transistor 91 drops, its V_GSThe voltage magnitude increases to a new value Z3. While maintaining I_DS＝I_SINKHigher V of Z3 at new current of + Δ i_GSV of the voltage reducing transistor 91_DSVoltage, back to the original value of Q.

In the two previous examples of operation of the circuit of fig. 15, it was assumed that Vcc remained constant. As a result, the voltage fluctuation at node 100 is only due to the error current Δ i introduced by the capacitively coupled input signal Vin to cause V across transistor 91_DSCaused by the wave motion. Thus, by actively modulating the control input Z of transistor 91 to maintain the voltage at node 100 constant, V across transistor 91_DSCan be maintained relatively constant. In other words, by locating node 100Returns to its initial value, and may return to V of transistor 91_DSReverting to its initial value. Thus, regardless of the cause of these fluctuations, circuit blocks 57, 58, and 59 modulate the gate of transistor 91 according to the voltage fluctuations at node 100. For example, if the voltage fluctuation at node 100 is introduced by fluctuations in Vcc, the present invention will also adjust transistor 91 to restore the voltage at node 100 to its original steady state value as described with reference to FIGS. 12-14. Thus, if the voltage fluctuation at node 100 is not caused by the error current Δ i, but rather by power fluctuations in Vcc, then voltage monitoring device 58 will respond to these fluctuations by communicating a measure of the voltage fluctuation to characteristic control 57. Subcircuit 57 will then respond by modulating the control gate of transistor 91 and shifting its vertical load line to a new operating point until the voltage at node 100 returns to its original value. In the case where the voltage fluctuation at node 100 is caused by power fluctuations and the introduction of an error current Δ i, the circuit in fig. 15 will respond to both errors simultaneously and adjust node 100 to its initial value again.

Referring to fig. 16, an ac signal amplifier including a preferred embodiment of the present invention is shown. For clarity, all elements having similar functions to those of fig. 15 are denoted by similar reference numerals in fig. 15, which have been given above. The input signal Vin is applied to a voltage amplifier 111 having an output signal Vout. Voltage amplifier 111 is comprised of a pmos transistor 113 and an nmos transistor 115 connected in series between Vcc and ground, with Vout tapped at the drains of transistors 113 and 115. Input signal Vin is coupled to the control gate of transistor 115; transistor 113 acts as a constant current source to establish a predetermined load line and gain for amplifier 111. The transistor 113 has a constant control signal V_BIASThe determined quiescent current value. The input signal Vin is also shown through an internal capacitor 54 and the control gate of pmos transistor 113 and V_BIASAre coupled.

Generating a control signal V by pmos transistor 91, circuit block 117 and circuit block 102_BIAS。PmThe os transistor 91 has its source coupled to Vcc and its drain connected to the circuit block 117 at node 100. Circuit block 117 is one preferred implementation of a current transformer that is insensitive to power and temperature. More preferably, it establishes a steady state current value sufficient to place the pmos transistor 91 in its saturation mode of operation. The current transformer 117 includes a constant current source 105 coupled between Vcc and transistor 107. The drain 108 of the transistor 107 is coupled to its control gate 106 so that it generates a source-gate voltage that depends on the value of the current source 105. The source-gate voltage of transistor 107 is reflected on transistor 107. The transistor 107 establishes a current path from the node 100 to ground.

Circuit block 102 includes sub-circuits 57, 58, and 59 shown in fig. 15. As shown in FIG. 16, the voltage at node 100 is monitored at the gate of pmos transistor 93. As described above, the pmos transistor 93 captures a measure of the source-to-drain current through transistor 91 and the fluctuations in Vcc. A current through transistor 93 is reflected in transistor 99 via transistor 95. In response to the current through transistor 99, transistor 101 establishes a compensation voltage and passes it to the control gate of pmos transistor 91 via a low pass filter comprising capacitor 103. In this way, circuit block 102 monitors power fluctuations in the error currents Δ i and Vcc through transistor 91 and adjusts the operating point of transistor 91 so as to maintain the voltage at node 100 constant. In effect, circuit block 102 establishes a switchable vertical load line for transistor 91. Thus, over a wide range of power fluctuations in Vcc and current fluctuations introduced by input signal Vin, V_BIASRemain relatively constant. Due to the voltage V at the gate of transistor 113_BIASIs relatively unaffected by Vin, so the circuit operates as if it had a very high impedance 119 coupling capacitor 54 to V_BIASAnd the control gate of transistor 113. Thus, the present invention achieves an effective high impedance node and constant V of node 100 using only active devices and eliminating the need for large resistors_BIAS。

Claims

1. A constant voltage source having an output voltage node, and further comprising:

a first electrical mains and a second electrical mains;

means for establishing a reference current;

2. The constant voltage source of claim 1, wherein the active nonlinear device is one of a BJT transistor, a JFET transistor, and a MOS transistor.

3. The constant voltage source of claim 1 further comprising power monitoring means for detecting an error voltage in said first and second power rails, said feedback means being responsive to said power monitoring means for operating said active nonlinear device according to a third I-V curve, wherein said predetermined voltage shifts by an amplitude substantially equal to said error voltage.

4. The constant voltage source of claim 1 further comprising means for coupling an input signal to said output voltage node, said input signal producing said error current.

5. The constant voltage source of claim 1, wherein said current monitoring means comprises a voltage monitoring means coupled across said first node and one of said first and second power rails, whereby current fluctuations through said nonlinear device are indirectly detected by said voltage monitoring means as consequent voltage fluctuations across said first and second nodes.

6. The constant voltage source of claim 5, wherein the active nonlinear device is one of a BJT, a JFET, and a MOS transistor.

7. The constant voltage source of claim 5, wherein said second node is connected to one of said first and second power rails, whereby the voltage at said first node fluctuates with said error current through said active nonlinear device and with the error voltage of Vcc.

8. The constant voltage source of claim 7, wherein said voltage monitoring means comprises first and second MOS transistors, said first MOS transistor having a first source, a first drain, and a first control gate, said second MOS transistor having a second source, a second drain, and a second control gate;

the first and second MOS transistors are coupled in series between the first power rail and a second power rail, wherein the first source is coupled to one of the first and second power rails, the first control gate is coupled to the output voltage node, and the second drain is coupled to the second control gate, thereby producing a measure of voltage fluctuation at the output voltage node at the second control gate.

9. The constant voltage source of claim 8, wherein said feedback means comprises third and fourth MOS transistors, said third MOS transistor having a third source, a third drain, and a third control gate, said fourth MOS transistor having a fourth source, a fourth drain, and a fourth control gate,

the third and fourth MOS transistors are coupled in series between the first and second power rails, wherein the third source is coupled to one of the first and second power rails, the fourth control gate receives the measure voltage, and the third control gate is coupled to the third drain, thereby producing a compensation voltage at the third control gate that is applied to the control input of the nonlinear device.

10. The constant voltage source of claim 9, wherein said compensation voltage is applied to said control input via a low pass filter.

11. The constant voltage source of claim 10, wherein said low pass filter comprises a capacitor coupled between said control input and one of said first and second power rails.

12. The constant voltage source of claim 7 further comprising means for coupling an input signal to said output voltage node, said input signal effective to generate said error current.

13. The constant voltage source of claim 12, wherein said means for coupling an input signal is a coupling capacitor.

14. The constant voltage source of claim 13, wherein said coupling capacitor is an intrinsic capacitor.

15. A constant voltage source having an output voltage node, and further comprising:

a first electrical mains and a second electrical mains;

means for establishing a reference current;

16. The constant voltage source of claim 15, wherein said ac monitoring means comprises second and third MOS transistors, said second MOS transistor having a second source, a second drain and a second control gate, said third MOS transistor having a third source, a third drain and a third control gate, said second and third MOS transistors being coupled in series between said first and second power rails, said second control gate being coupled to said voltage output node, said third control gate being coupled to said third drain, whereby said ac monitoring means further monitors voltages in said first and second power rails, said third control gate producing a measured voltage being dependent on current fluctuations through said first MOS transistor and error voltages in said power rails.

17. The constant voltage source of claim 17, wherein one of said second and third MOS transistors is a PMOS device and the other is an NMOS device.

18. The constant voltage source of claim 17, wherein said third control gate is coupled to said characteristic control circuit.

19. The constant voltage source of claim 15, wherein said characteristic control circuit comprises:

a fourth MOS transistor having a fourth source, a fourth drain, and a fourth control gate;

a fifth MOS transistor having a fifth source, a fifth drain, and a fifth control gate;

the fourth and fifth MOS transistors are coupled in series between the first and second power rails, the fourth control gate is coupled to the ac monitoring device, the fifth control gate is coupled to the fifth drain, the fifth control gate further selects an output for a curve coupled to the first control gate.

20. The constant voltage source of claim 20, wherein one of said fourth and fifth transistors is a PMOS device and the other is an NMOS device.

21. The constant voltage source of claim 15, wherein said curve select output is coupled to said first control gate via a low pass filter.

22. The constant voltage source of claim 22, wherein said low pass filter comprises a capacitor coupled from said curve select output to one of said first and second power rails.

23. The constant voltage source of claim 15, wherein said coupling capacitor is an intrinsic capacitor.

24. A constant voltage source having an output voltage node, and further comprising:

a first electrical mains and a second electrical mains;

a current source generating a reference current;

a current monitoring device for detecting the offset current;

25. The constant voltage source of claim 24, wherein said current monitoring means comprises:

a second MOS device having a second source, a second drain, and a second control gate, the second control gate coupled to the output voltage node;

a third MOS device having a third source, a third drain, and a third control gate, the third control gate coupled to the third drain;

the second and third MOS devices are coupled in series between the first and second power rails, whereby the ac monitoring means further monitors the error voltage in the first and second power rails, the third control gate producing a measurement voltage being dependent on fluctuations in current through the first MOS device and the error voltage in the power rails, the third control gate being coupled to the characteristic control circuit.

26. The constant voltage source of claim 25, wherein said characteristic control circuit comprises:

a fourth MOS transistor having a fourth source, a fourth drain, and a fourth control gate, the fourth control gate coupled to the third control gate;

a fifth MOS transistor having a fifth source, a fifth drain, and a fifth control gate, the fifth control gate coupled to the fifth drain;

the fourth and fifth MOS transistors are coupled in series between the first and second power rails, the fifth control gate is further a profile select signal coupled to the first control gate, the profile control circuit is further responsive to the measured voltage according to a third I_DSTo V_DSCurve operating said first MOS device, wherein said predetermined voltage is offset by an amplitude substantially equal to said error voltage.

27. The constant voltage source of claim 26, wherein one of said second and third MOS devices is a PMOS device and the other is an NMOS device, and wherein one of said fourth and fifth MOS devices is a PMOS device and the other is an NMOS device.

28. The constant voltage source of claim 26, wherein the fifth control gate is coupled to the first control gate via a low pass filter.

29. The constant voltage source of claim 28, wherein said low pass filter comprises a capacitor coupled from said fifth control gate to said first and second power rails.

30. The constant voltage source of claim 26, wherein said means for coupling an input signal is a coupling capacitor.

31. The constant voltage source of claim 30, wherein said coupling capacitor is an intrinsic capacitor.

32. The constant voltage source of claim 26, wherein said first MOS device is a PMOS transistor.