HK1021777B - Frequency lock indicator for fpll demodulated signal having a pilot - Google Patents

Description

Frequency lock indicator for FPLL demodulated signal with one pilot

This application is a continuation-in-part application of the present inventors to application D6957, entitled D6957: the FPLL polarity is controlled using a pilot signal and a polarity inverter.

The present invention relates generally to demodulation systems and, more particularly, to a demodulation system incorporating an FPLL (frequency and phase locked loop) for demodulating Vestigial Sideband (VSB) digital signals using a pilot.

FPLL demodulation circuits have been used for many years and are described in detail in U.S. patent nos. 4,072,909 and 4,091,410. Both assigned to the assignee of the present application and incorporated herein by reference. FPLLs are bi-phase stable and therefore require some mechanism to ensure proper polarity of the demodulated output signal when, for example, they are used in television receiver circuits and the like. In prior art circuits, an information signal (e.g., a data signal) is generated at an output terminal that includes a known component indicative of the lock phase or polarity of the FPLL. This component is used to control the inverter to selectively invert the FPLL output signal to ensure a particular polarity.

The invention uses a transmitted digital signal that includes a small in-phase pilot to ensure signal acquisition in the receiver. The pilot is inserted into the data signal prior to modulation, in the form of a baseband DC bias voltage, and when demodulated in the receiver, generates a corresponding DC voltage. The present invention uses the dc voltage to determine the polarity of the FPLL lock in the receiver and to correct the polarity of the demodulated output signal if necessary.

One of the main objects of the present invention is: a novel FPLL system is provided for digital signals having a pilot.

Another object of the invention is: an improved demodulator is provided for digital signals having a pilot.

Further objects of the invention are: a novel frequency lock indicator is provided for an FPLL demodulated signal having a pilot.

These and further objects, as well as advantages, of the present invention will become apparent upon reading the following description and upon reference to the accompanying drawings.

FIG. 1 is a simplified block diagram of a prior art FPLL demodulator;

FIG. 2 is a block diagram of an FPLL demodulator included in the present invention;

FIGS. 3, 4 and 5 are waveform diagrams of points indicated by the block diagram of FIG. 2;

FIG. 6 is a frequency lock indicator of the present invention; and

fig. 7 is a waveform of selected points of the circuit of fig. 6.

Referring to the prior art FPLL of fig. 1, a first multiplier 10 and a second multiplier 12 having a common input signal and a demodulated signal having a phase difference of 90 ° after passing through a phase shifter 14, the phase shifter 14 being driven by a Voltage Controlled Oscillator (VCO)16 which is in turn driven by the output of an APC filter 18, the output of a third multiplier 20 being provided at 18. Two low pass filters 22 and 24 are connected to the outputs of the first and second multipliers 10 and 12, respectively. Low pass filter 22 provides the demodulated signal to signal processor 30 for further processing. The output of low pass filter 22 is also provided to AFC low pass filter 26. The AFC low-pass filter 26 is connected to a limiter 28, the output of which is provided to one input of the third multiplier 20. The other input of the third multiplier 20 is provided by a low pass filter 24.

The prior art FPLL circuit is capable of demodulating an input signal and inputting it to signal processor 30. As is known, the upper part of the block diagram generally includes an Automatic Frequency Control (AFC) loop and the lower part includes an Automatic Phase Control (APC) loop. When frequency locking between the VCO signal and the input signal occurs, the polarity of the demodulated signal input to the signal processor 30 may be positive or negative depending on the phase relationship between the input signal and the demodulated output of the phase shifter 14. In the circuit of fig. 1, since no means are shown to compensate for the bi-phase stability of the loop, and thus to make the demodulated output either polar, i.e. positive or negative.

In the circuit of fig. 2, the FPLL circuit of fig. 1 is repeated as necessary, and like elements are designated by like reference numerals. The low pass filter 2 outputs at the junction labelled a to a further low pass filter 32 which has a different characteristic (e.g. low bandwidth) to the AFC low pass filter 26. The output of the low pass filter 32 is labeled B and is input to a limiter 34, the output of which is labeled C. The limiter 34 is connected to a polarity determination circuit 36 and a frequency locker indication circuit 38. The frequency lock indicator circuit 38, in turn, is connected to and controls the operation of the polarity determination circuit 36. The phase determination circuit 36 is connected in solid lines to an inverter 40 between the input signal terminal and the first and second multipliers 10 and 12. Polarity determination circuit 36 is also connected in dashed lines to an inverter 42 (in dashed lines) between low pass filter 22 and signal processor 30. It can be understood that: only one of the dashed and solid line forms of the circuit is implemented.

After FPLL locking, the output of low pass filter 32 includes the demodulated data signal and a DC voltage representing the pilot. The signal is input to a low pass filter 32 and a limiter 34 which generates a DC voltage at the output of the limiter 34 indicative of the pilot polarity. As can be seen in connection with fig. 4 and 5, the output of limiter 34 may be above or below the zero carrier level before locking and at a positive or negative level when frequency locking occurs, depending on the locking phase of the bistable FPLL. By the pilot demodulation signal level, the phase determination circuit 36 determines whether the input signal or the demodulation output signal should be inverted to input a predetermined polarity signal to the signal processor 30. Depending on the circuit implementation used, the inversion is achieved using either a feed-forward or a feedback approach. An inverter 40 is included in the solid line circuit when the polarity of the demodulation pilot signal indicates that the demodulated output signal will not have a predetermined polarity, and a feedback scheme is used when the input signal is inverted. On the other hand, the feed forward circuit approach, indicated by the dashed line circuit including inverter 42, will accomplish the same result by inverting the demodulated output signal before it is input to signal processor 30.

It should be noted that the polarity determination circuit 36 is not activated until the frequency lock indicator circuit 38 determines the lock state. This occurs when the output of limiter 34 becomes static (does not change) over a period of time. In practice, if the limiter output is constant for a predetermined time, it can be assumed that the FPLL is either frequency locked or is so close to being frequency locked that it is within one half cycle of the PLL lock range. In either state, the polarity of the demodulator output can be determined and corrected if necessary. Further confidence in the frequency lock may be obtained by using a confidence counter indicating that a sufficient number of predetermined discontinuities have occurred in succession to warrant a frequency lock condition. Alternatively, a long predetermined break may be used to check the limiter output. For example, for a 1.0 millisecond interval, a beat frequency of 500Hz or higher is considered an unlocked signal. In other FPLL applications, where a frequency lock detection scheme (using small pilots) is used, frequency locking must occur before other signal processing can take place.

Upon receiving a digital 8-level VSB signal containing a DC in-phase pilot component, fig. 3, 4 and 5 show signal waveforms at points a, B and C, respectively, of the FPLL of fig. 2. The legend labeled case (1) indicates a state where the FPLL is positively locked, the legend labeled case (2) indicates a state where the FPLL is negatively locked, and the legend labeled case (2) indicates that the FPLL is frequency unlocked.

For case (3) (frequency unlocked), the signal at the data output of LPF22 (fig. 3) varies at zero-mean above and below the zero-carrier level. This causes a sinusoidal ripple signal at the output of the LPF (fig. 4) in response to the frequency difference of the two signals input to the multiplier 10. A corresponding square wave signal is thus generated at the output of limiter 34 (fig. 5). The square wave signal at the output of limiter 34 indicates a condition where the FPLL frequency is not locked and is detected by frequency lock indicator circuit 38 to disable polarity determination circuit 36.

Once frequency locked, the demodulated data signal at the output of AFC LPF26 will take one of the forms in case (1) or (2) of fig. 3. The average level of the data signal is greater than the zero carrier level in case (1) and causes the output of LPF32 (fig. 4) to be a positive DC voltage. The output of limiter 34 (fig. 5) is thus a +1 signal, which is detected by frequency lock indicator circuit 38 and activates polarity determination circuit 36. Circuit 36, in turn, senses the +1 output of limiter 34 to determine that the FPLL has reached positive polarity lock and generates an output control signal to either inverter 40 or 42 to maintain the current state of the inverter.

For case (2) of fig. 3, the average level of the data signal at the output of the LPF is below the zero carrier level and therefore the output of the LPF32 (fig. 4) is made a negative DC voltage. The output of limiter 34 (fig. 5) is thus a-1 signal, which is also detected by frequency lock indicator circuit 38 and enables polarity determination circuit 36. Circuit 36, in this case, senses the-1 output of limiter 34 to determine that the FPLL has reached negative polarity lock and generates an output control signal to inverter 40 or 42 to change the current state of the inverter. That is, if the inverter is in a non-inverting state, it will switch to an inverting state, and vice versa.

The frequency lock indicator circuit 38 of the present invention is illustrated in detail in fig. 6 and 7. Part of the circuitry of the FPLL in fig. 1 is duplicated. In particular, the low pass filters 22 and 24, the APC LPF26, the limiter 28, and the third multiplier 20 are drawn. The frequency lock indicator circuit includes a zero crossing detector 50, a first latch 56, a timer 58 and a second latch 62. An optional confidence counter 60 is drawn in dashed lines. The clock input of second latch 62 is connected to the reset terminal of first latch 56. Thus, the output of the second latch 62 remains constant as long as it is locked or unlocked. The zero crossing detector 50 includes a delay circuit 52 and an exclusive or gate (XOR) 54. With an input provided by the limiter 28 (labeled F) output, which is also provided to the polarity determination circuit 36. Delay 52 and XOR54 combine an edge detector that acts as the square wave output of limiter 28 and generates a pulse corresponding to the square wave edge. This is illustrated in detail in fig. 7.

Waveform E of fig. 7 is input to limiter 28, which is a pulse frequency signal at an attenuated frequency due to the phase lock of the FPLL. At phase lock, the signal becomes either +1 or-1, depending on the phase that the FPLL locks. Waveform F, as described above, is a square wave generated by limiter 28 from waveform E. The edges of the square wave F correspond to the zero crossings of the pulse frequency signal E. Waveform G is obtained at the output of XOR54 and is treated as a series of spikes that correspond to square wave F, i.e. occur at the zero crossings of waveform E. The width of the pulse depends on the delay of the delay, which is not critical.

Referring again to fig. 6, the pulses of waveform G are stored in first latch 56, and timer 58 controls the sampling of first latch 56 via a clock input and the resetting of first latch 56 via a reset input. First latch 56 may conveniently set its output to a "1" level if no zero crossing is collected by latch 56 within the time period set by timer 58. Since no zero crossing occurs within the predetermined time period, a control signal indicative of frequency locking may be generated. In this embodiment, the time period may be quite long, on the order of seconds. If, on the contrary, one or more edges are collected by latch 56 within the established time period, a control signal indicative of a frequency unlocked condition will be generated at the latch output. The control signal output of first latch 56 is provided through second latch 62 to polarity determination circuit 36, which observes the polarity of the signal received from the output of slicer 28. In response to the detection of the frequency lock, if the polarity is correct, no modification is made. Conversely, if not, polarity determination circuit 36 outputs an appropriate signal to inverter (40 or 42) to produce a data output of the appropriate polarity.

In the case where an optional confidence counter 60 is used, the signal output of the first latch 56 will be provided to the confidence counter 60 through a second latch 62, which will sample at a higher frequency. The confidence counter will increment each time a non-zero-crossing is found within the selected sample time until a predetermined number of "non-zero-crossing samples" is reached. When this occurs (corresponding to the DC output of limiter 28), the confidence counter will provide a lock indication signal to polarity determination circuit 36 and operation will proceed as described above.

A novel FPLL frequency lock indicator circuit is described for use with digital signals having a pilot. It will be appreciated that those skilled in the art can make various modifications to the embodiments of the invention without departing from the spirit and scope of the invention. The invention is limited only by the claims.

Claims (10)

1. A frequency lock indicator for use with an FPLL demodulator for demodulating a received signal having a pilot signal, the frequency lock indicator comprising: zero-crossing detector means for detecting zero-crossing points of said demodulated pilot signal; control signal generating means for generating a control signal in response to said zero-crossing detecting means; and frequency locking indication generating means responsive to said control signal for generating a frequency locking indication.

2. The frequency locked indicator of claim 1, wherein: said control signal generating means comprises means for detecting one or more zero crossings of said demodulated pilot signal during a selected time interval.

3. The frequency locked indicator of claim 2, wherein: the frequency lock indication generating means comprises a confidence counter for determining when the control signal is substantially DC.

4. The frequency locked indicator of claim 2, wherein: said FPLL demodulator producing a beat frequency square wave signal when the frequency is not locked, and further characterized in that the zero crossing detector means comprises means for converting said square wave beat signal into pulses.

5. The frequency locked indicator of claim 4, wherein: the frequency lock indication generating means comprises confidence counter means for generating said frequency lock indication when no zero crossing is detected within a predetermined number of said pulses.

6. The frequency locked indicator of claim 4, wherein: said conversion means comprises an exclusive or gate and a delay circuit, said beat frequency square wave signal being applied to said exclusive or gate directly and through said delay circuit.

7. An FPLL demodulator characterized by means for demodulating an input signal having a pilot signal, said demodulating means including means for generating a pair of oscillator signals 90 ° out of phase to produce a limited output signal corresponding to said demodulated pilot signal, zero crossing detecting means for receiving said limited output signal and determining zero crossing points, sampling means for determining whether one or more of said zero crossing points occur within a predetermined time interval, and means responsive to said sampling means for generating a lock signal indicative of the frequency lock of said FPLL demodulator.

8. The FPLL demodulator of claim 7, wherein: the zero-cross detection means includes means for generating a pulse corresponding to the zero-cross point, and wherein the sampling means includes latch means for temporarily storing the pulse generated by the zero-cross detection means.

9. The FPLL demodulator of claim 8, wherein: the pulse generating means comprises a delay circuit and an exclusive or gate to which the limited output signal is applied directly and via the delay circuit.

10. The FPLL demodulator of claim 8, wherein: the lock signal generating means comprises confidence counter means for determining from the pulses when the substantially DC limited output signal has been received.