HK1021245B - A device for processing sampled analogue signals - Google Patents

Description

Apparatus for processing sampled analog signals

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The present invention relates to a method for processing a sampled analog signal in a digital BiCMOS process, and an apparatus for processing a sampled analog signal in a digital BiCMOS process.

The switched current (SI) technology is a relatively new analog sampling digital signal processing technology that fully utilizes digital CMOS technology, such as "switched currents, an analog technology in digital technology" written by Peter peregrinus, c.toumazou, j.b.hughes and n.c.batterby, 1993. The ultimate performance of the SI circuit is mainly determined by the transconductance g of the MOS transistor_mAnd a capacitance C looking into its gate_gAnd (4) determining. Although high speed operation (about 100MHz) is possible, its speed and accuracy performance is limited by its own technology. To have high accuracy, large C is usually required_gSince the clock feed-through error is AND_gIn inverse proportion. Thus, g is increased_mIs the only way to increase speed. With the same bias current, the transconductance of the MOS transistor is significantly lower than that of the bipolar transistor. Thus, the use of bipolar transistors may increase speed and/or improve accuracy. BiCMOS technology opens the possibility of using both MOS and bipolar transistors.

One technique for processing high-speed sampled data signals in BiCMOS has been proposed, for example, "a new BiCMOS technology for conversion of the real time signaling" written by p.shak and c.toumazou, in proc.1995 innovative symposium on circuit and systems pp.323-326. The use of bipolar transistors breaks the gm/Cg limit of the SI circuit. It first converts the current into a voltage through a transconductor and then converts the voltage into a current through a transconductor. The voltage is sampled and held at the input of the transconductor, whose input device is a MOS transistor. However, the accuracy of the conversion is determined by the absolute values of some elements. For example, the resistor determines the transimpedance value, while the size and operating conditions of the transistor determine the transconductance value. This technique is therefore sensitive to process variations, another drawback being its complexity.

A patent application on the technique known as switched current technology, has been proposed by John b.hughes, philips, u.k, e.g. EP89203067.7, 1989-12-04. All of these applications focus on digital CMOS processing technology.

In digital BiCMOS processing, the memory capacity of the MOS transistors and the large transconductance of the bipolar transistors can be exploited in such a way that their speed is mainly determined by the transconductance of the bipolar transistors and the capacitance seen by the MOS transistors. The advantages to the existing SI technology in CMOS are higher speed, less error, and higher accuracy. The advantages to other technologies in BiCMOS as described in the background of the invention are smaller errors and higher accuracy. A unique feature of the present technology is the combination of the high input impedance of the MOS device and the high transconductance of the bipolar device, which are available only in BiCMOS processing and not in CMOS processing.

Fig. 1 is a circuit configuration proposed according to the technique of the present invention.

Fig. 2 is another circuit configuration proposed according to the technique of the present invention.

Fig. 3 shows a simulated response of the circuit of fig. 1.

Fig. 4 shows the variation of the simulation error with respect to the input current according to the present invention.

The proposed new technology employs a composite transistor composed of a MOS transistor and a bipolar transistor. As shown in fig. 1, the MOS transistor is in a common-drain configuration, and the bipolar transistor is in a common-emitter configuration. Current source I₀₁，I₀₂And I₁₃Are respectively a transistor M₀₄，Q₀₅And Q₁₆A bias current is provided. Capacitor C₀₇Is represented in a transistor M₀All capacitances on the gate of (1), C₁₈Is represented in a transistor M₀All of the capacitances on the source.

All switches are controlled by a non-overlapping clock. At clock phase ph₀While, the switch S is turned on₀₉And S_{1 10}Closing, and adding S_{2 11}And (4) opening. Input current I_in12Inflow transistor Q₀Thereby causing its base-emitter voltage to change. Due to the transistor M₀In the transistor M, the gate-source voltage of which is not changed₀The potential on the gate of (a) is also scaled. When reaching steady state, the transistor M₀The potential on the gate of (1) is generated, the transistor Q₀To a heat sink (or source) and input current to a transistor Q₀. Because of the transistor Q₀And Q₁Having the same base-emitter voltage, and outputting a current I if both transistors have the same emitter region_{01 14}Equal to the input current Iin.

At clock phase ph₁During the period, switch S₀And S₁Is opened and switch S₂And (5) closing. MOS transistor M₀Is isolated and the potential on the gate is maintained. Because of the transistor M₀Is constant, transistor Q₀The base-emitter voltage is constant. Thus, Q₀Is constant. Output current I_{00 13}Equal to the input current Iin, at clock phase ph₀During which this is to the transistor Q₀Is input. Because of the transistor Q₀And Q₁Having the same base-emitter voltage, and outputting a current I if the two transistors have the same emitter region₀₁Is equal to the output current I₀₀。

Thus, the output current I₀₀Is the storage of an input current Iin, an output current I₀₁The track and hold function performed on the input current Iin is realized. Since will be in contact with M₀And Q₀The same device as used as both the input and output means. At input current Iin and output current I₀₀There is no mismatch problem between them, just as in a secondary SI storage unit. By selecting different emitter regions, the output current I can be realized₀₁And the input current Iin.

When the switch S₀And S₁The speed of the circuit is determined by adjusting the time when closing. Neglecting the on-resistance of the switching transistor, the system is a two-pole system. Frequency W of main pole₀Is equal to g_mQo/C₀Wherein g is_mQoIs a bipolar transistor Q₀Transconductance of (C)₀Is M₀The total capacitance on the gate. Frequency Wn of non-dominant pole is equal to g_mmo/C₁Wherein g is_mmoIs a MOS transistor M₀Transconductance of (C)₁Is in the transistor M₀The total capacitance at the source.

For SI circuits in CMOS processing, the dominant pole frequency is determined by the transconductance of the MOS transistors and the total capacitance seen by the gates of the MOS transistors. Due to the high transconductance of the bipolar transistor, the proposed technique has a very high speed performance if the dominant non-frequencies are sufficiently high. Can be reduced in M by reducing in circuit design₀In particular by using a suitably large capacitance C₀To reduce clock feedthrough errors.

By using large capacitors C₀Speed can also be chosen for accuracy trade-off, since the clock feed-through error is with C₀In inverse proportion. Furthermore, due to the use of bipolar transistors, M is made₀Becomes smaller even at the gate electrodeThis is also true with large current inputs, which reduces signal dependent clock feedthrough errors. Another source of error in SI circuits in CMOS processing is due to drain-gate parasitic capacitance. When the drain potential changes, it will couple to the gate through drain-gate parasitic capacitance, which will cause excessive errors, especially for high frequency applications. In the proposed circuit shown in FIG. 1, the drain potential of the MOS transistor is tied to V_CCTherefore, there is no influence in the conversion of the gate voltage. Thus, the proposed technique has much smaller errors, both for signal-dependent and signal-independent errors.

Device M is implemented as in secondary SI memory cells in CMOS processing₀And Q₀Used as both input and output devices, the mismatch does not introduce any errors. However, when transistor Q is in use₁And mismatch plays an important role, the current mirrors need to implement different coefficients in most cases. Since the matching of the bipolar transistor is better than that of the MOS transistor, the proposed technique is also superior to the SI technique in MOS processing in terms of accuracy.

Finally, the simplicity is worth noting. Because the bipolar transistor has a large early voltage and is in the input and output stage Q₀The potential change at the collector of (a) is small and works well without the need for elaborate circuitry as shown in figure 1. In principle, SI circuits are also simple in CMOS processing. However, to handle different errors, such as clock feed-through errors, limited input/output conductance ratio errors, errors due to gate-drain parasitic capacitance, require more complex circuitry and/or clocks. The proposed technique does not require a linear capacitance as does the SI technique in MOS processing. Compared to earlier proposed techniques, this new technique does not require matching between the transconductor and the resistor, and the circuit design is much simplified.

Another circuit implementation is shown in fig. 2. It is similar to the nascent SI memory cell in CMOS processing. In fig. 2 different devices are used for input and output. Transistor M₀₁₅And Q₀₁₆As an input device, andtransistor M_{1 17}And Q_{1 18}Serving as an output device. Current source I_{0 19}，I_{0 20}，I_{1 21}And I_{1 22}Are respectively a transistor M₀，Q₀，M₁And Q₁A bias current is provided.

Capacitor C_{0 26}Representative transistor M₀All capacitances on the gate. Capacitor C_{1 27}Representative transistor M₀All of the capacitances on the source. Capacitor C_{2 28}Representative transistor M₁All capacitances on the gate. Capacitor C_{3 29}Representative transistor M₁All of the capacitances on the source.

Suppose a transistor M₀And M₁Having the same size, transistor Q₀And Q₁Having the same dimensions. When the switch S_{0 23}Clock phase ph at closure₀During period M₁Is equal to M₀Of the transistor, thus the transistor Q₀And Q₁Are equal. This makes Q₀And Q₁Are equal. Thus, the output current I_{0 24}Is equal to the input current Iin₂₅. At the time of switching on/off the switch S₀Open clock phase ph₁During period M₁The gate of (2) is isolated, maintaining the potential. This makes Q₁And thus the collector current, is constant. Output current I₀Remain unchanged. Thus, the circuit implements a track-and-hold function, just as a nascent SI memory cell in a CMOS process. As mentioned above, the circuit exhibits superior performance for its CMOS counterpart.

To verify its functionality, the circuit shown in fig. 1 was simulated by using the parameters of a 3.3v digital BiCMOS process. The supply voltage is 3.3 v. In fig. 3, the input current Iin and the output current I are shown₀₁. The input current is a 20-MHz100 mua sine wave and the clock frequency is 100 MHz. Obviously, a track and hold function is implemented.

The simulated current error is plotted in fig. 4 against the input current for a fully differential design based on the circuit scheme shown in fig. 1. The bias current in each branch is about 360 mua. It can be seen that the error is less than 0.55% and the variation is small when the sampling frequency is 100 MHz. This shows good linearity. When the clock frequency increases to 250MHz, the error increases due to the adjustment error. When the input current is less than 50% of the bias current, the error change is still small, and good linearity is represented.

Although the foregoing description contains many specifics and specificities, it should be understood that these are merely illustrative of the invention and are not to be construed as limitations thereof. It will be apparent to those skilled in the art that many modifications are possible without departing from the spirit and scope of the invention, which is defined in the following claims and their legal equivalents.

Claims (2)

1. An apparatus for processing sampled analog signals in a digital BiCMOS process using MOS transistors and bipolar transistors in the BiCMOS process, wherein means are provided for temporarily storing a voltage on the gate of the MOS transistor, means are provided for increasing the speed using the transconductance of the bipolar transistor, characterized in that: connecting a MOS transistor (4) of a common drain structure and a bipolar transistor (5) of a common emitter structure for use as input and output means at different clock phases controlled by non-overlapping clocks; and by connecting an additional bipolar transistor (6) the track and hold function with a possible scaling factor determined by the emitter regions of the two constituent bipolar transistors (5, 6) is realized, wherein the bases of the two bipolar transistors (5, 6) are interconnected.

2. The apparatus of claim 1, wherein: connecting a MOS transistor (15) of a common drain structure and a bipolar transistor (16) of a common emitter structure as an input device; connecting a MOS transistor (17) of another common-drain structure and a bipolar transistor (18) of another common-emitter structure as output means; the input and output devices are connected together only at one clock phase controlled by the non-overlapping clocks.