HK1020297A - Conductors for integrated circuits - Google Patents

Description

Conductor of integrated circuit

The present invention relates to electrical conductors in Integrated Circuits (ICs) with low substrate losses and methods of making such conductors, and more particularly to methods of making spiral inductors and integrated circuit inductors.

Today, used in high speed electronic applications in the frequency range of 1-2GHz are enhanced silicon bipolar, CMOS and BiCMOS type circuits that replace devices that could previously only be made from materials in groups iii-v of the periodic table.

When fabricating modules such as resonators and filters, high frequency circuits often require inductive elements. One problem common to all integrated circuits is how to implement integrated circuit inductors with high quality factor Q and high operating frequency, which is limited by the resonance frequency.

The quality factor, i.e. the Q-value, is the ratio of the stored energy to the dissipated energy, and can be calculated for the inductance by the formula Q =2 × pi × f × L/R, where f is the operating frequency, L is the inductance value, and R is the resistive loss of the metal, without taking into account any parasitic losses introduced by the substrate.

The Q value of the inductor decreases due to the influence of the conductive properties of the substrate. By selectively removing the silicon under the inductor, higher Q values and higher resonant frequencies can be achieved. The Q value can be increased by a factor of two using this removal process. The removal process is performed according to a Silicon etch process, which gives an air gap several hundred microns wide, see J.Y.C. Chang, A.A.Abidi, M.Gaitan, "Large Suspended Inductor on Silicon and Their Use in a 2 μm CMOS RF Amplifier" IEEE Transactions on Electron devices Vol.40, No.5, p.246, May 1993, but such a removal process is not feasible in mass production or compatible with Silicon IC processes.

Recent advances in the process of fabricating integrated circuits on silicon wafers have allowed the fabrication of inductor structures with higher inductance and lower loss per integrated circuit area because of the reduced size of the circuit and the use of multiple metal layers, utilizing thick oxide layers to better isolate the inductor from the substrate. Losses are still large due to the resistance of the metal and the losses of the IC substrate being fabricated. It is difficult to obtain an inductance element having a Q value higher than 5 to 10 in a frequency range of 1 to 2GHz using the existing method of treating a silicon wafer.

The inductive element is usually designed as a square spiral metal strip, see for example n.m. nguyen, r.g. meyer, "Si IC-Compatible Inductor and LC Passive Filter", ieee journal of Solid-State Circuits vol.25, No.4, p.1028, August 1990. Furthermore, ICs typically contain multiple metal layers, with up to five metal layers now being common in complex Very Large Scale Integration (VLSI) circuits. The spiral structure requires at least two metal layers, one for the spiral and one for the closed structure, i.e. forming a conductor path from the center of the spiral to the output on the edge of the inductor. The resistance of the topmost metal layer is typically low due to the large thickness of this layer, and this metal layer should therefore be used.

With a circular spiral, the resistance value can be reduced by 10% for the same inductance value, increasing the Q value of an inductor formed with the same magnitude. This circuit structure is not suitable for general software used in Computer Aided Design (CAD), but an octagonal structure can be used instead of a circular structure without increasing the resistance value of the Inductor, see s.chaki, s.aono, n.andoh, y.sasaki, n.tanio, "Loss Reduction of a helical Inductor", Technical Report of IEICE, p.61 ED93-166, MW93-123,1CD93-181 (1994-01).

A better way to reduce the resistance is to make the inductor with parallel spiral paths in adjacent layers, for example parallel to the topmost metal layer. In this way the Q-value of the inductor can be increased by a factor of 1.5-2 at the expense of a reduced resonance frequency, since the thickness of the isolation layer is reduced. By increasing the number of turns of the spiral, the inductance value can be made large. However, the capacitance of the inductor spiral to the substrate also increases, resulting in a decrease in the resonant frequency, limiting the usable operating frequency range of the inductor.

Thus, U.S. patent 5,446,311 describes a structure having an inductor fabricated in multiple metal layers to reduce the resistance of the inductor.

Further, japanese patent application JP a 07-106514 discloses a structure similar to that described in us patent 5,446,311, in which the loss due to electrostatic capacitance is reduced while increasing the Q value by making an inductor having two spiral metal paths formed in different metal layers, the inductors being connected by a third layer.

Modern IC processes use deep trenches to isolate devices. The advantage of such trenches is reduced parasitic capacitance and reduced device pitch. By dry etching and then filling oxide and undoped polysilicon or insulating material, a trench with a depth of 5-20 μm and a width of 1-2 μm can be obtained. After the filling process, the surface of the substrate is covered with a layer of filling material, so that the surface is substantially flat, so that the metal layer can be covered on the groove without limitation.

Us patents 5,336,921 and 5,372,967 also describe a method of making an inductor in a vertical slot. The purpose of the inductor is to solve some of the problems encountered with conventional horizontal inductors in integrated circuits by providing a method of making a vertical inductor in the form of an inductor coil in a slot.

Furthermore, us patent 5,095,357 discloses an inductive structure with low parasitic capacitance integrated directly in a semiconductor integrated circuit.

It is an object of the present invention to provide a method which enables a conductor with low losses to be obtained in a simple manner.

Another object of the invention is to obtain an integrated circuit structure that makes it possible to obtain an inductor with a high Q-value.

These and other objects are achieved by a trench located below the spiral inductor structure and filled with an isolation material, wherein the trench increases the effective distance of the metal to the semiconducting substrate. Thus, substrate loss and capacitance to the substrate of the integrated device are reduced. The Q value and resonant frequency of the inductor are increased accordingly.

In the case of only two metal layers, filling the trench is sufficient to obtain acceptable Q values and resonant frequencies.

In another case with multiple metal layers, typically four to five, the spirals should be placed in the topmost metal layer, which further reduces the parasitic capacitance to the substrate that has been reduced by the filled slots in the substrate and gives a higher self-resonant frequency. The topmost layer typically has the least sheet resistance, which also increases the Q value.

The reduced substrate capacitance can also be used for parallel connection of upper metal layers, for example for producing a spiral third and fourth metal layer, counted from the substrate, for producing a cross-over second metal layer, counted from the substrate, whereby the Q value can be increased again by a factor of 1.5 to 2.

Such a slot may be used under any metal line or metal pad in order to reduce parasitic capacitance and substrate losses.

In addition, if a new Si-IC process is used, this structure can be achieved without any process changes or additional process steps.

Thus, in a method of manufacturing an integrated circuit inductor or an integrated circuit comprising an inductor, the inductor is manufactured on or in a semi-conducting or semi-insulating substrate, in particular by depositing or applying various layers on a silicon substrate. Inductors generally comprise an electrical conductor path structure extending substantially in one or more planes, e.g. substantially parallel planes. Before the conductor paths are made, in particular before the inductor metal paths are applied or deposited on the substrate, trenches are etched in the substrate which extend from appropriate locations on the surface of the substrate. The location of the slots should ensure that the inductor path is above or close to the slots, that the slots will intercept an imaginary current path inside the substrate material, and that no slots are present in the substrate when inductors are used and current flows therethrough, and that the slot structure will therefore weaken or obstruct the current inside the substrate. The trenches are filled with an electrically insulating material, in particular a dielectric material or a semiconducting material, in order to obtain a substantially planar surface in a subsequent process step of manufacturing the conductor paths.

The position of the slots is then preferably configured such that the slots occupy the largest possible area under the inductance, i.e. the slots can be closely distributed. Also, the grooves are preferably arranged in a substantially parallel groove structure or a network structure.

Thus, in most cases, an integrated circuit having an inductor integrated therein comprises a thin plate of a material having a lower or weaker electrical conductivity than the substrate, such "plate" being the filled trench described above. The arrangement of the plates in certain areas of the conductor paths in the substrate, for example below the inductor path, but structures with plates between the planes of the conductor paths and above the inductor path are feasible in complex multilayer structures. In any case, the plates may be arranged substantially perpendicular to the plane of the conductor paths or have any other suitable geometry so as to provide undesired current paths from one location in the conductor to another, sufficiently long to provide these current paths with a large resistance when the circuit is in use and when desired currents are flowing in the conductor paths, which significantly reduces these currents.

Thereby, the plates may be arranged substantially parallel to each other, at least for a part of the plates out of all plates. Thus, the plates may be arranged in a mesh formed by two parallel plate subsets, when seen in the direction of the conductor paths. The plate has a suitable thickness so as to effectively cut off the current path inside the substrate, limiting the current in the substrate to have only a long path inside the substrate. For example, for a typical plate material, the thickness of the plate may be substantially equal to the thickness of the conductor paths. The width or depth of the plate, as seen from the conductor path, should be sufficient to limit the current path inside the substrate. The plates are then also preferably closely arranged so as to have a dense or compact spacing such that the spacing between adjacent plates is small, which also limits the current path, thereby limiting the current flow from closely located one location to another on the conductor within the substrate material. For example, the spacing may be 2 or several times, e.g. 5 times, the thickness of the plate. This can also be done in such a way that the plates or slots are arranged to occupy the largest possible area, as seen from the inductance, however the cross-sectional area of each plate is small, as seen in this view.

Integrated circuits such as those described above typically comprise metallic conductors fabricated on or in a semi-conductive or semi-insulating substrate, particularly in a silicon substrate, the conductors being, for example, part of inductive paths. Also, plates or slots may be provided in one or several areas adjacent to the above-mentioned conductors in order to reduce the conductor to substrate losses. For example, the plates described above may be arranged substantially perpendicular to the plane of the conductors or the plane of the current paths therein. The plate may be a filled slot arranged across the current path in the metal conductor and preferably extending in a direction substantially perpendicular to the current path and/or the longitudinal direction of the conductor.

The invention will now be described in detail with reference to the accompanying drawings, in which:

figure 1 is a highly simplified rectangular spiral structure as seen from the top of an integrated circuit inductor fabricated using prior art techniques,

figures 2a and 2b are cross-sectional views of the inductor of figure 1,

figure 3 is a cross-sectional view of an integrated circuit inductor,

figure 4 is a pattern of grooves for a substrate,

fig. 5 is a pattern of slots under a metal conductor line.

Fig. 1 shows a prior art rectangular spiral structure forming an inductor. In this case, the inductor is made in the fourth layer from the bottom, i.e. the topmost metal layer 101, by a number of rectangular turns of the spiral conductive path, typically between 5 and 10. The lower metal layer 103, in this case the third layer, closes the spiral structure by means of a cross-under.

The inductor structure of fig. 1 is also shown in the cross-sectional views of fig. 2a and 2b, the cross-sections being taken along the lines a-a and b-b, respectively, in fig. 1. Thus, fig. 2a shows a fourth metal layer metal 201 forming a rectangular loop. Below the metal spiral 201 there is an oxide layer 203 applied on a silicon substrate 205. The thickness of the metal layer is typically between 1-2 μm, the thickness of the oxide layer is typically 6 μm, the width of the conductor vias is about 5 μm, and the distance between adjacent vias has the same magnitude as the width of the vias.

In the cross-sectional view 2b, taken along the line b-b in fig. 1, the third metal layer 207 is also shown. The third metal layer 207 constitutes a conductive feedthrough for the closed inductor. The fourth metal layer 201 and the third metal layer are connected together by a conductive connection terminal 209. These connection terminals can be made in separate steps by etching and metallization or by first making suitable holes and then filling the holes with the fourth layer of material.

Fig. 3 shows a cross-sectional view of an inductor 305 with enhanced isolation performance, with the inductor path being made in the fourth metal layer on the topmost layer, i.e., the silicon substrate 301. However, before fabricating structures on the silicon substrate 301, an etching operation for fabricating trenches needs to be performed on the silicon substrate 301, and then the trenches are filled with an insulating material, i.e., a material having a lower conductivity than the substrate. The padding trench 303 serves to increase the effective distance of the metal layer of the inductor to the semiconductive substrate. Thus, substrate loss and substrate capacitance are reduced. Accordingly, the Q value and the self-resonant frequency of the inductor are increased.

The slot may be made substantially in accordance with conventional methods of achieving device isolation in modern IC processes. Thus, deep and narrow trenches can be fabricated using dry etching and filling the etched voids with an insulating material such as silicon dioxide, undoped polysilicon or an insulating material. The substrate surface produced in the refill process is still substantially planar. The width of the grooves is about 1-2 μm and the depth is about 5-20 μm. The width of the substrate material between adjacent grooves should be as small as possible, for example 2-4 μm. The slots are arranged in a suitable pattern so as to span the overlying conductor paths.

Figure 4 shows a partial view from above of a substrate 401 where a preferred trench pattern 403 has been etched. A slot pattern is then used under the inductor in order to reduce substrate losses. The pattern comprises a first set of several identical straight grooves parallel to each other and equally spaced, and a second set of several identical straight grooves parallel to each other and equally spaced, the grooves of the second set being perpendicular to the grooves of the first set. The slot should always be long enough and enable it to pass over the outermost inductor winding into the free material surrounding the inductor. However, the pattern of grooves used may have any net-like shape, and it is generally desirable to be able to remove as much of the substrate as possible.

Finally, fig. 5 shows how the method described herein can be applied to another application. In this case, a trench 501 is etched under the metal line 503 in order to reduce parasitic capacitance and substrate loss. The slots may have the same dimensions as described above, and they are arranged to cross the conductive path from below at substantially right angles. They may be located symmetrically under the conductor path and extend each side of the path as desired or as far as possible, e.g. 4-10 μm. This slot structure or the preferred mesh structure of fig. 3 may also be used to reduce pad loss.

Claims (14)

1. An integrated circuit comprising a metallic conductor formed on or in a semiconducting or semi-insulating substrate, in particular a silicon substrate, characterized in that a sheet of material is a conductor which is less or less electrically conductive than the substrate, which sheet is arranged in a conductor region in the substrate, which sheet is in particular a slot in the substrate which is located below the conductor and which is filled with an electrically insulating material, in particular an insulating or semiconducting material, which sheet is arranged substantially perpendicular to the plane of the conductor or a current path plane therein, in particular is arranged to span the current path in the conductor and preferably extends in a direction substantially perpendicular to the current path and/or the longitudinal direction of the conductor.

2. A circuit according to claim 1, characterized in that the plates are arranged substantially parallel to each other.

3. A circuit according to one of claims 1-2, characterized in that the boards are compactly arranged such that the gap between adjacent boards is small, preferably equal to two or several times the thickness of the boards, in particular the slots are arranged to occupy the largest possible area under the conductors.

4. A circuit according to one of claims 1-3, characterized in that the plates are arranged in a mesh structure.

5. A method of fabricating a low substrate loss conductor in an integrated circuit, comprising:

etching a trench in the substrate before applying the metal conductor on the substrate,

-the trench is then filled with an electrically isolating material, in particular an insulating or semiconducting material or a material which is less conductive than the substrate, characterized in that during etching of the trench, the longitudinal direction of the trench is arranged to span the current path in the metal conductor, in particular to extend in a direction substantially perpendicular to the longitudinal direction of the path and/or conductor.

6. An inductor to be manufactured on or in an integrated circuit on a semiconducting or semi-insulating substrate, in particular a silicon substrate, comprising a conductor path structure extending in one or more mutually parallel planes, characterized in that a sheet of material is a conductor which is less or weaker electrically than the substrate, which sheet is arranged in the substrate in the region of the conductor path, in particular the sheet is a trench in the substrate which is situated below the inductor path and which is filled with an electrically isolating material, in particular an insulating or semiconducting material.

7. An inductor according to claim 6, characterized in that the plates are arranged substantially perpendicular to the plane of the one or more conductor paths.

8. A circuit according to one of claims 6 or 7, characterized in that the plates are arranged substantially parallel to each other.

9. A circuit according to any of claims 6-8, characterized in that the width of the plate is substantially equal to the width of the conductor path.

10. A circuit according to any of claims 6-9, characterized in that the boards are compactly arranged so that the gap between adjacent slots is small, preferably equal to two or several times the width of a slot.

11. A circuit according to any of claims 6-10, characterized in that the plates are arranged in a mesh structure.

12. Method of manufacturing an inductor for an integrated circuit on or in a semiconducting or semi-insulating substrate, in particular a silicon substrate, the inductor having an increased Q-value and comprising an electrical conductor path structure extending in one or more substantially parallel planes,

etching grooves in the substrate at these locations before making the conductor paths, in particular before applying the inductive paths on the substrate,

-then filling the trenches with an electrically isolating material, in particular an insulating or semiconducting material or a material which is less conductive than the substrate,

13. a method according to claim 12, characterized in that the slots are arranged to occupy the largest possible area below the inductance.

14. A circuit according to one of claims 12 or 13, characterized in that the slots are arranged in a substantially parallel slot structure or a network structure.