HK1019819B - Method for forming semiconductor device having a sub-chip-scale package structure - Google Patents

Description

Method for manufacturing semiconductor device with sub-chip scale packaging structure

Technical Field

The present invention relates to a packaged semiconductor device and a method of packaging a semiconductor device, and more particularly, to a chip scale package.

Background

Chip Scale Packaging (CSP) is a modern semiconductor package of current interest. Chip scale packaging is a relatively new packaging technique in which a semiconductor die is bonded to a substrate, such as plastic or ceramic, with the dimensions of the substrate being substantially the same as or slightly larger than the dimensions of the semiconductor die. Attention is now focused on chip scale packaging primarily to reduce the board area of such packages, which allows the final assembler of an electronic device to improve the functionality of the device by assembling a maximum number of semiconductor devices within a given space.

Japanese patent laid-open No. 9-213838A discloses a method of forming a package structure in which a substrate is smaller than a die. The method is performed by singulating or cutting the die and then packaging the die.

According to the state of the art, chip scale packaging is relatively expensive and has many reliability issues that are mainly caused by the relative complexity of such packaging. In addition, the reliability of chip scale packaging and any packaged semiconductor device is directly proportional to the size of the die. As semiconductor manufacturers implement more and more functions on a die, die size increases while lacking technology that can reduce the feature size of the die. Reliability of routing between a semiconductor die and a substrate (i.e., level 1 package interconnect) becomes more questionable as die sizes increase. Furthermore, as the size of packaged semiconductor devices increases (and thus board footprint increases), the reliability of the connections between the packaged semiconductor devices and the printed circuit board (i.e., level 2 package interconnections) becomes of greater concern. Such reliability problems are essentially due to differences in thermal expansion coefficients between the semiconductor die material, the substrate, and the printed circuit board, which cause stress on the wiring during ambient temperature and power cycling.

In addition to the problems of reducing the package size and keeping reliability constant, there has been an increased interest in packaging semiconductor dies in wafer form at the wafer level, i.e., before being diced into individual dies (singulated). Wafer level encapsulation is believed to improve reliability and reduce cost by reducing the number of individual components that must be handled by automated mechanisms. However, the use of existing packaging techniques to create a low cost method of reliably removing the thermal expansion mismatch stress between the semiconductor die and the package substrate while ensuring BGA (ball grid array) reliability has not been developed to enable wafer level packaging.

Disclosure of Invention

Therefore, there is a demand for low cost, high reliability, and allowing wafer level packaging in an effort to improve chip scale packaging using standard assembly equipment.

According to the present invention, there is provided a method of forming a semiconductor device, wherein the semiconductor device comprises a semiconductor die having a surface and a peripheral dimension X and a peripheral dimension Y, the peripheral dimension X and the peripheral dimension Y of the semiconductor die being perpendicular to each other, and the semiconductor device comprises a substrate having a peripheral dimension X 'and a peripheral dimension Y' which are perpendicular to each other, the peripheral dimension X 'of the substrate being smaller than the peripheral dimension X of the respective semiconductor die, the peripheral dimension Y' of the substrate being smaller than the peripheral dimension Y of the respective semiconductor die, wherein the method is characterized by the steps of: providing a wafer having a plurality of semiconductor dies; covering the plurality of substrates onto the plurality of semiconductor dies such that each substrate of the plurality of substrates is electrically connected to the plurality of electrical contacts of a respective semiconductor die of the plurality of semiconductor dies; and dicing the plurality of semiconductor dies into individual dies after covering the plurality of substrates.

Drawings

A better understanding of the present invention can be obtained from the following detailed description when read in conjunction with the following drawings.

Fig. 1 and 2 illustrate embodiments of the invention in which a die has been attached to a substrate and has been underfilled with an underfill encapsulation layer.

Fig. 3 illustrates, in plan view, one embodiment of the invention in which multiple dies are packaged simultaneously on a wafer-level scale.

Fig. 4, 5 and 6 illustrate additional embodiments of the present invention that depict relative differences in semiconductor die/substrate dimensions.

It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Also, where considered appropriate, have been repeated among the figures to indicate corresponding or analogous elements.

Detailed Description

As shown in fig. 1, a semiconductor die 10 is provided that includes an active portion 11 and an interlayer dielectric (ILD) layer 12 on top of the active portion 11, the ILD layer 12 having been patterned to provide a circuit contact pad 14 shape and being disposed proximate a die periphery 30. Note that the active portion 11 comprises a silicon substrate on which active devices defining an active surface 11a are formed, the active devices 11a being wired with a higher level of metal (not shown), as is well known to those skilled in the art. As is well known to those skilled in the art, higher level metal layers are desirable such as M1 (Metal 1) through M6 (Metal 6). The details of the active portion 11 will be known to one of ordinary skill in the art and are not particularly important to a complete understanding of the present invention. The redistribution contact wires 16 are connected to the circuit contact pads 14 to establish electrical connection inward toward the center of the semiconductor die. As shown, the redistribution contact line 16 terminates on a lower protruding electrode metallization (UBM) pad 15. Thereafter, a passivation layer 18 is deposited and patterned to leave a window over the UBM pad 15, and solder bump electrodes 20 are formed over the UBM pad 15, respectively.

With the above semiconductor die 10, the solder bump electrodes 20 are electrically connected to the active surface of the semiconductor die 10. As is well known to those skilled in the art, the semiconductor die 10 shown in fig. 1 is considered to be a 'protruding electrode' die. The projecting electrode die is flipped with the active surface facing down (as shown) for subsequent bonding to a substrate. The solder bump electrodes may be formed using known controlled collapse circuit connection (C4) techniques or alternatively by bump electrode forming techniques (i.e., stencil printing or application of solder spray). In addition, a scribe line 102 is drawn along the die periphery 30, as will be described in more detail below with reference to fig. 3. ILD layer 12 may be formed from any suitable dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, polyimide, and the like. The passivation film 18 is formed to protect the active surface, and may be constructed using a mixture including a phosphosilicate glass, silicon nitride, a polyimide layer, and the like. Also, for purposes of terminology used in reference to the description of fig. 1, it is desirable that the solder bump electrodes 20 combined with the UBM pads 15 be considered together as an electrical contact formed on the surface of the semiconductor die. It is clear that such an electrical contact can be implemented in another form. For example, the solder bump electrodes 20 may be replaced with gold wire stud solder balls and electroless nickel/gold plated solder balls, or conductive polymer solder balls, for example. The electrical contact may also be implemented as a non-projecting electrode metal pad that is multilayered with a polymer comprising a conductive component, such as nickel powder or gold-plated polymer beads, dispersed in a thermosetting or thermoplastic film or paste. As is well known to those skilled in the art, the process of forcing an electrical connection between a semiconductor die and a substrate such that a thin layer of conductive composition remains between a non-protruding electrode type metal contact pad and a paired contact line on the substrate, such as a direct die attach (DCA) bond pad. Polymeric materials of this type are generally desirable for use as an anisotropically conductive adhesive. Such adhesives may also be used with gold-wire tack balls, electroless nickel/gold plated balls, and similar configurations as described above.

With respect to the substrate 50 of fig. 1 and 2, a construction is shown having an insulating layer 51 desirably formed over an organic polymer. However, the insulating layer 51 may be formed of an insulating ceramic material and a metal layer having an insulating film formed on the facing surfaces and through holes extending over the entire surface, as is well known to those skilled in the art. According to one embodiment of the present invention, the organic polymer forming the insulating layer 51 may be composed of a polyimide flexible circuit or a glass fiber reinforced with an epoxy laminate. Organic reinforcement such as aramid fibers may also be used in place of the glass fiber component. As shown in fig. 1, a plurality of direct die attach (DCA) bond pads 52 are formed on the 1 st surface (i.e., the top surface) of the insulating layer 51. Which are respectively aligned with the solder bump electrodes 20 of the semiconductor die 10. The solder mask 53 is used to prevent an undesirable flow of solder material consisting of solder bump electrodes during the reflow process to form a connection between the substrate 50 and the semiconductor die 10. As is well known, a plurality of electrical connections connecting the DCA bond pads to Ball Grid Array (BGA) bond pads 56 in the form of vias 54 or plated through holes are formed on the 2 nd surface, i.e., bottom surface, of the substrate. A 2 nd solder bump electrode 57 is formed on the BGA bond pad 56, on which a Ball Grid Array (BGA) ball 58 is formed of solder material. Reference numeral 60 shows one peripheral surface of the substrate. As used hereinafter, the term 'substrate' is considered to be a mechanical component that carries the semiconductor die and that also has (i.e., supports) electrical connection elements (here elements 52, 54, 56 and 58) that provide electrical connection from the semiconductor die to the next level of wiring, such as through a printed circuit board.

Turning next to fig. 2, a completed packaged semiconductor device is shown in fig. 2, wherein a substrate 50 is attached to the semiconductor die 10. A substrate 50 is placed on the semiconductor die 10. The underfill encapsulant layer includes a fillet 72 that circumscribes the active surface of the semiconductor die exposed proximate the substrate and the substrate peripheral surface 60. The fillet is formed along the peripheral surface 60 of the substrate due to the wetting action of the material of the underfill encapsulant layer 70. The electrical connection is made simultaneously by the formation of the underfill encapsulant layer 70 or may be made, such as by reflow, prior to the formation of the underfill encapsulant layer 70. The material of the underfill encapsulant layer is typically composed of a spherical fused silica particle-filled epoxy resin that is cured using conventional techniques (i.e., heating techniques). The underfill encapsulant layer 70 may be deposited by any known technique, such as by depositing the material around the last edge of the die and by capillary action of the material driven into the interface between the semiconductor die 10 and the plate 50.

Also, all of the plurality of electrical contacts (i.e., solder bump electrodes 20, UBM and pads 15) are located within the outer perimeter of the substrate 50. This particular feature of the present invention is advantageous in making all electrical connections from the external environment to the packaged semiconductor device. In addition, the present invention allows array bonding within the CSP to occur between the semiconductor die and the substrate rather than bonding at the outer surface. Furthermore, the array bonding of the present invention allows for relatively large dimensional differences between the semiconductor die and the substrate, across the range of known CSPs to which the external surface bonding technique is applied. In such known CSPs, the reduction in size of the substrate will result in very long bonding wires between the die and the substrate. Such long bond wires lack the thermal stability of the relatively short bond wires used in present external surface bonded CSPs and may more easily create a hazard.

Although in the embodiment shown in fig. 1 and 2 BGA balls 58 are provided on substrate 50 prior to attachment to semiconductor die 10, it should be understood that BGA balls 58 may be attached to substrate 50 after attachment to semiconductor die 10 in the desired wafer form or after being diced into dies. According to the embodiment shown in fig. 1 and 2, electrical connection is made between the substrate 50 and the semiconductor die 10 using the solder bump electrodes 20, followed by underfill encapsulation with an underfill encapsulant material. The underfill encapsulant may be formed at the same time that the electrical connection is made. In this embodiment, the material forming the underfill encapsulant layer 70 is first deposited onto the semiconductor die and then the substrate is placed on top of it. In subsequent processes, electrical connection between the protruding electrode 20 and the DCA bond pad 52 is completed (e.g., using reflow), and an underfill encapsulation layer 70 is added (e.g., using a curing technique). The reflow and the hardening may be performed simultaneously.

Turning now to fig. 3, fig. 3 illustrates a plan view of packaging a plurality of semiconductor die in wafer form. As shown, a plurality of semiconductor dies (16 in this embodiment) are packaged simultaneously. The dimensions X 'and Y' of the substrate and the dimensions X and Y of the semiconductor die are perpendicular to each other. Here, both of the following shown are satisfied: (i) the X 'dimension of the substrate is smaller than the dimension of the semiconductor die X, (ii) the Y' dimension of the substrate is smaller than the dimension of the semiconductor die Y. It should be noted, however, that one or the other of the X 'and Y' dimensions may be made smaller than the X and Y dimensions of the corresponding semiconductor die in accordance with the present invention. In this embodiment, during die dicing along dicing lines 102, the edges of the substrate that protrude beyond the edges of die 10 will be simultaneously cut off in alignment with the edges of the substrate. However, it is desirable to have both substrate dimensions X 'and Y' smaller than the dimensions X and Y of the semiconductor die.

As shown in fig. 3, the semiconductor wafer 100 has scribe lines 102 separating individual dies from each other. As shown in dashed lines in fig. 1 and 2, the material along the cut line has been substantially removed.

Fig. 4, 5 and 6 show another embodiment of the present invention, somewhat similar to the embodiment described above with respect to fig. 1-3, with a semiconductor die 10 that is 10mm square, 0.4mm thick, and has 100 electrical contacts. The thickness of the substrate was 0.5 mm. Although fig. 4-6 show one essentially identical semiconductor die 10, 3 different redistribution diagrams are shown.

First, fig. 4 shows a bold redistribution diagram in which 81 BGA balls 58 are arranged on a 5mm square substrate with a step pitch of 0.5 mm. Fig. 5 shows 120 BGA balls 58 arranged on a 7.5mm square substrate with a 0.65mm pitch. Finally, 144 BGA balls 58 are shown in fig. 6, arranged on a 9.5mm square substrate, with a 0.80mm pitch. According to fig. 4, a relatively bold redistribution diagram is shown, which is advantageous from the point of view of reducing the footprint of the substrate 50. The reduction in the board occupation area of the substrate 50 will improve the reliability of the wiring between the substrate 50 and the printed circuit board on which the substrate 50 is to be mounted. As shown, the portion of semiconductor die 10 that extends outside of the substrate around the periphery of the substrate does not contribute significantly to the stresses on the wiring (not shown) to the circuit board as determined by the BGA balls, which stresses are caused by coefficient of thermal expansion mismatch. This portion of the die that extends beyond the edge of the plate 50 is only thermo-mechanically coupled to the substrate 50 by the fillet 72 of the underfill encapsulant 70 shown in fig. 3. Despite this advantage, given that the circuit contact pads are formed near the outer perimeter of the semiconductor die 10, as in the embodiment shown in connection with fig. 1-2, a relatively long redistribution network is required, which may induce undesirable parasitic losses and may also have a negative impact on the heat transfer from the semiconductor die 10 to the substrate 50. It should also be noted that the number of legs is reduced from 100 electrical contacts (between die and substrate) to 81 contacts. Such a reduction in the number of electrical contacts is achieved by applying common power and ground planes, or segments, in the substrate.

From the standpoint of the tension of the relative design with the aggressive re-profiling shown in fig. 1, higher frequency and/or higher power devices require less aggressive re-profiling as shown in fig. 5 and 6. As shown, fig. 5 and 6 have increased in the number of BGA balls that improve electrical performance and power consumption. It should be noted that all embodiments are compatible with state-of-the-art heat sinks, such as those that may be attached to the passivated surface of semiconductor die 10.

As discussed above, it is apparent that the present invention provides an improved sub-chip scale package that meets several requirements of the state of the art. With the present invention, not only the reliability of the wiring between the die and the substrate but also the reliability of the wiring between the substrate and the printed circuit board is improved by reducing the board-occupying area of the substrate. In this sense, unlike chip scale packages where the substrate and die are the same size, the present invention provides a form of under-fill seal fillet that is applied to the area of the die that extends beyond the edge of the substrate, instead of a substrate segment, in which area the under-fill seal fillet caps the die in a typical CSP. This has been shown to be effective in relaxing the stresses that arise due to the mismatch in thermal expansion coefficients between the substrate and the die. Further, unlike state-of-the-art chip scale packages, the present invention can be manufactured and implemented at relatively low cost due to its relatively simple, easy-to-make construction disclosed herein. Furthermore, the present invention also provides a method for reducing the price of a substrate to 40 to 80% due to the reduction in the size of the substrate. Also, the present invention does not require additional or more equipment expense to be incurred in the manufacture of semiconductors, as existing flip-chip die packaging equipment can be used to form packaged semiconductor devices employing the techniques of the present invention. The present invention also enables wafer level packaging whereby all semiconductor die can be packaged onto a wafer simultaneously.

In addition, the present invention also provides increased throughput with higher yield during packaging operations. In particular, unlike previous techniques, the substrate on which embodiments of the present invention are based is placed on semiconductor die in wafer form prior to being diced. Due to the accuracy with which semiconductor dies are formed on a wafer, highly accurate fiducials (fiducials) can be formed over the entire extent of the wafer top side, which have an exact relationship to the dies on the wafer per se. A vision system of suitable performance can detect a universal fiducial on the wafer so that each substrate can be placed on a vertical die using only that fiducial. In contrast, according to the prior art, a printed circuit board to be cut into a plurality of substrates is provided, and the cut dies are mounted on the printed circuit board. However, with the prior art, the printed circuit board is fabricated with a relatively low precision universal fiducial that does not provide as much alignment as the universal fiducial for the wafer according to the present invention. This will reduce product throughput because the vision system must be positioned on local fiducials on the die and substrate.

It should be noted that many variations are possible without departing from the spirit and scope of the invention as defined in the following claims. For example, although not shown in the figures, the substrates may be joined together in a single piece or in several multi-unit segments and then cover the entire wafer. Then, dicing is performed to separate the substrates from each other. It is desirable to use a single substrate because this would eliminate waste and reduce the price of the substrate placed on a wafer that has been previously subjected to probe testing.

Claims (3)

1. A method of forming a semiconductor device, wherein the semiconductor device includes a semiconductor die having a surface and a peripheral dimension X and a peripheral dimension Y, the peripheral dimension X and the peripheral dimension Y of the semiconductor die being perpendicular to each other, and the semiconductor device includes a substrate having a peripheral dimension X 'and a peripheral dimension Y' that are perpendicular to each other, the peripheral dimension X 'of the substrate being less than the peripheral dimension X of the respective semiconductor die, the peripheral dimension Y' of the substrate being less than the peripheral dimension Y of the respective semiconductor die, wherein the method is characterized by the steps of:

providing a wafer having the plurality of semiconductor dies;

forming a plurality of electrical contacts on a surface of each of the semiconductor dies;

covering the plurality of substrates onto the plurality of semiconductor dies such that each substrate of the plurality of substrates is electrically connected to the plurality of electrical contacts of a respective semiconductor die of the plurality of semiconductor dies; and

the plurality of semiconductor dies are diced into individual dies after the plurality of substrates are covered.

2. The method of claim 1, further comprising: each of the substrates has a periphery and a plurality of electrical contacts are located within the periphery of each of the semiconductor substrates.

3. The method of claim 1, further comprising: there is also the step of depositing an underfill encapsulant layer between each of the substrates and each of the semiconductor dies.