HK1018721A - Dc blocking apparatus and technique for sampled data filters - Google Patents

Description

DC blocking apparatus and techniques for sampled data filters

no marking

The present invention relates generally to integrated sampled data filters and in particular to dc blocking of integrated circuits used in sampled data filters.

One example of a sampled data integrator is a switched capacitor integrator. The lossless switched capacitor integrator shown in fig. 1 finds wide application in Integrated Circuit (IC) design, using switched capacitors to overcome process tolerances associated with other resistor and capacitor combinations. In operation, by approximating with a time constantFor the alternate charging path of the switched capacitor integrator 100, the capacitor C1 is charged at a cycle rate f_clockAnd (6) charging.

Since the time constant is a function of the capacitance ratio, all process variations are eliminated. An additional input to switched capacitor integrator 100 may be implemented using a coupling additional capacitor, such as capacitor C3 at node 102. The value of the capacitance C3 is selected to be equivalent to the value of the capacitance C1 and is at the same cycle rate f_clockThe same time constant is maintained for opening and closing. At multiple input ends，V_in1, ,V_in2A summing point is created in between.

Switched capacitor integrators are commonly used for integral ladder filter design, and FIG. 2 shows a block diagram of a simple integrated sampled data ladder filter 200, where each block represents a k_iA switched capacitor integrator representing its unity gain frequency, filter 200 represents a conventional switched capacitor low pass filter, and filter 200 may be used in a variety of applications, such as noise and acoustic signal processing in radio receivers.

Fig. 3 shows a typical simulated frequency response curve 300 for a two-pole switched capacitor low pass filter. The frequency response curve 300 is shown in terms of frequency in hertz (Hz) along the horizontal axis and gain in decibels (dB) along the vertical axis, with a transition frequency f_d302。

The stages (stages) of the radio generate dc offsets and many radio circuits, such as squelch and audio circuits, suffer performance degradation due to the presence of these offsets. It is not uncommon for a ladder filter to be coupled between two stages, where one stage produces an ac signal with a dc bias while the other stage is sensitive to this bias. Any DC offset V induced at the input of the ladder filter 200 before and after the filter 200_inV to be at output_outAnd (4) reproducing. In the past, these dc biases were isolated by using discrete capacitors external to the chip in front of or behind the filter 200. This is appropriate when the different stages of the radio circuit are located on separate Integrated Circuits (ICs), which is a problem when these circuits are present on-chip, because these require too large a dc blocking capacitance to achieve a low transition frequency or are difficult to integrate.

The ability to couple external elements off-chip creates a number of design problems as the direction of development tends to increase integration. Space and size constraints are defined and each pinout increases the cost of the integrated circuit. An on-chip dc blocking circuit for an integrated sampled data filter is therefore required.

FIG. 1 is a prior art switched capacitor integrator;

FIG. 2 is a prior art sampled data ladder filter;

FIG. 3 is a typical frequency response curve for a two-pole switched capacitor ladder filter;

FIG. 4 is an integrated sampled-data filter with DC blocking according to the present invention;

FIG. 5 is a frequency response line for a two-pole integrated switched capacitor ladder filter according to the present invention;

fig. 6 is a block diagram of a radio receiver using the filter of the present invention.

Referring to fig. 4, there is shown a block diagram of a sampled-data filter 400 that provides on-chip dc blocking in accordance with the present invention. The filter 400 is formed of a plurality of sampled data integrators 402,404,406,408,410 arranged in a ladder configuration and provided with a transition frequency f_dThe low-pass transfer function of (1). The plurality of sampled data integrators 402,404,406,408,410 are preferably formed by switched capacitor integrators, but other sampled data integrators, such as switched current integrators, may be used. But in the preferred embodiment of the invention is discussed in terms of a switched capacitor integrator.

Each switched capacitor integrator 402,404,406,408,410 is characterized by a unity gain frequency denoted as ki. In accordance with the present invention, filter 400 includes a Very Large Time Constant (VLTC) integrator 412 to substantially eliminate dc offset present at the output signal Vout of filter 400. The ratio between the clock frequency of the VLTC integrator and the unity gain frequency of the integrator is very large. The VLTC integrator 412 provides a zero at DC and a low frequency f₁A pole of (a), wherein f₁Below the high-end transition frequency f_d(f₁＜f_d). For example, frequencies below 300 Hertz (HZ) may be used at the low-end transition frequency, while frequencies above 3 Kilohertz (KHZ) may be used at the high-end transition frequency.

In FIG. 4, integrator 412 is shown to have its unity gain frequency k_LAnd (5) characterizing. According to the invention, the low-side transition frequency f₁By varying the unity gain frequency k_LAnd adjusted as required without changing the frequency response and high-end transition frequency f of other parts in the pass band_d. The unity gain frequency of the VLTC integrator 412 in the feedback path 414 is selected to be lower than the unity gain frequency of the sampled data integrators.

In accordance with the present invention, the VLTC integrator 412 is coupled to the negative feedback path 414 of the first switched-capacitor integrator 402. An ac signal with dc bias can be considered an input signal Vin to the non-inverting input of the first switched capacitor integrator 402 and an integrated output 418 is generated and fed back to the feedback input 420 through the large time constant integrator 412. The dc offset is subtracted at the summing junctions of the non-inverting 416 and inverting 420 inputs, respectively. Therefore, the direct current is fundamentally eliminated from the output signal Vout of the filter 400. The dc blocking technique of the present invention is also applicable to filters formed by a single sample data integrator, as shown by the configuration of the filter having multiple sample data integrators. The VLTC integrator is coupled to the negative feedback path of the sampled data integrator to block DC.

The VLTC integrator 412 may comprise any of the known art maximum time constant integrators, such as a T-cell integrator or k.nagaraj, which is published in the IEEE journal of circuits and systems (IEEE-T-CASI) 36, ninth, 1989, entitled "non-parasitic sensitive area efficient method for achieving a maximum time constant for a switched capacitor circuit", which is incorporated herein by reference. The use of a VLTC integrator in the feedback path of the first data sample integrator 402 provides the advantage of blocking dc offsets appearing at the filter output.

Fig. 5 shows a simulation of a frequency response curve 500 of an integrated two-pole switched capacitor filter with a VLTC integrator in accordance with the present invention. This simulation uses the same two-pole switched capacitor filter as the simulation used in fig. 3, but with the addition of a VLTC integrator in the feedback path. Frequency converterThe rate is expressed in Hertz (HZ) along the horizontal axis, while the gain is expressed in decibels (dB) along the vertical axis. According to the invention, the VLTC integrator provides a zero at DC processing and a low frequency (f)₁)502, a pole is provided, wherein f₁Lower than f_d504(f₁＜f_d). When compared to the graph of fig. 3, it is apparent that the passband and the high-side transition frequency f_dIs retained. Thus, on-chip coupling is accomplished without significantly altering the frequency response of the desired frequencies of interest. The switched capacitor filter with the inventive VLTC integrator allows an arbitrary flexible control of the low side corner frequency and blocks dc. All of these advantages are accomplished on-chip and preserve signal integrity.

Thus, by providing an integrated sampled data filter having at least one sampled data integrator characterized by a time constant controlling the high side transition frequency, and generating a predetermined time constant in the feedback path of the sampled data integrator, the "feedback" time constant being longer than the time constant associated with the sampled data integrator, a dc blocking technique is provided which controls the low side transition frequency of the filter. Changing the predetermined time constant of the VLTC integrator controls this low frequency and provides a zero at dc without disturbing the response of the high end passband of the filter. If it is desired to move the low-end corner frequency closer to the high-end corner frequency (within the passband), then predistortion of the unity gain frequency of the sampled-data integrator can be used to move the low-end corner point upward while maintaining the remaining passband.

The switched capacitor filter of the present invention can be combined with a variety of integrated circuit technologies such as bipolar complementary metal oxide semiconductor, gallium arsenide, and many others. The cost of a very large time constant integrator is minimal compared to both adding pins and using additional external components. The use of the dc blocking technique of the present invention advances the art by providing increased integration and on-chip coupling between the various stages of the circuit.

Referring now to fig. 6, a simplified block diagram of a radio receiver 600 is shown. A Radio Frequency (RF) signal is received by the antenna 602, amplified at the preamplifier stage 604, and mixed with a local oscillator signal 608 at the mixer 606 to produce an Intermediate Frequency (IF) signal 610. The intermediate frequency signal 610 is demodulated at demodulator 612 and filtered at filter 400 constructed in accordance with the invention to remove any dc offset from the demodulated signal. A filtered signal 614 is provided to audio and noise processing circuits 616,618 without any dc bias that would degrade noise suppression, and audio performance is provided at speaker 620. These dc offsets are removed inside the filter 400 without using any external components.

Thus, an integrated sampled data filter is provided that allows coupling of on-chip circuitry, eliminating at least one integrated circuit pad and one external coupling capacitance. The reduction in the number of discrete components required yields the benefits of reduced manufacturing costs and improved cycle time.

While the preferred embodiments of the invention have been illustrated and described, it will be clear that the invention is not so limited. Numerous and varied technically and technically equivalent adjustments, modifications, variations, omissions and equivalents will occur without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (10)

1. An integrated ladder filter comprising:

a first sampled-data integrator having a non-inverting input and first and second inverting inputs and an output, the non-inverting input receiving an ac signal having a dc offset; and a second sampled-data integrator having a non-inverting input coupled to the output of the first sampled-data integrator, the second sampled-data integrator having an output coupled to the first inverting input of the first sampled-data integrator, the second sampled-data integrator having an inverting input coupled to the output of the second sampled-data integrator and providing the output of the integrated filter, the first and second sampled-data integrators providing a low-pass frequency response having a predetermined high-side breakover frequency; and is

A third sampled-data integrator has an input coupled to the output of the first sampled-data integrator and has an output coupled to the second inverting input of the first sampled-data integrator, the third sampled-data integrator being characterized by a unity gain frequency selected such that the transfer function of the integrated filter provides a zero at dc and a pole at a frequency below the predetermined high-side corner frequency.

2. An integrated ladder filter as set forth in claim 1, wherein the first and second sampled-data integrators comprise switched-capacitor integrators.

3. An integrated ladder filter as recited in claim 1, wherein the low-end corner frequency of the integrated ladder filter is adjustable by changing the unity gain frequency of the third sampled-data integrator.

4. A method for providing dc isolation within an integrated sampled data filter, comprising the steps of:

providing a sampled data ladder filter having a first sampled data integrator and a second sampled data integrator coupled in a ladder configuration, the first and second sampled data integrators providing first and second time constants, respectively;

controlling the high-side transition frequency of the sampled-data filter by the first and second time constants;

providing a maximum time constant (VLTC) integrator;

generating a predetermined time constant, the predetermined time constant being longer than the first and second time constants; and is

A predetermined time constant is provided in the feedback path of the first sampled-data integrator to produce a low-side corner frequency and a zero at dc for the sampled-data filter.

5. The method of claim 4, further comprising the step of changing the predetermined time constant to adjust a low-end transition frequency of the sampled-data filter.

6. A sampled-data filter integrated circuit comprising:

first and second integrator circuits characterized by first and second unity gain frequencies, respectively, the first and second sampled-data integrators being coupled in a ladder configuration and providing a frequency response having a predetermined high-side breakover frequency; and is

A Very Large Time Constant (VLTC) integrator having a unity gain frequency lower than the first and second transition frequencies, the VLTC integrator coupled in a negative feedback path of the first sampled data integrator, the VLTC integrator having a unity gain frequency controlling a pole of a predetermined low-end transition frequency of the frequency response, the VLTC integrator providing a zero at a direct current of the frequency response.

7. A sampled-data filter integrated circuit as described in claim 6, wherein the unit-gain frequency, the predetermined low-end transition frequency of the frequency response, of the VLTC integrator is adjustable.

8. An integrated filter comprising:

the plurality of sampling data integrators are coupled in a trapezoidal configuration to provide a high-end transition frequency and receive an alternating current signal with direct current bias, and at least comprise a first sampling data integrator; and is

A Very Large Time Constant (VLTC) integrator is coupled in the feedback path of the first sampled-data integrator, said (VLTC) integrator controlling the low-end breakover frequency response of the integrated filter and providing a zero for the direct current.

9. An integrated filter as described in claim 8, wherein the low-end corner frequency response of the integrated filter is adjustable by varying the predetermined time constant of the VLTC integrator.

10. An integrated filter as described in claim 8 wherein the plurality of sampled-data integrators comprises switched-capacitor integrators.