HK1017115B - Cache enabling architecture - Google Patents

Description

Cache enabling architecture

Technical Field

The present invention relates to a cache enabling architecture (cache enabling architecture) in which information at the output and/or input of a memory read and/or write device may be cached. The cache enabling architecture may be implemented, for example, in a computer system to which the memory read and/or write devices are connected. Generally, the connection is made via a data bus.

Background

Caching information from a memory device is a well known technique. Specifically as an example, many solutions are known to cache Random Access Memory (RAM), hard drives, and other mass storage devices. The various storage devices are typically used in or in conjunction with computers. The requirement to cache a storage device is essentially to provide a faster memory in which information can be accessed more efficiently than in the storage device, and essentially to copy determined information from the storage device to the faster memory or vice versa. The determined information may for example be the information that is most likely to be needed or that is needed most often. The copying and identification of determined information among the information contained in the storage device (or faster memory) is done with the cache processor. The cache processor may be, for example, a software program running on a computer. Caching thus improves the overall performance of an information handling system, such as microprocessor processing information stored in RAM or computer processing information stored in a mass storage peripheral.

Computers are commonly used with peripheral devices such as magnetic and/or optical storage devices. These memory devices are connected directly or indirectly to the data bus. The microprocessor performs an exchange of information between devices connected to the data bus on the data bus. The performance expressed in terms of the number of accesses of information stored in each storage device varies depending on the characteristics of each storage device. The performance of, for example, magnetic hard disk drives is significantly better than that of optical disk devices. It is known to cache optical disk devices by using a disk drive as a faster memory.

In one implementation of caching, the cache processor caches by using a direct connection that exchanges information between the optical disc device and the hard disk drive. This direct connection is necessary because there is no other way to exchange information between the optical disk device and the magnetic hard disk device without involving a microprocessor, which in turn significantly reduces the speed of the computer. On the other hand, a direct connection is a piece of hardware that is not a standard computer device and thus may increase the production cost of a computer equipped with a memory peripheral.

Recent computer hardware includes a data bus on which two peripherals can exchange data without significantly disturbing other peripherals connected to the data bus. This means that the microprocessor, also called central processing unit, can perform other tasks than the exchange of information between two peripheral devices. For example, a microprocessor may process data stored in RAM. Such a data bus may be based on an IEEE 1394 bus, for example.

Disclosure of Invention

It is an object of the present invention to find a solution that makes it possible to cache an optical storage peripheral with another storage peripheral without having a direct connection of its own between the two peripherals. The present solution should make best use of existing computer hardware.

According to the present invention a solution to the above mentioned problems is found, namely a cache enabling means for caching information at the output and/or input of an optical memory read and/or write means, comprising at least one high capacity write and read means, a set of data buses and a cache processor, said high capacity write and read means being based on a magnetic hard disk drive; the data bus is connected with the high-capacity writing and reading device and a cache processor in parallel, and instructions from other devices except the optical storage device also reach the high-capacity writing and reading device through the data bus; the cache processor caches information by using the high capacity write and read device. The cache processor is directly connected to the mass write and read device. The output and/or input of the optical memory read and/or write device and the cache processor are connected by a data bus for directly exchanging information between said output and/or input and said cache processor.

In accordance with the present invention, another solution to the above-described problem is found in a magnetic hard disk drive for use in a computer system. The computer system comprises at least one central processing unit, an optical memory reading and/or writing device and a set of data buses to which the central processing unit and the optical memory reading and/or writing device are indirectly or directly connected. The magnetic hard disk drive further comprises a connection circuit for connecting the magnetic hard disk drive to the data bus in parallel with the cache processor, the cache processor receiving requests from the data bus to read and/or write information intended for the optical memory read and/or write device, the cache processor also exchanging information between the magnetic hard disk drive and the optical memory read and/or write device over the data bus to cache the optical memory read and/or write device.

Brief description of the drawings

Other objects and features of the present invention will become apparent from the following description of the embodiments with reference to fig. 1.

FIG. 1 is a schematic diagram of a cache architecture.

Detailed Description

The described embodiments are not limiting and those skilled in the art may consider other embodiments that are still within the scope of the invention.

Fig. 1 shows a data bus 1 which may be part of a computer (not shown). The data bus 1 may be, for example, an IEEE 1394-based bus. The IEEE 1394 bus is a high-speed serial bus that allows transfer of digital data. In addition, IEEE 1394 also allows direct communication with devices connected to the bus and data exchange with each other.

The optical memory reading and/or writing means 2 are connected to the data bus 1 via an output and/or input connector connection circuit 22. The optical memory reading and/or writing device 2 can be, for example, a CD-ROM, DVD-ROM/RAM or CD-RW (rewritable) drive, i.e. data is read/written optically or magneto-optically. Optical disc drives provide a relatively inexpensive way to access/store large amounts of information.

The mass writing and reading means 3 are connected to the data bus 1 via a connection 4. The high capacity write and read device 3 may be, for example, a magnetic hard disk drive. Magnetic hard disk drives offer an advantageous performance/price ratio and are therefore used in most computers.

The cache processor 5 is connected to the mass write and read device 3 via a connection 6 and to the data bus 1 via a connection 4.

The performance of the high capacity writing and reading apparatus 3 in terms of the number of accesses to information and the transfer rate is generally better than the performance of the optical disc memory reading and/or writing apparatus 2. The cache processor 5 exchanges information with the optical memory read and/or write device 2 directly via the data bus 1. The cache processor 5 may for example send a request for information to the optical memory reading and/or writing device 2, upon receipt of which the optical memory reading and/or writing device 2 sends the requested information to the cache processor 5. The cache processor 5 transfers the received requested information to the mass writing and reading device 3 which stores the information.

Thus, no special direct connection is required between the optical memory reading and/or writing device and the mass writing and reading device. The present cache-enabled architecture takes advantage of the possibility that two devices exchange information with each other over a data bus.

In general, a further device 7 is connected to the data bus 1. The further device 7 may for example be a microprocessor. The other device 7 issues a request for information to the mass writing and reading apparatus 3 or to the cache processor 5 on behalf of the optical memory reading and/or writing apparatus 2. The cache processor 5 handles these requests for information, gets the requested information from the mass writing and reading means 3 if it is already stored therein, and gets the requested information from the optical memory reading and/or writing means 2 otherwise, and finally sends the information to the further device 7.

The cache processor 5 may also analyze the request for information according to a cache policy over a period of time. Caching strategies are well known to those skilled in the art. As a result of the analysis, the cache processor 5 may determine which of the determined information is requested more often by the other device 7 than other information. The cache processor 5 may store this determined information in a mass writing and reading device as long as it is frequently requested. The cache processor 5 may also implement a cache policy called read-ahead, to wait in advance for a request for information by another device 7.

In another embodiment, the cache processor 5 may also be used to receive information sent by another device 7 on the data bus 1, intended to be stored in the optical memory reading and/or writing means 2. The cache processor 5 will first send the received information to the mass writing and reading device 3, which stores the information first and then copies it from the mass writing and reading device 3 to the optical memory reading and/or writing device 2. By utilizing the writing properties of the high capacity writing and reading device 3, the writing properties of the optical memory reading and/or writing device 2 are substantially improved.

The various devices connected to the data bus 1 exchange information using a communications protocol. In a preferred embodiment, the communication protocol between the optical memory reading and/or writing device 2 and the cache processor 5 may be an optimized version of the communication protocol between the further device 7 and the cache processor 5 to enhance simplicity and performance.

In general, the mass writing and reading apparatus 3 may include its own dedicated cache processor that caches itself. In a preferred embodiment, the functionality of cache processor 5 may include the functionality of a dedicated cache processor, thereby eliminating the need for a physically distinct dedicated cache processor and further reducing costs.

Claims (5)

1. Cache enabling device for caching information at an output and/or an input of an optical storage read and/or write device (2), comprising:

at least one high capacity write and read device (3) based on a magnetic hard disk drive,

a data bus (1) to which said mass writing and reading device (3) and a cache processor (5) are connected in parallel, instructions from other devices (7) than said optical memory reading and/or writing device (2) also reaching said mass writing and reading device (3) via said data bus (1),

a cache processor (5) for caching said information by using said mass writing and reading device (3), said cache processor (5) being directly connected to said mass writing and reading device (3),

wherein said output and/or input of said optical memory read and/or write device (2) and said cache processor (5) are connected via said data bus (1) for directly exchanging said information between said output and/or input and said cache processor (5).

2. Cache enabling device according to claim 1, characterized in that said cache processor (5) is an integral part of said mass writing and reading device (3).

3. Cache enabling device according to claim 1, characterized in that said data bus (1) is based on an IEEE 1394 bus.

4. Cache enabling device according to claim 2, characterized in that said data bus (1) is based on an IEEE 1394 bus.

5. A magnetic hard disk drive for use in a computer system, the computer system comprising: at least one central processing unit, an optical memory reading and/or writing device (2) and a data bus (1), wherein the central processing unit and the optical memory reading and/or writing device (2) are indirectly or directly connected to the data bus (1), the magnetic hard disk drive further comprising:

a cache processor (5) receiving requests from said data bus (1) to read and/or write information intended for said optical memory read and/or write device (2), said cache processor (5) also exchanging information between said magnetic hard disk drive and said optical memory read and/or write device (2) over said data bus (1) to cache said optical memory read and/or write device (2); and

connection circuitry for connecting the magnetic hard disk drive to the data bus (1) in parallel with the cache processor (5).