HK1015246B - A system for measuring and indicating changes in the resistance of a living body - Google Patents

Description

System for testing and displaying change of resistance of living body

The present invention relates to an improved apparatus for displaying and testing changes in the resistance of a living body.

With the advent of the Lafayette R.Hubbard test and display device for changes in living bodies, it was realized that small changes in the resistance of living bodies could be identified by electromechanical testing. The apparatus generally includes a resistance test circuit, an amplification circuit, and a display circuit. Although this apparatus is sufficient for the purpose of testing the change in the resistance of the living body, it cannot accurately display the change in the test. Various improvements attempted to address this problem are set forth and illustrated in U.S. patent No.3,290,589 and U.S. patent No.4,459,995. These devices produce a signal of small variation in the resistance of the living body, which is then amplified into a recognizable and useful signal on a display, such as a visual display, that is perceptible to a human being. One problem with these devices is that the interference features in the signal mask or erroneously reflect small variations. These interference characteristics may be due to interference at radio frequencies and/or to non-linear performance within the device itself. Therefore, an apparatus capable of more accurately displaying the change in the resistance of the living body is required.

It is a general object of the present invention to accurately display small changes in the resistance of a living body.

It is a particular object of the invention to eliminate the interference signature in the live resistance signal.

It is a feature of the present invention to include an active correction circuit that gives a generally constant amplitude response for a given test input.

An advantage of the present invention is that the sensitivity of the device is maintained at a constant level.

In accordance with the objects, features and advantages of the present invention, an improved resistance testing and display device is provided which includes a resistance testing circuit having an input terminal connected to a living subject for generating a test signal indicative of the resistance of the living subject. The amplification circuit receives the test signal and amplifies it to a perceptible level. The display circuit receives the amplified signal and provides the test signal in perceptible form. The present invention advantageously includes passive and active devices to eliminate the interference characteristics of the test signal.

One of the features of the present invention is an active correction circuit. The effect of the correction circuit is to give a generally constant amplitude at the display circuit in response to the resistance change given by the resistance test circuit. In a preferred embodiment of the correction circuit, the feedback circuit portion and the control circuit portion cooperate to monitor operation of the device and to predict changes in the amplitude response in the display circuit. In order to predict the change in amplitude, a compensator is included to adjust or correct the amplification circuit.

Objects and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings.

FIG. 1 is a functional block diagram of a conventional apparatus for testing the resistance of a living body;

FIG. 2 is a functional block diagram of the apparatus of the present invention;

FIG. 3 is a functional block diagram of a preferred resistance test circuit of the present invention;

FIG. 4A is a functional block diagram of a preferred amplification circuit of the present invention;

FIG. 4B is a functional block diagram of a variable resistance circuit and a boost circuit;

FIG. 4C is a functional block diagram of a feedback and control circuit;

FIGS. 5A-5D are flow diagrams of a main software program;

FIG. 6 is a flow chart of a delay routine;

FIG. 7 is a flow chart of a select meters routine;

FIG. 8 is a flow chart of an analog-to-digital low resolution routine;

FIG. 9 is a flow chart of an analog-to-digital high resolution routine;

FIG. 10 is a flow chart of an analog-to-digital conversion routine;

FIG. 11 is a flow chart of an analog-to-digital interrupt routine;

FIG. 12 is a flow chart of a programmable boost setting routine;

fig. 13 is a flowchart of a resolution mode setting routine;

FIG. 14 is a flow chart of a query low potential routine;

FIG. 15 is a flow chart of a select digital resistance routine;

fig. 16 is a flow chart of a program for changing the digital resistance.

Referring to the figures, the present invention may be used in conjunction with any conventional three-stage circuit that tests and displays changes in the resistance of a living body. Referring to fig. 1, the apparatus typically employs a resistance test circuit 20 to convert the measured resistance of the living body into a form of a test signal. The resistance test circuit is connected to the amplification circuit 22 to amplify the test signal to a perceptible level. A display circuit 24, coupled to the amplification circuit 22, converts the test signal into a perceptible form. The resistance testing circuit can adopt a conventional bridge type or voltage division circuit to test the resistance of the living body. U.S. patent No.4,702,259, U.S. patent No.4,459,995, and U.S. patent No.3,290,589, which are incorporated herein by reference, disclose three-stage circuits having bridge circuits suitable for this purpose. Three-stage circuit with voltage divider circuit suitable for this purpose is included in "HUBBARD^TMPROFESSIONAL MARK SUPER VII "device, manufactured and sold by Hubbard electronic Instrument Inc. of los Angeles, Calif.

Based on the above, known joint implementations require means for the circuit to increase sensitivity automatically at high resistance levels and to adjust automatically at low resistance levels. The present improvement provides for a constant amplitude response in the display circuit 24.

The preferred embodiment of the present invention, as shown in the functional block diagram of FIG. 2, fuses the inventive features to the conventional "HUBBARD^TMPROFESSIONAL MARK SUPER VII' circuit. The circuit is additionally providedA voltage regulator 26 is also employed to achieve a stable dc voltage level throughout the circuit. A digital circuit 28 controlled by a microprocessor (not shown in these conventional devices) is used to track the signal from terminal 31 from resistance test circuit 20, to display the date and time, and to perform various conventional switching functions. The display terminal 32 provides a signal to a conventional LCD clock and signal tracking display of the display circuit 24. The digital circuit may also be of the form disclosed in U.S. patent No.4,702,259. Terminals 33 are led from the voltage regulator circuit 26, the resistance test circuit 20 and the amplifier circuit 30, and are connected to various conventional manual controllers (not shown) in a conventional manner. These terminals may intercept radio signals causing Radio Frequency (RF) interference. In the preferred embodiment of the invention, the circuit board includes an inductor 35 that leads from the slide terminal 37 of the manual controller. The manual controller comprises a function switch, a low-voltage potentiometer, a remote low-voltage potentiometer, a fine-tuning variable resistor and a sensitivity controller.

The amplification circuit 30 is typically a two-stage amplification according to the present invention. The first stage amplifier circuit 34 receives the test signal and logarithmically amplifies it. A second stage amplifier circuit 36 connected to the output of the first stage amplifier circuit 34 adjusts and amplifies the gain of the test signal. The computer interface 40 selectively provides the required signals to the voltage-to-current conversion circuit 38 for situations requiring analog test signals. A voltage-to-current conversion circuit connected to the output of the second stage of amplification circuitry conditions the test signal into a form usable by the display circuitry 24. The voltage-to-current conversion circuit 38 also provides feedback to the second stage amplification circuit 42 and the computer interface 40. The variable resistance circuit 42 is coupled to the second stage amplification circuit 36 and provides an amplifier feedback signal to amplify the measurement signal from the resistance test circuit 20. The variable resistance circuit 42 includes high and low programmable gain sections 46 and 44. An isolated boost switch circuit 48 is connected to the variable resistance circuit 42 for manual gain adjustment. The correction circuit 50 is also connected to the variable resistance circuit 42. The correction circuit 50 adjusts the output of the amplification circuit as correction means. In the preferred embodiment, the correction circuit 50 includes a feedback circuit 52, a control circuit 54, and a compensation circuit 55.

The resistance test circuit of the preferred embodiment (fig. 3) is of the voltage divider type. In the voltage divider circuit, a high potential 56 is connected in series with a first voltage divider resistor 58. The first resistance may be adjusted or compensated for using the variable resistor 60. The conventional meter test switch 62 is either manually selectable or selectively switchable for control by the digital circuit 28 between connecting the live subject's external terminal 66, terminal 64 and a 5K ohm resistor 68 as a test resistor in place of the live subject. Conventional electrodes intended to be connected to a living body are connected by a plug (not shown). When the plug is inserted, the outer terminals 64 and 66 are connected to the living body. With the plug removed, another switch 70 connects the high potential terminal 66 to a 5K ohm resistor 68. In addition, the capacitor 72 connected between the outer terminals 64 and 66 is connected in series with the inductor 86. The function of the inductor 86 and the capacitor 72 is to reduce signal interference. A second voltage dividing resistor is located between the meter test switch and output terminal 88. Third voltage-dividing resistor 74 is connected in series between output terminal 88 and low potential terminal 76.

The low potential value is manually adjusted using a manual adjustment device 78. The manual adjustment device 78 preferably includes a slide terminal 80 for a potentiometer 82 connected between high and low voltages. The circuit of slider terminal 80 includes an inductor 87 which is typically connected through an analog switch circuit 90 to terminal 91, with capacitor 92 being grounded to reduce interference. The manual adjustment device 78 is typically a built-in potentiometer 82 or an external potentiometer 94. The external potentiometer 94 is also connected to the analog switch circuit through high and low voltage terminals 96 and 98 and a slider terminal 100. The external variable resistor 94 also includes a REM or remote signal terminal 102 and a ground terminal 104. An analog switch circuit 90, which conventionally includes a manually controlled switch or voltage divider and latch, is connected to an analog switch (not shown) that selectively drives either an internal or external potentiometer. Alternatively, the potentiometer is selected based on the voltage state of the REM signal terminal 102. When the internal potentiometer 82 is employed, the signal remains "high" and is connected to ground 104 through the external potentiometer terminal 106. In use, the voltage values at the slider end 91, the high end 108 and the low end 100 of the potentiometer are fed into the digital circuit 28 (fig. 2) to calculate the digital potentiometer signal values. The signal at slider terminal 91 is sent through signal buffer 112 with a voltage follower, which avoids the loss of current at low potential 76.

Referring to fig. 4A, B and C, the primary amplification circuit 34 receives a test signal from the resistance test circuit signal output 88. The first stage amplifier circuit 34 includes an operational amplifier (op-amp)124 having a positive input 126 coupled to the output 88 of the resistance test circuit 20 (fig. 1). The operational amplifier 124 is connected as a voltage follower with a feedback terminal 128 connected from the output terminal 130 of the operational amplifier to a negative input terminal 132. A capacitor 134 is connected between the positive input terminal 126 and the negative input terminal 132 to help reduce RF interference in the test signal. The op amp output 130, in parallel with the feedback loop 136, provides a negative input to the op amp 138 as a primary amplifier. Resistor 140 is connected to output 130 of the voltage follower. The resistor 140 is connected to a preset potentiometer 142 and an output 144 of the primary amplifier via two parallel resistor branches. The first branch includes a resistor 146 connected between the preset potentiometer 142 and the first resistor 140. The second branch comprises a conventional user adjustable potentiometer connected to an electrode 148 in series with a resistor 150 and a preset variable resistor 142. The user adjustable potentiometer (not shown) acts as a sensitive gauge with the gauge electrode 148 including a wiper terminal 152 connected to the negative input 154 of the primary amplifier via an inductance 156. The positive input 158 of the first stage operational amplifier receives a voltage reference signal 160 from the voltage regulator 26, and the voltage regulator 26 provides a regulated reference voltage of 5.25 volts. The voltage reference 160 is also connected to a resistive feedback branch comprising a second preset adjustable resistor 162 and a fixed resistor 164 connected to the output 166 of the primary amplifier. The output 144 of the primary amplifier is also connected to the output 166 through a fixed resistor 170. It will be appreciated by those skilled in the art that the configuration of the primary amplification circuit provides a decaying summing amplifier, the value of the signal output 88 of the resistance test circuit 20, amplified by the gain of the operational amplifier 138, is summed with the value of the voltage reference 160. The operational amplifiers 124 and 138 of the first stage of the amplifying circuit are OP420 type operational amplifiers manufactured by analog devices of manchester Norwood. The summed, amplified signal output 166 is coupled to the two-stage amplification circuit 36. The first stage of the amplifier circuit changes the instrument gain logarithmically from 1 to 10 as the variable resistor 142 changes from low to high.

The two-stage amplification circuit 36 comprises an OP90 type operational amplifier with a variable resistance feedback branch, produced by analog devices. This particular type of operational amplifier requires offset compensation by using a variable resistor 174 connected through its slider terminal 178 to ground 176. Other types of amplifiers suitable for the present purpose do not require this circuit. The output 166 of the first stage amplifier circuit 34 is connected to the positive input 180 of the second stage operational amplifier 172. The variable resistance circuit 42 provides gain feedback to the negative input 182 of the secondary amplifier 172. The positive input 184 of the secondary amplifier 172 is connected to the gate 186 in latch gate 186-187. These gates selectively connect the voltage-to-current converter 38 to the second stage amplification circuit 36 and the computer interface 40. The digital circuit 28 performs switching to respond to the operator's selections in a conventional manner.

The computer interface 40 is connected to the voltage-to-current conversion circuit 38 through latch gates 188 and 189. The computer interface 40 includes an amplifier 190 similar to a secondary circuit having an E-IN signal terminal 192 from the signal bus and connected to a positive input 194 of the amplifier. A first capacitor 196 provides filtered feedback and is connected between the negative input and the output of amplifier 190. The negative input is further connected to a voltage divider feedback circuit comprising a reference voltage 201, two positive bias resistors 202 and 203, a latch gate 188 and a third resistor 204 connected to ground. The computer interface E-IN terminal 192 receives the reproduction signal of the previously recorded portion or the analog reproduction signal, and the output is reproduced on the display circuit using the amplifier 190 of the computer interface. The signal terminal E _ OUT206 receives a signal indicating a change in the resistance of the living body from the display circuit 24 and transmits a test signal to the computer interface 40.

The voltage-to-current conversion circuit 38 includes a transistor 208 having an emitter terminal 210 coupled to a "high" voltage 201 through a biasing resistor 202 and to gates 187 and 188, a base terminal 212 coupled to a "high" voltage through a forward biasing resistor 214, and two series diodes 216 and 217 biased oppositely to the base terminal 212. Diodes 216 and 217 are connected to the output of the secondary amplifier 172 and the computer interface amplifier output through gates 186 and 189, respectively. The transistor collector is connected to the output 221 of the display circuit 24.

The variable resistance circuit 42 (fig. 4B) includes a programmable gain reduction circuit 44 and a programmable gain increase circuit 46. The change in the low potential 76 of the resistance test circuit (fig. 3) indicates which of these variable resistance circuits is used to provide variable gain, as will be explained below. The variable resistance circuit 42 is connected to the negative input 182 of the operational amplifier via terminals 226 and 228 (fig. 4A and 4B), to the voltage-to-current conversion circuit 38 via a gate circuit 187, and to the voltage source 201 via the resistor 202. The capacitance 223 between the positive input terminal 180 and the negative input terminal 182 mitigates the RF interference signal. The programmable gain boost circuit 46 includes four circuit portions connected in parallel between the terminals 226 and 228 of the variable resistance circuit. The first portion includes a capacitor 230. The second section includes a latch gate 232 and a resistor 234, the third section includes a latch gate 236 and a resistor 238, and the fourth section includes three series resistors 240 and 242. The latch gates 232 and 236 are controlled by the isolated boost switch circuit 48. The programmable gain reduction circuit 44 includes a separate latch gate 244 that is connected to the correction circuit 50, discussed in more detail below, and the programmable gain reduction circuit 44 also includes three branches connected in parallel. Each branch of the programmable gain reduction circuit includes latch gates 246, 248 and 250 in series with resistors 252, 253 and 254, respectively, selectively connected in circuit according to the setting of the isolated boost switch circuit 48.

The boost switch circuit 48 includes a switch 256 having a slider end 258 that enables the placement of three separate low 260, normal 262 and high 264 terminals. Terminals 260, 262 and 264 are grounded through respective negative bias resistors 268, 267 and 266. The gates connected to these terminals are closed when a ground voltage is detected. The slider end 258 includes a positive or high voltage. When the slider end is connected to one of the high end 264, the normal end 262 and the low end 260, the connection end is raised to a high voltage level. When a high voltage is detected, the latch gate connected to the different terminal will be open. The programmable gain boost circuit is always on even in the programmable gain reduction mode. The input signal from the first-stage amplifier is further amplified according to the low, normal, and high states of the boost switch, which linearly changes the gain of the operational amplifier in units of 10. The two-stage operational amplifier provides additional gain through the boost switch, so that in the low boost position, the gain is multiplied by 1, in the normal boost position, the gain is multiplied by 10, and in the high boost position, the gain is multiplied by 100. In addition, the two-stage operational amplifier provides a gain ranging from 0.7 × to 50 × under the control of the micro control unit. Since the micro-control gain is independent of sensitivity and booster, it can be regarded as the third stage. The three stages are each a factor of the overall gain of the circuit, and the output gain is thus the product of the three stages. The lowest possible gain is 1.0 × 1.0 × 0.7 to 0.7, and the highest possible gain is 10 × 100 × 50 to 50,000.

The control and feedback circuit 50 (fig. 4C) provides active correction of the amplifier in response to changes in the manual adjustment device 78 of the resistance test circuit 20. Control and feedback circuit 50 is coupled to the negative input 182 of the operational amplifier with the variable resistance circuit as shown at terminal 356 (fig. 4C), terminals 356 and 226 (fig. 4B) and the negative input 182 of operational amplifier 172 in series, control latch terminal 272 (fig. 4B, 4C) of control and feedback circuit 50 coupled to programmable gain down/up latch gate 244, control and feedback circuit 50 providing active correction in response to any change in the circuit that may produce a glitch characteristic of the test signal. In the preferred embodiment, the control and feedback circuitry monitors and responds to changes in the manual adjustment device 78. Referring to fig. 3, a manual adjustment device 78 controls the low potential 76 of the voltage divider. The skilled person will know that a change at low potential varies the supply voltage through the voltage divider inversely. As the voltage provided by the voltage divider varies, the operating range that defines the maximum value of test signal 88 also varies inversely with the value of low potential end 76. The variation in the operating range affects the display range of the maximum value provided by the display circuit 24. To maintain the display range at a normal level of correction in display circuit 24, the feedback and control circuit adjusts the feedback gain of the two-stage amplification circuit to compensate for variations in the operating range of test signal 88. It will also be appreciated that when the low potential 76 is adjusted to closely match the high voltage level 56, the voltage range of the detectable resistance difference is very small. Because of this small range, programmable gain-up circuitry is required. The feedback and control circuit adjusts the output of the operational amplifier by adjusting the gain of the negative input of the operational amplifier throughout the low potential range. To achieve the adjustment of the gain of the negative input of the operational amplifier and to switch between programmable gain up and down modes, the feedback and control circuit includes a feedback circuit 52, a control circuit 54 and a compensation circuit 55.

The feedback circuit 52 of the feedback and control circuit includes a terminal connected to the low potential terminal 76, which is connected through a resistor 306 to a low resolution input terminal 308 connected to a Micro Control Unit (MCU), and a capacitor connected to ground for signal filtering. The output of the resistor 306 is connected to the positive input 312 of an operational amplifier 314. The negative input 316 of the operational amplifier comprises a gain circuit comprising a resistive feedback branch 318 in series with a potentiometer 324 and a capacitive branch 320 in parallel between the negative input 316 and an output 322. The potentiometer 324 is balanced by a pair of fixed resistors 326 and 328 and a variable resistor 330 to provide the desired amplification offset. The high resolution input 332 is connected to the output of the high resolution operational amplifier 314 through a resistor 331.

The control circuit 54 includes a Micro Control Unit (MCU)334, model ST62TI0B6/SWD, manufactured by SGS Thompson electronics of Carrolton, Tex. The MCU334 in this particular example is also commonly referred to as a Central Processing Unit (CPU) and includes a first eight-bit port set by software to receive the outputs of the output terminals 308 and 332 of the feedback circuit via pins 14 and 15, respectively. These pins are connected in circuit to an internal analog-to-digital converter which is contained in the MCU and which is capable of recognizing discrete changes in the input signal in increments ranging from 0 to 255. When the manual adjustment device 78 is varied in the range of 0.5 to 6.5, the low resolution input is continuously varied, which corresponds to a voltage variation range of about 1.4 to 5.2 volts. The high resolution input is active but does not actually change until the manual adjustment device 78 is above about 4.8 volts. Below this level, the high resolution input is maintained at 0.7 volts (boost above zero), the high resolution input range is corrected to 1.00 volts as the manual adjustment device 78 reaches 5.0 volts, and the voltage continues to rise linearly to approximately 5.2 volts as the manual adjustment device 78 is raised to 6.5 volts.

Control circuit 54 (fig. 4C) also includes a latch trigger circuit 336. The controller 54 is not used when the manual adjustment device 78 is in the transition period. Because the triggering is intermittent, the controller 54 includes a power-saving static trigger 338. Static flip-flop 338 is a set-reset flip-flop model 4013B produced by motorola. Terminal 340 of digital circuit 28 (fig. 2) triggers a trigger latch gate that is normally set to a "high" voltage 341. When the digital circuit 28 detects a change in the low potential slide output 91 (FIG. 3), it changes the signal from "high" to "low" and is sent to the display circuit 24 by terminal 340. Terminal 340 is also connected to trigger circuit 336. When the terminal 340 drops to zero potential or "low", the flip-flop 338 changes the signal output 342 and issues an interrupt signal to the MCU to "wake up" the MCU.

Control circuit 54 includes power and ground terminals 344 and 346 that are connected in a conventional connection to pins 1, 2, 5, 6 and 20. The MCU reset interrupt circuit 348 is connected to MCU pin 7. The reset switch periodically sends out a reset signal to the pin 7, so that the power of the circuit is reduced. The reset trigger on/off is designed to be at the 4.5 volt limit. When the voltage rises from zero to 4.5 volts, the reset is off. When the voltage rises to 4.5 volts, the reset is on as long as the voltage remains at or above 4.5 volts. When the voltage drops below 4.5 volts, the reset is off, as long as the voltage remains at or below 4.5 volts, the reset is off. A 4MHZ clock 350, which is a loose production PX400 type, is connected to pins 3, 4.

A controller 54 responsive to the feedback circuit 52 and controlled by software generates the correction signal. The correction signal is provided to the compensation circuit 55 through the MCU pins 18 and 19 via 356.

The compensation circuit 55 of the preferred embodiment includes a digitally controlled variable resistor 354 or a digital potentiometer. The digital potentiometer 354 is a model X9C103 digital potentiometer manufactured by Xicor of Milpitas, california. The digital potentiometer 354 receives an input voltage TA _ Ref160, and TA _ Ref160 provides an input signal. The output 357 of the variable resistor circuit, filtered through a capacitor to ground to remove RF interference, is connected to the negative input 182 of the second operational amplifier at 226 as shown in fig. 4A. This terminal is the R + terminal in fig. 4A and 4C. The resistance of the digital potentiometer 354 changes in response to the correction signal of the micro control unit 334. The change in the variable resistance is used to cancel the expected interference signature in the measured signal.

Referring to fig. 4A, B and C, the micro-control unit 334 cooperates with the feedback 52 and compensation circuit 54 to automatically monitor the circuit for corrective functions under the control of software that sets the conventional micro-control unit 334. The software program includes a main program and eleven sub-programs. Reference is made to TA in the flow chart corresponding to the manual adjustment device 78. Each of the preferred embodiments is described below.

Main program 400 (FIGS. 5A-B) includes an initialization routine that sets interrupt address vector 401 and sets the micro-control unit hardware and ports 402. A delay loop is executed to stabilize the pin terminal of the micro control unit to a predetermined value. This loop includes an initialize counter step 403 and a do-entire loop 404 that calls the delay subroutine 406 twice. Next 408, a digital potentiometer or digital potentiometer is set. The range of the digital potentiometer is divided into 100 incremental steps and positive and negative limits are determined. Next, a digital potentiometer setting program (clkdp)410 is executed to set an initial value for the digital resistor. After the setup procedure, a meter type (sleeper) subroutine 412 is executed. The meter type subroutine 412 is complete, the initialization routine is complete, and the active correction mode is initiated.

The active correction mode is a main routine executed by the micro-control unit 334 (fig. 4C) and is continuously repeated while the micro-control unit is operating. First, a dormant trigger is set, at a TA detection enable step 414, to detect a transition in the TA value. Next, the TA potentiometer measurement subroutine at low resolution (a2dlow)416 is invoked. The boost setting subroutine (setboost)418 determines and sets the booster gate to a high or low programmable gain. A mode setting subroutine (setmode)420 internally determines and sets the resolution mode to "high" or "low" resolution. Next, the resolution mode is checked in a resolution check step 422. If the resolution flag is high, subroutine (a2dhigh)424 for testing TA at high resolution is invoked. Otherwise, no measurement is made. The TA solution subroutine (TA find) will next determine the value of TA. Next, as shown in FIG. 5C-1, a digital potentiometer setting subroutine (dpset)428 determines the required correction amount. Next, the clkdp routine 430 is invoked to reset the digital potentiometer to the new calibration position required. After compensator correction, a TA change verification step 432 is performed. If the TA table has changed, the dormant trigger is cleared at step 434 and the routine returns to the TA Enable 414 step. Otherwise, the main routine continues to reset the trigger step 436 to ensure proper setting of the trigger.

Next, referring to FIG. 5C-1, a count register is set for the three sampled do-loop cycle at step 438. As shown in fig. 5C-2, the high resolution verification step 440 calls a sub-routine 442 for measuring TA at high resolution if the verification result is high. Otherwise, the measure TA at low resolution subroutine 444 is invoked. Next 446, the measured samples are stored in memory. If the number of samples is less than three, the sample counter is decremented by 1, and it is detected whether the sampling is completed, and then step 448 returns to the resolution determination step. Otherwise, the program begins testing the sampled data. The purpose of the test is to determine whether the operator has adjusted the manual adjustment device to a new position. The micro control unit recognizes that the operator has completed the rotation of the device, at which time the measurement results will be stable when any two of the three sampled data are equal. When additional steps or other sampling of data are performed to determine whether the operator has completed the adjustment of the manual adjustment device, the preferred embodiment includes three data comparison steps 450 (FIG. 5C-2), 452 (FIG. 5D-1), and 454 (FIG. 5D-1). In a first test step 450, the first sampled data is compared to the second sampled data. If the first and second sample data are equal, the test stops and the routine continues with the TA State detection step 456 (FIG. 5D-1). Otherwise, the test continues with a second test step 452, comparing the first sampled data with the third sampled data. If the first and third samples are equal, the test stops and the routine continues with the TA status check step 456. Otherwise the test continues with a third test step 454, comparing the second and third sampled data. If the second and third sample data are equal, the routine continues with a TA condition check step 456. Otherwise, the TA is still adjusted and the process returns to the TA enable step 414 to correct the start of the process (fig. 5B).

If any two equalities in the current sampled data indicate that manual adjustment has been completed and the data is valid, a TA status check step 456 is performed to see if the manual adjustment device has been adjusted by checking the TA trigger to determine that sampling has begun. If the trigger is triggered, the trigger is cleared and reset at step 458 (FIG. 5D-1) and the routine returns to the TA Enable step 414. Otherwise, the compensator recalibrates in the following order: a2dlow416 (FIG. 5B), setboost subroutine 460 (FIG. 5D-1), define subroutine 462 (FIG. 5D-1), dpset subroutine 464 (FIG. 5D-2), and clkdp subroutine 466 (FIG. 5D-2). Next, the TA trigger is rechecked for adjustment 468 (FIG. 5D-2). If so, the TA trigger is cleared 470 and the routine returns to the TA Enable step 414. Otherwise, the process goes to sleep mode 472, conserving energy and suppressing noise. The working part of the MCU hardware monitors the input signal from the TA converter. If an interrupt is received, the MCU wakes up at step 474 and returns to the TA change check step 468. Thus, the main routine holds the correction of the amplifier circuit.

It is useful to detect sleep mode, otherwise the MCU334 will continuously calibrate the amplification circuit. This causes periodic jumps in the output of the display circuit relative to the resistance measurement circuit. During stabilization, the sleep mode eliminates random jumps by placing the controller in a sleep state, stabilizing the compensation circuit.

As discussed above with respect to the main program, the subroutines perform specific tasks within the main program. These subroutines will be described one by one in the order of their calls in the main routine.

The delay (dly 1) subroutine 480 includes a counter constant input step 482 for the do-loop, a counter decrement step 484, and an end of loop check step 486. After the required number of loop cycles is completed, the subroutine returns to the program call.

The meter select (selmeter)440 subroutine is called in the initialization portion of the main program. The feedback and control circuit of the present invention may be implemented on any of the previously known electronic meters employing voltage dividers or resistive bridges of the type described and referred to earlier. The circuitry and software of the present invention may be configured to operate with a voltage divider circuit or a resistive bridge circuit as in the preferred embodiment illustrated in the figures. The meter selection subroutine checks a port pin on the MCU. This pin is set to either a "high" or "low" voltage depending on the type of resistance measurement circuit employed. The meter selection subroutine 490 includes a pin verification step 492. If the pin is "high," an initialization step 494 of the voltage divider circuit is performed. Otherwise, an initialization step 496 of the resistive bridge circuit is performed. After any one of the initialization steps is completed, the program returns to the main routine.

The a2dlow subroutine 500 measures the TA value in the low resolution mode. This subroutine includes an initialization step 502 to set the MCU internal analog to digital converter in low resolution mode. Next, the analog to digital converter (a2d) subroutine is invoked, step 504. After return, the analog to digital converter is reset (step 506) and the subroutine returns to the program call.

The a2dhigh subroutine 510 measures the TA value in the high resolution mode. This subroutine includes an initialization step 512 to set the MCU internal analog to digital converter in high resolution mode. Next, the a2d subroutine is called 514. After return, the analog to digital converter is reset 516 and the subroutine returns to the program call.

The use of high resolution and low resolution modes allows the use of an 8-bit internal adc to function as a 12-bit adc, requiring the full voltage range of the 12-bit adc to be 0-5.2 volts, with low resolution in the 1-4.8 volt range and high resolution in the 4.8-5.2 volt range. The AD converter in the low resolution mode directly detects the slider voltage on TA, so that the voltage range of 1.4 volts to 5.2 volts corresponds to decimal values of approximately 67 to 255. The AD converter in the high resolution mode can detect an input range of 1.0 to 5.2 volts, corresponding to a voltage range on the TA slider of about 4.8 to 5.2 volts, corresponding to a decimal value of about 49 to 255.

The a2d subroutine 520 of the measured analog signal step 522, when called by the a2dlow subroutine (step 500), converts the analog signal measured on the MCU pin 14 to a digital signal; the analog signal measured on the MCU pin 15 is converted to a digital signal when called by the a2dhigh (step 510) subroutine. The a2d subroutine 520 then enters a wait mode 522 to cause the MCU analog to digital converter to complete the conversion. After the conversion is complete, the MCU generates an interrupt 524 that includes an address vector pointing to the a2din subroutine 528. The a2dint subroutine 528 resumes, saves the analog to digital converted data, and terminates the associated hardware 530. The a2dint subroutine returns to the a2d subroutine, and the a2d subroutine in turn returns to the subroutine that called it.

The boost setting subroutine 540 switches the boost resistance of the variable resistor circuit between programmable high and low gains of the variable resistor circuit. The boost setting subroutine includes a potential test to determine whether the TA analog to digital conversion setting is the high resolution mode or the low resolution mode. If the high resolution mode is set (step 542), the program jumps to the programmable gain increase enabled step 544. Otherwise additional tests will be performed. In this case, if the TA value is above the programmable gain minimum, the compare TA value to programmable minimum step 546 jumps to the programmable gain raise valid step 544. Otherwise additional tests will be performed. In this case, if the TA value is less than the programmable gain maximum, the compare TA value to programmable maximum step 548 jumps to a programmable gain reduction active step 554. Otherwise, the program moves to the programmable gain increase active step 544. For either the programmable gain raise active step 544 or the programmable gain lower active step 550, the subroutine sets the programmable gain latch terminal 552 according to either a high or low setting. The setboost subroutine then returns to the program call.

In the preferred embodiment, the programmable gain minimum is less than the programmable gain maximum. The skilled person will know that the flow chart will not require a comparison with a high value of the programmable gain in this case, since the TA value obtained from this test is always smaller than the highest value of the programmable gain. However, in another alternative embodiment, the highest value of the programmable gain is less than the lowest value of the programmable gain. This arrangement causes hysteresis in changing the setting. This is useful in preventing unwanted jumps in the data readout of the display circuit.

The mode setting subroutine 560 sets the analog-to-digital converter mode to a high resolution mode or a low resolution mode. This subroutine includes a comparison 562 of a TA value to the high resolution mode limit. If the TA value is greater than the limit for high resolution mode, the routine sets the high resolution flag bit to HIGH or TRUE 564. Otherwise, the program sets the high resolution bit to low or false 566. After the high resolution flag is set, the program returns to the program call.

the tafind subroutine 570 uses the TA value to determine the required correction to eliminate any interfering features in the signal output of the resistance measurement circuit. In the preferred embodiment, the TA value is detected by active calibration, and a change in the TA setting is detected. In the case of a voltage divider, the decrease in the range of the program voltage over which the resistance change can be measured has a direct relationship with the increase in the voltage value in the TA buffer. When the TA value is greater than or exceeds the TA resistance, which is preferably in the range of 5K to 12.5K ohms, the amplitude of the signal representing the change in the resistance of the living body is correspondingly undesirably reduced. the tadind subroutine overcomes this problem by determining the adjustment values for the variable resistance circuit to compensate for these changes, i.e., by adjusting the feedback of the amplification circuit accordingly using a look-up table to compensate for the change in TA voltage and perform a correction of the measured signal. the tailind subroutine 570 includes a setup step 572 that determines the correct look-up table for the voltage divider type or resistance bridge type resistance measurement circuit. Next, a high resolution mode check step 574 checks whether the device is in high resolution or low resolution mode. If in the high resolution mode, the lookup table portion of the high resolution mode is placed in memory (step 576). Next, in preparation step 578, the MCU loads the TA value and the lookup table value into memory. At a TA check step 580, the value of TA is tested against its index value. The table values are read in by the MCU in the lowest or highest order. If the TA value is less than the index value, the TA index value is next entered 582 and the routine returns to test 580. Otherwise, the value of the corresponding digital potentiometer is input to the lookup table (step 584). Digital potentiometer setting change step 586 then inputs the desired value to change the resistance of the digital potentiometer. The subroutine then returns to the program call.

The dpset subroutine 590 sets the MCU to adjust the digital potentiometer. Subroutine 590 includes a register entry step 592, a new position calculation step 594, and a check step 596 to determine whether the new value is high or low. If the value is high, a direction flag setting step 598 is performed to make it up, otherwise a direction flag setting step 600 is performed to make it down. Next, the values are entered and calibration of the digital potentiometer is started 602. The subroutine then returns to the program call.

The clkdp subroutine 610 calibrates the digital potentiometer in response to the voltage value measured from the TA potentiometer. This subroutine includes a direction bit check step 612. Such bit is high and the digital potentiometer is instructed to count up 614. Such bit is low, the digital potentiometer is instructed to count down 616. A no change check 618 is next performed. If the change is zero, the subroutine returns to the program call. Otherwise, the digital potentiometer is initialized 620 and the variable resistance is changed. In the direction checking step, the digital potentiometer is instructed to be increased by one unit in the determined direction. The incremental change is 100 ohms using a preferred digital potentiometer. The next step calls the delay subroutine 624, which causes the digital potentiometer to receive and process the signal. The counter is then decremented and checked 626. The counter is greater than zero and the process returns to the indicating step 622 to advance the digital potentiometer by one more unit. When the counter is zero, the program is terminated and the program is returned to the program calling step.

It will be appreciated from the above disclosure that the present invention can be used to actively calibrate an amplifier to eliminate any known predetermined interference characteristics. This can be done once a feature is determined and this feature conforms to a measurable change in the internal signal. The microprocessor includes a "look-up table" of gain compensation factors stored in memory, which is empirically derived by measuring a given resistance change magnitude at each selected point across the input resistance. From these compensation factors, the required gain and corresponding feedback resistance can be calculated, thereby creating a table of low potential (76) versus gain resistance of the variable resistor 42.

In operation, the device is initialized by adjusting trim control 60 (FIG. 3), boost converter circuit 48 (FIG. 4B) and sensitivity control (not shown) so that low potential 76 (FIG. 3) is balanced with the 5K ohm meter sense resistor. The living body is thus connected to the external terminals 64 and 66 of the resistance measuring circuit. In order to balance the circuit in terms of the total resistance of the living subject, manual adjustment device 78 is adjusted until low potential 76 and the total resistance of the living subject are balanced. Feedback circuit 52 (fig. 2 and 4C) provides a change in low potential 76 to control circuit 54 during the process of changing low potential 76 to reach equilibrium with the total resistance of the living subject. Control circuit 54, which is normally in a sleep mode, wakes up for movement of manual control device 78 when digital circuit 28 signals it. The control circuit 54 monitors the movement of the manual control device 78 until the adjustment is complete. After the adjustment is complete, the control circuit 54 determines a gain adjustment value using the look-up table and signals the compensator circuit 56 to adjust the gain of the amplifier circuit. The gain is adjusted to eliminate the interference characteristic of reduced sensitivity in response to increased low voltage potential 76. The gain is automatically adjusted so that the sensitivity is maintained at a constant value independent of the change in the low potential 76.

In another alternative embodiment of the correction circuit, the amplification circuit (not shown) comprises a voltage controlled operational amplifier. In this embodiment, the low potential 76 is connected to the control voltage input of the amplifier. The amplifier may be placed with the negative input and output terminals in series at the output corresponding to terminal 130 (fig. 4A) of the voltage follower. The positive input will be connected to a constant high voltage source. The operational amplifier corrects the amplifier gain in proportion to a change in the low potential. An operational amplifier suitable for this purpose is model VCA610 manufactured by Burr Brown of Tucson, Arizona.

In a second alternative embodiment of the correction circuit, the manual adjustment device 78 may comprise a conventional duplex potentiometer wherein the second non-linear increase in resistance may be adjusted to a resistance inversely proportional to the resistance of the variable resistor 82 (fig. 3). The second potentiometer would be connected between the reference voltage (fig. 4C) and the negative side input of the second operational amplifier circuit (fig. 4C).

Another embodiment of the present invention is to include a radio frequency isolating paint coating on the interior surface of the housing in which radio frequency interference can be further reduced. Paints suitable for this purpose are manufactured by Sandstrom Procclucts, Inc. of IL, Port Byron, sold under the model Sanpro A405, and are also known as silver-plated EMI/RFI protective coating paints.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims, which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent arrangements.

Claims (26)

1. An apparatus for displaying changes in the resistance of a living body, comprising a resistance test circuit having an external terminal, an amplification circuit connected to the resistance test circuit, a display circuit connected to the amplification circuit, and a sensitivity adjustment circuit connected to the amplification circuit,

the resistance test circuit is adapted to test the resistance of the living subject over a first range of relatively low variable in-vivo resistance and over a second range of relatively high variable in-vivo resistance to generate a test signal;

the amplifying circuit is suitable for amplifying the test signal to an observable level;

the display circuit is adapted to make the test signal in observable form; and

the sensitivity adjustment circuit is capable of automatically increasing the sensitivity of the display circuit for high variable living body resistance settings within the second range tested in the resistance test circuit.

2. The apparatus for displaying changes in the resistance of a living body of claim 1, wherein:

the sensitivity adjustment circuit is capable of automatically adjusting the sensitivity of the display circuit for low variable resistances within a first range of resistance tests in the resistance test circuit.

3. The apparatus for displaying changes in the resistance of a living body of claim 1, wherein:

the sensitivity adjustment circuit includes a control circuit.

4. The apparatus for displaying changes in the resistance of a living body of claim 1, wherein:

the sensitivity adjusting circuit comprises a duplex potentiometer.

5. The apparatus for displaying changes in the resistance of a living body of claim 1, wherein:

the sensitivity adjustment circuit includes a voltage controlled operational amplifier.

6. The apparatus for displaying changes in the resistance of a living body of claim 1, wherein said resistance test circuit includes a manually adjustable potentiometer (82, 94):

the amplification circuit includes a correction circuit that automatically adjusts the gain of the amplification circuit in response to manual adjustment movement of the manually adjustable potentiometer.

7. The apparatus for displaying changes in resistance of a living body according to claim 6, wherein the correction circuit includes:

a feedback circuit coupled to the resistance test circuit and adapted to receive a signal representative of a test input;

a control circuit coupled to said feedback circuit and adapted to determine a compensation value using said test input signal;

a compensation circuit responsive to the control circuit for adjusting the gain of the amplification circuit by the compensation value to maintain a generally constant amplitude response.

8. The apparatus for testing and displaying changes in the resistance of a living body of claim 6, wherein the calibration circuit comprises a feedback circuit adapted to receive a signal representative of the total resistance of the living body.

9. The apparatus for testing and displaying changes in the resistance of a living body according to claim 8, wherein said correction circuit includes a control circuit connected to said feedback circuit and adapted to determine a compensation signal corresponding to a change in the gain of the amplification circuit from the test signal.

10. The apparatus for testing and displaying changes in the resistance of a living body of claim 9, wherein said correction circuit includes a compensation circuit adapted to receive said compensation signal and adjust said amplification circuit so as to maintain a generally constant amplitude response.

11. The apparatus for testing and displaying changes in resistance of a living body according to claim 7 or 9, wherein said fed circuit monitors a known state, and said correction circuit comprises:

a software program executed by the control circuit, the program comprising:

a method of reading in said known state signal from said feedback circuit;

a method of predicting and determining a response to an interference signature using signals representative of said known states;

a method of generating a response to the interference signature; and

a method of adjusting the compensation circuit to cancel the interference signature.

12. The apparatus for testing and displaying changes in the resistance of a living body according to claim 11, wherein said prediction and determination method includes a sleep mode.

13. The apparatus for testing and displaying changes in the resistance of a living body according to claim 11, wherein the prediction and determination method includes detecting the stability of the known state.

14. The apparatus for testing and displaying changes in the resistance of a living body according to claim 11, wherein:

the control circuit comprises an analog-digital converter;

the prediction and determination method includes reading in data generated by the analog-to-digital converter.

15. The device for displaying changes in the resistance of a living body of claim 1 comprising a plurality of manually controlled devices,

at least one conductive terminal extending from each of the resistance test circuit, the amplification circuit and the display circuit,

at least one inductor contained within said resistance test circuit and within said amplification circuit;

thereby reducing radio interference conducted via the circuit.

16. The apparatus for displaying changes in resistance of a living body according to claim 1, further comprising:

a housing surrounding the resistance test circuit, the amplification circuit, and the display circuit; and

paint covering the enclosure to isolate radio frequencies.

17. The device for displaying changes in the resistance of a living body of claim 6, wherein the device comprises a computer interface adapted to provide the simulated test signal.

18. The apparatus for displaying changes in resistance of a living body according to claim 6, wherein the amplifying circuit comprises an operational amplifier having a capacitor connected to the circuit between the positive and negative inputs of said operational amplifier.

19. The apparatus for displaying changes in the resistance of a living body according to claim 7, wherein the control circuit further comprises: a microcontroller adapted to receive a signal from the feedback circuit; and

an analog-to-digital converter adapted to identify discrete variations in a signal from the feedback circuit.

20. The apparatus for displaying changes in the resistance of a living body according to claim 7, wherein the control circuit further comprises: a trigger circuit adapted to trigger the control circuit upon a transition of the manually adjustable potentiometer.

21. The apparatus for displaying changes in the resistance of a living body according to claim 7, characterized in that the apparatus comprises:

a microcontroller within the control circuit adapted to receive a feedback signal from the feedback circuit; and

software executed by a computer adapted to configure the microcontroller and generate a correction signal in response to the feedback signal.

22. The apparatus for displaying changes in the resistance of a living body according to claim 21, characterized in that the apparatus comprises:

a compensation circuit including a digital potentiometer and adapted to provide a corrective input signal to the amplification circuit.

23. The apparatus for displaying changes in the resistance of a living body according to claim 6, characterized in that the apparatus comprises:

a microcontroller within the correction circuit; and

computer-implemented software adapted to configure the correction circuit continuously detects changes in the manually-adjusted potentiometer, determines and sets a resolution mode from a set of predetermined resolution modes.

24. In an apparatus for in vivo resistance change testing having a resistance testing circuit, a method for maintaining a generally constant amplitude response to a predetermined test input, comprising the steps of:

initializing the resistance test circuit and the amplifying circuit;

connecting the living body to the resistance test circuit;

determining the total resistance of the living body; the gain of the amplification circuit is adjusted according to a predetermined ratio to produce a generally constant magnitude response to the measured resistance change.

25. The method of claim 24, characterized in that the method comprises:

as part of determining the total resistance, a potentiometer is manually adjusted;

the resolution mode for determining the total resistance of the living body is set to one of a plurality of predetermined resolution modes.

26. The method of claim 25, characterized in that the method comprises:

the gain of the amplifying circuit is further adjusted by matching a predetermined compensation factor signal with a resistance change value of the total resistance of the living body corresponding to a change in the total resistance of the living body.