HK1011227B - Field programmable gate array with distributed ram - Google Patents

Description

Field programmable gate array with distributed RAM

Technical Field

The present invention relates to a programmable multi-function digital logic array integrated circuit of the type known as a Field Programmable Gate Array (FPGA), and more particularly to improvements in the structure of configurable logic cells of such FPGAs, as well as direct cell-to-cell connections and interconnection bus networks of such FPGAs, which design improves cell utilization and functionality for performing logic functions. The invention also relates to an FPGA including user accessible memory cells therein to integrate the storage capacity of some of the memory for use by the logic cells of the FPGA device.

Background

Digital logic may be implemented using several available integrated circuit configurations, including hard-wired Application Specific Integrated Circuits (ASICs), mask or fuse programmed Custom Gate Arrays (CGAs), Programmable Array Logic (PALs), Programmable Logic Arrays (PLAs), and other Programmable Logic Devices (PLDs) that are configured by the user, typically using non-volatile EPROM or EEPROM memory cell technology, and Field Programmable Gate Arrays (FPGAs) that typically use SRAM configuration bits set during each power-up of the chip. Of these various configurations, configurations having user programmable, erasable and reprogrammable capabilities are generally preferred over configurations that are fixed or programmable only once functions. FPGAs can implement large-scale high-complexity logic functions that do not require conversion to the two-level product sum form to program these devices. The SRAM controlled switch can not only be loaded with different functions to reconfigure the device very easily, but also optimized to operate at high speed.

A wide variety of FPGAs are now available, varying in the complexity of the component logic and the interconnect resources provided. As described in, for example, U.S. patent 4,706,216; 4,758,985, respectively; 4,758,985, respectively; 5,019,736, respectively; 5,144,166; 5,185,726, respectively; 5,231,588, respectively; 5,258,688, respectively; 5,296,759, respectively; 5,343,406, respectively; 5,349,250, respectively; 5,352,940, respectively; 5,408,434 and many other patents.

A typical FPGA architecture consists of a two-dimensional array or configurable matrix that can be selectively connected together using programmable interconnect structures to provide two direct connections between adjacent logic cells and the bus network and switches to distribute the connections between the cell rows and columns of the matrix. Near the perimeter of the matrix, a set of input/output terminals are connected to the bus network, the peripheral logic units, or both, to enable signals to be transferred to and from the chip. Each individual logic cell is programmed to implement a simpler logic function. Each logic cell typically includes input and output selection logic (MUX), combinatorial logic, one or more memory cells (flip-flop registers) for synchronous operation, and possibly one or more internal feedback lines for subsequent logic. The combinatorial logic of some FPGA cells is in the form of fixed function logic gates, which may have a configuration of selectable inputs. However, preferred FPGA cells use look-up table memory (configured SRAM) to provide a variety of logic functions. The memory cells of the lookup table store a set of data bits whose values correspond to the truth table for a particular function. A set of input signals present on the address lines of the memory cause the memory to provide a one-bit output that is the value stored at the address indicated by the input signals. Thus, the look-up table memory implements the function of true value determination stored within the memory. This interconnect structure provides a direct connection between each cell and the most adjacent cell on the same row or column of the matrix. U.S. patent No.5,296,759 additionally provides a unidirectional diagonal connection to adjacent cells. In addition to the direct cell-to-cell connection, there is a set of "logical" bus lines that connect between the cells and the bus network. Configurable switches (called repeaters) at regular intervals connect short local bus segments to the long dc-fast bus. Repeaters are typically aligned in rows and columns, dividing the entire array into cell blocks. One common arrangement is to organize groups of 64 logic cells into 8 x 8 blocks, each block having an associated set of local bus segments. Unlike the local bus portion, the fast bus passes through the repeater across more than one block of cells, passing signals between different blocks of cells. The express bus line accesses the logic unit only through the local bus portion to reduce propagation delay of signals on the express bus line.

FPGA designers continue to try to improve to provide speed and functional flexibility of the devices. For example, one design objective is to improve the functional capabilities of each logic cell while keeping the cell small and simple, which is a major feature of FPGA construction. Another aspect that needs improvement is the utilization of all the cells of the circuit. In particular, due to the number of tradeoffs and inefficiencies in bus networks and unit bus interfaces, FPGA units are often used only as "wiring units" to transfer signals between other units, providing right corners, staggered connections, and signal fanouts. Such signal routing inefficiently uses logic cells. The ideal routing should be provided only by direct connections and bus networks, while the logic unit is used only for logic. Moreover, because the power realized by the units is relatively simple, some designs provide units that are dedicated to performing specific functions, such as coding and fast forwarding operations. Unfortunately, if this particular function is not needed, the unit is wasted. The cell design itself helps to fully utilize the cells in the array. Preferably, the cells have a mirror image and are rotationally symmetric with respect to the function that can be achieved with their multiple inputs and outputs, to reduce the need for signal rotation and simplify the functional routing of the cell array. Finally, in most FPGAs, Random Access Memory (RAM) is required to be accessible to the user. Various manufacturers use different schemes to provide this required on-chip memory. For example, Altera corporation places RAM on the outer edge of the array, while Actel corporation places cross-stripes of logic cells and RAM. Xilinx corporation updates the look-up table memory within the logic cells by the user during device operation to change the functionality provided by these cells.

It is an object of the present invention to provide an FPGA that improves the functionality of logic cells, improves cell utilization, makes signal routing more efficient through bus networks and cell-to-cell direct connections, and integrates user accessible memory capabilities in the device.

Disclosure of Invention

This object is achieved by an FPGA matrix in which user accessible memory structures (or dedicated logic), i.e. memory structures and dedicated logic that can be considered "dedicated functional elements", are provided in the space formed at the corners of each block of logic cells at the row and column crossing points of the relay switch cells. One memory structure may be a random access memory, i.e., RAM, structure. The address and data lines of the RAM are connected to the bus as are the write enable and output enable control terminals of the RAM. The RAM may be single-ended or double-ended SRAM. Pairs of adjacent RAM columns may be addressed by the same set of buses. The storage structure may also be a non-volatile storage structure.

The object is also achieved by an FPGA matrix in which the trunk switch cells connected to local bus segments associated with logic cells are evenly spaced every N logic cells, thus dividing the cells into blocks of N x N cells, the cells in each block being connected only to the associated local bus segment group and not to a local bus segment associated with another block of cells. The repeater switch units connect each local bus segment to the express buses at opposite ends of the block, and the repeaters are arranged in a staggered configuration so that each express bus encounters the repeater unit less often than the local bus, e.g., every 2 · N logic units, and thereafter.

This object is also achieved by an FPGA in which the logic cell matrix has a first set of direct connections to the four nearest neighbouring logic cells within the same cell row and cell column and also has a second set of direct connections to other diagonally neighbouring logic cells.

The object is also achieved by an FPGA in which each logic cell comprises combinatorial logic in the form of pairs that can function as look-up tables, user accessible storage elements, or both. These structures are addressable by the same set of inputs, the outputs of which are selectively available to the same set of outputs, one of which has selective access to registers, and the inputs of another pair of cells can selectively output one or the other of the storage element outputs to effectively combine two storage elements into a larger overall addressable memory cell. The two storage element address inputs may receive an input selected from any of four direct connect inputs or local bus inputs.

Also, there may be many global clock signals per column of cells, which may have a polarity and enable selection based on the number of cell sectors in a column of cells. The global set or reset signal may also have a polarity and allow selection according to different sectors.

The I/O ports may be connected to a plurality of logic cells at the periphery of the cell matrix and may also be connected to a plurality of rows or columns of buses. Each peripheral logic unit and each row or column bus may be connected to any of several I/O ports. There may be additional I/O ports connected only to the bus.

Therefore, according to the above object of the present invention, the present invention provides a configurable logic integrated circuit, comprising:

a set of input and output terminals for receiving the input signal,

a plurality of non-dedicated programmable logic cells organized into blocks of cells having cells, in each block, communicating with each other along paths within the block, blocks communicating with each other along paths spanning more than one block, some or all of the paths being coupleable to the terminals, and

a plurality of dedicated functional elements disposed in spaces between the blocks, each dedicated functional element being associated with a block of cells and connectable to a path associated with the block, the dedicated functional elements including memory structures;

the paths form a bus network and are distributed along the rows and columns of the logic units;

the bus network comprises local bus groups within each block and a set of direct fast buses across the blocks, the local buses within any one group being connectable to each other and selectively connectable to logic units within the block associated with that group, the direct fast buses being selectively connectable to each other and to the local buses but not directly to any logic unit;

the bus network also includes a group of relay switch units spaced along the bus, and selectively connecting the direct-fast buses to each other and to the associated local buses, and causing the direct-fast buses connected thereto to cross over more than one block of logic cells;

the relay switch units are aligned in rows and columns along the boundaries between the blocks, thus leaving spaces at the corners of the blocks where the rows and columns of relay switch units cross, the dedicated functional elements being located in the spaces where the rows and columns of relay switch units cross.

Brief description of the drawings

FIG. 1 is a top plan view of the FPGA circuit of the present invention.

Fig. 2 is a top plan view of four logic cells of the FPGA circuit of fig. 1, showing direct connections between the cells.

Fig. 3 is a top plan view of four logic cells of the FPGA circuit of the present invention showing another embodiment of direct cell-to-cell connections.

Fig. 4 is a top plan view of a block of 4 x 4 logic cells of the FPGA circuit of fig. 1, with a bus network and RAM connected.

Fig. 5 is a logic circuit diagram of one logic cell block of the FPGA circuit of fig. 1.

Fig. 6 is a schematic circuit diagram of the unit-bus interface of the logic unit of fig. 5.

Fig. 7 and 8 are logic circuit diagrams of two logic cell embodiments of the FPGA circuit of the present invention.

Fig. 9 and 10 are partial plan views of the FPGA circuit of fig. 1 showing the clock and reset signal distribution of the present invention.

Fig. 11 is a top view of the four cell blocks of fig. 4, showing the staggered configuration of the relay switch cells of the FPGA circuit of the present invention.

Fig. 12 is a top plan view of a 3 x 3 set of cell blocks of the FPGA of fig. 1 and 4, showing the location of dedicated functional elements (DEF), such as RAM, at each block corner between relay rows and columns.

FIG. 13 is a logic circuit diagram of the RAM and RAM-bus interface of the FPGA circuit of the present invention.

Fig. 14 is a partial plan view of an FPGA circuit of the present invention having eight blocks of logic cells and their associated RAM blocks, showing an alternative RAM to bus network connection scheme as shown in fig. 4.

Fig. 15 is an enlarged view of a RAM block in the broken line 150 of fig. 14.

FIG. 16 is a partial schematic diagram of a set of logic cells on the perimeter of the FPGA circuit of FIG. 1, showing the connection of the cells to a set of I/O ports of the circuit.

FIG. 17 is a logic circuit diagram of an on-corner logic cell and cell-to-port interface of an FPGA according to one embodiment of the present invention.

FIG. 18 is a partial schematic diagram of a group of logic cells on the periphery of the FPGA circuit of FIG. 1, showing an alternative connection of such cells to the I/O terminals of the circuit shown in FIG. 16.

Fig. 19 is a logic circuit diagram of the connected unit-terminal interface shown in fig. 18.

Fig. 20 and 21 are logic circuit diagrams of two types of unit-port interfaces of I/O terminals according to a third connection embodiment.

Modes for carrying out the invention

Referring to fig. 1, a Field Programmable Gate Array (FPGA) integrated circuit of the present invention includes a matrix or two-dimensional array of programmable logic cells 11 having a plurality of rows and columns. Each of the individual logic cells 11 may be configured or programmed to implement a specific logic function. These cells are connected together, as shown in fig. 2 or 3, to connect adjacent cells in both directions, and, as shown in fig. 4, to connect the switches through a bus line network, allowing all FPGA devices or chips to implement more complex overall logic functions, the FPGA devices or chips being composed of many simple functions provided by each individual cell. Thus, in an FPGA device, the function need not be calculated as the sum of two products, since this interconnect structure makes it possible to feed the output of any logic cell to the input of any other logic cell. Thereby forming a chain of logic cells that can produce a function with multi-level logic.

The logic and fast bus lines of the bus network of fig. 11 and their pattern of connecting relay switches divide the basic array of logic cells into smaller blocks of rectilinear cells. The set of dashed lines seen in fig. 1 represents this partitioning arrangement, in which 16 groups of logic cells are organized into 4 x 4 square blocks of cells. Each block 15 has its own set of associated local bus segments dedicated to that particular group of logic cells, as will be seen below with reference to fig. 4 and 11, while the fast bus lines extend over more than 1 block to transfer signals between different logic blocks. While the circuit shown in fig. 1 has 32 rows and 32 columns of cells (1024 total logic cells), organized as an 8 x 8 matrix of 4 x 4 cell blocks, other devices may generally have as few as 16 rows and columns of cells or as many as 64 (or more) rows and columns of cells. The size of the blocks 15 of logic cells 11 need not be the same across the entire FPGA device. For example, different quadrants of the device may contain 4 × 4, 6 × 6, or 8 × 8 square blocks, or 4 × 6, 4 × 8,6 × 6, 6 × 12, or 8 × 16 rectangular blocks, etc.

The FPGA circuitry also has input/output (I/O) terminals 17 which are connected to the bus lines and logic cells along the periphery of the cell matrix to allow signal transmission into and out of the chip. The connection of the input/output terminals will be described in detail below with reference to fig. 16 to 21.

Fig. 2 shows the cell-to-cell direct connection of one embodiment of the circuit. Each logic cell 11 has each set of identical a outputs and a second set of identical B outputs. The A output end of any unit is connected to all four adjacent nearest logic units on the same row or column to serve as an output unit. Likewise, the B output of this cell is also connected to all four nearest neighbor cells. Each logic cell also has a set of A inputs (labeled A)_n，A_e，A_s，A_w) Receiving the signal output from each of the a outputs of the four nearest neighboring cells. Each logic cell has a set of B inputs (here labeled B)_n，B_e，B_s，B_w) And receives the signal output from each of the B outputs of the four nearest neighboring cells. Thus, between any two nearest neighboring cells on the same row or column, there are four connecting signal paths, two in each direction.

FIG. 3 shows a cell-to-cell direct connection of another embodiment of an FPGA circuit according to the present invention. In this embodiment, each cell 12 has a first set of identical A outputs and a second set of identical B outputs. The A output of any cell is connected to all four nearest-neighbor logic cells in the same row or column as the output cell, but the B output of that cell is connected to four diagonally-adjacent cells. Each logic cell also has a set of A inputs (labeled A)_n，A_e，A_s，A_w) Receiving as receiving units the signal output from each of the a outputs of the four nearest neighboring units on the same row or column, and a set of B inputs (here labeled as B)_nw，B_ne，B_se，B_sw) And receives the signal output from each of the B outputs of the four nearest neighboring cells. Thus, each logic cell is connected to all eight adjacent cells, and between any two cells, there are two connecting signal paths, one for each direction.

Fig. 4 shows the connection of the cells of the FPGA circuit to the bus. The 4 x 4 groups of logic cells 11 in a block have bus lines distributed between the rows and columns of cells. In particular, there may be five sets of three vertical bus lines 19 on each column adjacent to the logic cells and five sets of three horizontal bus lines 21 on each row adjacent to the logic cells. Each set of three bus lines comprises one local bus line 23 and two fast bus lines 25. The logic unit 11 is directly connected to only the local bus line 23, and the access to the fast bus line 25 is directly through the local bus line on the connection repeater unit 27, the connection repeater unit 27 being located at the periphery of each cell block. As explained below with reference to fig. 11, the repeaters 27 have staggered bus connections so that each fast bus line only intersects one repeater every 8 cells, rather than every four cells. Each logic cell 11 has 10 bidirectional data bus lines 29 connecting the logic cell to 5 horizontal local bus lines and 5 vertical local bus lines adjacent to each row and column of the cell within which the particular logic cell is located. These 10 bi-directional lines 29 (labeled V0-V4 and H0-H4 in FIG. 6) are connected to their respective logic cells in such a manner as will be described in more detail below with reference to FIG. 6 to provide a data signal path through which the cell inputs (A in FIGS. 5 and 6)_L、B_L、C_LAnd D_L) And the cell output (L in fig. 5 and 6) may communicate between the logic cell and the bus network.

Referring to FIG. 5, one embodiment of the logic cells within an FPGA of the present invention has four sets of inputs, including those labeled A (direct connection A from adjacent cells)_n，A_e，A_s，A_wAnd a local bus input A_L) The second group of targetsInput terminal of B (direct connection B from adjacent cell)_n，B_e，B_s，B_wAnd a local bus input B_L) Marked as C_LAnd a third local bus input terminal denoted by D_LTo the fourth local bus input. The logic cell also has three sets of outputs, including an a output and a B output connected to each of the a and B inputs of four adjacent cells, and a local bus output L. The a and B outputs and the direct a and B inputs are connected as described above with reference to fig. 2. The local bus input (A) of the unit is as described above with reference to FIG. 4_L、B_L、C_L、D_L) And the local bus output (L) is connected to ten adjacent horizontal and vertical local bus lines 23 (described in more detail in fig. 6) by connection signal paths 29. In particular, in FIG. 6, each local bus connection signal path (H0-H4 and V0-V4) passes through a respective pass gate 31 to five intermediate signal lines 33 within the cell₀-33₄One of them. Each intermediate signal line 33₀-33₄May be coupled to one of the two local buses by pass gates, connecting signal paths, one from the respective vertical bus (via paths V0-V4) and the other from the horizontal bus line (via paths H0-H4). Then, these five intermediate signal lines 33₀-33₄Is connected to four bus input selection multiplexers 35_A-35_DThe above. Thus, each multiplexer 35_A-35_DHaving five inputs, one for each intermediate signal line 33₀-33₄. Each multiplexer 35_A-35_DForms the four local bus inputs (A) of the unit_L、B_L、C_L、D_L). Thus, due to the configuration of pass gate 31 and multiplexer 35_A-35_DThe logic unit may be connected to any one of ten adjacent local buses to which the logic unit is connected, and may provide an input signal to any one of four local bus inputs. The local bus output L of the logic unit is further connected to five intermediate signal lines 33 via a set of pass gates 37₀-33₄The above. Thus, due to the configuration of pass gates 37 and 31, output L may be connected to provide an output signal to any one of the ten adjacent local bus lines. If desired, the two corresponding connection pass gates 31 are opened, and the output L can also be connected to both the horizontal bus lines and the vertical bus lines. Although, typically, one pass gate 37 selects one of the intermediate signal lines for the local bus output L, the other four intermediate signal lines 33 are routed through a multiplexer 35_A-35_DSelects (and closes the corresponding output pass gate 37) to receive the local bus input signal, but if an additional feedback path is required, the user can select to output pass gate 37 and input select multiplexer 35_A-35_DProviding a feedback path for a local bus output L to a local bus input A_L、B_LOr D_LOne of them. (As shown in FIG. 5, the internal cell structure has allowed the use of multiplexer 39 for C_LThe local bus input selects feedback. )

Returning to fig. 5, the internal logic of each logic cell may include two 8-bit look-up tables (l.u.t.)45 and 47, which are addressed by A, B and the C input. The look-up table is typically composed of static RAM memory cells that operate as read-only memory, i.e., loaded during initial configuration of the FPGA device, and not dynamically reprogrammed during operation. Group A input terminal (A)_n，A_e，A_s，A_w，A_L) Received by the multiplexer 41 and one of them is selected. Connecting the selected output of the A-multiplexer to a of the first L.U.T.45₀Address input and a of a second L.U.T.47₁And inputting an address. The B group inputs (B) are also selected by the B input selection multiplexer 43_n，B_e，B_s，B_w，B_L) And connecting the selected output to a of a second L.U.T.47₀Address input and a of first L.U.T.45₁And inputting an address. The third multiplexer 39 receives the local bus input C on the feedback line 40_LAnd internal feedback signals and outputs one of the signals to a of the first and second L.U.T.45 and 47₂And inputting an address. Local unit looks for using two 8 bitsTables 45 and 47 to provide various combinational logic. The SRAM cells of both l.u.t.45 and 47 store a set of data bits whose values correspond to a truth table for a particular logic function. When a set of input signals appears at three address inputs (a) at each l.u.t₀-a₂) Both tables read the respective bit values stored at the addresses indicated by these input signals. Thus, each l.u.t.45 and 47 represents a one-bit output signal of a particular function of the set of inputs on its respective output 49 and 51, wherein the function implemented by the memory is determined by the stored true value.

Outputs 49 and 51 of look-up tables 45 and 47 are split into multiple signal paths and directed to units a and B and local bus output L. In particular, l.u.t. outputs 49 and 51 are connected to respective data lines 52 and 53, and the respective data lines 52 and 53 may be coupled by respective first and second output multiplexers 54 and 55 to output lines 56 and 57 to provide output signals to the respective a and B outputs. The l.u.t. outputs 49 and 51 are also connected to respective second data lines 59 and 60 leading to a third output multiplexer 61. The control signal of the multiplexer 61 is input D from the local bus_LOr from a fixed logic level signal ("0" or "1") selected by multiplexer 62. When the logic "0" signal is selected the third output multiplexer 61 transmits the output of the first look-up table 45 received via the second data line 59 to its output 63, but when the logic "1" signal is selected the third output multiplexer 61 transmits the output of the second look-up table 47 received via the further second data line 60 to its output 63. When local bus input D is selected_LThe control of the third output multiplexer 61 is dynamic. In effect, the two 8-bit lookup tables 45 and 47 together function as a 16-bit lookup table in which the local bus input D is input_LUsed as a fourth address input to access the desired data bits stored in the combined look-up table. The selected third multiplexed output 63 is split into two parallel paths, one being a combined or non-registered path 65 and the other being a registered path containing a flip-flop 66. A fourth output multiplexer 67 connects one of these two paths to its output 69. The fourth multiplexer output 69 is also split into several parallel pathsA path. One of these paths 70 is connected to a first output multiplexer 54 which may be selected for coupling to the a output of the cell and the other of these paths 71 is connected to a second output multiplexer 55 which may be selected for coupling to the B output of the cell. The third path is coupled to an output line 75 via an output buffer 73 to provide an output signal to the local bus output L of the unit. The output buffer 73 may be a tri-state buffer controlled by an enable signal provided by a further multiplexer 74. Alternatives include a logic "1" signal always asserted by the buffer 73 and two dynamic output enable signals OE received from the dedicated bus lines_HAnd OE_V. The fourth path of the fourth multiplexer output 69 is the feedback path 40, connected to the local bus input C_LTo a possibly selected input multiplexer 39.

This cell structure provides it with significant flexibility while maintaining a relatively simple structure and small volume. The a and B input multiplexers 41 and 43 are fully symmetric with the four nearest neighbor cells. Likewise, the local bus input circuit of fig. 6 provides the exact same option for local bus connections for all ten units. At the output of the unit, the a and B outputs are provided with matching options. The output of the first lookup table 45 may be set for the a output, either unregistered via the direct signal line 52 or registered via the second signal line 59 and the register 66 and signal line 70. Alternatively, it is supplied with the output of the second lookup table 47 registered or unregistered via the second signal line 60 and the signal line 70. Or when the multiplexer 62 selects the local bus input D_LAs a fourth address input, an output may be provided as a registered or unregistered combination of 16-bit l.u.t. Likewise, the B output may be provided with the output of the second lookup table 47, the first lookup table 45, or a combined 16-bit lookup table, either data of which may or may not be registered. The same entries may be used for the local bus outputs L of the units.

In addition to symmetric and flexible input and output options, the cell structure also results in faster throughput from input to direct cell to cell output of the cell. Due to the simple structure of the unit, soThere may be as few as three circuit elements between the input and output of the cell. In particular, A, B, C and the D input signal arrive at address input a₀、a₁、a₂Or through only one of the selection circuits, i.e. one of the multiplexers 41, 43, 39 and 62, before centrally controlling the control input of the multiplexer 61 for accessing the data bits stored in the look-up tables 45 and 47. Also, on the output side of the look-up tables 45 and 47, the signals provided by the look-up table output lines 49 and 51 may pass through only one multiplexer 54 or 55 to reach the A or B output of the cell.

Fig. 7 shows another logic cell according to the invention. The cell includes a set of input multiplexers 41 ', 43', 39 'and 62' to receive and select A, B, C and the D input. As shown in FIG. 5, the A input includes a direct cell-to-cell input A from the nearest neighbor logic cell in the same row or column as the above-described cell_n，A_e，A_sAnd A_wAnd also a logic bus input A_L. The B input may also be the same as that shown in FIG. 5, or alternatively, except for the local bus input B_LIn addition to cell-to-cell inputs B that may include diagonally adjacent logic cells_nw，B_ne，B_seAnd B_sw. Thus, the B input may correspond to the cell-to-cell connection shown in fig. 3. Input multiplexer 39' selects local bus input C_LOr a logic "1" signal. Its output 42 'is connected to one input of an and gate 44'. Multiplexer 38 'selects the feedback signal on feedback line 34', logic bus input D_LOr a logic "1" signal and places the selected signal on its output 40 'to the other input of and gate 44'. Thus, AND gate 44' can input the local bus into C_LOr D_LOr feedback signals are transmitted to its output 46', or the local bus inputs C may be logically combined (and)_LAnd D_L(or input C)_LCombined with the feedback signal) to form a logical product of the two inputs. The cell with and gate 44' provides the possibility of implementing an array multiplexer of one element within a single cell. As shown in fig. 5, the selected input is processedThe outputs of the in-multiplexers 41 ' and 43 ' are connected to two address inputs a of two 8-bit lookup tables 45 ' and 47₀And a₁. The output 46 ' of the AND gate 44 ' is connected to the third address input a of the look-up tables 45 ' and 47₂。

As shown in fig. 5, the outputs of the look-up tables 45 'and 47' are connected to the respective a and B outputs of the logic cells via the outputs of the multiplexers 54 'and 55'. Tables 45 'and 47' are also connected to local bus input D, controlled by a fixed "0" or "1" control signal, or selected by yet another multiplexer 62_LOn the controlled third multiplexer 61'. When the local bus input D is selected, as previously described_LTwo lookup tables 45 'and 47' are associated with local bus input D as a fourth address input_LEffectively combined into a single 16-bit table. The output of the selected third multiplexer 61 'is connected to a register/non-register circuit consisting of a non-register signal path 65', a flip-flop register 66 'in the register signal path and a multiplexer 67' selecting one of the two signal paths. The resulting output 69 'is connected to the a and B outputs of the unit via multiplexers 54' and 55 'and to the local bus output L of the unit via an output buffer 73'. Further, the output buffer 73 'may be a tri-state buffer in response to the output enable signal selected by the multiplexer 74'. Fig. 7 also shows that the output buffer circuit 73 'may also include output polarity control through yet another multiplexer 72'.

Referring to fig. 8, another logic cell according to the present invention uses two 8 x 1 static RAMs that are writable during device operation by providing write permission from the bus network and data access to the cell. This may use the cell as on-chip memory or alternatively may implement logical functions performed by a preloaded and fixed look-up table that changes dynamically during operation, for example by the device itself as a result of some functions performed by other cells within the FPGA device. In this embodiment, input multiplexers 44 ", 43", and 39 "are connected to A, B and the C direct and local bus inputs and feedback line 40", also as shown in FIG. 5Connected to the address inputs a of the SRAMs 45 'and 47' in the same manner₀、a₁And a₂. Outputs 49 "and 51" of SRAMs 45 "and 47" are split into unregistered paths 64 "and 65" and registered paths containing flip-flops 66 "and 68", which are coupled to output multiplexers 54 "and 55", respectively. The outputs of multiplexers 54 "and 55" are connected along signal paths 56 "and 57" to the cell-to-cell direct A and B outputs of the logic cells, and are also connected along second signal paths 59 "and 60" to a local bus output selection multiplexer 61 "controlled by the signal selected by multiplexer 62". The selection includes a fixed low level ("0") and a logic high level ("1") and a dynamic local bus input D derived from the horizontal and vertical local buses, respectively_HAnd D_V. If dynamic local bus input D is selected_HOr D_VTo control the output multiplexer 61 "and efficiently use this input as the fourth address input to the combined 16-bit SRAM consisting of the two 8-bit SRAMs 45" and 47 ". The output multiplexer 61 "selected output 69" is connected to the feedback line 40 ", to the input multiplexer 39" and also to the local bus L via the buffer 73 ". As previously described, the register 73 "may have a local bus OE through a multiplexer 74 ″_HOr OE_VThe output from the controller allows control. On the other hand, the circuitry between SRAM outputs 49 "and 51" and the address A and B outputs and local bus output L may be the same as shown in FIG. 5.

Through data inputs d connected to the FPGA bus network and 47 'of two SRAMs 45'₀DATA _ IN line 84' and address input a₀-a₂And write access unique to the present embodiment cell to the SRAMs 45 "and 47" is provided by a write circuit that provides a write enable signal WE to one of the SRAMs 45 "and 47". The write enable circuit includes two AND gates 76 'and 77' each having three inputs 78 '80' and an output, the write enable input being coupled to one of the SRAMs 45 'and 47'. One of the and gate inputs 78 "receives the control signal selected by the same multiplexer 62" as the local bus output multiplexer 61 ". I.e. input78' selectively receives either a fixed logic low ("0") or high ("1") level, or a dynamic local bus input signal D_HOr D_V. The input 78 "is inverted before reaching the and gate 76" and not inverted before reaching the further and gate 77 ". Thus, at some point, only one of SRAMs 45 "and 47" will receive the write signal. If input 78 "is at a low logic level, the left SRAM 45" will be enabled, and if input 78 "is at a high logic level, the right SRAM 47" will be enabled. The same control signal of the local bus output multiplexer 61 "can be used to ensure that the data written from the data input line 84" is verified on the local bus output L. The second and gate input 79 "provides an inverted CLOCK (CLOCK) signal to the and gates 76" and 77 "to ensure that the input data to be written has been properly established on the data input line 84" before the write enable signal WE is passed to the selected SRAM45 "and 47". The third and gate input 80 "provides the write enable signal WE itself through the multiplexer 82" which enables the write operation selectively inhibited by the logic cell (by the fixed logic low input "0").

Referring to fig. 9 and 10, the flip-flop registers (or registers) 66, 66', 66 ", and 68" within each cell (fig. 5, 6, and 8, respectively) receive a clock input and a reset (or set) input. FIG. 9 shows the clock distribution circuitry of the FPGA of the present invention. There may be multiple global clock lines CK0-CK7 to provide clock signals that differ from each other in frequency, phase, or both. Other possible clock distribution structures may include some other clock lines, portions of global multiplexer 88, etc. Each column of logic cells 11 may be provided with its own clock selection multiplexer 88, the inputs of which multiplexer 88 are connected to part or all of the global clock lines CK0-CK7, respectively. Thus, each column of logic cells 11 may be provided with a different clock signal than the other columns of logic cells 11. The output of each clock select multiplexer 88 forms the main column line 92 which distributes the selected clock signal to each cell within that column. A column of logical cells may be subdivided into 4 or 8 sectors, typically N cells each. In fig. 9, it can be seen that the sector 14 is composed of 4 cells. For each sector of the cell, branching off the main column line 92, a clock polarity selection and distribution enable circuit 94 is provided. The circuit 94 includes a first multiplexer 106 having one input connected to the main column line 92 for receiving a clock signal and another input receiving a fixed logic high ("1") signal. If the multiplexer 106 selects a clock signal, this signal is distributed to the corresponding sector 14 of the unit 11, but if the fixed signal is selected, no clock signal is supplied to this sector 14. Circuit 94 also includes bifurcated signal paths (105 and 107) coupled to a second multiplexer 108. One input of the second multiplexer comes directly from the output 105 of the first multiplexer 106, while the other input first passes through an inverter 107. The second multiplexer 108 enables the polarity of the clock signal to select the corresponding sector, and thus enables other sectors in the same column of the logic unit 11 to receive clock signals of opposite polarity. Finally, some sectors of cells may alternately receive the direct A outputs 110 of cells within adjacent sectors of the same column, rather than the uppermost group of sectors closest to global clock lines CK0-CK 7.

In fig. 10, the RESET (RESET) signal provided by global RESET (RESET) line 114 to RESET column line 115 may likewise have its polarity determined by the sectors of the logic cells by RESET polarity selection and distribution enable circuit 116, which is constructed in the same manner as clock circuit 94.

Referring to fig. 11, the logic units 11 are organized as 4 x 4 blocks of cells 15, on the boundaries 13 of which there is arranged a set of connection switches of the bus network, called "repeaters" 27. As previously described, the bus network comprises a set of horizontal buses 21 running between rows of logic cells 11 and a set of vertical buses 19 running between columns of logic cells 11. Each set of buses 19 or 21 includes a local bus 23 limited to one block 15 of cells and two fast buses 25 extending through multiple blocks of cells through repeaters 27. For simplicity, only one set of three buses 23 and 25 is shown for each row and column of cells. However, as also previously mentioned, there are typically five sets of three buses 19 and 21 for each row and column of cells, as seen in FIG. 4. A repeater 27 may connect the local bus 23 to the express bus 25. The local bus is only directly connected to the local unit 11. The repeaters 27 have a staggered configuration in which any one repeater 27 provides a selectable connection between the local bus 23 and only one of the two express buses 25 in the group, with the following repeater 27 being connected to another express bus in the group. Thus, each fast bus 25 encounters a repeater 27 every 8 rows or columns of cells 11, rather than every 4 rows or columns, and each local bus 23 encounters a repeater 27 every 4 rows or columns of cells 11. Each local bus 23 within a block 15 of a unit 11 is connected to its respective one of the fast direct buses 25 on opposite ends of the block 15. One convenient way to route repeaters 27 to achieve the desired staggered configuration is to have all rows or columns of repeaters 27 connected to matching buses within each group of three buses (e.g., all connected to the leftmost or uppermost bus), have subsequent rows or columns of repeaters 27, have four remote logic units, etc., connected to opposing matching buses within the group (e.g., all connected to the rightmost or bottommost bus), etc. Fig. 11 also shows that additional switches 81 may be provided where the rows and columns of the bus intersect to turn the signal 90 degrees between the rows and columns of the bus. These switches 81 connect the local bus to other local buses and the express bus to other express buses.

Referring to fig. 12, at the corners of each block 15 of logic cells 11, in space at the intersection of the rows and columns of repeaters 27 at the boundaries of block 15, is a dedicated functional element 83(DFE) which may be a memory structure such as a Random Access Memory (RAM) block or other dedicated or special circuitry such as multiplexers, shift registers, fixed function digital or analog logic, microcontrollers, comparators, and analog-to-digital or digital-to-analog converters, etc. Since the space in the corners is created by the block structure of cells and their associated buses and repeaters, the memory specific logic within that space can be arranged to consume less or no silicon area of the entire device.

Each dedicated functional element 83 may be a block of RAM or other memoryThe memory structure (e.g., non-volatile memory), as shown in fig. 4 and 13, is organized into 32 4-bit data words, totaling 128 bits per block. Referring to FIG. 13, each RAM block 83 may contain an SRAM85 having five synchronous address inputs a₀-a₄Receiving address lines 86 through a set of toggle registers 87₀-86₄And four bidirectional data terminals d₀-d₃. Data terminal d₀-d₃Is connected to each data line 89₀-89₃Each data line is in turn connected to a pair of input and output buffers 90 and 91. The input buffer 90 is connected to a data line 95 through a flip-flop 93₀-95₃The above. The output buffer 91 is directly connected to the data line 95₀-95₃The above. The write enable signal WE is received from the write enable line 96 through the flip-flop register 97. The register output Q of flip-flop 97 is connected via a first branch to the write enable input of SRAM85, via a second branch 99 via branches 99 on each side₀-99₃Connected to each data terminal d₀-d₃The tri-state control input of input buffer 90. An output enable signal 0E is also received from the output enable line 102 through the flip-flop register 103. The output 104 of the register 103 is connected to a first input of the and gate 101 and the third branch 100 of the output of the toggle register 97 is connected to a second, complementary input of the and gate 101. The output 105 of the AND gate 101 passes through each side branch 105₀-105₃Connected to each data terminal d₀-d₃The tri-state control input of the output buffer 91.

Therefore, to write data into SRAM85, a 5-bit address is synchronously received from the output of register 87 on address terminals 90-94, and a write enable signal is also synchronously received from toggle register 97 via first branch 98 on write enable terminal WE of SRAM 85. The write enable signal can also pass through the side branch 99₀-99₃Allowing input buffer 90 to pass through AND gate 101 and side branch 105₀-105₃The output buffer 91 is disabled. Thus, at the data line 95₀-95₃The data bits received on pass through an input buffer 90 and data lines 89₀-89₃To each data terminal d₀-d₃And at the address terminal a₀-a₄The received address port is written to SRAM 85. To read the stored data from the SRAM85, at address terminal a₀-a₄And an and gate 101 synchronously receives the address and output enable signal OE through registers 87 and 103, respectively. The write enable signal WE transmitted from the register 97 is at low level and passes through the branch line 99₀-99₃Disable input buffer 90 via branch line 105₀-105₃The output buffer 91 is allowed. Passing the data stored at the received address through the data terminal d₀-d₃Output to the data line 95₀-95₃. On the other hand, the RAM block 83 may be appropriately modified so that the write enable and output enable signals are active low.

Returning to fig. 4, the RAM block 83 of fig. 13 may be connected to a bus network such that each of the five address lines 86 is connected to a different one of the five vertical local buses 23 corresponding to a column of cells 11, the write enable and output enable lines 96 and 102 are connected to two vertical fast buses 25 corresponding to the same column of cells, and each of the four data lines 95 is connected to a different horizontal local bus corresponding to each of the four rows of cells in the 4 x 4 cell group adjacent to the RAM block 83. Other attachment methods may also be employed.

On the other hand, instead of the structures shown in fig. 4 and 13, the RAM block 83 may be connected to the bus network in the manner shown in fig. 14 and 15. Fig. 14 shows eight 4 x 4 blocks 15 of logic cells 11 and some vertical and horizontal fast bus lines 19 and 21 running between cells 11 and between blocks 15. The rotary switch 81 connects the selected vertical and horizontal buses 19 and 21 to each other where they cross. In the lower right hand corner of each block 15 of the logical unit 11 is a RAM block 83. As shown in FIG. 15, each RAM block 83 may be a dual-ended SRAM having a write enable terminal WE and a write address terminal A_inAnd a data input terminal D_inTo write to SRAM, and has read enable terminal OE and separate read address terminal A_outAnd a separate data output D_outTo read data from the SRAM. Thus, read and write operations can be performed independentlyEven simultaneously on separate address and data lines.

Returning to fig. 14, a 6-bit write address corresponding to a set of locations within RAM to which 8 data bits are to be written is received from an external end of the bus network or device (WRITE ADDR.). Two of the six bits are input to a conventional 2-to-4-bit decoder 171. The decoder 171 activates one, and only one, of its four outputs 173 depending on some of the four possible two-bit input values it receives. Each of the four decoder outputs 173 is connected to one input of one of the four or gates 175. A global write enable signal WE is received on the other input of the four or gates 175. Or gate output 177 is connected to the vertical fast bus 19 corresponding to each of the four columns in block 15 and to the column on RAM block 83 to which they correspond. The write enable terminals WE of these RAM blocks are connected to these particular vertical fast buses to receive the decoded write enable signals from the corresponding or gate outputs 177. Thus, for any combination of two write address bits, if the global write enable signal WE is activated, one of the four columns of the RAM block 83 will be activated. The other four write addresses of the 6-bit addresses are connected to the horizontal fast bus 21 and then to the vertical bus 19 via the transfer switch 81, and these buses 19 are connected to the write address terminal a of each RAM block 83_in. 8 data input lines D_in(0)-D_in(7) Connected to the data input D of the RAM block 83 by a horizontal bus 19 adjacent to each row of logic cells 11_inAbove, each RAM block 83 is driven from D_in(0)-D_in(3) Or D_in(4)-D_in(7) Four parallel data input signals are received. Thus, two rows of RAM blocks are required to write a write signal byte of data to any given address.

Similarly, for a read operation, a 6-bit read address (READ ADDRESS) is provided with two address bits connected to another 2-to-4-bit decoder 172 providing four outputs 174, and the remaining four address bits connected through the horizontal fast bus 21 and the switch 81 to the vertical fast bus 19 for connection to the read address side of the RAM block. Furthermore, all 8 RAM blocks are provided with fourAddress bits, but only a column of RAM blocks is provided with a read enable signal derived from two address bits input to decoder 172. 8 data output lines D_out(0)-D_out(7) Connected to the data output terminals D in the two-row RAM block 83 by a horizontal fast bus_out。

A useful structure is the read and write address terminals A in adjacent columns of the RAM block 83_inAnd A_outProviding mirror symmetry therebetween. When a dual-ended RAM element is constructed, the vertical bus resources required for approximately half the address signals are reduced. Note that in fig. 14, the first two columns of RAM blocks share the same read address line 176. Likewise, the last two columns of RAM blocks share the same read address line 178. The second and third column RAM blocks share the same write address line 179. In memory blocks having larger groups, such as memory blocks having 8 or 16 columns of RAM blocks and 3 to 8 or 4 to 16 bit decoders, the vertical bus resources are used to use the read address lines of one column of logic blocks 15 as write address lines for the next column of logic blocks 15.

The dedicated functional elements at each corner of the logic cell may also be specific logic structures, such as multiplexers. For example, a 4 x 4 multiplexer can be connected to the bus network in the same manner as a double ended SRAM as seen in fig. 14 and 15, with one set of address inputs being replaced by one four bit operand and the other set of address inputs being replaced by every second four bit operand. The 8-bit product output of the multiplexer replaces the two four-bit data on the RAM data output line.

Referring to fig. 16, the logic cells 11 on the edge of the array can be connected to input/output (I/O) terminals 17 in any of a variety of ways. One method shown herein connects each logic cell, e.g., cell 112, to three adjacent I/O terminals 117 and 119 via I/O lines 121 and 123, and also connects each I/O terminal, e.g., terminal 118, to three adjacent logic cells 111 and 113 via I/O lines 122, 124 and 125. This approach is usually an exception at the corners of the array and at the end points of the port lines. Thus, port 131 of the endpoint is connected to only two logic units 134 and 135 via I/O lines 132 and 133. The logic cell 135 at the corner is connected to four I/O ports, i.e., ports 130 and 131 on one line of I/O ports and ports 139 and 140 on another line of ports, by I/O lines 132 and 136 and 138. Other configurations are possible.

Fig. 17 shows the connection at the corner in detail. The connections to the other logic units and the I/O ports are similar. The particular logic cell 135 seen in fig. 17 is the bottom right corner cell of the array, i.e., the bottom row and right column of cells of fig. 1. As shown in fig. 16, the specific unit 135 is connected to two rightmost I/O ports 139 and 140 in the rightmost row of ports and also to two rightmost I/O ports 130 and 131 in the rightmost row of ports of the circuit. The cell 135 of fig. 17 is connected to a set of adjacent vertical and horizontal buses 19 and 21, as are all other cells in the array, either directly to the local bus 23 or indirectly to the fast bus 25 through the local bus 23 and the repeatable switch 27. As shown in fig. 4 and 6, the connection between the unit 135 and the 5 horizontal and 5 vertical local buses 23 may be implemented by a set of bidirectional data buses 29. The cells 135 at the corners are also directly connected to the nearest neighbor cells (not shown) as shown in fig. 2. However, since there is no adjacent cell to the right and below of cell 135, the four unused A and B are input directly (A)_E，B_E，A_SAnd B_S) And four unused a and B direct outputs (two a 'and two B') for convenient connection to I/O ports and to some express bus 25.

In particular, each of the 5 lines 25 that do not intersect the end relay unit 27 is connected to a pair of 5-to-1 multiplexers 141 and 143 and a pair of five-cell switch banks 145 and 147. Likewise, 5 vertical straight lines 25 that do not intersect the end relay unit 27 at the end of the bus column are connected to multiplexers 142 and 144 and switch banks 146 and 148. The outputs of multiplexers 141 and 142 are connected to respective direct B inputs B_EAnd B_SAnd also to output signal paths 153 and 154 for connection to I/O ports. The outputs of multiplexers 143 and 144 are connected only to output signal paths 155 and 156 for connection to the I/O ports. Switch groups 145 and 146 connect the direct B output of unit 135 to the unsharedThe repeater 27 ends on 10 horizontal and vertical express lines 25. Switch groups 147 and 148 connect input signal paths 169 and 170 of the I/O ports to the same 10 horizontal and vertical express lines 25. Input signal paths 169 and 170 are also connected to respective direct A inputs A of cell 135_EAnd A_S。

The right input signal paths 151, 153 and 155 all enter the two lowermost terminals 130 and 131 on the port line on the right in fig. 16 and the port 139 on the rightmost port line on the bottom. Bottom output signal paths 152,154, and 156 all go to the rightmost two ends 139 and 140 on the lower port line in fig. 16 and the bottommost port 131 on the right port line. Thus, each of the input signal paths 151-156 can be selectively connected to any one of three different ports using four available port connections. Signal paths 155 and 156 may also be used to provide tri-state enable signals to output buffers between paths 151 and 154 and the I/O ports. Input signal paths 169 and 170 may likewise be connected to I/O ports. Leads 161, 163 and 165 are connected to respective ports 130, 131 and 139 seen in fig. 16, while leads 162, 164 and 166 are connected to respective ports 131, 139 and 140 seen in fig. 16. Input select multiplexers 167 and 168 both connect selected wires 161-166 to input signal paths 169 and 170.

Referring to fig. 18 and 19, the number of I/O ports is increased from one port 17 per peripheral logic unit 11 of fig. 16 to three ports 17' per pair of peripheral logic units 12 shown in fig. 18 and 19, or even up to 2 ports per peripheral logic unit, if desired. In FIG. 18, the I/O ports 180, 181, 183, 184, etc. directly facing the non-upper peripheral logic units 187-190 may be connected to the three peripheral logic units and their associated buses as shown in FIG. 16. For example, I/O port 181 may connect a peripheral logic unit 187-189 to an associated bus as will be seen below with reference to FIG. 19. In addition to the I/O ports 182, 185, etc., as shown in fig. 19, the spaces not directly facing the peripheral logic units but respectively disposed with respect to the spaces between the logic units 188 and 189 and the logic units 190 and 191 are indirectly connected to the two nearest peripheral logic units through their associated buses. Similarly, peripheral logic units 187-190, etc. at each non-corner may be connected to four I/O ports. For example, the unit 188 may be connected to the I/O port 180-183. The cells 191 at the corners, etc., are connected to the six I/O ports 184-186 and 192-194, three from each port line.

As shown in FIG. 19, the I/O port 181 is connected to the input buffer 201, and the output 202 thereof is divided into three input lines 203-205 connected to the direct cell inputs 206-208 of the logic cells 187-189. The output 202 of the buffer is also connected through programmable switch 209 to bidirectional signal lines 210 and 212 for connection to relay switch unit 27 at the end of the horizontal bus associated with each column of the three-column logic cells comprising cells 187 and 189. Associated with I/O port 181 is an output multiplexer 213. The multiplexer 213 is connected to the bi-directional signal lines 210-212 from the three rows of horizontal buses 21 associated with the logic cells 187-189 and also to the cell output lines 214-216 from the direct cell outputs 217-219 of the logic cells 187-189. Each of these signal lines 210 and 217 and 219 is connected to an input of a multiplexer 213 that selects at most one of them for transmission to the I/O port 181 through an output buffer 220. The I/O ports 180 and 183, which directly face the units 187 and 189, are connected in the same manner as the I/O port 181.

Additional I/O ports 182 are located between I/O ports 181 and 183. When the I/O ports 181 and 183 are arranged to directly face the peripheral logic units 188 and 189, the port 182 does not face either logic unit, but is instead arranged to face the space between the rows associated with the units 188 and 189 and containing the horizontal bus 21 associated with the unit 189. The I/O port 182 is coupled to an input buffer 221 whose output may be coupled to bidirectional signal lines 223 and 224 through a programmable switch 222. These signal lines 223 and 224 are also coupled through an output multiplexer to an output buffer 226, which is connected to the I/O port 182. Bidirectional signal lines 223 and 224 are connected to signal line 210, with signal line 210 connected to and from the end relay switches of horizontal bus 21 associated with units 188 and 189.

Referring to fig. 20 and 21, a further embodiment of the input/output interface of the FPGA of the present invention is shown for two I/O ports 230 and 231. To allow easy viewing of the multipath signal paths, fig. 20 shows only the paths associated with one I/O port 231 directly facing the logic unit 228. The figure is repeated on each cell 227, 228, 229, etc. around the perimeter of the cell matrix of the FPGA device. Also, FIG. 21 shows only the paths associated with one I/O port 230 disposed to face the location between two logic units 227 and 228. This figure is also repeated around the perimeter of the FPGA, although typically these second I/O ports 230 are only present at every other available location between cells. As can be seen from the second I/O interface embodiment of fig. 19, both types of I/O ports, i.e. the port directly facing the logic cell and the port between the facing cells, are typically found in FPGAs.

As seen in fig. 20 and 21, I/O ports 231 and 230 have pull-up transistors 232 and 252 whose gates are controlled (pulled-up) by user-configurable bits. The main function of these transistors 232 and 252 is to provide a logic "1" to the unused port. When transistor 232 or 252 is on, it is coupled to power supply V_CCTo about 10K of resistors. Each port 231 and 230 has an input buffer 234 and 254, respectively, connected thereto and an output buffer 233 and 253, respectively, also connected thereto. Input buffers 234 and 254 have selectable threshold levels, TTL or CMOS, which are determined by user configurable bits (TTL/CMOS). Output buffers 233 and 253 have selectable DRIVE levels, controlled by another user configurable bit (HALF/FULL DRIVE). The drive levels differ in their dc current sinking capabilities. On the other hand, each buffer has a controllable slew rate, either fast or slow, with the same full dc current sinking capability. For outputs where speed is not a critical issue, half-drive or slow rotation rates (one of which reduces noise and ground vibration) are recommended. The "open collector" configuration bit may selectively enable or disable active pullup of output buffer 233 or 253. Multiplexers 235 and 255 select the enable signal (TRI-STATE) of TRI-STATE output buffers 233 and 253 from a plurality of options. These optionsAn entry typically includes fixed logic levels "0" and "1" that the buffer is either always driven or never driven, as well as a number of dynamic signals generated in the array. The primary I/O port 231 directly facing the peripheral logic CELL 228 has three dynamic signal selections (CELL1, CELL2, CELL3) associated with the three available output CELLs 227, 228, and 229, while the secondary I/O port 230 located in a intercell location has two dynamic signal selections (CELL1, CELL2) associated with its two available output CELLs 227 and 228. The dynamic signal may be generated within the units themselves or may be provided by the bus 247, 248 or 249 associated with the units.

Referring now only to FIG. 20, I/O port 231 is connected by lines 241-244 to buses 247, 248 and 249 associated with three adjacent peripheral logic CELLs 227, 228 and 229 (labeled CELL1, CELL2 and CELL3, respectively) through output select multiplexer 237 and output buffer 233. Note that two signal options are available from bus 248 associated with unit 228 facing port 231, while only one signal option is available from adjacent buses 247 and 249. The output selection multiplexer 237 also receives a direct cell output 245 from the logic cell 228. The I/O port 231 is coupled to the direct cell input 250 through the input buffer 234, coupled to the logic cell 228, and coupled to the same line group 241-244 through the user configurable switch 251 to be coupled to the buses 247-249.

Referring now to fig. 21, a port 230 disposed to face a location between cells 227 and 228 is connected by lines 261 and 262 to buses 247 and 248 associated with cells 227 and 228 through an output selection multiplexer 257 and an output buffer 253. Multiplexer 257 also receives direct diagonal cell outputs 263 and 264 from cells 227 and 228. The I/O port 230 is connected to the direct diagonal unit inputs 265 and 266 of the units 227 and 228 via the input buffer 254 and to the lines 261 and 262 via the user configurable switch 267 for connection to the buses 247 and 248.

The FPGA device may also use various other I/O interface configurations as shown in fig. 16-21.

Claims (26)

1. A configurable logic integrated circuit, comprising:

a set of input and output terminals for receiving the input signal,

a plurality of non-dedicated programmable logic cells organized into blocks of cells having cells, in each block, communicating with each other along paths within the block, blocks communicating with each other along paths spanning more than one block, some or all of the paths being coupleable to the terminals, and

a plurality of dedicated functional elements disposed in spaces between the blocks, each dedicated functional element being associated with a block of cells and connectable to a path associated with the block, the dedicated functional elements including memory structures;

the paths form a bus network and are distributed along the rows and columns of the logic units;

the bus network comprises local bus groups within each block and a set of direct fast buses across the blocks, the local buses within any one group being connectable to each other and selectively connectable to logic units within the block associated with that group, the direct fast buses being selectively connectable to each other and to the local buses but not directly to any logic unit;

the bus network also includes a group of relay switch units spaced along the bus, and selectively connecting the direct-fast buses to each other and to the associated local buses, and causing the direct-fast buses connected thereto to cross over more than one block of logic cells;

the relay switch units are aligned in rows and columns along the boundaries between the blocks, thus leaving spaces at the corners of the blocks where the rows and columns of relay switch units cross, the dedicated functional elements being located in the spaces where the rows and columns of relay switch units cross.

2. The circuit of claim 1, wherein the logic cells are arranged in a matrix of rows and columns of cells, the circuit forming a field programmable gate array.

3. The circuit of claim 2, wherein the blocks of cells are also arranged in a row and column grid pattern of blocks.

4. A circuit as claimed in claim 3, wherein said dedicated functional units are provided in spaces provided at corners of said block.

5. The circuit of claim 1, wherein the memory structure comprises a Random Access Memory (RAM).

6. The circuit of claim 1, wherein the memory structure comprises a non-volatile memory.

7. The circuit of claim 1 wherein said memory structure comprises a dual-part memory having address inputs for separate read and write operations and separate data buses for said read and write operations.

8. The circuit of claim 1 wherein said pairs of fast buses are connected to said trunk switch units in a staggered manner such that successive trunk switch units are alternately connected to said different pairs of fast buses.

9. The circuit of claim 8, wherein the logic cells are arranged in a row-column matrix of cells and organized as an nxn block of cells, wherein the relay switch cells are evenly spaced every N logic cells.

10. The circuit of claim 9, wherein N-4.

11. The circuit of claim 2, wherein each logic cell in the matrix has up to four directly adjacent and orthogonal nearest neighbor logic cells on the same row or column as the logic cell, up to four directly adjacent diagonally nearest neighbor logic cells along one of two diagonally adjacent logic cells comprising the logic cell, each logic cell having a direct cell-to-cell input connection to at least one directly adjacent orthogonally nearest neighbor logic cell and having a direct cell-to-cell input connection to at least one directly adjacent diagonally nearest neighbor logic cell, each logic cell also having a direct cell-to-cell output connection to its immediate cell-to-cell input connection-same set of nearest neighbor logic cells, each logic cell having means for selecting one of the orthogonal direct cell-to-cell input connections and means for selecting the diagonal direct cell-to-cell input connection A device according to any one of the preceding claims.

12. The circuit of claim 11, wherein each cell has a direct cell-to-cell input connection and a direct cell-to-cell output connection to all logic cells nearest to it.

13. The circuit of claim 2 wherein each logic cell in the matrix has up to four directly adjacent diagonally nearest logic cells on one of the logic cells along two diagonals including the logic cell, each logic cell connecting a direct cell-to-cell input to each logic cell diagonally nearest thereto, each logic cell having means for selecting only from said diagonal direct cell-to-cell connections, and

the bus network comprises horizontal and vertical buses, distributed along rows and columns of cells, each logic cell having a selection bus connection to at least one horizontal bus and at least one vertical bus.

14. The circuit of claim 13, wherein each logic cell in the matrix further has up to four directly adjacent orthogonally nearest neighboring logic cells on the same row or column as the logic cell, each logic cell further having a direct cell-to-cell input connection and a direct cell-to-cell output connection to each nearest neighboring logic cell orthogonal thereto.

15. The circuit of claim 1 wherein each logic cell includes first and second lookup tables, each lookup table having a set of address inputs and outputs, the address inputs of both lookup tables receiving signals from the same set of cell inputs, each logic cell further having an AND logic gate disposed therein, a pair of gate inputs selectively connected to both cell inputs, the gate output connected to one address input of both lookup tables, the outputs of the first and second look-up tables being selectively connected to respective first and second cell outputs, each logic cell further comprising an output multiplexer, the multiplexer is selectively coupled to the third cell output and has first and second multiplexer inputs coupled to respective first and second look-up table outputs and a control input selectively coupled to the additional cell input.

16. The circuit of claim 15 wherein said cell inputs and cell outputs comprise direct cell-to-cell connections between diagonally adjacent logic cells, one of said two cell inputs being connected to the input of said and logic gate as one of said direct cell-to-cell connections.

17. The circuit of claim 1, wherein each logic cell comprises:

(a) a pair of look-up tables, each look-up table having N address inputs and an output, where N is an integer greater than 1, the N address inputs of both look-up tables receiving signals from the same cell input,

(b) means responsive to dynamic selection of additional cell inputs and outputs of one of said pairs of look-up tables to effectively form a combined (N +1) input look-up table from said pair of look-up tables,

(c) means for registering the output of at least one of said look-up tables, and

(d) a pair of output selection means, each selection means receiving a data signal from (i) the output of an N input look-up table, (ii) a dynamically selected combination (N +1) of the outputs of the input look-up tables and (iii) a registered output of one of said look-up tables, each selection means providing a signal selected from the received data signal to the cell output.

18. The circuit of claim 17 further comprising third output means for providing the output of the dynamically selected combination (N +1) input look-up table to another unit output connected to the bus network.

19. The circuit of claim 2, wherein each logic cell includes at least one synchronization cell responsive to a clock signal,

a set of clock lines including a plurality of master clock lines for receiving different clock signals and a plurality of column clock lines associated with each other and selectively coupled to particular columns of logic cells, each column clock line selectively coupled to any of the master clock lines for receiving a selected clock signal therefrom, an

Each column clock line is selectively coupled to its particular associated column of logic cells via a plurality of sector clock lines coupled to the column clock line, each sector clock line being coupled to a subset of logic cells within the associated column of logic cells.

20. The circuit of claim 2, wherein each logic cell includes at least one synchronization element responsive to a clock signal, and

a set of clock lines including at least one master clock line for receiving a clock signal, a plurality of column clock lines connected to the at least one master clock line and associated with a particular column of logic cells, and a plurality of sector clock lines for each column clock line connected to the column clock line, each sector line connected to a subset of the columns of logic cells and providing the clock signal.

21. The circuit of claim 20 wherein means for selectively inverting said clock signal is provided along each sector clock line.

22. The circuit of claim 2, wherein each logic cell includes at least one register element therein having set/reset capability responsive to a set/reset signal, and

a set of control lines including a global set/reset line receiving said set/reset control signal, a plurality of column position/reset lines connected to said global set/reset line and each associated with a particular column of logic cells, and a plurality of sector set/reset lines connected to the column position/reset line for each column set/reset line, each sector set/reset line connected to and providing said set/reset control signal to a subset of logic cells within the associated column of logic cells.

23. The circuit of claim 22, wherein means for selectively inverting the set/reset control signal is provided along each sector set/reset line.

24. The circuit of claim 22, wherein each logic cell has means for selectively designating the set/reset control signal as either a set signal or a reset signal.

25. The circuit of claim 2, further comprising:

means for connecting each of a plurality of said input/output terminals to more than one logic cell via a direct connection, an

Means for connecting each of a plurality of said logic cells to more than one input/output terminal via a direct connection;

each of a plurality of the input/output terminals is not connected to the bus network through a cell.

26. The circuit of claim 2 wherein the input/output terminals are connected to outermost logic cells of the matrix, each input/output terminal being directly connected to cell inputs of an immediately adjacent logic cell and two diagonally adjacent logic cells, at least some of said outermost logic cells in the matrix being connected to more than one input/output terminal including an immediately adjacent terminal and at least one diagonally adjacent terminal;

the logic cells are connected by a bus network arranged between rows and columns of logic cells, at least some of the input/output terminals being connected to the bus network.