HK1096482B - Oled display with ping pong current driving circuit and simultaneous scanning of lines - Google Patents

Description

OLED display with ping-pong current drive circuit and synchronous line scan

Technical Field

The present invention relates to a display driving apparatus, a display apparatus, and a driving control method thereof, and more particularly to a display driving apparatus which can be applied to a display panel on which a plurality of display pixels each including a current control type light emitting element which emits light with a predetermined luminance gradation by supplying a current corresponding to display data are arranged; and a display device including the display driving device; and a drive control method thereof.

Technical Field

Conventionally, a light emitting element type display (display device) is known which includes a display panel in which each display pixel includes a current control type light emitting element which emits light with a predetermined luminance gradation depending on a current value of a supplied drive current, the display pixels being two-dimensionally arranged like an organic electroluminescence element (which will be referred to as an "organic EL element" hereinafter) or a Light Emitting Diode (LED).

In particular, a light emitting element type display employing an active matrix driving mode has a higher display response rate, has no field angle dependency, and can realize high luminance/high contrast, high definition of display image quality, reduction in power consumption, and other advantages, as compared with a liquid crystal display device (LCD) which has been widely used in recent years. In addition, the light-emitting element type display includes light-emitting element type display pixels, and thus does not require a backlight as in the liquid crystal display device. Therefore, the light emitting element type display has excellent characteristics, can further reduce the thickness and weight, and has been intensively studied and developed as a next-generation display.

Fig. 18 is a schematic diagram showing a configuration example of a main part of a light emitting element type display in which an active matrix driving mode is adopted in the related art.

Fig. 19 is an equivalent circuit diagram showing a configuration example of a display pixel applied to a light emitting element type display employing an active matrix driving mode in the related art.

As shown in fig. 18, a light-emitting element type display adopting an active matrix driving mode in the related art has a structure including: the display panel 110P in which a plurality of display pixels EMP are arranged in a matrix form (n rows × m columns). Each display pixel EMP includes, for example, in the vicinity of each intersection of a plurality of scanning lines SL and a plurality of data lines DL, a pixel drive circuit described later and a current control type light emitting element (e.g., an organic EL element), where SL and DL are arranged substantially perpendicular to each other. The scan driver 120P is connected to the scan lines SL of the display panel 110P, and sets the display pixels EMP of each row to a selected state by sequentially applying a scan signal Vsel to each scan line SL at a predetermined timing. The signal driver 200P is connected to the data lines DL of the display panel 110P, acquires display data at a predetermined timing, and supplies a gradation current Ipix corresponding to the display data to each of the data lines DL.

In such a display, the operation states of the scan driver 120P and the signal driver 200P are controlled by, for example, scan control signals, data control signals, and the like, wherein the generation of these signals is based on timing signals supplied from the outside, and the display pixels set to the selected state in each row are written by the application of the scan signals corresponding to the level currents of the display data. As a result, each display pixel emits light having a predetermined gradation of brightness, thereby displaying desired image information.

In such a light emitting element type display employing an active matrix driving mode, various types of driving control mechanisms or control methods are proposed which control light emission of the above-described current control type light emitting element. For example, a display device including a pixel driving circuit is known, in which the circuit is composed of a plurality of switching devices that control light emission of light emitting elements and the light emitting elements in accordance with each display pixel constituting a display panel.

For example, as shown in fig. 19, such a pixel driving circuit specifically includes: the pixel drive circuit DP 1; and an organic EL element OEL having an anode terminal connected to the drain terminal of the transistor Tr124 of the pixel drive circuit DP1, and a cathode terminal to which a ground potential is applied. In the vicinity of each intersection of a pair of the scanning lines SL1 and SL2 arranged in parallel with each other and the data line DL, the pixel drive circuit DP1 includes: a first transistor Tr121 having a gate terminal connected to the scan line SL1, and source and drain terminals connected to the data line DL and the contact N121; a second transistor Tr122 having a source terminal and a drain terminal connected to the contact N121 and the contact N122; a third transistor Tr123 having a gate terminal connected to the contact N122, a drain terminal connected to the contact N121, and a source terminal to which a higher power supply voltage Vdd is applied; a fourth transistor Tr124 having a gate terminal connected to the contact N122 and a source terminal to which a higher power supply voltage Vdd is applied.

In this example, in fig. 19, the first transistor Tr121 includes an n-channel type field effect thin film transistor, and each of the second to fourth transistors Tr122 to Tr124 includes a p-channel type field effect thin film transistor. In addition, CP1 represents parasitic capacitance formed between the gates and sources of the third and fourth transistors Tr123 and Tr 124.

In the pixel drive circuit DP1 having such a structure, the organic EL element OEL is subjected to light emission control as follows by turning on/off four transistors (switching devices) including the transistors Tr121 to Tr124 at predetermined timings.

That is, in the pixel drive circuit DP1, when the scan driver 120P sets the display pixel to the selected state by applying the high-level scan signal Vsel1 to the scan line SL1 and the low-level scan signal Vsel2 to the scan line SL2, respectively, the transistors Tr121, Tr122, and Tr123 are made conductive, and the level current Ipix corresponding to the display data flows through the transistors Tr121 and Tr123, wherein the signal driver 200P supplies the display data to the data line DL. At this time, since a portion between the gate and the drain of the transistor Tr123 is electrically shorted by the transistor Tr122, the Tr123 operates in a saturation region. As a result, the current level of the gradation current Ipix is changed to the voltage level by the transistor Tr123, thereby generating a predetermined voltage between the gate and the source (write operation). The transistor Tr124 is turned on in accordance with the voltage generated between the gate and the source of the transistor Tr123, and a predetermined drive current flows from the high power supply voltage Vdd through the transistor Tr124 and the organic EL element OEL to the ground potential, so that light is emitted from the organic EL element (light emitting operation).

Subsequently, when, for example, the advanced scan signal Vsel2 is applied to the scan line SL2, the transistor Tr122 is turned off. As a result, the voltage generated between the gate and the source of the transistor Tr123 is held by the parasitic capacitance CP 1. Next, when the low-level scan signal Vsel1 is applied to the scan line SL1, the transistor Tr121 is turned off. As a result, the data line DL and the pixel driving circuit DP1 are electrically disconnected. Therefore, the fourth transistor Tr124 continuously maintains the on state by a potential difference which flows a predetermined drive current from the high power supply voltage Vdd, through the transistor Tr124 and the organic EL element OEL, into the ground potential based on the voltage maintained in the parasitic capacitance CP1, and thus continues the light emitting operation of the organic EL element OEL.

Here, the drive current supplied to the organic EL element OEL through the transistor Tr124 is controlled to have a current value based on the luminance gradation of the display data, and the light emitting operation is controlled for a period of, for example, one frame until the gradation current corresponding to the next display data is written in each display pixel.

The drive control method in the pixel drive circuit having such a circuit configuration supplies a gradation current having a specific current value corresponding to display data to each display pixel (the gate terminal of the third transistor Tr 123), and controls a drive current, which passes through the organic EL element, based on a voltage held in accordance with the current value, thereby affecting a light emitting operation having a predetermined luminance gradation. Therefore, this method is referred to as a current application mode (or current specification mode).

Like fig. 19, there is also known a drive control method employing a voltage application mode (or voltage designation mode) which applies a gradation voltage having a designated voltage value corresponding to display data to each display pixel including a pixel drive circuit and an organic EL element, and which controls a drive current in accordance with the voltage value of the gradation voltage, wherein the current passes through the organic EL element OEL, thereby affecting a light emitting operation with a predetermined luminance gradation. In a pixel drive circuit employing such a voltage designation mode, irregularities or fluctuations (degradation) are generated in the element characteristics (channel resistance of a transistor or the like) of a switching element having a selection function or a light emission drive function depending on the external environment (ambient temperature or the like), use time, and the like, so that the drive current is affected. Thus, the pixel drive circuit has a problem that desired light emission characteristics (display at a predetermined luminance gradation) cannot be stably realized for a long time in time. Alternatively, when each display pixel is finely formed, in order to realize high definition of the display panel, irregularities in the operation characteristics (current between the transistor and other source and drain) of the switching element constituting the pixel drive circuit become large, and thus appropriate hierarchical control cannot be performed. Therefore, the pixel drive circuit has a disadvantage in that generation of irregularity in the light emission characteristic of each display pixel causes deterioration in the quality of a displayed image.

In contrast, the pixel driving circuit adopting the current designation mode includes a third transistor Tr123 (current/voltage conversion transistor) that converts the current level of the gradation current corresponding to the display data supplied to each display pixel into the voltage level; and a fourth transistor Tr124 (light emission driving transistor) which supplies a driving current having a predetermined current value to the organic EL element OEL. By setting the current value of the drive current supplied to the organic EL element OEL, the pixel drive current can suppress the influence of irregularities in the operation characteristics of the respective transistors Tr123 and Tr124, and thus has an advantage that the problem of the pixel drive circuit employing the voltage specification mode can be solved.

However, the pixel drive circuit adopting the current designation mode has the following problems.

In the case where the gradation current is written based on the display data having the lowest luminance or relatively low luminance in each display pixel (at the time of low-level display), a signal current having a small current value corresponding to the luminance gradation of the display data must be supplied to each display pixel.

Here, since the operation of writing the gradation current in each display pixel corresponds to charging a capacitive element (constituting a wiring capacitance and a holding capacitance of the display pixel) which is parasitic on the data line to a predetermined voltage, the wiring length of the data line becomes long due to, for example, an increase in the size of the display panel. In addition, when the number of display pixels connected to the data line increases, when the current value of the gradation current becomes small, that is, when a (effect with) lower level display is realized, the time required to charge the data line becomes long, and thus the time required for the writing operation with respect to each display pixel increases. The writing operation with respect to each display pixel cannot be completed within a preset writing time, and a so-called insufficient writing state is generated in which a steady state (saturated state) is not reached. As a result, the display pixels cannot emit light with a suitable luminance gradation corresponding to the display data, resulting in degradation of the display image quality.

In addition, when the number of scanning lines arranged on the display panel is increased and the selection period (i.e., the writing time) of each scanning line is set to be short in order to achieve high definition of the display panel, since the current value of the gradation current is decreased, a sufficient writing operation cannot be performed with respect to each display pixel and an insufficient writing state is generated, resulting in deterioration of display image quality or limitation of high definition of the display panel.

Disclosure of Invention

In a display driving apparatus that drives display pixels of a display panel based on display data and a display apparatus including the display driving apparatus, the present invention has an advantage that in an operation of writing a gradation current in each display pixel, occurrence of an insufficient writing state can be suppressed and high definition of the display panel can be excellently realized.

To achieve the above advantages, according to one aspect of the present invention, there is provided a display driving device that drives a plurality of two-dimensionally arranged display pixels constituting a display panel based on display data, the display driving device including at least:

a selection circuit that sets display pixels in a plurality of specific rows of the display panel to a selected state, having periods that at least overlap with each other;

a gradation signal generation circuit that generates a gradation signal for controlling a luminance gradation of each display pixel based on the display data; and

and a current writing circuit which acquires signal currents corresponding to the display pixels in the plurality of specific rows and supplies the display pixels in the plurality of specific rows with a gradation current having a current value based on the gradation signal in accordance with a timing at which the selection circuit sets the display pixels in a selected state.

The current writing circuit is preferably formed in a configuration independent of the display panel, or is constituted by a plurality of field-effect thin-film transistors each having an amorphous silicon semiconductor layer having a single channel polarity as a channel layer, or is constituted by a plurality of field-effect thin-film transistors having a polycrystalline silicon semiconductor layer as a channel layer, and is integrated with the display panel.

Preferably, the gradation signal generating circuit generates a signal current as a gradation signal for supplying a luminance gradation corresponding to display data to the display pixels, and the current writing circuit has means for generating and outputting a gradation current having a current polarity opposite to that of the signal current supplied from the current generating section.

Preferably, the selection circuit has means for synchronously setting the display pixels on a plurality of specific rows of the display panel to a selected state based on a single selection signal; the current writing circuit has means for synchronously supplying a gradation current to the display pixels in a plurality of specific rows in accordance with the timing at which the selection state is set by the selection signal; a gradation current generation circuit having means for sequentially supplying a gradation signal to the current writing circuit in a time series, wherein the gradation signal corresponds to a plurality of display pixels in each column of the display pixels in a plurality of specific rows; the current writing circuit includes a plurality of signal distributing circuits provided in accordance with each column of display pixels in a plurality of specific rows, and the circuit sequentially distributes the gradation signals supplied from the gradation signal generating circuit in accordance with the plurality of display pixels in each column at a timing of a time-series source, and a plurality of current holding circuits individually holding the gradation signals distributed by the signal distributing section and simultaneously supplying the display pixels in the plurality of specific rows with a current value based on the held gradation signals as the gradation current. At a plurality of stages, a signal holding/outputting section of a plurality of stages is provided for each of the current holding circuits, the signal holding/outputting section including a signal holding section holding the signal current distributed by the signal distributing circuit, and a gradation current outputting section outputting a current as a gradation current in accordance with each of a plurality of display pixels in each column of the display pixels in a plurality of specific rows, wherein the current corresponds to the signal current held in the signal holding section. The operation of acquiring and holding the signal current, which is performed by the signal holding section at one of the signal holding/outputting sections of the plurality of stages, is controlled to be performed simultaneously with the operation of outputting the hierarchy current at any other stage by the hierarchy current outputting section.

Preferably, the selection circuit has means for sequentially setting the display pixels corresponding to the plurality of specific rows to a selected state having an overlap period by sequentially applying a selection signal to each specific row of the display panel at the overlap period, wherein the selection signal sets the display pixels in each row to the selected state. The current writing circuit has a means for supplying the gradation current to each specific row with an overlapping period at a timing corresponding to the application of the selection signal of the selection circuit. The gradation signal generating circuit has a means for sequentially supplying, in time series, gradation signals corresponding to a plurality of display pixels in each column of display pixels in a plurality of specific rows to the current writing circuit. The current writing circuit includes a plurality of current holding circuits which are provided in accordance with respective columns of display pixels in a plurality of specific rows, sequentially hold the gradation signal provided by the gradation signal generating circuit in accordance with timing of the time-series source, and sequentially supply a current having a current value based on the gradation signal to each of the specific rows as the gradation current. In accordance with a plurality of display pixels in each column of display pixels in a plurality of specific rows, each of the current holding circuits includes a plurality of current holding/output sections each having a signal distributing section distributing a signal current in accordance with a timing of the time-series source; further comprises a signal holding section for holding the signal current distributed by the signal distributing section; and a gradation current output section that outputs a current corresponding to the signal current held in the signal holding section as a gradation current. An operation of outputting a level current based on the signal current held in the signal holding section by the level current output section of one of the current holding/output sections and holding the signal current distributed by the signal distributing section in the signal holding section of the other current holding/output section, and an operation of outputting the level current by the level current output section based on the signal current held in the signal holding section are controlled to be performed in synchronization within the overlapping period.

Preferably, the signal holding section includes a charge storage circuit that stores charges based on the signal current and holds the charges as a voltage component, and the level current output section has a current mirror circuit structure that generates and outputs a current having a current value with a predetermined current ratio with respect to a current value corresponding to the level signal supplied from the level signal generating circuit as the level current.

To achieve the above advantages, according to another aspect of the display device of the present invention, there is provided a display device displaying image information based on display data, the display device including at least:

a display panel having a plurality of scanning lines arranged in a row direction and a plurality of data lines arranged in a column direction, and a plurality of display pixels arranged in a matrix form in the vicinity of intersections of the plurality of scanning lines and the plurality of data lines;

a scan driver setting display pixels corresponding to a plurality of specific scan lines to a selected state, the scan lines being at least a part of the plurality of scan lines of the display panel, the selected state having periods at least overlapping each other; and

a signal driver including a gradation signal generation circuit to which display data is supplied and which generates a gradation signal that controls a luminance gradation of each display pixel based on the display data; and a current writing circuit which acquires a signal current corresponding to a display pixel corresponding to a plurality of specific scanning lines, and supplies a gradation current having a current value based on the gradation signal to the display pixel corresponding to the plurality of specific scanning lines in accordance with a timing at which the display pixel is set to a selected state by the scan driver.

Preferably, the signal driver is formed in a configuration independent of the display panel, or by using a plurality of field-effect thin film transistors each having an amorphous silicon semiconductor layer having a single channel polarity as a channel layer, or a plurality of field-effect thin film transistors having a polycrystalline silicon semiconductor layer as a channel layer, thereby constituting a current writing circuit in the signal driver, and integrated with the display panel on a single insulating substrate.

Preferably, the gradation signal generation circuit generates a signal current as a gradation signal to supply a luminance gradation corresponding to the display data to the display pixel. In addition, the current writing circuit in the signal driver has means for generating and outputting a level current whose current polarity is opposite to the signal current supplied by the current generating section.

The display pixel may include a pixel driving circuit generating a predetermined driving current based on the gradation current output from the signal driver, and a current control type light emitting element emitting light having a predetermined luminance gradation based on a current value of the driving current.

The pixel drive circuit may be constituted by using a plurality of field-effect thin film transistors in which an amorphous silicon semiconductor layer having a single channel polarity is a channel layer, or using a plurality of field-effect thin film transistors in which a polysilicon semiconductor layer is a channel layer, and the light-emitting element is, for example, an organic electroluminescence element.

The display panel may have a plurality of data line groups in which a plurality of data lines corresponding to the number of scan lines of each scan line group are determined as one group. Each of the data line groups is arranged according to an area between a plurality of columns of display pixels arranged in a matrix form in the display panel, and the display panel has a plurality of scan line groups in which a plurality of specific scan lines are determined as one group.

Preferably, the scan driver has means for synchronously setting the display pixels corresponding to the plurality of specific scan lines to the selected state by applying a single scan signal to each of the scan line groups, wherein the scan signal sets the display pixels to the selected state. A gradation signal generating circuit in the signal driver has a means for sequentially supplying gradation signals corresponding to a plurality of display pixels corresponding to each of the scanning line groups in each of the data lines in each of the data line groups to the current writing circuit in time series. A current writing circuit in a signal driver includes: a plurality of signal distributing circuits arranged in accordance with the respective data line groups and sequentially distributing the level signals supplied from the level signal generating circuit in accordance with each data line in each data line group at a timing of the time-series source; and a plurality of current holding circuits that individually hold the gradation signals assigned by the signal assigning section and synchronously supply a current having a current value based on the held gradation signals to each data line in each data line group as a gradation current in accordance with a timing of applying the scan signals to each scan line group. A signal holding/outputting section of a plurality of stages is provided for each current holding circuit, each signal holding/outputting section including a signal holding section holding a gradation signal assigned by the signal assigning circuit, and a gradation current outputting section outputting a current having a current value based on the gradation signal held in the signal holding section as a gradation current in accordance with each data line in each data line group. The operation of acquiring and holding the gradation signal performed by the signal holding section at one of the signal holding/output sections of the plurality of stages and the operation of outputting the gradation current by the gradation current output section at the other stage are controlled to be performed in synchronization.

Preferably, the scan driver has a means for sequentially setting the display pixels corresponding to the plurality of specific scan lines to a selected state having an overlap period by sequentially applying a scan signal to each of the specific scan lines at the overlap period, wherein the scan signal sets the display pixels to the selected state. A current writing circuit in the signal driver has a means for supplying a gradation current to each data line of each data line group in turn in an overlapping period at a timing corresponding to application of a scan signal to the scan driver.

Preferably, the scan driver has a means for setting the display pixels corresponding to the plurality of specific scan lines to a selected state in an overlapping period by applying a scan signal to each of the specific scan lines in turn in the overlapping period, wherein the scan signal sets the display pixels to the selected state. A gradation signal generating circuit in the signal driver has a means for sequentially supplying gradation signals corresponding to a plurality of display pixels corresponding to a plurality of specific scanning lines in each data line group to the current writing circuit in time series. The current writing circuit includes a plurality of current holding circuits which are provided in accordance with respective data line groups, sequentially hold the gradation signal provided by the gradation signal generating circuit in accordance with timing of a time-series source, and sequentially supply a current having a current value corresponding to the gradation signal as the gradation current to each data line in each data line group at timing of application of the scanning signal. Providing a plurality of signal holding/output sections for each current holding circuit in accordance with the respective data lines in each data line group, each signal holding/output section including a signal distributing section that sequentially distributes a hierarchical signal in accordance with each data line in each data line group at a timing of a time-series source; a signal holding section that holds the level signal distributed by the signal distributing section; and a level current output section outputting a current having a current value based on a level signal as a level current, wherein the level signal is held in the signal holding section. In one of the current holding/outputting sections, an operation of holding the level signal distributed by the signal distributing section in the signal holding section and outputting a level current based on the level signal by the level current outputting section, and in any other current holding/outputting section, an operation of outputting a level current based on the level signal held in the signal holding section by the level current outputting section are controlled to be performed in synchronization in the overlapping period.

The signal holding section may include a charge storage circuit that stores charges corresponding to the gradation signal and holds the charges as a voltage component. The level current output section may have a current mirror circuit structure, and generate and output a current having a current value having a predetermined current ratio with respect to a current value corresponding to the level signal supplied from the current generating section as the level current.

According to a driving method of a display device in a further aspect of the present invention to achieve the above object, display pixels corresponding to a plurality of specific scanning lines which are at least a part of the plurality of scanning lines in the display panel are set to a selected state having at least an overlapping period, thereby providing display data. A level signal is generated based on the display data, wherein the level signal controls a luminance level of each display pixel. A level signal corresponding to a display pixel corresponding to a plurality of specific scan lines is acquired. A gradation current having a current value based on the gradation signal is generated, and the generated gradation current is supplied to display pixels corresponding to a plurality of specific scanning lines in accordance with the timing at which the display pixels are set to a selected state. The display pixels to which the gradation current is supplied and written operate at display luminance based on the current value of the gradation current.

The operation of generating the gradation signal generates a signal current as the gradation signal, which supplies a luminance gradation corresponding to the display data to the display pixels. The operation of generating and outputting the level current having the current value based on the level signal may include an operation of generating a current having a predetermined current ratio with respect to the current value corresponding to the level signal, and outputting the generated current as the level current.

The operation of setting the display pixels to the selected state may include an operation of synchronously applying a single scan signal, which sets the display pixels to the selected state, to the plurality of specific scan lines, so that the display pixels corresponding to the plurality of scan lines may be synchronously set to the selected state. The operation of supplying the level current may include an operation of synchronously supplying the level current to the display pixels corresponding to the plurality of scan lines. The operation of synchronously supplying the gradation current to the display pixels corresponding to the plurality of scanning lines may include an operation of synchronously performing an operation of acquiring and holding the gradation signal corresponding to each scanning line, and an operation of outputting the gradation current based on the gradation signal acquired and held at the above-described timing.

Preferably, the operation of setting the display pixels to the selected state sequentially applies a scanning signal, which sets the display pixels to the selected state, to each of the specific scanning lines in an overlapping period in order that the display pixels corresponding to the plurality of scanning lines are sequentially set to the selected state with the overlapping period. The operation of supplying the gradation current includes an operation of supplying the gradation current to the display pixels in turn in an overlapping period at the timing of application of the scan signal, wherein the display pixels correspond to each of the scan lines. An operation of sequentially supplying the level currents to the display pixels corresponding to the plurality of scanning lines, an operation of holding the level signals and outputting the level currents based on the level signals, and an operation of outputting the level currents based on the level signals held at the above-described timings are performed in synchronization with the overlapping period.

Brief Description of Drawings

Fig. 1 is a schematic block diagram showing the entire structure of a display apparatus according to one embodiment of the present invention;

fig. 2 is a structural view showing a part of the display device according to the embodiment shown in fig. 1;

fig. 3 is a block diagram showing a configuration example of a current generation section which can be applied to the display apparatus according to the embodiment shown in fig. 1;

fig. 4 is a circuit configuration diagram showing a configuration example of a current holding/distributing portion which can be applied to the display device according to the embodiment shown in fig. 1;

fig. 5A and 5B are conceptual diagrams illustrating a schematic operation of a current holding/distributing section, which can be applied to the embodiment shown in fig. 1;

fig. 6 is a timing chart illustrating a drive control operation (drive control method) in the display device according to the embodiment shown in fig. 1;

FIG. 7 is a schematic configuration diagram showing a main part of another configuration example of the display device according to the embodiment shown in FIG. 1;

fig. 8 is a schematic configuration diagram showing a main part of still another example of the display device according to the embodiment shown in fig. 1;

fig. 9 is a structural view showing a part of a second embodiment of a display device according to the present invention;

fig. 10 is a circuit configuration diagram showing a configuration example of a current holding/distributing portion which can be applied to the display device according to the embodiment shown in fig. 9;

fig. 11A and 11B are conceptual diagrams illustrating a schematic operation of a current holding/distributing section which can be applied to the embodiment shown in fig. 9;

fig. 12 is a timing chart showing a drive control method of the display device according to the embodiment shown in fig. 9;

fig. 13 is a schematic configuration diagram showing a main part of another configuration example in the second embodiment of the display device according to the present invention;

fig. 14 is a circuit configuration diagram showing a specific circuit example of a display pixel which can be applied to a display device according to the present invention;

fig. 15A and 15B are conceptual diagrams illustrating a driving control operation of the pixel driving circuit according to the embodiment illustrated in fig. 9;

fig. 16 is a schematic block diagram showing a structural example of a display device to which the display pixel according to the embodiment shown in fig. 14 can be applied;

fig. 17 is a schematic block diagram showing another configuration example of a display device to which the display pixel according to the embodiment shown in fig. 14 can be applied;

fig. 18 is a schematic diagram showing a configuration example of a main portion of a light emitting element type display employing an active matrix driving mode in the related art; and

fig. 19 is an equivalent circuit diagram showing a structural example of a display pixel applied to a light emitting element type display employing an active matrix driving mode in the related art.

Detailed Description

Hereinafter, a display device and a driving control method thereof according to the present invention will be described based on the illustrated embodiments.

< first embodiment of display device >

A schematic structure of a display device to which the display driver device according to the present invention can be applied will be described first.

Fig. 1 is a schematic block diagram showing the entire structure of a display apparatus according to one embodiment of the present invention.

Fig. 2 is a structural diagram showing a main portion of the display device according to this embodiment.

As shown in fig. 1, a display device 100 according to the present invention mainly has a display panel 110A, a scan driver (selection circuit) 120A, a current generation section (hierarchical signal generation circuit) 130, a current holding/distributing section (current writing circuit) 140A, a system controller 150, and a display signal generation section 160.

As shown in fig. 2, the display panel 110A basically has a plurality of display pixels EM which are two-dimensionally arranged (n rows × m columns) and connected to the selection transistor Trsel. A plurality of scanning line groups SGi are arranged in accordance with the display pixels EM in a plurality of rows (two rows in the present embodiment), and wherein a plurality (two in the present embodiment) of scanning lines SLia and SLib (i is a positive integer falling within a range of 1. ltoreq. i.ltoreq.n ', for example, a divisor of the total number n of rows provided in the display panel 110A; n' and n are positive integers) are determined as one group. A plurality of data line groups DGj are arranged in accordance with the display pixels EM in each column corresponding to each scan line group SGi, and wherein a plurality of (two in this embodiment) data lines DLja and DLjb (j is a positive integer falling within the range 1. ltoreq. j.ltoreq.m, m is a positive integer, and is the total number of pixel columns set in the display panel 110) are determined as one group. Each display pixel EM is provided near an intersection of the scan lines SLia and SLib constituting each scan line group SGi and the data lines DLja and DLjb constituting each data line group DGj.

The scan driver (selection circuit) 120A is generally connected to the scan line group SGi of the display panel 110A, and sequentially applies the scan signal Vsel to each scan line group SGi at a predetermined timing to synchronously set the display pixels EM corresponding to a plurality of rows (two rows in the present embodiment) connected to the scan line group SGi.

The current generation section (gradation signal generation circuit) 130 generally acquires display data corresponding to display pixels supplied from a later-described display signal generation section 160, the display pixels corresponding to a plurality of rows (two rows in the present embodiment) of the scanning line group SGi, and supplies signal currents (gradation signals) Ic with respect to the plurality of corresponding rows to the current holding/distributing section 140A in time series.

The current holding/distributing section (current writing circuit) 140A is generally connected to each data line group DGj of the display panel 110A, distributes the signal currents Ic corresponding to a plurality of rows (two rows in the present embodiment) sequentially supplied from the current generating section 130 in a time series at a predetermined timing, holds the currents in accordance with each row, and synchronously supplies the gradation current Ipix based on the held signal currents Ic to the display pixels EM in the plurality of rows (two rows in the present embodiment). In this embodiment, the current generation section 130 and the current holding/distributing section 140A constitute a signal driver 200A.

The system controller 150 generates and outputs a scan control signal and a data control signal, and controls at least the operation states of the scan driver 120A, the current generation section 130, and the current holding/distributing section 140A based on, for example, a timing signal supplied from the display signal generation section 160.

The display signal generation section 160 generates display data (e.g., digital data) based on, for example, a video signal supplied from the outside of the display device 100, supplies the display data to the current generation section 130, further generates or extracts a timing signal (system clock or the like) which displays the display data as an image in the display panel 110A, and supplies the timing signal to the system controller 150.

In the structure shown in fig. 2, the current holding/distributing part 140A is integrated with the pixel array on the insulating substrate BASE as a structural example, and a plurality of display pixels EM (i.e., pixel array) constituting the display panel 110A are formed on the substrate, but the present invention is not limited to this structure. For example, the signal driver 200A may have a configuration of a driver chip and be mounted (packaged) on the BASE substrate.

The specific configuration of each structure will now be described.

(display panel)

For example, as shown in fig. 2, the display panel 110A has a structure in which the display panel can be applied to the display device according to this embodiment, and in the structure, each scan line group SGi corresponding to two rows in which two separate scan lines SLia and SLib are determined as one group and each data line group DGj corresponding to one pixel column in which two data lines DLja and DLjb are determined as one group are arranged to be perpendicular to each other. Each display pixel EM is connected to an intersection of each scanning line SLia and each data line DLja, and an intersection of each scanning line SLib and each data line Dljb.

In this embodiment, in the structure shown in fig. 2, the display pixels EM in the odd-numbered rows are connected to the scanning lines SLia in each scanning line group SGi, and the display pixels EM in the even-numbered rows are connected to the scanning lines SLib.

As shown in fig. 2, the present invention is not limited to the structure in which each scan line group SGi corresponds to two rows of display pixels EM, with respect to the number of rows corresponding to the scan lines constituting each scan line group SGi. For example, a configuration may be adopted in which each scan line group SGi corresponds to k rows of display pixels EM (k being a submultiple of the total number n of rows provided in the display panel 110), and which optionally has n/k groups (i.e., the above-described n' groups) of scan line groups, for example, a configuration may be adopted in which one (single) scan line group is provided depending on the rows (n rows) constituting the display panel 110A, and all the display pixels EM on one screen are connected in common to the scan line group. In this case, all the display pixels EM on one screen are set to the selected state together by a single scan signal output from the scan driver 120A.

Each display pixel EM has a gate terminal connected to each scan line SLia or SLib, and a source terminal connected to the drain terminal of each selection transistor Trsel connected to each data line DLja and DLjb. Each display pixel EM includes a current control type light emitting element, and emits light having a predetermined luminance gradation based on the gradation current Ipix supplied from the current holding/distributing section 140 through each data line DLja or DLjb and the selection transistor Trsel.

In the display panel 110A having such a structure, by applying the scanning signal Vsel to a specific scanning line group SGi from a scanning driver 120A described later, the selection transistors Trsel connected to the plurality (two) of scanning lines SLia and SLib constituting the scanning line group SGi are turned on in synchronization, and the display pixels EM corresponding to a plurality of rows (two rows) are set to a selected state together. In a state (selected state) where the scan signal Vsel is applied to a specific scan line group SGi, display data is written in display elements EM corresponding to a plurality of rows (two rows) which are simultaneously set to the selected state by the selection transistor Trsel being turned on by supplying a level current Ipix corresponding to the display data from a current generating section 130 and a current holding/distributing section 140A described later to each data line group DGj all at once. A specific circuit example or a circuit operation of the display pixel EM including the selection transistor will be described in detail later.

(Scan driver)

The scan driver 120A simultaneously sets the display pixels EM corresponding to a plurality of rows (two rows in this embodiment) to a selected state, which are connected to the scan lines SLia and SLib constituting each scan line group SGi, by performing an operation of sequentially applying the scan signal Vsel at a selection level (e.g., high level) to each scan line group SGi based on the scan control signal supplied from the system controller 150. That is, for example, as shown in fig. 2, the scan driver 120A includes shift modules SB1, SB2,. SBi,. SBn ', each including a shift register and a buffer at multiple stages according to respective scan line groups SGi (in fig. 2, n' ═ n/2; n is the total number of lines provided in the display panel 110A). When sequentially shifting from the upper portion to the lower portion of the display panel 110A, the shift register outputs a shift signal, which is sequentially applied to each scan line group SGi as a scan signal Vsel having a predetermined selection stage (high stage) through a buffer based on a scan control signal (scan start signal SST, scan clock signal SCK, and the like) supplied from a system controller 150 described later.

As described above, for example, when a structure is adopted in which all the display pixels EM constituting the display panel 110A are connected to the single line group SGi, such a shift block as shown in fig. 2 is not necessary, and all the display pixels EM on one screen are set to a selected state together by applying the single scan signal Vsel to the scan line group SGi based on the scan control signal at a predetermined timing.

(Current generating section)

The current generation section 130 sequentially acquires display data supplied from a later-described display signal generation section 160 at a predetermined timing based on a data control signal input from the system controller 150, wherein the display data correspond to a plurality of rows (two rows in the present embodiment) of display pixels in the data line group DGj, the data line group DGj corresponds to the scanning line group SGi to generate a signal current (gradation signal) Ic having a current value corresponding to a gradation value of the display data, and supplies the signal current Ic of the plurality of rows to the current holding/distributing section 140A sequentially in accordance with each column in a time series. The current generation section 130 sequentially and repeatedly performs this operation for one screen. The specific structure and operation of the current generation section 130 will be described in detail later.

(Current holding/distributing section)

The current holding/distributing section 140A sequentially acquires, in time series, the signal currents Ic of a plurality of rows corresponding to each scanning line group SGi supplied from the current generating section 130 based on the data control signal input at the predetermined timing system controller 150, individually holds the signal currents Ic in accordance with the plurality of display pixels EM in each column of each data line group DGj, and synchronously supplies the gradation current Ipix based on the held signal current Ic to the display pixels EM of a plurality of rows (two rows in the present embodiment) in each data line group DGj in accordance with the timing of setting each scanning line group SGi to the selected state by using the above-described scan driver 120.

Specifically, for example, as shown in fig. 2, the current holding/distributing section 140A includes at least a plurality of current distributing circuits 141 each provided in accordance with each of the data line groups DGj arranged in the display panel 110A and distributing the signal current Ic supplied from the current generating section 130 in time series in accordance with each of the plurality of (two in the present embodiment) data lines DLja and DLjb of each data line group DGi; and a plurality of current holding circuits 142 each provided so as to be connected to each of the data line groups DGi arranged in the display panel 110A and holding in parallel a signal current Ic corresponding to a plurality of (two in the present embodiment) data lines distributed by the current distribution circuit 141.

The current holding/distributing section 140A sequentially acquires the signal currents Ic of a plurality of rows (two rows in the present embodiment) connected to the scanning lines SLia and SLib constituting each scanning line group SGi at a timing based on the data control signal, and distributes and holds the signal currents Ic in accordance with each data line in each data line group SGi. The section 140A also generates a gradation current Ipix based on the held signal current Ic, and synchronously supplies the gradation current Ipix to a plurality of rows (two rows in the present embodiment) of display pixels EM through each of the data line groups DGi at the timing of setting the scan line group SGi to the selected state. The specific structure and operation of the current holding/distributing portion 140A will be described in detail later.

(System controller)

The system controller 150 allows the scan driver 120A, the current generating section 130, and the current holding/distributing section 140A to operate at predetermined timings to generate/output the scan signal Vsel, the signal current Ic, and the gradation current Ipix by outputting the scan control signal and the data control signal, which control the operating state, to the scan driver 120A and the current generating section 130, and outputting the scan signal Vsel, the signal current Ic, and the gradation current Ipix to the current holding/distributing section 140 through the current generating section 130, writes the display data generated by the display signal generating section 160 to each display pixel EM to emit light therefrom, and controls the display panel 110A to display predetermined image information based on the video signal.

(display Signal generating section)

The display signal generation section 160 extracts a luminance gradation signal component from, for example, a video signal supplied from the outside of the display device 100 in accordance with each line of the display panel 110A, and supplies the luminance gradation signal component to the current generation section 130 as display data. In this embodiment, when the video signal includes a timing signal component defining the display timing of image information like a television broadcast signal (composite video signal), the display signal generation section 160 may have a function of extracting a luminance gradation signal component and a function of extracting the timing signal component and supplying it to the system controller 150. In this case, the system controller 150 generates a scan control signal and a data control signal supplied to the scan driver 120A, and the current generation section 130 or the current holding/distributing section 140 is based on the timing signal supplied from the display signal generation section 160.

< specific examples of Current generating portions >

A specific configuration example of the current generation section which can be applied to the display device according to this embodiment will now be described.

Fig. 3 is a block diagram showing a configuration example of a current generation section which can be applied to the display device according to this embodiment.

For example, as shown in fig. 3, the current generation section 130 includes a shift register circuit 131, a data register circuit 132, a data latch circuit 133, a D/a converter 134, and a voltage-current conversion/current source circuit 135. The shift register circuit 131 outputs a shift signal while sequentially shifting the sampling start signal STR based on a shift clock signal CLK supplied from the system controller 150 as a data control signal. The data register circuit 132 sequentially acquires one line of display data D0 to Dm (digital data) supplied from the display signal generating section 160 based on the input timing of the shift signal. The data latch circuit 133 holds one line of the display data D0 to Dm acquired by the data register circuit 132 based on the data latch signal STB. The D/a converter 134 converts the held display data D0 to Dm into predetermined analog signal voltages (gradation voltages Vpix) based on the gradation reference voltages V0 to Vp supplied from the unillustrated power supply device. The voltage-current conversion/current source circuit 135 generates the signal current (gradation signal) Ic corresponding to the display data converted into the analog signal voltage, and sequentially supplies the signal current Ic corresponding to the display pixels EM in each column to the current holding/distributing section 140A for a plurality of rows connected to each scanning line group SGi based on the output enable signal OE supplied from the system controller 150 in accordance with each data line group DGj arranged in the display panel 110 in time series.

< specific examples of Current holding/distributing portion >

A specific example of the current holding/distributing portion, which can be applied to the display device according to this embodiment, will now be described.

Fig. 4 is a circuit configuration diagram showing a configuration example of a current holding/distributing portion which can be applied to the display device according to this embodiment.

In this example, only one configuration example is explained, which can be applied to the display device according to this embodiment, and the present invention is not limited to this circuit configuration.

For example, as shown in fig. 4, each of the current distribution circuits (signal distribution sections) 141 constituting the current holding/distributing section 140A includes a switching transistor Tr41a and a switching transistor Tr41 b. In the switching transistor Tr41a, the signal current Ic output from the current generation section 130 is supplied to one end (source terminal) of the current path, the other end (drain terminal) of the current path is connected to the first output contact N41a extending to the current holding circuit 142, and the first current pickup signal WTodd as a data control signal supplied from the system controller 150 is applied to the control terminal (gate terminal). In the switching transistor Tr41b, the signal current Ic output from the current generation section 130 is supplied to one end (source terminal) of the current path, the other end (drain terminal) of the current path is connected to the second output contact N41b extended to the current holding circuit 142, and the second current acquisition signal WTevn supplied as the data control signal is applied to the control terminal (gate terminal).

Each of the current holding circuits 142 constituting the current holding/distributing section 140A has a structure in which the latch portions (signal holding/outputting portions) 142a and 142c at two stages are provided in parallel with the latch portions (signal holding/outputting portions) 142b and 142d at two stages in common, in which 142a and 142c are connected in parallel with the data line DLja in common, and the signal current Ic supplied from the current distributing circuit 141 through the first output contact N41a is supplied to 142a and 142c in common, and 142b and 142d are connected in parallel with the data line jdlb in common, and the signal current Ic supplied from the current distributing circuit 141 through the second output contact N41b is supplied to 142b and 142d in common.

For example, as shown in fig. 4, each latch portion 142a (or 142c) includes: a transistor Tr42a (or Tr42c) having a current path (source-drain) connected between the output contact N41a and the contact N42a (or N42c) of the current distribution circuit 141, and having a control terminal (gate) to which the first latch signal LCup (or the second latch signal LClw) is applied; a transistor Tr43a (or Tr43c) having a current path connected between the contact N42a (or N42c) and the contact N43a (or N43c) and having a control terminal to which the first latch signal LCup (or the second latch signal LClw) is applied; a transistor Tr44a (or Tr44c) in which one end of the current path is connected to the contact N42a (or N42c) while a predetermined low potential voltage (-Vcc) is applied to the other end thereof, and the control terminal is connected to the contact N43a (or N43 c); a transistor Tr45a (or Tr45c) in which one end of the current path is connected to the contact point N42a (or N42c) while the other end thereof is connected to the data line DLja, and the second latch signal LClw (or first latch signal LCup) is applied to the control terminal; and a storage capacitor Ca (or Cc) connected between the contact point N43a (or N43c) and the low potential voltage (-Vcc).

For example, as shown in fig. 4, each of the above-described latch portions 142b (or 142d) includes, like the latch portions 142a and 142 c: a transistor Tr42b (or Tr42d) in which a current path (source-drain) is connected between the output contact N41b and the contact N42b (or N42d) of the current distribution circuit 141, and a first latch signal LCup (or a second latch signal LClw) is applied to a control terminal (gate); a transistor Tr43b (or Tr43c) in which a current path is connected between the contact N42b (or N42d) and the contact N43b (or N43d), and the first latch signal LCup (or the second latch signal LClw) is applied to a control terminal (gate); a transistor Tr44b (or Tr44d) in which one end of the current path is connected to the contact N42b (or N42d) while a predetermined low potential voltage (-Vcc) is applied to the other end thereof, and the control terminal is connected to the contact N43b (or N43 d); a transistor Tr45b (or Tr45d) in which one end of the current path is connected to the contact point N42b (or N42d) while the other end thereof is connected to the data line DLjb, and the second latch signal LClw (or the first latch signal LCup) is applied to the control terminal; and a storage capacitor Cb (or Cd) connected between the contact point N43b (or N43d) and the low potential voltage (-Vcc).

In this embodiment, although the respective transistors Tr41a, Tr41b in the current distribution circuit and the respective transistors Tr42a to Tr45a, Tr42b to Tr45b, Tr42c to Tr45c, and Tr42d to Tr45d in the current holding circuit 142 according to this embodiment are not limited to a specific type, for example, an n-channel type field effect thin film transistor having an amorphous silicon layer as a channel layer or a field effect thin film transistor having a polysilicon layer as a channel layer may also be applied. In this case, as shown in fig. 2, the current holding/distributing part 140A may be integrated with the pixel array on the insulating substrate BASE to constitute the display panel 110A. In addition, each of the storage capacitances Ca to Cd provided in the respective latch sections 142a to 142d may be a parasitic capacitance formed between the gate and the source of each of the transistors Tr44a to Tr44d or a separately provided capacitive element.

In the above-described current holding circuit 142, the storage capacitances Ca to Cd constitute the signal holding section and the charge storage circuit according to the present invention, and the transistors Tr44a to Tr44d and Tr45a to Tr45d constitute the gradation current output section according to the present invention.

< operation of Current holding/distribution portion >

The operation of the current holding/distributing section having such a structure will now be described.

Fig. 5A and 5B are conceptual diagrams illustrating a conventional operation of the current holding/distributing section to which this embodiment can be applied.

In this example, for the latch portions 142a to 142d constituting each current holding circuit 142, for the sake of convenience, illustration and description will be given with respect to the side provided with the latch portions 142a and 142c, but the same operation is performed also on the side provided with the latch portions 142b and 142 d.

The operation of the current holding/distributing section 140A (the current distributing circuit 141 and the current holding circuit 142) according to this embodiment has: a current distributing operation of distributing a signal current (gradation signal) Ic supplied from the current generating section 130 to the output contact N41a side and the output contact N41b side in time series based on writing of display pixels of a plurality of rows (two rows in this embodiment) corresponding to the respective scanning lines SLia and SLib constituting the scanning line group SGi by the current distributing circuit 141; in synchronization with the current distributing operation, a current holding operation of taking and holding the distributed signal current Ic is performed in the latch portions 142a and 142b or the latch portions 142c and 142d constituting the current holding circuit 142; and performing a current output operation of synchronously outputting the tier current Ipix to the respective data lines DLja and DLjb constituting the data line group DGj based on the signal current Ic held in the current holding operation from the other of the latch portions 142a and 142b and the latch portions 142c and 142d constituting the current holding circuit 142 in synchronization with the current holding operation. The current holding operation and the current output operation are controlled to be selectively repeatedly performed between the latch portions 142a and 142b and the latch portions 42c and 142d constituting the current holding circuit 142 while repeating the current distributing operation in accordance with all the scanning line groups SGi in the display panel 110A.

That is, in a period in which the signal current Ic supplied from the current generating section 130 is taken and held on the side of the latch section constituting the current holding circuit 142 based on the display data according to each column, the gradation current Ipix is read and output at the same time on the other side of the latch section. Therefore, the operations of acquiring the signal current Ic based on the display data and outputting the gradation current Ipix to the data line group DGj for each column are basically performed.

Each operation will now be described in detail with reference to each circuit structure of the current holding/distributing section.

(Current sharing operation)

In the current distributing operation, in the current distributing circuit 141, by selectively setting the first and second current acquisition signals WTodd and WTevn as data control signals supplied from the system controller 150 to the high level, one of the switches Tr41a and Tr41b is turned on in sequence, and corresponding to the signal current Ic of the display pixels EM in each row, in time series, in synchronization with the timing of turning on the switches, is output from the current generating section 130. As a result, the signal current Ic is distributed in accordance with each row and is output to the individual latch portions 142a and 142c or 142b and 142d constituting the current holding portion 142 described later through each output contact N41a or N41 b.

(Current holding operation/Current output operation)

In the current holding circuit 142 (the latch portions 142a to 142d), by selectively setting the first and second latch signals LCup and LClw as data control signals supplied from the system controller 150 to the high level, the latch portions 142a and 142c connected in parallel with the output contact N41a, and one of the latch portions 142b and 142d (the latch portions 142a and 142b or the latch portions 142c and 142d) connected in parallel with the output contact N41b are set to the current holding operation state, and the remaining latch portions (the latch portions 142c and 142d or the latch portions 142a and 142b) are set to the current output operation state described later.

In the current holding operation, as shown in fig. 5A (the latch portions 142a and 142c are shown separately for convenience reasons), the first latch signal LCup is set to a high level, and the second latch signal LClw is set to a low level. As a result, in the latch portion 142a connected to the output contact N41a, the transistors Tr42a, Tr43a, and Tr44a are turned on, and the transistor Tr45a is turned off. At this time, since a portion between the gate and the drain of the transistor Tr44a is electrically short-circuited by the transistor Tr43a, the transistor Tr44a operates in a saturation region. Accordingly, the signal current Ic supplied from the current generation section 130 and output to the output contact N41a through the switch Tr41a of the current distribution circuit 141 flows to the low potential voltage (-Vcc) side through the transistors Tr42a and Tr44a of the latch section 142a, and the current level of the signal current Ic is converted into the voltage level between the gate and the source of the transistor Tr44a, so that the signal current Ic is stored in the storage capacitor Ca as electric charge.

In the current output operation, as shown in fig. 5B, the first latch signal LCup is set to a low level, and the second latch signal LClw is set to a high level. As a result, in the latch portion 142a, the transistors Tr42a and Tr43a are turned off, and the transistor Tr45a is turned on. At this time, a potential (high voltage) based on the electric charge (signal current Ic) stored in the storage capacity Ca by the current holding operation is held in the contact N43a, and thus the transistor Tr44a continues the on operation. Therefore, the data line DLja arranged in the display panel 110 (not shown) is connected to the low potential voltage (-Vcc) through the transistors Tr45a and Tr44a of the latch section 142a, and the level current Ipix flows in such a manner as to be pulled from the data line DLja side (that is, the display pixel EM side) toward the latch section 142a (current holding circuit 142).

In addition, in a state where the first latch signal LCup is set to a low level and the second latch signal LClw is set to a high level (that is, the above-described current output operation state of the latch portion 142 a), the transistors Tr42c and Tr43c are turned on, and a portion between the gate and the drain of the transistor Tr44c is electrically short-circuited by the transistor Tr43a, so that in the latch portion 142c connected in parallel with the output contact N41a, the transistor Tr44c is turned on in a saturation region and the transistor Tr45c is turned off. Accordingly, the signal current Ic output to the output contact N41a flows to the low potential voltage (-Vcc) side through the transistors Tr42c and Tr44c of the latch section 142c, and the current stage of the signal current Ic is converted into the voltage stage between the gate and the source of the transistor Tr44c, so that the signal current Ic is stored in the storage capacitor Cc as electric charge.

That is, in a period in which one of the latch portions 142a and 142c is set to the current holding operation state, the other is synchronously set to the current output operation state. Such an operation state is also performed in a combination of the door latch portions 142b and 142d, which are not illustrated.

A description has been given of an example in which a function (current polarity inverting section) is provided, a negative gradation current Ipix is generated (current direction is switched) corresponding to the signal current Ic having a positive polarity supplied from the current generating section 130, and the gradation current Ipix is pulled from the data line (display pixel) side in response to a circuit configuration of a pixel drive circuit described later, which is supplied to the display pixels EM in the current holding/distributing section 140A according to this embodiment. However, the present invention is not limited thereto, and may have a structure in which the level current Ipix having a positive polarity is generated, and the level current Ipix passes through the data line (display pixel) depending on the circuit structure of the display pixel EM.

Note that almost all known current drive circuits (corresponding to current generation sections) distributed and available on the market have a structure that outputs a level signal (signal current) having a positive polarity, and therefore a level current whose current direction is switched can be easily generated by a known current driver by applying a current holding/distributing section having the above-described structure.

< method for controlling drive of display device >

A drive control operation (drive control method) in the display device having the above-described structure will now be described.

Fig. 6 is a timing chart illustrating a drive control operation (drive control method) in the display device according to this embodiment.

In this example, a description will be given with reference to each structure of the above-described display device.

In the display device having the above-described configuration, by using the display signal generation section 160, display data including digital data that allows each display pixel (light emitting element) EM constituting the display panel 110A to emit light with a predetermined luminance level is first extracted from a video signal, and the extracted display data is sequentially supplied to the current generation section 130 as serial data corresponding to each row of the display panel 110A.

The display data (digital data) supplied to the current generating section 130 is converted into a signal current (gradation signal) Ic corresponding to the display data at a timing based on the data control signal input by the system controller 150, and is output to the current holding/distributing section 140A supplied in accordance with the data line group DGj for each column arranged in the display panel 110A.

In this example, for example, the signal current Ic output from the current generation section 130 is output in a time series in units of the data line group DGj corresponding to each column in the display panel 110A in accordance with each row of the respective display pixels EM connected to the respective data lines DLja and DLjb constituting the data line group DGj.

As shown in fig. 6, the current distribution operation is performed in the current holding/distributing portion 140A. In the current distributing operation, the signal currents Ic corresponding to the display pixels EM arranged in a plurality of rows (two rows in this embodiment) per column are sequentially acquired, the transistors or switches Tr41a and Tr41b of the current distributing circuit 141 are selectively turned on at the timing based on the data control signals (the first and second current acquisition signals WTodd and WTevn) supplied from the system controller 150, and the signal currents Ic are sequentially supplied to the latch portions 142a (or 142c) and the latch portions 142b (or 142d) of the current holding circuit 142.

Next, in synchronization with this timing, the latch portions 142a and 142b of the current holding circuit 142 are set to the current holding operation state based on the data control signals (the high-level first latch signal LCup and the low-level second latch signal LClw) supplied from the system controller 150. As a result, the current holding operation is sequentially performed only in a period in which the signal current Ic is supplied to the respective latch portions 142a and 142 b. In the current holding operation, a charge based on the signal current Ic corresponding to the display pixels EM in the respective rows (for example, the first row and the second row) is stored in the respective storage capacitances Ca and Cb.

As shown in fig. 6, such current distributing operation and current holding operation are selectively repeated in the latch portions 142a and 142b and the latch portions 142c and 142d, with appropriate setting of the signal levels of the first and second current acquisition signals WTodd and WTevn and the first and second latch signals LCup and LClw. Therefore, the signal current Ic corresponding to the display pixels EM in two rows based on the display data is held in each of the current holding circuits 142 in turn.

Subsequently, after the current holding operation, the latch portions 142a and 142b of the current holding circuit 142 are set to the current output operation state based on the data control signals (the low level first latch signal LCup and the high level second latch signal LClw) supplied from the system controller 150. As a result, a current output operation is performed in the respective latch portions 142a and 142 b. In the current output operation, a gradation current Ipix based on the electric charges stored in the respective storage capacitances Ca and Cb is synchronously supplied to the display pixels EM in the respective rows (for example, the first row and the second row) through the respective data lines DLja and DLjb constituting the data line group DGj.

Accordingly, the level current Ipix is output from the current holding/distributing section 140A through the data line group DGj for each column, and the advanced scan signal Vsel is applied from the scan driver 120A to the specific scan line group SGi at a timing based on the scan control signal supplied from the system controller 150. As a result, all the selection transistors Trsel connected to the respective scan lines SLia and SLib constituting this scan line group SGi are turned on, and the gradation current Ipix supplied to the display pixels EM in a plurality of rows (for example, two rows including the first row and the second row) through the data lines DLja and DLjb of each data line group DGj is written to the respective display pixels EM, thereby performing a light emitting operation with a predetermined luminance gradation based on the gradation current Ipix.

In addition, in the respective latch portions 142a and 142b, in a period in which the current output operation is performed, as shown in fig. 6, the latch portions 142c and 142d of the current holding circuit 142 are set to the current holding operation state based on the data control signals (the low level first latch signal LCup and the high level second latch signal LClw) supplied from the system controller 150. As a result, the current holding operation is sequentially performed. In this operation, in the respective latch sections 142c and 142d, the signal current Ic of each row continuously supplied from the current generating section 130 is acquired, and the electric charge based on the signal current Ic corresponding to the display pixels EM in the respective rows (for example, the third row and the fourth row) is stored in the respective storage capacitances Cc and Cd.

Next, after the current output operation in the latch portions 142a and 142b, the system controller 150 again sets the first latch signal LCup to the high level and the second latch signal LClw to the low level. As a result, the latch portions 142a and 142b are set to the current holding operation state again. Therefore, a current output operation is performed in the respective latch portions 142a and 142 b. In the current output operation, a charge based on the signal current Ic corresponding to the display pixels EM in the respective rows (for example, the fifth row and the sixth row) is stored in the respective capacitors Ca and Cb.

In addition, at this time, when the latch portions 142c and 142d of the current holding circuit 142 are set to the current output operation state, the current output operation is performed in which the gradation current Ipix based on the electric charges stored in the respective storage capacitances Cc and Cd at the aforementioned timing is synchronously supplied to the display pixels EM in the respective rows (for example, the third row and the fourth row) through the respective data lines DLja and DLjb constituting the data line group DGj.

As a result, in the latch portions 142a and 142b and the latch portions 142c and 142d on two stages constituting the respective current holding circuits 140A provided in accordance with the respective columns in the current holding/distributing portion, the control of synchronously performing the current holding operation and the current outputting operation is alternately repeated in accordance with a predetermined operation period. Accordingly, an operation is performed in which the signal current Ic corresponding to the display data of each row output by the current generation section 130 is continuously acquired and held in the current holding circuit and supplied in synchronization to the display pixels in a plurality of rows as the gradation current Ipix.

Therefore, this embodiment is configured in such a manner that display pixels in a plurality of rows (two rows in this embodiment) are set together in a selected state by applying a single scanning signal issued by a scanning driver to a display panel in which the plurality of display pixels are two-dimensionally arranged, and display data corresponding to the display pixels in the plurality of rows is sequentially acquired and held by the signal driver at a predetermined timing (for example, one scanning period), while gradation currents corresponding to the plurality of rows are synchronously supplied to the respective display pixels. Therefore, compared with the known drive control method in which one scan signal is applied to one scan line, the number of scan lines driven at a single scan timing (the number of rows of selected display pixels) becomes several times, and the time required to write a gradation current in a display pixel can be basically set to several times (twice in this embodiment).

In addition, since the data lines arranged in each column are formed as a data line group in which a plurality of (two in this embodiment) data lines are determined as one group, it is possible to greatly reduce (1/2 in this embodiment) the capacitance component including the holding capacitance parasitic to each data line and existing in each display pixel, or the parasitic capacitance of the driving transistor, compared to the structure of the known display device in which one data line is arranged in one column. Therefore, the time required to write the gradation current supplied to each data line in each display pixel can be reduced, or the delay of this writing time can be suppressed.

As a result, a sufficiently long time for writing the display data in each display pixel can be ensured. Therefore, when the display panel is increased in size or high definition is realized, or even when an image is displayed at a low gradation level, the wiring capacitance of the data line can be satisfactorily charged to a predetermined voltage, thereby eliminating an insufficient writing state of display data. In addition, each display pixel can be allowed to emit light with an appropriate luminance gradation corresponding to display data, and the luminance gradation (irregularity in display) generated in the display panel can be greatly reduced, thereby improving the display image quality.

The present invention is constituted in such a manner that the scanning lines arranged in each row are formed as a scanning line group in which a plurality of (two in this embodiment) scanning lines are determined as one group, and by using a single scanning signal, a plurality of rows (two rows in this embodiment) of display pixels are set in a selected state together. Therefore, the number of scan signals output from the scan driver to the display panel (1/2 in this embodiment) can be greatly reduced, and the number of connection terminals between the display panel and the scan driver (1/2 in this embodiment) can be greatly reduced. As a result, even if high definition is realized in the display panel, an increase in the number of output terminals of the driver chip can be suppressed, and the pitch (gap) between the terminals can be prevented from becoming small, thereby simplifying the positional accuracy of the connection step of the driver chip, or reducing the number of steps.

In addition, when a field effect thin film transistor in which an amorphous silicon layer or a polycrystalline silicon layer is used as a channel layer is applied to each transistor constituting a current holding/distributing portion, the current holding/distributing portion can be integrated on the same substrate as a display panel (pixel array), and an increase in the number of devices can be suppressed, thereby keeping the production cost of the display device down.

The example has been described above in which the scanning line groups are arranged so as to correspond to, for example, display pixels in two rows, and the data line groups corresponding to the display pixels in two rows are arranged so that the display pixels in two rows can be synchronously set to a selected state by using a single scanning signal, as the first embodiment of the display device according to this embodiment. However, the present invention is not limited thereto. Another structural example of the display device according to this embodiment will now be described.

Fig. 7 is a schematic configuration diagram showing a main part of another configuration example of the display device according to this embodiment.

Fig. 8 is a schematic configuration diagram showing a main part of still another configuration example of the display device according to this embodiment.

That is, for example, as shown in fig. 7, the display panel 110A may be configured to have each scan line group SGi arranged to correspond to two or more rows (four rows), and each data line group DLj including a plurality (four) of data lines DLja to DLjd, the number (four) of which corresponds to the plurality of rows, arranged according to each pixel row. By using a single scanning signal Vsel, the display pixels EM in a plurality of rows (four rows) can be set to the selected state synchronously.

As shown in fig. 8, as a configuration of one scan line group arranged so as to correspond to a plurality of rows (layout format of scan lines), for example, one scan line SLi may be extended (drawn) (transition direction) without being divided within the display panel 110A and connected in common to the display pixels EM in a plurality of rows (two rows).

< second embodiment of display device >

A second embodiment of a display device according to the invention will now be described with reference to the accompanying drawings.

Fig. 9 is a structural diagram showing a main part of a second embodiment of a display device according to the present invention.

Here, the structures equivalent to those in the first embodiment are denoted by the same or similar reference numerals, and therefore, explanations thereof are omitted.

The display device according to the first embodiment described above includes: a display panel in which each scan line group SGi corresponding to a plurality of rows and each data line group DGj including a plurality of data lines corresponding to a plurality of rows are arranged; and peripheral circuits (a scan driver and a signal driver including a current generating section and a current holding/distributing section) corresponding to the display panel. A display device according to a second embodiment includes: a display panel in which each scan line provided in accordance with each row and each data line group including a plurality of data lines corresponding to a plurality of rows are arranged; and peripheral circuits (a scan driver and a signal driver including a current generating section and a current holding/distributing section) corresponding to the display panel.

As shown in fig. 9, the display panel 110B according to this embodiment generally includes: a plurality of display pixels EM arranged in two dimensions (n rows × m columns) and connected to each other through a selection transistor Trsel; a plurality of scanning lines SLq arranged in accordance with the display pixels EM in each row (q is a positive integer falling within a range of 1. ltoreq. q. ltoreq.n; n is a positive integer and is a set total number of rows of pixels in the display panel 110); and a plurality of data line groups DGj arranged in accordance with the display pixels EM in each column, and in which a plurality of (two in this embodiment) data lines DLja and DLjb (j is a positive integer falling within a range of 1. ltoreq. j.ltoreq.m; m is a positive integer and is the total number of columns of pixels set in the display panel 110) are determined as one group. Each display pixel EM is disposed at each intersection of the scan line SLq and the data lines DLja and DLjb constituting each data line group DGj.

The scan driver (selection circuit) 120B is normally connected to the scan lines SLq in the display panel 110B, and sequentially applies a scan signal Vsel to each of the scan lines SLq at a predetermined timing to sequentially set the display pixels EM connected to the scan lines SLi in each row (one row) to a selected state.

The current generation section 130 normally generates a signal current (gradation signal) Ic having a current value corresponding to a luminance gradation value based on the display data in accordance with the display data supplied from the display signal generation section 160.

The current holding/distributing section 140B is generally connected to each data line group DGj in the display panel 110B. The section 140B acquires the signal current Ic supplied from the current generation section 130 corresponding to each row (two rows in this embodiment) in time series, and sequentially applies the gradation current Ipix based on the signal current Ic to the display pixels EM in a plurality of rows (two rows in this embodiment) at predetermined timing. In this embodiment, the current generation section 130 and the current holding/distributing section 140B constitute a signal driver 200B.

Note that in the structure shown in fig. 9, the current holding/distributing portion 140B is integrated with the pixel array on the insulating substrate BASE on which the plurality of display pixels EM (that is, the pixel array) constituting the display panel 110B are formed as a structural example, but the present invention is not limited thereto. For example, the signal driver 200B may have a configuration of a driver chip and be mounted (packaged) on the BASE substrate. Details will be described later.

The specific configuration of each structure will now be described.

(display panel)

For example, as shown in fig. 9, the display panel 110 has a structure in which each scan line SLq corresponding to each pixel row and each data line group DGj having two data lines DLja and DLjb are determined as one group and correspond to one pixel column, the scan lines and the data lines are arranged perpendicular to each other, and the display pixel EM is connected to the intersection of the odd scan line SLi and the data line DLja in each column and the intersection of the even scan line SLi and the data line DLjb in each column, and the display panel can be applied to the display device according to this embodiment.

In this embodiment, in the structure shown in fig. 9, although the data line group DGj arranged in each column is configured to have two data lines DLja and DLjb determined as one group, the present invention is not limited thereto, and two or more data lines may be determined as one group. In this case, when the number of data lines constituting the data line group DGj is q (that is, the number of data lines DLj1 to DLjq is q), a structure is provided in which a display pixel EM is connected to an intersection of a scan line in each row and a first data line DLj1 in each column, where the row can be calculated by dividing the number of lines by q and remaining 1 (each scan line of the first, q +1, 2q + 1.... times. rows), the display pixel EM is connected to an intersection of a scan line in each row and a second data line DLj2 in each column, where the row can be calculated in the same manner and remaining 2 (each scan line of the second, q +2, 2q + 2.. times. rows), the display pixel and the data line are connected in the same relationship, and the display pixel EM is connected to an intersection of a scan line in each row and a q-th (last) data line DLjq in each column, where the row can be calculated in the same way with the remainder 0 (q, 2q, 3 q.... for each scan line of the row).

In addition, like the display pixels EM in fig. 2, each display pixel EM generally has a structure in which a gate terminal is connected to each scanning line SLi, a source terminal is connected to a drain terminal of a selection transistor Trsel connected to each data line DLja or DLjb, and includes a current control type light emitting element in which light having a predetermined luminance gradation is emitted based on a gradation current Ipix supplied through the selection transistor Trsel.

In the display panel 110B having such a structure, by applying the scan signal Vsel from the scan driver 120B described later to the scan line SLi in a certain row, the selected transistor Trsel connected to this scan line SLi is turned on, and the display pixels EM in this row are set to the selected state together. In this selected state, when the level current Ipix corresponding to the display data is supplied to a specific data line in each of the data line groups DGj in synchronization, the display data is written in synchronization to the display pixels set to the selected state in this row through the selection transistor Trsel which has been turned on.

(Scan driver)

The scan driver 120B sequentially performs the application of the scan signal Vsel of the selection stage (i.e., the high stage) to each of the scan lines SLq based on the scan control signal supplied from the system controller 150, so that the display pixels EM connected to each of the scan lines SLi in each row are synchronously set to the selected state, and at least the display pixels EM in the adjacent rows are synchronously set to the selected state for a predetermined period. That is, for example, as shown in fig. 9, the scan driver 120 includes shift modules SB1, SB2, n., SBi, n, each including a shift register and a buffer at a plurality of stages (n stages in this embodiment) according to the respective scan lines SLq. The shift signal, which is output when sequentially shifted from the upper portion to the lower portion in the display panel 110 through the shift register, is applied to each of the scan lines SLq through each of the buffers as a scan signal Vsel having a predetermined selection level (high level) based on scan control signals (a scan start signal SST, a scan clock signal SCK, and the like) supplied from the system controller 150. Here, in this embodiment, in the scan driver having the above-described structure, for example, the scan clock signal SCK is set to a regular time width which sets a selected state (a selection time width of each row to which the scan signal Vsel is applied) in a predetermined period (one horizontal scan period) in accordance with each row, and the scan start signal SST is set to a selection time width of two rows (two horizontal scan periods). As a result, a shift signal having a time width of two rows is shifted between the respective shift modules SB1, SB2, and SBi, and SBn, and a scan signal Vsel based on the shift signal is applied to at least the adjacent scan lines SLi in an overlapping manner within a predetermined period.

(Current generating section)

The current generation section 130 has the same structure as the current generation section 130 in the first embodiment as shown in fig. 3, and repeatedly performs operations in sequence for one screen. In this operation, the current generation section 130 sequentially acquires display data corresponding to a plurality of rows (two rows in this embodiment) of display pixels in each of the data line groups DGj at a predetermined timing, supplies the display data from the display signal generation section 160 based on a data control signal input from the system controller 150, generates a signal current (gradation signal) Ic having a current value corresponding to a gradation value of the luminance of the display data, and sequentially supplies the signal currents Ic of the plurality of rows in time series according to each column to the current holding/distributing section 140B.

(Current holding/distributing section)

The current holding/distributing section 140B sequentially acquires and holds the plural lines of signal currents Ic corresponding to each of the data line groups DGj, which are supplied from the current generating section 130 based on the data control signal input from the system controller 150 in the time series, at a predetermined timing. The section 140B synchronously supplies the signal current Ic as the gradation current Ipix to the display pixels EM in each row which are set to the selected state through each of the data line groups DGj.

Specifically, for example, as shown in fig. 9, the current holding/distributing section 140B includes at least a plurality of current holding/distributing circuits 143 provided in accordance with respective data line groups DGj arranged in the display panel 110B. In addition, the current holding/distributing section 140B distributes and holds the signal current Ic supplied from the current generating section 130 in time series in accordance with the plurality of (two in the present embodiment) data lines DLja and DLjb in each data line group DGj at the timing of setting each scanning line SLq to the selected state, and sequentially supplies the gradation current Ipix based on the held signal current Ic to the display pixels EM of the respective data lines DLja and DLjb.

Note that the specific structure and operation of the current holding/distributing portion 140B will be described in detail later.

< specific examples of Current holding/distributing portion >

A specific example of the current holding/distributing section that can be applied to the display device according to this embodiment will now be described.

Fig. 10 is a circuit configuration diagram showing a configuration example of a current holding/distributing portion that can be applied to the display device according to this embodiment.

Note that only a configuration example that can be applied to the display device according to this embodiment is described here, and the present invention is not limited to this example.

The current holding/distributing circuits 143 each constituting the current holding/distributing section 140B are configured, for example, as shown in fig. 10 so as to have a secondary latch section including a holding section (signal holding/outputting section) 143a connected to the data line DLja and a latch section (signal holding/outputting section) 143B connected to the data line DLjb, these sections 143a and 143B being connected in common in parallel with the signal current Ic outputted from the current generating section 130 being supplied. Data lines DLja and DLjb form each data line group DGj.

For example, as shown in fig. 10, the current holding/distributing section 143a includes a transistor Tr46a in which the signal current Ic output from the current generating section 130 is supplied to one end (source or drain) of the current path, the other end thereof is connected to the contact N46a, and the first current pickup signal WTodd is applied to the control terminal (gate); a transistor Tr47a, wherein a current path is connected between the contact N46a and the contact N47a, and the first current acquisition signal WTodd is applied to the control terminal; a transistor Tr48a in which one end of the current path is connected to the contact N46a, the other end thereof is connected to the low potential voltage (-Vcc), and the control terminal is connected to the contact N47 a; a transistor Tr49a in which one end of the current path is connected to the low potential voltage (-Vcc), the other end thereof is connected to the data line DLja, and the control terminal is connected to the contact N47 a; and a storage capacitor Ce connected between the contact N47a and the low potential voltage (-Vcc).

In addition, the current holding/distributing section 143b also includes, for example, as shown in fig. 10, a transistor Tr46b in which the signal current Ic output from the current generating section 130 is supplied to one end (source or drain) of the current path, the other end thereof is connected to the contact N46b, and the second current take-out signal WTevn is applied to the control terminal (gate); a transistor Tr47b in which a current path is connected between the contact N46b and the contact N47b, and the second current acquisition signal WTevn is applied to the control terminal; a transistor Tr48b in which one end of the current path is connected to the contact N46b, the other end thereof is connected to the low potential voltage (-Vcc), and the control terminal is connected to the contact N47 b; a transistor Tr49b in which one end of the current path is connected to a low potential voltage (-Vcc), the other end thereof is connected to the data line DLjb, and the control terminal is connected to the contact N47 b; and a storage capacitor Cf connected between the contact N47b and the low potential voltage (-Vcc).

Here, in the current holding/distributing section 140B according to this embodiment, for example, an n-channel type field effect thin film transistor in which an amorphous silicon layer is a channel layer, or a field effect thin film transistor in which a polysilicon layer is a channel layer may be applied as each of the transistors Tr46a to Tr49a and Tr46B to Tr 49B. In this case, as shown in fig. 9, the current holding/distributing part 140B may be integrated with the pixel array on the insulating BASE constituting the display panel 110B.

In addition, each of the storage capacitances Ce and Cf provided to the respective latch sections 143a and 143b may be a parasitic capacitance formed between the gate and the source of each of the transistors Tr49a and 49b, or a capacitive element provided separately.

In the current holding/distributing circuit 143, the storage capacitances Ce and Cf constitute a signal holding section and a charge storage circuit according to the present invention, the transistors Tr46a, Tr47a, Tr46b, and Tr47b constitute a signal distributing section according to the present invention, and the transistors Tr48a, Tr49a, Tr48b, and Tr49b constitute a hierarchical current output section according to the present invention.

The current holding/distributing part having the above-described structure in the present invention will now be explained.

Fig. 11A and 11B are conceptual diagrams illustrating a conventional operation of the current holding/distributing section to which this embodiment can be applied.

The operation of the current holding/distributing section 140B (current holding/distributing circuit 143) according to this embodiment has: a current holding/output operation of sequentially acquiring, in time series, the signal current Ic based on the display data corresponding to the display pixels in two rows supplied from the current generation section through the respective latch sections 143a and 143b of the current holding/distributing circuit 143, generating the gradation current Ipix based on the signal current (gradation signal) Ic, and individually outputting the generated signals to the respective data lines DLja and DLjb constituting the data line group DGj at predetermined timings; and a current output holding operation of continuously outputting the stage current Ipix in the current holding/output operation for a predetermined period. The current holding/distributing portion 140B is controlled to alternately repeat the current holding/outputting operation and the current output holding operation in partially overlapping periods between the latch portions 143a and 143B connected in parallel. As a result, the output periods of the gradation current Ipix output from the respective latch portions 143a and 143b in the current holding/output operation can be set to partially overlap.

This operation will now be described in detail with reference to each circuit structure in the current holding/distributing section.

In the current holding/distributing circuit 143 (the latch sections 143a and 143b), the first and second current acquisition signals WTodd and WTevn supplied as the data control signals from the system controller 150 are selectively set to high levels. As a result, one of the latch portions 143a and 143b (the latch portion 143a or 143b) is set to a current holding/output operation state in which the signal current Ic is taken and the gradation current Ipix corresponding to the signal current Ic is output, and the other latch portion (the latch portion 143b or 143a) is set to a current output holding operation state in which the output state of the gradation current Ipix in the current holding/output operation state of the aforementioned timing is continued.

Specifically, in the current holding/output operation, as shown in fig. 11A, the first current pickup signal WTodd is set to a high level, and the second current pickup signal WTevn is set to a low level. As a result, in the latch portion 143a, the transistors Tr46a and Tr47a are turned on, and a portion between the gate and the drain of the transistor Tr48a is electrically short-circuited by the transistor Tr47a, so that the transistor Tr48a is turned on in a saturation region. As a result, the signal current (gradation signal) Ic supplied from the current generation section 130 flows to the low potential voltage (-Vcc) side through the transistors Tr46a and Tr48a of the latch section 143a, and the current level of the signal current Ic is converted into the voltage level between the gate and the source of the transistor Tr48a, so that the signal current Ic is stored as electric charge in the storage capacitor Ce.

At this time, as the electric charge is stored in the storage capacitor Ce, the transistors Tr48a and Tr49a constituting the current mirror circuit are turned on by the increase of the electric potential at the contact N47a, and the gradation current Ipix flows in such a manner that the gradation current Ipix having a predetermined current ratio set in the current mirror circuit with respect to the signal current Ic is pulled from the data line Dlja side to the low potential voltage (-Vcc) direction (that is, from the display pixel EM side to the latch portion 143a) through the transistor Tr49 a.

In the current output holding operation, as shown in fig. 11B, the first current pickup signal WTodd is set to a low level, and the second current pickup signal WTevn is set to a high level. As a result, in the latch portion 143a, the transistors Tr46a and Tr47a are turned off. At this time, since the potential (high voltage) based on the electric charge (signal current Ic) stored in the storage capacity Ca is held at the contact N47a by the current holding/output operation, the transistor Tr49a continues the on state. Thus, the operation state is maintained in which the level current Ipix is pulled from the data line DLja side toward the latch portion 143a (current holding/distributing circuit 143).

In addition, in a state where the first current pickup signal WTodd is set to a low level and the second current pickup signal WTevn is set to a high level (that is, the current output of the above-described latch section 143a is kept in an operating state), the transistors Tr46b and Tr47b are turned on, and a portion between the gate and the drain of the transistor Tr48b is electrically short-circuited by the transistor Tr47b, so that the transistor Tr48b is turned on in a saturation region in the latch section 143b connected in parallel with the latch section 143 a. Thus, the current holding/output operation is performed. In this operation, the signal current Ic flows to the low voltage potential (-Vcc) through the transistors Tr46b and Tr48b of the latch portion 143b, and the current level of the signal current Ic is converted into the voltage level between the gate and the source of the transistor Tr48b, so that the signal current Ic is stored as electric charge in the storage capacitor Cf. In addition, as the potential at the contact point N47b increases, the transistors Tr48b and Tr49b constituting the current mirror circuit are turned on, and the gradation current Ipix flows in such a manner that the gradation current Ipix, which has a predetermined current ratio with respect to the signal current Ic, is pulled from the data line DLjb side to the low potential voltage (-Vcc) side (that is, from the display pixel EM side to the latch portion 143b) through the transistor Tr49 b.

That is, in a period in which one of the latch portions 143a and 143b is set to the current holding/output operation state, the other portion is simultaneously set to the current output holding operation state.

Note that description has been given regarding an example in which a negative gradation current Ipix is generated corresponding to the signal current Ic having a positive polarity supplied from the current generation section 130, and the gradation current Ipix is pulled from the data line (display pixel) side in the current holding/distributing section 140B in response to a circuit configuration of a pixel drive circuit provided in the display pixel EM described later. However, the current holding/distributing section 140B may have a structure in which the level current Ipix having the positive polarity is generated, and the level current Ipix passes through the data line (display pixel) depending on the circuit structure of the display pixel EM.

< method for controlling drive of display device >

The driving control operation in the display device having the above-described structure will now be explained.

Fig. 12 is a timing chart showing a driving control method of the display device according to this embodiment.

In the display device having the above-described configuration, display data including digital data for making each display pixel (light emitting element) EM constituting the display panel 110B have a predetermined luminance gradation is first extracted from a video signal by the display signal generation section 160, and the extracted display data is then sequentially supplied to the current generation section 130 as serial data corresponding to each row of the display panel 110B.

The display data supplied to the current generation section 130 is converted into a signal current (gradation signal) corresponding to the display data at a timing based on a data control signal input from the system controller 150, and is output to the current holding/distributing section 140B provided in accordance with each column data line group DGj arranged in the display panel 110B.

In the current holding/distributing section 140B, as shown in fig. 12, the latch section 143a of the current holding/distributing circuit 143 is set to the current holding/output operating state based on the data control signals (the high-level first current acquisition signal WTodd and the low-level second current acquisition signal WTevn) supplied from the system controller 150. As a result, the current holding/output operation is performed. In this operation, the signal current Ic corresponding to the display pixels EM in each column is acquired for one row (for example, the first row), and electric charges based on the signal current Ic are stored in the storage capacitance Ce. Meanwhile, a level current Ipix having a predetermined current value is generated based on the electric charge stored in the storage capacitor Ce and the current ratio set by the current mirror circuit (the transistors Tr48a and Tr49a), and the generated level current Ipix is supplied to each display pixel EM in this row (first row) through each data line DLja.

Subsequently, after the current holding/outputting operation, the latch portion 143a of the current holding/distributing circuit 143 is set to the current output holding operation state based on the data control signals (the low-level first current acquisition signal WTodd and the high-level second current acquisition signal WTevn) supplied from the system controller 150. As a result, the current output holding operation is performed. In this operation, the gradation current Ipix based on the electric charge stored in the storage capacitor Ce (i.e., the signal current Ic) is continuously supplied to each display pixel EM in this row (first row) through each data line DLja in the latch section 143 a.

On the other hand, as shown in fig. 12, in the latch portion 143a, in a period in which the current output holding operation is performed, the latch portion 143b of the current holding/distributing circuit 143 is set to the current holding/output operation based on the data control signals (the low-level first current acquisition signal WTodd and the high-level second current acquisition signal WTevn) supplied from the system controller 150. As a result, the current holding/output operation is performed. In this operation, the signal current Ic for the next row (for example, the second row) continuously supplied from the current generation section 130 is acquired in the latch section 143b, and electric charges are stored in the storage capacitor Cf. Meanwhile, a gradation current Ipix having a predetermined current value is generated based on the electric charge stored in the storage capacitance Cf and the current ratio set by the current mirror circuit (the transistors Tr48b and Tr49b), and the generated gradation current Ipix is then supplied to each display pixel EM in this row (the second row).

Next, after the current output maintaining operation in the latch section 143a, the system controller 150 sets the first current acquisition signal WTodd to the high level and the second current acquisition signal WTevn to the low level again. As a result, the latch portion 143a is set to the current holding/outputting operation state again. Thus, the current holding/output operation is performed. In this operation, the charge based on the signal current Ic for the next row (for example, the third row) is stored in the storage capacitor Ce. Meanwhile, a level current Ipix based on the ratio of the electric charge stored in the storage capacitor Ce and the current set by the current mirror circuit is supplied to each display pixel in this row (third row) through each data line DLja.

In addition, at this time, when the latch portion 142b of the current holding/distributing portion 143 is set to the current output holding operation state, the current output holding operation is performed. In this operation, each display pixel EM of one row, which is one subject (second row) of the current holding/output operation, is supplied with the gradation current Ipix based on the electric charge stored in the storage capacitance Cf at the aforementioned timing through each data line DLjb.

As a result, in the current holding/distributing section 140B, control of simultaneously performing the current holding/outputting operation and the current output holding operation is alternately repeated with a predetermined operation period between the latch sections 143a and 143B on two stages provided in accordance with each column, the latch sections constituting each current holding/distributing circuit 143. As a result, the operation is performed in which, in the current holding circuit, the signal current Ic sequentially supplied from the current generating section 130 corresponding to the display data of each row is continuously acquired and held, and at the same time, the signal current Ic is synchronously supplied to the display pixels in each row as the gradation current Ipix.

Therefore, the level current Ipix is output from the current holding/distributing section 140B via the data line group DLj of each column, and the advanced scan signal Vsel is applied from the scan driver 120 to at least the adjacent scan line SLq in an overlapping manner at a timing based on the scan control signal supplied from the system controller 150 in a predetermined period. As a result, the gradation current Ipix sequentially supplied through the data lines DLja and DLjb of each data line group DLj is written into the display pixels EM in a plurality of rows (for example, two rows including the first row and the second row) corresponding to the respective scanning lines SLi, and the light emitting operation is performed at a predetermined luminance gradation based on the gradation current Ipix.

As described above, in this embodiment, by applying the scanning signals in an overlapping manner from the scanning driver to at least adjacent scanning lines in the display panel having a plurality of two-dimensionally arranged display pixels therein within a predetermined period, the display pixels in each row are sequentially set to the selected state, and the display data corresponding to the display pixels in each row are sequentially acquired and held at each latch section by the signal driver. At the same time, the level current for each row is supplied to each display pixel in turn. Accordingly, the gradation current based on the display data can be synchronously written in the display pixels in a plurality of rows having a simple structure including latch portions corresponding to a plurality of data lines constituting the data line group in each row, thereby setting the gradation current writing time to be substantially longer.

Specifically, as shown in fig. 9, in the structure in which the data line group arranged in each column includes two data lines and two latch portions, which are provided in the current holding/distributing portion in accordance with each data line group, it is possible to set 1/2, which is a period in which display pixels are selected for a scanning period in a specific row, to overlap with a period in which display pixels are selected in the next row. That is, it is possible to set the selection periods to overlap in adjacent rows only in a period corresponding to the number of data lines constituting the data line group.

In addition, like the first embodiment, the number of display pixels (1/2 in this embodiment) connected to each data line constituting a data line group in each column can be greatly reduced compared to the known display device in which one data line is arranged in one row. Accordingly, a capacitance component including a holding capacitance provided in the display element or a parasitic capacitance of the driving transistor can be reduced, and thus a time required to write a gradation current supplied to the data line in the display pixel can be reduced, or a delay in this writing time can be suppressed.

Note that this embodiment is configured in such a manner that display data corresponding to display pixels in each row is acquired and held in each latch section by a signal driver, and at the same time, a gradation current for each row is generated and supplied to each display pixel in turn, so that a latch operation in a current holding/distributing circuit (latch section) can be performed quickly. If the timing of the latch operation deviates due to a signal delay or the like, there is a possibility that the display operation is hindered.

Thus, in this embodiment, the latch operation of the display data (signal current) in the current holding/distributing circuit (latch portion) is performed quickly with a small current, and the current mirror circuit structure is applied to the output stage of each data line. As a result, the current value (absolute value) of the gradation current can be simply controlled to obtain a large current, and delay in the latch operation can be suppressed.

As described above, in fig. 9, each transistor constituting each current holding/distributing circuit 143A in the current holding/distributing section 140B includes an n-channel type field-effect thin film transistor having an amorphous silicon semiconductor layer as a channel layer or a field-effect thin film transistor having a polysilicon semiconductor layer as a channel layer, and this current holding/distributing section 140B is integrated with a pixel array on an insulating substrate BASE on which a plurality of display pixels EM constituting the display panel 110B are formed. However, the present invention is not limited to this structure.

For example, the present invention may have a configuration in which the signal driver including the current generation section and the current holding/distributing section is an independent driver chip, and this driver chip is mounted (packaged) on the substrate of the display panel.

An example of the structure in this case will now be briefly explained.

Fig. 13 is a schematic configuration diagram showing a main part of another configuration example in the second embodiment of the display device according to the present invention.

Here, structures equivalent to those of the foregoing structure example structures are denoted by similar or identical reference numerals, and thus the explanation is simplified.

In fig. 13, the signal driver 200C including the current holding/distributing section 140B and the current generating section 130 is configured as an independent driver chip. Here, for example, the current holding/distributing circuit 143 in fig. 13 includes a plurality of field effect transistors or the like formed on a single-crystal silicon substrate. The driver chip constituting this signal driver 200C is configured to be mounted (packaged) on the BASE constituting the display panel 110B.

< specific circuit example of display Pixel >

Specific circuit examples of display pixels that can be applied to the display device according to the present invention will now be described with reference to the accompanying drawings.

Fig. 14 is a circuit configuration diagram showing a specific circuit example of a display pixel which can be applied to a display device according to the present invention.

Fig. 15A and 15B are conceptual diagrams illustrating a driving control operation of the pixel driving circuit according to this embodiment.

Fig. 16 is a schematic block diagram showing a structural example of a display device to which the display pixel according to this embodiment can be applied.

Fig. 17 is a schematic block diagram showing another configuration example of a display device to which the display pixel according to this embodiment can be applied.

As shown in fig. 14, a display pixel EM' (the structure including the display pixel EM and the selection transistor Trsel described in association with the first embodiment) is generally configured to have: a pixel driving circuit DC which sets the display pixel EM' to a selected state in which the level current Ipix supplied from the current holding/distributing section 140A or 140B is taken out and a driving current corresponding to the level current Ipix is passed to the light emitting element, based on a scanning signal Vsel applied by the scanning driver 120A or 120B; and a current control type light emitting element including an EL element or an OEL element which emits light having a predetermined luminance gradation based on a driving current supplied from the pixel driving circuit DC.

For example, as shown in fig. 14, the pixel drive circuit DC includes: an N-channel type transistor Tr11 in which a control terminal (gate terminal) is connected to a scan line SLi (corresponding to the scan lines SLia, and SLib or SLq constituting the scan line group SGi described in association with each of the foregoing embodiments), and a current path (source-drain) is connected to the power supply line VL and the contact N11; an N-channel type transistor Tr12 in which a control terminal is connected to the scan line SLi, and a current path is connected to the data line DLj (each of the data lines DLja or DLjb constituting the data line group DGj described in association with each of the foregoing embodiments) and the contact N12; an N-channel type transistor Tr13 in which a control terminal is connected to the contact N11, and a current path is connected to the power supply line VL and the contact N12; and a capacitance (holding capacitance) Cs connected between the contact N11 and the contact N12. The anode terminal of the organic EL element OEL is connected to the contact N12, and the cathode terminal of the element is connected to the ground terminal. Here, the capacitance Cs may be a parasitic capacitance formed between the gate and the source of the transistor Tr 13. In addition, the transistor Tr12 corresponds to the selection transistor Trsel described in association with each of the foregoing embodiments.

By, for example, synchronously setting the display pixels EM' in a plurality of rows to a selected state within a scanning period Tsc as one cycle, light emission drive control of the light emitting elements (organic EL elements OEL) in the pixel drive circuit DC having such a structure is performed so that the selected states of the display pixels overlap within a predetermined period, and a selection period (write operation period) Tse in which a drive current Ipix corresponding to display data is written and held as a voltage component is set, and a non-selection period (light emission operation period) Tnse in which a drive current corresponding to display data is supplied to the organic EL elements based on the voltage component written and held in the selection period Tse to emit light having a predetermined luminance gradation (Tse ═ Tse + Tnse) are set.

(selection period)

That is, in the selection period Tse of the display pixels EM ', the display pixels EM' in a plurality of rows are first synchronously (or overlapping for a predetermined period) set to a selected state by applying the high-level scan signal Vsel from the scan driver to the specific scan line SLi, and at the same time, the low-level power supply voltage Vsc is applied to the power supply lines VL of the display pixels in a plurality of rows. In addition, in synchronization with this timing, a gradation current Ipix having a negative polarity is supplied from the current holding/distributing section to each data line DLj corresponding to display data of the display pixels EM' in a plurality of rows.

As a result, as shown in fig. 15A, the transistors TR11 and TR12 constituting the pixel drive circuit DC are turned on, and the low-stage power supply voltage Vsc is applied to the contact N11 (that is, the gate terminal of the transistor TR13 and one end of the capacitor Cs). In addition, an operation of pulling the level current Ipix to the current holding/distributing portion through the data line DL is performed. As a result, a voltage level having a potential lower than the power supply voltage Vsc of the low level is applied to the contact N12 (that is, the source terminal of the transistor Tr13 and the other end of the capacitor Cs).

In this way, a potential difference is generated between the contacts N11 and N12 (between the gate and the source of the transistor Tr 13). As a result, the transistor Tr13 is turned on, and the write current Ia corresponding to the gradation current Ipix flows from the power supply line VL to the current holding/distributing section through the transistor Tr13, the contact N12, the transistor Tr12, and the data line DL.

At this time, electric charges corresponding to the potential difference generated between the contacts N11 and N12 (between the gate and the source of the transistor Tr 13) are stored in the capacitor Cs and held (charged) as a voltage component. In addition, a power supply voltage Vsc having a voltage level not higher than the ground potential is applied to the power supply line VL, and the write current Ia is controlled to flow in the direction of the data line DL. Therefore, the potential applied to the anode terminal (contact N12) of the organic EL element becomes lower than the potential (ground potential) of the cathode terminal, and a reverse bias voltage is applied to the organic EL element OEL. Therefore, the driving current does not flow through the organic EL element OEL, and the light emitting operation is not performed.

(non-selection period)

Subsequently, in a non-selection period Tnsec after the completion of the selection period Tse, the low-level scan signal Vsel is applied from the scan driver to the specific scan line SLi so that the display pixels in the plurality of rows are set to a non-selected state, and the high-level power supply voltage Vsc is applied to the power supply lines VL of the display pixels in the plurality of rows. In addition, in synchronization with this timing, the operation of pulling the level current Ipix performed by the current holding/distributing section is terminated.

As a result, as shown in fig. 15B, the transistors Tr11 and Tr12 constituting the pixel drive circuit DC are turned off, and the application of the power supply voltage Vsc to the contact N11 (that is, the gate terminal of the transistor Tr13 and one end of the capacitor Cs) is interrupted. In addition, due to the operation of pulling the level current Ipix performed by the current holding/distributing section, the application of the voltage level to the contact point N12 (that is, the source terminal of the transistor Tr13 and the other end of the capacitance Cs) is interrupted. Therefore, the capacitor Cs holds the charge stored in the selection period.

When the capacitance Cs holds the charge voltage in the writing operation in this way, a potential difference between the contacts N11 and N12 (between the gate and the source of the transistor Tr 13) is held, and thus the transistor Tr13 maintains an on state. In addition, since the power supply voltage Vsc having a voltage level higher than the ground potential is applied to the power supply line VL, the potential applied to the anode terminal (contact N12) of the organic EL element OEL becomes higher than the potential of the cathode terminal (ground potential).

Accordingly, a predetermined drive current Ib flows from the power supply line VL to the organic EL element OEL in the direction of forward bias through the transistor Tr13 and the contact N12, and the organic EL element OEL emits light. Here, since the potential difference (charge voltage) held by the capacitance Cs corresponds to the potential difference at the time of introducing the write current Ia corresponding to the gradation current Ipix into the transistor Tr13, the drive current Ib flowing through the organic EL element OEL has the same current value as the write current Ia.

As a result, in the non-selection period Tnse after the selection period Tse, the drive current is continuously supplied through the transistor Tr13 based on the voltage component corresponding to the display data (gradation current Ipix) written in the selection period Tse, and the organic EL element OEL is continuously operated to emit light having a gradation of luminance corresponding to the display data.

Next, based on the driving control operation of the display device, the series of operations are repeatedly performed in sequence for all the scanning lines SLi constituting the display panel 110A or 110B. As a result, display data on one screen of the display panel is written, light having a predetermined luminance gradation is emitted, and desired image information is displayed.

Here, in the image drive circuit DC according to this embodiment, since the transistors Tr11 to Tr13 can be constituted by using transistors having the same channel polarity (n-channel type), it is possible to apply an n-channel type field effect thin film transistor in which an amorphous silicon layer is used as a channel layer, or a field effect thin film transistor in which a polysilicon layer is used as a channel layer, like the circuit structures of the current holding/distributing sections (the current distributing circuit, the current holding circuit, and the current holding/distributing circuit) 140A and 140B. In this case, the current holding/distributing parts 140A and 140B and the display panels 110A and 110B may be integrated on a single insulating substrate. In particular, when the display panel and the current holding/distributing portion are constituted by applying an n-channel type field effect thin film transistor using an amorphous silicon semiconductor layer, a field effect thin film transistor having stable operation characteristics can be manufactured relatively inexpensively by applying a certain amorphous silicon manufacturing technique. Therefore, even if high definition of the display panel is realized or the size of the display panel is increased, a display device having good display image quality can be easily and excellently realized.

Here, as a structure of applying the predetermined power supply voltage Vcs to the power supply line VL in the pixel driving circuit DC according to this embodiment, with respect to the structure described in fig. 2, for example, as shown in fig. 16, it is possible to excellently apply a structure in which the power supply driver 170A connected to each power supply line group VGi is provided in the peripheral region of the display panel 110C in which each power supply line group VGi including the power supply lines VLia and VLib is arranged in parallel with the respective scanning lines SLia and SLib of each scanning line group SGi, and the power supply voltage Vcs having a predetermined voltage value is applied from the power supply driver 170A to each power supply line group VGi based on the power supply control signal input from the system controller 150 in synchronization with the timing of outputting the scanning signal Vsel from the scanning driver 120A.

In addition, with respect to the structure described with reference to fig. 13, for example, as shown in fig. 17, it is possible to excellently apply a structure in which a power supply driver 170B connected to each power supply line VLi is provided in a peripheral region of the display panel 110D in which each power supply line VLi is arranged in parallel with each scanning line SLi in each row, and a power supply voltage Vcs having a predetermined voltage value is applied from the power supply driver 170B to each power supply line VLi in synchronization with the timing of outputting the scanning signal Vsel from the scanning driver 120B based on a power supply control signal input from the system controller 150.

Note that description has been given regarding a circuit structure corresponding to the current application scheme in which three transistors are included as the pixel drive circuit DC and the level current Ipix is pulled in the direction of the current holding/distributing portion (that is, the direction of the signal driver) through the data line DLj in the display pixel EM', but the present invention is not limited to this embodiment. As long as the display device has a light emission control transistor that controls supply of a drive current to a light emitting element and a write control transistor that controls a gradation current write operation, and the display device holds a gradation current (write current) corresponding to display data and then turns on the light emission control transistor based on the gradation current to supply the gradation current, thereby allowing the light emitting element to emit light having a predetermined luminance gradation, it is possible to use a display device including a pixel drive circuit to which at least a current application mode is applied and having another circuit configuration. For example, the present invention may have a circuit configuration including, for example, four transistors, or a circuit configuration in which a level current is conducted from the side of the current holding/distributing portion (that is, the side of the signal driver) in the direction of the display pixel (pixel driving circuit) through the data line.

In addition, although a description has been given with respect to the structure in which an organic EL element is applied as a light emitting element constituting the display pixel in the foregoing embodiments, the display device according to the present invention is not limited thereto. As long as it is a current control type light emitting element that emits light with a predetermined luminance gradation depending on the current value of the supplied driving current, it is possible to excellently apply, for example, a light emitting diode or any other light emitting element as the above-described organic EL element.

Claims (47)

1. A display driving device that drives a plurality of two-dimensionally arranged display pixels constituting a display panel based on display data, the display driving device comprising at least:

a gradation signal generation circuit that generates a gradation signal for controlling a luminance gradation of each display pixel based on the display data;

a selection circuit that sets the respective display pixels in a plurality of specific rows of the display panel to a selected state in which a gradation current based on the gradation signal is written, and sets at least a part of periods, which are at least a part of periods in which the display pixels in the respective rows of the plurality of specific rows are set to the selected state, to periods that overlap each other; and

a current writing circuit that extracts the gradation signal corresponding to the display pixels in the plurality of specific rows, supplies a gradation current having a current value based on the gradation signal to the display pixels in the plurality of specific rows in accordance with a period set to a selected state by the selection circuit, and supplies the gradation current simultaneously in the overlapping period.

2. The display driving apparatus according to claim 1, wherein at least the current writing circuit has a structure independent of the display panel.

3. The display driving apparatus according to claim 1, wherein at least the current writing circuit is integrated with the display panel.

4. The display driving apparatus according to claim 1, wherein at least the current writing circuit has a plurality of field-effect thin film transistors each having a single channel polarity and having an amorphous silicon layer as a channel layer.

5. The display driving apparatus according to claim 1, wherein at least the current writing circuit has a plurality of field-effect thin film transistors each having a polysilicon layer as a channel layer.

6. The display driving apparatus according to claim 1, wherein the gradation signal generating circuit generates a signal current as the gradation signal, the signal current providing the display pixel with a gradation of luminance corresponding to the display data.

7. The display driving apparatus according to claim 1, wherein the current writing circuit has means for generating and outputting the level current having a current polarity opposite to the signal current supplied from the current generating section.

8. The display driving apparatus according to claim 1, wherein the selection circuit has means for simultaneously setting the display pixels in the plurality of specific rows of the display panel to the selected state based on a single selection signal, and

the current writing circuit has a means for simultaneously supplying the gradation current to the display pixels in the plurality of specific rows at a timing when the display pixels are set to the selected state in accordance with the selection signal.

9. The display driving device according to claim 8, wherein the gradation signal generating circuit has means for sequentially supplying the gradation signal corresponding to a plurality of the display pixels in each of the columns of the display pixels in the plurality of specific rows to the current writing circuit in time series, and

the current write circuit includes:

a plurality of signal distributing circuits that sequentially distribute the gradation signal supplied from the gradation signal generating circuit in accordance with the plurality of display pixels in each row at the timing of the time-series source; and

a plurality of current holding circuits that individually hold the gradation signal distributed by the signal distributing section and simultaneously supply a current having a current value based on the held gradation signal to the display pixels in the plurality of specific rows as the gradation current;

the signal distribution circuit and the current holding circuit are provided according to each column of the display pixels in the plurality of specific rows.

10. The display driving apparatus according to claim 9, wherein each of the current holding circuits has a signal holding/outputting section at a plurality of stages, the signal holding/outputting section comprising: a signal holding section holding the signal current distributed by the signal distributing circuit in accordance with each of a plurality of the display pixels in each of the plurality of specific rows; and a level current output section that outputs a current corresponding to the signal current held in the signal holding section as the level current,

wherein the operation of acquiring and holding the signal current, which is performed by the signal holding section at one of the signal holding/outputting sections of the plurality of stages, is controlled to be performed in synchronization with the operation of outputting the level current by the level current outputting section at any other stage.

11. The display driving apparatus according to claim 10, wherein the signal holding section includes a charge storage circuit which stores a charge based on the signal current and holds the charge as a voltage component.

12. The display driving apparatus according to claim 10, wherein the level current output section has a current mirror circuit structure which generates and outputs a current having a current value having a predetermined current ratio with respect to a current value corresponding to the level signal supplied from the level signal generating circuit as the level current.

13. The display driving apparatus according to claim 1, wherein the selection circuit has means for sequentially applying a selection signal to each of the plurality of specific rows of the display panel in the overlapping period, wherein the selection signal sets the display pixels in each row to the selected state, thereby sequentially setting the display pixels corresponding to the plurality of specific rows to the selected state in the overlapping period.

14. The display driving apparatus according to claim 13, wherein the current writing circuit has means for sequentially supplying the gradation current to each of the plurality of specific rows in the overlapping period at a timing when the selection circuit applies the selection signal.

15. The display driving device according to claim 13, wherein the gradation signal generating circuit has means for sequentially supplying the gradation signal to the current writing circuit in time series, wherein the gradation signal corresponds to a plurality of the display pixels in each of the columns of the display pixels in the plurality of specific rows, and

the current writing circuit includes a plurality of current holding circuits provided in accordance with the display pixels of respective columns in the plurality of specific rows, sequentially holds the level signal provided by the level signal generating circuit in accordance with timing of the time-series source, and sequentially supplies a current having a current value based on the level signal as a level current to each of the plurality of specific rows.

16. The display driving device according to claim 15, wherein each of the current holding circuits comprises:

a signal distributing section that distributes the signal current in accordance with the timing of the time-series source; and

a plurality of current holding/output sections according to a plurality of the display pixels in each of the plurality of specific rows, each of the current holding/output sections having: a signal holding section that holds the signal current distributed by the signal distributing section; and a gradation current output section that outputs a current corresponding to the signal current held in the signal holding section as a gradation current;

wherein there are two kinds of operations controlled to be simultaneously performed within the overlapping period, that is, an operation of outputting the level current based on the signal current held in the signal holding section by the level current output section of one of the current holding/output sections, and an operation of holding the signal current distributed by the signal distributing section in the signal holding section of the other current holding/output section and outputting the level current based on the signal current held in the signal holding section by the level current output section.

17. The display driving apparatus according to claim 16, wherein the signal holding section includes a charge storage circuit which stores a charge based on the signal current and holds the charge as a voltage component.

18. The display driving apparatus according to claim 16, wherein the level current output section has a current mirror circuit structure which generates and outputs a current having a current value having a predetermined current ratio with respect to a current value corresponding to the level signal supplied from the level signal generating circuit as the level current.

19. A display device that displays image information based on display data, the display device comprising at least:

a display panel having a plurality of scanning lines arranged in a row direction and a plurality of data lines arranged in a column direction, and a plurality of display pixels arranged in a matrix form in the vicinity of intersections of the plurality of scanning lines and the plurality of data lines;

a scan driver which sets the display pixels corresponding to a plurality of specific scan lines, which are at least a part of the plurality of scan lines of the display panel, to a selected state in which a gradation current based on the display data is written, and sets at least a part of periods, which are at least a part of periods in which the display pixels of respective lines of the plurality of specific lines are set to the selected state, to periods overlapping each other; and

a signal driver, comprising: a gradation signal generation circuit to which display data is supplied and which generates a gradation signal that controls a luminance gradation of each display pixel based on the display data; and a current writing circuit that acquires a gradation signal corresponding to the display pixel corresponding to the plurality of specific scanning lines, and supplies a gradation current having a current value based on the gradation signal to the display pixels corresponding to the plurality of specific scanning lines in accordance with a period set to a selected state by the scanning driver, and supplies the gradation current simultaneously in the overlapping period.

20. The display device of claim 19, wherein at least the signal driver has a construction independent of the display panel.

21. The display device according to claim 19, wherein the display panel and at least the current writing circuit in the signal driver are formed on a single insulating substrate.

22. The display device according to claim 19, wherein the current writing circuit in the signal driver has means for generating and outputting the level current having a current polarity opposite to that of the signal current supplied from the current generating section.

23. The display device according to claim 19, wherein at least the current writing circuit has a plurality of field-effect thin film transistors each having a single channel polarity and having an amorphous silicon layer as a channel layer.

24. The display device according to claim 19, wherein at least the current writing circuit has a plurality of field-effect thin film transistors each having a polysilicon layer as a channel layer.

25. The display device according to claim 19, wherein the gradation signal generating circuit generates a signal current as the gradation signal, the signal current providing the display pixel with a gradation of luminance corresponding to the display data.

26. The display device of claim 19, wherein the display pixels comprise:

a pixel driving circuit generating a predetermined driving current based on the level current output from the signal driver; and

and a current control type light emitting element for emitting light having a predetermined luminance gradation based on a current value of the drive current.

27. The display device according to claim 26, wherein the pixel driving circuit has a plurality of field effect thin film transistors each having a single channel polarity, and an amorphous silicon layer as a channel layer.

28. The display device according to claim 26, wherein the driving circuit has a plurality of field-effect thin film transistors each having a polysilicon layer as a channel layer.

29. The display device according to claim 26, wherein the light-emitting element is an organic electroluminescent element.

30. The display device according to claim 19, wherein the display panel has a plurality of data line groups each having a plurality of data lines corresponding to the number of scanning lines of each of the plurality of data lines determined as one set.

31. The display device according to claim 30, wherein each of the data line groups is arranged in each of areas between columns of the plurality of display pixels arranged in a matrix form in the display panel.

32. The display device according to claim 30, wherein the display panel has a plurality of scanning line groups, each of the scanning line groups having a plurality of specific scanning lines determined as one set,

the scan driver has means for applying a single scan signal to each of the scan line groups to simultaneously set the display pixels corresponding to the particular scan lines to a selected state, wherein the single scan signal sets the display pixels to the selected state,

the gradation signal generating circuit in the signal driver has a means for sequentially supplying the gradation signal corresponding to a plurality of display pixels corresponding to each scanning line group in each data line of each data line group to the current writing circuit in time series, and

the current writing circuit in the signal driver includes: a plurality of signal distributing circuits that sequentially distribute the hierarchical signal supplied from the hierarchical signal generating circuit in accordance with each data line in each data line group at the timing of the time-series source; and a plurality of current holding circuits which individually hold the gradation signal assigned by the signal assigning section and synchronously supply a current having a current value based on the held gradation signal to each data line in each data line group as a gradation current in accordance with a timing of applying the scan signal to each scan line group, the signal assigning circuit and the current holding circuit being supplied in accordance with the respective data line groups.

33. The display device according to claim 32, wherein each of the current holding circuits has a signal holding/outputting section having a plurality of stages, each of the signal holding/outputting sections comprising: a signal holding section that holds the level signal distributed by the signal distributing circuit in accordance with each data line of each data line group; and a level current output section that outputs a current having a current value based on the level signal as the level current, wherein the level signal is held in the signal holding section,

wherein an operation of acquiring and holding the level signal at one of the signal holding/outputting sections of the plurality of levels by the signal holding section and an operation of outputting the level current at the other level by the level current outputting section are controlled to be performed in synchronization.

34. The display device according to claim 33, wherein the signal holding portion includes a charge storage circuit which stores a charge corresponding to the gradation signal and holds the charge as a voltage component.

35. The display device according to claim 33, wherein the level current output section has a current mirror circuit structure which generates and outputs a current having a current value having a predetermined current ratio with respect to a current value corresponding to the level signal supplied from the level signal generating circuit as the level current.

36. The display device of claim 30, wherein the scan driver has a means for applying a scan signal to each of the specific scan lines in turn in the overlap period to set the display pixels corresponding to the specific scan lines in turn in the selected state in the overlap period, and

the current writing circuit in the signal driver has a means for sequentially supplying the level current to each data line of each data line group in the overlapping period at a timing when the scan driver applies the scan signal.

37. The display device according to claim 30, wherein the scan driver has a means for applying a scan signal to each of the plurality of specific scan lines in turn in the overlap period to set the display pixels corresponding to the plurality of specific scan lines in turn in the selected state in the overlap period, wherein the scan signal sets the display pixels in the selected state,

the gradation signal generating circuit in the signal driver has a means for sequentially supplying the gradation signals corresponding to the plurality of display pixels corresponding to the plurality of specific scanning lines in each data line of each data line group to the current writing circuit in time series, and

the current writing circuit has a plurality of current holding circuits each of which is provided in accordance with each of the data line groups, sequentially holds the level signal provided by the level signal generating circuit in accordance with timing of the time-series source, and sequentially supplies a current having a current value corresponding to the level signal as the level current to each of the data lines of each of the data line groups at timing corresponding to application of the scanning signal.

38. The display device according to claim 37, wherein each of the current holding circuits includes a plurality of current holding/output sections in accordance with each of the data lines in each of the data line groups, the current holding/output sections having: a signal distributing section that sequentially distributes the level signal in accordance with each data line in each data line group at a timing of the time-series source; a signal holding section that holds the level signal distributed by the signal distributing section; and a level current output section that outputs a current having a current value based on the level signal as a level current, wherein the level signal is held in the signal holding section,

wherein there are two kinds of operations controlled to be simultaneously performed in the overlapping period, that is, an operation of holding the level signal distributed by the signal distributing section in the signal holding section in one of the current holding/outputting sections and outputting the level current based on the level signal by the level current outputting section, and an operation of outputting the level current based on the level signal held in the signal holding section by the level current outputting section in any other current holding/outputting section.

39. The display device according to claim 38, wherein the signal holding portion includes a charge storage circuit which stores a charge corresponding to the gradation signal and holds the charge as a voltage component.

40. The display device according to claim 38, wherein the level current output section has a current mirror circuit structure which generates and outputs a current having a current value having a predetermined current ratio with respect to a current value corresponding to the level signal supplied from the current generating section as the level current.

41. A driving method of a display device for displaying image information based on display data,

the display device has a display panel having a plurality of scanning lines arranged in a row direction and a plurality of data lines arranged in a column direction, and arranged in the vicinity of intersections of the plurality of scanning lines and the plurality of data lines, and a plurality of display pixels arranged in a matrix form,

the driving method at least comprises the following steps:

receiving the display data and generating a level signal for controlling a luminance level of each display pixel based on the display data;

setting the display pixels corresponding to a plurality of specific scanning lines to be in a selected state in which the hierarchical current based on the display data is written, wherein the specific scanning lines are at least a part of the scanning lines in the display panel;

setting the operation to the selected state includes setting at least a part of periods to periods overlapping with each other, the at least a part of periods being at least a part of periods in which the display pixels of each of the plurality of specific rows are set to the selected state;

acquiring the gradation signal corresponding to the display pixel corresponding to the specific scanning lines, generating the gradation current having a current value based on the gradation signal, and supplying the gradation current to the display pixel corresponding to the specific scanning lines according to a period set to the selected state;

providing the level current to the display pixels corresponding to the specific scanning lines simultaneously in the overlapping period; and

the display pixel is operated with a display luminance based on a current value of the gradation current supplied and written in the display pixel.

42. The method for driving a display device according to claim 41, wherein the operation for generating the gradation signal generates a signal current as the gradation signal, the signal current providing the display pixel with a gradation of luminance corresponding to the display data.

43. The driving method of a display device according to claim 41, wherein the operation of generating and outputting the level current having a current value based on the level signal comprises:

and an operation of generating a current having a current value having a predetermined current ratio with respect to a current value corresponding to the level signal, and outputting the generated current as the level current.

44. The method for driving a display device according to claim 41, wherein the operation of setting the display pixel to the selected state comprises an operation of simultaneously applying a single scan signal to the plurality of specific scan lines so that the display pixels corresponding to the plurality of scan lines are simultaneously set to the selected state, wherein the single scan signal sets the display pixels to the selected state, and

the operation of supplying the level current includes an operation of simultaneously supplying the level current to the display pixels corresponding to the plurality of scan lines according to the timing of applying the scan signal.

45. The method for driving a display device according to claim 44, wherein the step of synchronously providing the gradation currents to the display pixels corresponding to the plurality of scanning lines comprises the step of synchronously performing:

an operation of acquiring and holding the gradation signal corresponding to each scanning line; and

an operation of outputting the level current based on the level signal acquired and held at the above timing.

46. The method for driving a display device according to claim 41, wherein the operation of setting the display pixel to the selected state sequentially applies a scanning signal to each of a plurality of specific scanning lines in an overlapping period such that the display pixels corresponding to the plurality of scanning lines are sequentially set to the selected state in the overlapping period, wherein the scanning signal sets the display pixel to the selected state, and

the operation of supplying the level current includes an operation of sequentially supplying the level current to the display pixels corresponding to each of the plurality of scan lines at the timing of applying the scan signal in the overlapping period.

47. The method for driving a display device according to claim 46, wherein the step of sequentially supplying the gradation currents to the display pixels corresponding to the plurality of scanning lines is performed synchronously in overlapping periods of:

an operation of holding the level signal and outputting the level current based on the level signal; and an operation of outputting the level current based on the level signal held at the above timing.