HK1095944B - Method and apparatus for the formatting of data for transmission - Google Patents

Description

Method and device for formatting transmission data

The present application is a divisional application of chinese patent application No. 01101208.0 entitled "method and apparatus for formatting transmission data", filed on 5.1.2001.

Technical Field

The present invention relates to the formation of data for transmission, and more particularly, to a novel and improved method and apparatus for formatting vocoded data, non-vocoded data, and signaling data for transmission.

Background

In the field of data communication, various devices for digital data transmission have been utilized. The data bits are structured according to a common format for transmission over the transmission medium.

It is therefore an object of the present invention to provide a data format that is delivered in a structured form to facilitate the communication of various types of data, and data at various rates.

The present invention is a novel and improved method and system for formatting digital data for communication over a transmission medium.

In communication systems, it is important to utilize data formats that allow for the overall communication of data between users. In communication systems such as Code Division Multiple Access (CDMA) where various types of data are required and communication is performed at various rates, the data format selected must allow maximum flexibility in a predetermined data structure. In addition, it is desirable to allow the various data types to be generated to share the largest resources together. In this case, the data must be structured in such a way that the data therein can be easily extracted according to the type and rate of the data.

Disclosure of Invention

An aspect of the present invention is to provide a subsystem for combining data packets with additional data in data frames in a digital communication system, wherein variable rate data packets are transmitted in data frames, and a data capacity of one of said variable rate data packets is smaller than a data capacity of one of said data frames for transmission, characterized in that said subsystem comprises: encoding means for receiving input data and encoding said input data at an encoding rate selected in accordance with a characteristic of said input data to provide said data packets; input means for receiving said data packet and said additional data and combining said additional data in said data frame with said data packet in response to a control signal; and control means for providing said control signal indicative of a combination format for combining said data packet with said additional data.

Another aspect of the present invention is to provide a subsystem for combining said data packets with additional data in data frames in a spread spectrum communication system, wherein variable length data packets are transmitted in data frames, and a data capacity of a data packet of said variable length data packets is smaller than a data capacity of a data frame of said data frames for transmission, characterized in that said subsystem comprises: encoding means for receiving input data and encoding said input data at an encoding rate selected in accordance with a characteristic of said input data to provide said data packets; input means for receiving said data packet and said additional data and combining said additional data in said data frame with said data packet in response to a control signal; and control means for providing said control signal indicative of a combination format for combining said data packet with said additional data.

The method and apparatus according to the present invention arranges various types of data and data at various rates into a uniquely structured format for transmission. The data provided may be vocoded data or different types of non-vocoded data. The data is structured as frames of a predetermined time period for transmission. The data frame is structured at one of several data rates depending on the data. The vocoded data is provided at one of a plurality of data rates and is structured in accordance with a predetermined format. Each frame may be composed of shared vocoded data with non-vocoded data that will be at the highest frame data rate. The non-vocoded data may be structured so that it also operates at the highest frame rate. In each data frame, additional control data may be provided to support the requirements of various aspects of transmission and recovery upon reception.

Drawings

The features, objects, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

fig. 1 is a block diagram of an exemplary illustration of a transmitter of a transceiver;

FIGS. 2 a-2 h are a series of diagrams illustrating frame data formats for various data rates, types, and modes;

FIG. 3 is an exemplary diagram illustrating a circuit implementation of the CRC and Tail Bit (Tail Bit) generator of FIG. 1;

FIGS. 4 a-4 e are flow diagrams of composing a data frame;

FIGS. 5 a-5 d are series of diagrams illustrating the order of code symbols interleaved at data transmission rates of 9.6, 4.8, 2.4, and 1.2kbps, respectively;

fig. 6 is a Walsh symbol diagram illustrating the set of symbols with respect to each encoder;

FIG. 7 is a block diagram of the long code generator of FIG. 1;

FIGS. 8 a-8C are a series of diagrams illustrating a long code Mask (Mask) for various channel types; and

fig. 9 is a diagram illustrating the frequency response of the digital filter of fig. 1.

Detailed Description

Referring now to the drawings, FIG. 1 shows an exemplary embodiment of a transmit section 10 of a CDMA mobile station transceiver or PCN handset. In a CDMA cellular communication system, information is transmitted from a cell site to a mobile station using a forward CDMA channel. Instead, information is transmitted from the mobile station to the cell site using a reverse CDMA channel. The communication of signals from the mobile station may be characterized in terms of access channel or traffic channel communications. The push-to-channel is used for short signaling information such as call origination, response paging, and registration. Traffic channels are used for communication in the form of (1) primary traffic, typically including the voice of a user; or (2) secondary traffic, typically including user data; or (3) signaling traffic, such as command and control signals; or (4) a combination of primary traffic and secondary traffic; or (5) a combination of primary traffic and signaling traffic.

The transmitting section 10 starts data to be transmitted on the reverse CDMA channel at a data rate of 9.6kbps, 4.8kbps, 2.4kbps or 1.2 kbps. While transmission is in progress, transmission on the reverse traffic channel may be at any of these data rates, while the access channel is at a 4.8kbps data rate. The duty cycle of transmissions on the reverse traffic channel varies with the transmission data rate. Specifically, the transmission duty cycle for each rate is provided in table 1. Since the duty cycle varies for transmission in proportion to the data rate, the transmission rate of the actual data string is fixed at 28800 code symbols per second. Since six code symbols are modulated as one of 64 walsh symbols for transmission, the walsh symbol transmission rate will be fixed at 4800 walsh symbols per second, resulting in a walsh chip rate fixed at 307.2 kcps.

All data transmitted on the reverse CDMA channel is convolutionally encoded, block interleaved, modulated by a 64-matrix modulation scheme, and direct sequence PN spread prior to transmission. Table 1 also defines the relationship between data rate and symbol rate for various transmission rates on the reverse traffic channel. The number (numerology) is the same for the access signal except that the transmission rate is fixed at 4.8kbps and the duty cycle is 100%. As described below, each bit transmitted on the reverse CDMA channel is convolutionally encoded using an 1/3 code rate. The symbol rate of the code is therefore always three times the data rate. The rate of the direct sequence spreading function will be fixed at 1.2288MHz so that each walsh chip is spread by exactly four PN chips.

TABLE 1

Bit rate 9.64.82.41.2

(kbps)

PN chip rate 1.22881.22881.22881.2288

(MCPS)

Code rate (bit/1/31/31/31/3)

Code symbol)

Send duty cycle 100.050.025.012.5

(％)

Code symbol rate 28.80028.80028.80028.800

(sps)

Modulation (code symbols/6666)

Volvin sign)

Walsh symbol rate 4800480048004800

Rate (sps)

Walsh chip rate 307.2307.2307.2307.2

Rate (kcps)

Walsh symbols 208.33208.33208.33208.33

(μs)

PN time slice/code symbol 42.6742.6742.6742.67

PN time slice/Walsh 256256256256

Symbol

PN time slice/Walsh 4444

Time piece

When the functional mode is the main traffic, the transmitting section 10 transmits an audible signal such as voice and/or background noise as a digital signal through a transmission medium. To facilitate digital communication of the voiced signals, the signals are sampled and digitized by well-known techniques. For example, in fig. 1, voice is converted into digital symbols by the microphone 12. The encoder 14 typically implements an analog to digital conversion process using a standard 8-bit/μ -law format. Alternatively, the analog signal may be converted directly to digital form using a uniform Pulse Code Modulation (PCM) format. In an exemplary embodiment, encoder 14 samples and provides an 8-bit sample output at the sampling rate using 8KHz to achieve a data rate of 64 kbps.

The 8-bit samples are output from encoder 14 to vocoder 16 where the μ -law/uniform transcoding process is performed. In vocoder 16, the samples are formed into frames of input data, where each frame consists of a predetermined number of samples. In a preferred embodiment of vocoder 16, each frame contains 160 samples or 20ms of speech at an 8KHz sampling rate. It should be understood that other sampling rates and frame sizes may be utilized. Each frame of speech samples is rate-variable by being encoded by vocoder 16 using synthesis parameter data formatted in a corresponding data set. The vocoder data is then output to the microprocessor 18 and associated circuitry for transmission formatting. Generally, the microprocessor 18 includes a program instruction memory containing program instructions, a data memory, and appropriate interfaces and associated circuitry as is well known in the art.

The preferred embodiment of vocoder 16 utilizes a Code Excited Linear Prediction (CELP) coding technique (coded Predictive) to provide a variable rate in the encoded voice data. Performing Linear Predictive Code (LPC) analysis when the value of the sample is a constant number; when the number of samples is variable, pitch (pitch) and codebook search are performed depending on the transmission rate. This type of variable rate vocoder is described in more detail in co-pending U.S. patent application No.07/713661, filed on 11/6/1991, assigned to the assignee of the present invention. Vocoder 16 may be implemented in an Application Specific Integrated Circuit (ASIC) or in a digital signal processor.

In the variable rate vocoder just described, the voice analysis frame is 20ms in length, meaning that the extracted parameters are output to microprocessor 18 at 50 times per second. In addition, the rate of data output is variable from roughly 8kbps to 4kbps to 2kbps and to 1 kbps.

In the full rate, also referred to as 1 rate, data transfer between the vocoder and the microprocessor is at 8.55 kbps. For full rate, the data parameters for each frame are encoded and represented by 160 bits. The full rate data frame also includes an 11-bit parity check. The final full-rate frame thus comprises a total of 171 bits. In a full rate frame, the transmission rate between the vocoder and the microprocessor would be 8kbps in the absence of parity bits.

In the case of half rate, also known as 1/2 rate, data transmission between the vocoder and the microprocessor is at 4kbps per frame using 80 bits of encoding parameters. In the case of the quarter rate, also known as the 1/4 rate, data transmission between the vocoder and the microprocessor is at the 2kbps rate using 40 bits of encoding parameters per frame. In the case of the eighth rate, also known as the 1/8 rate, data transmission between the vocoder and the microprocessor is performed at a rate slightly below 1kbps using 16 bits of encoded data per frame.

In addition, non-information frames may be transmitted between the vocoder and the microprocessor, this type of frame being called a blank frame and may be used for signaling or other non-vocoded data.

The vocoder data sets are then output to the microprocessor 18 and to a CRC and Tail bit generator (Tail BitGenerator) to complete the formatting of the transmission. The microprocessor 18 receives a rate indication of the rate at which frames of speech samples are encoded, while receiving sets of parameter data every 20 ms. The microprocessor 18 also receives input of secondary traffic data, if present, for output to the generator 20. The microprocessor 18 also internally generates signalling data for output to the generator 20. Whether primary traffic, secondary traffic or signaling traffic data, if present, is output from the microprocessor 18 to the generator 20 every 20ms frame.

Generator 20 generates and appends a set of parity or cyclic redundancy check bits (CRC bits) at the non-tail of the full-rate and half-rate frames, which are used as frame quality indicators at the receiver. For a full rate frame, whether the data is full rate primary, secondary, or signaling traffic, or a combination of half rate primary and secondary traffic, or a combination of half rate primary and signaling traffic, the generator preferably generates a set of CRC bits according to a first polynomial. For half rate data frames, generator 20 preferably generates a set of CRC bits according to a second polynomial. For all frame rates, generator 20 also generates a set of code tail bits that follow the CRC bits at the end of the frame if data is present or data is not present. A more detailed description of the operation of microprocessor 18 and generator 20 is provided below with reference to fig. 3 and 4.

The reverse traffic channel frames provided by generator 20 at the 9.6kbps rate are 192 bits in length and 20ms apart frames. These frames are shown in fig. 2 a-2 e and include a single mixed mode bit, auxiliary format bits if present, message bits, a 12-bit frame quality indicator (CRC), and 8 encoder tail bits. The mixed mode bit will be set to "0" during any frame in the case where the message bits are only primary traffic information. When the mixed mode bit is "0", the frame will include the mixed mode bit, 171 main traffic bits, 12 CRC bits, and 8 encoder tail bits.

The mixed mode bit is "1" and contains secondary or signaling traffic for each frame. In these cases, the first bit following the mixed mode bit is a burst format bit that specifies whether the frame is in "blank-and-burst" format or "dim-and-burst" format. The "blank-burst" operation is a format in which the entire frame is used for secondary traffic or signaling traffic, while the "fuzzy-burst" operation is a format in which the primary traffic shares the frame with secondary traffic or with signaling traffic. If the burst format bit is "0" then the frame is in "fuzzy and burst" format, and if "1" then the frame is in "blank and burst" format.

The second bit after the mixed mode bit is the traffic class bit. The traffic class bit is used to specify whether the frame contains secondary traffic or signaling traffic. If the traffic class bit is "0" then the frame contains signaling traffic and if "1" then the frame contains secondary traffic. Fig. 2 a-2 e illustrate burst format bits and traffic class bits.

When the burst format bit is "0", representing a "fuzzy and burst" operation, the two bits following the traffic type bit are traffic mode bits. These bits indicate the number of bits used for primary traffic information and the number of bits to be used for signaling or secondary traffic information in the frame. For the default mode, the traffic pattern is determined to be "00" only if all its traffic patterns are inverted for other bit types and sums. Referring to fig. 2b and 2C, in this example and preferred embodiment, 80 bits are used for primary traffic (half rate vocoded data set) and 86 and 87 bits are used for signaling and secondary traffic, respectively.

In each frame where signaling traffic bits are present, the first bit of the signaling portion of the frame is a start message (SOM) bit. The SOM bit is 1 if the reverse traffic channel message (signaling message) starts one bit after. Generally, the first bit of the reverse traffic channel message does not start at all, except after the SOM bit in the frame. However, it should be the frame that contains a portion of a message that begins with the previous frame whose SOM bit is "0". If the SOM bit is "0", the following bit is part of the message, but it is not the first bit of the complete message.

In the preferred embodiment, only the main traffic in the frame is sent at 4.8kbps, 2.4kbps, and 1.2kbps rates. In general, mixed mode operation cannot be supported except at the 9.6kbps rate. Although such support is easily achieved. The frame formats for these particular rates are shown in fig. 2f-2 h. For a 4.8kbps rate, the frame is 96 bits in length and the time period that its bits occupy the frame is 20ms, as described below. The 4.8kbps rate frame contains 80 main traffic bits, 8 frame quality indication (CRC) bits, and 8 encoder tail bits. For a 2.4kbps rate, as also described below, the frame is 48 bits long in length, with the time period that its bits occupy the frame being 20 ms. The 2.4kbps frame contains 40 main traffic bits and 8 encoder tail bits. For a 1.2kbps rate, as also described below, the frame is 24 bits long, with the time period of the frame occupied by bits being 20 ms. The 1.2kbps rate frame contains 16 main traffic bits and 8 coded tail bits.

In a preferred embodiment, the access channel data is generated by the microprocessor 18 for transmission at a 4.8kbps rate. Since such data is prepared in the same manner as the 4.8kbps frame format data, such as coding, interleaving, walsh coding. In the coding scheme implemented for 4.8kbps data, redundant data is generated for both reverse traffic channel data and access channel data. Unlike the reverse traffic channel, where redundant data is canceled upon transmission, all data including redundancy in the access channel is transmitted. Details of various aspects of access channel data frame transmission are provided below.

Fig. 3 illustrates an exemplary embodiment of various components used to format data according to fig. 2 a-2 h. In fig. 3 the data is transmitted from the microprocessor 18 (fig. 1) to the generator 20. Generator 20 includes data buffer and control logic 60, CRC circuits 62 and 64, and tail bit circuit 66. Rate commands from the microprocessor along with data may be selectively provided. Data is transferred from the microprocessor to the logic circuitry temporarily stored therein at one frame per 20 ms. For each frame, the logic 60 may count the number of bits per frame transmitted by the microprocessor or, alternatively, utilize rate commands and count clock cycles in the formatted data frames.

Each frame of the traffic channel includes a frame quality indicator. For 9.6kbps and 4.8kbps transmission rates, the frame quality indicator is CRC. For 2.4kbps and 1.2kbps transmission rates, the frame quality indicator means that no additional frame quality bits are transmitted. Two functions are supported by the frame quality indicator in the receiver. The first function is to determine the transmission rate of the frame and the second function is to determine whether the frame has errors. These determinations are made in the receiver by a combination of decoder information and CRC checks.

For the 9.6kbps and 4.8kbps rates, the frame quality indicator (CRC) is calculated over all bits in the frame except for the frame quality indicator (CRC) itself and the encoder tail bits. Logic 60 provides data at 9.6kbps and 4.8kbps rates to CRC circuits 62 and 64, respectively. Typically, circuits 62 and 64 are made up of series of shift registers, modulo-2 adders (typically exclusive-or gates) and switches as shown.

Data at a transmission rate of 9.6kbps utilizes a 12-bit frame quality indicator (CRC) which is transmitted in frames of 192 bits long as described with reference to figures 2 a-2 e. The generator polynomial for a 9.6kbps rate, as in the CRC circuit 62 of fig. 3, is represented by the following equation:

g(X)＝X¹²+X¹¹+X¹⁰+X⁹+X⁸+X⁴+X+1 (1)

the data at the 4.8kbps transmission rate utilizes an 8-bit CRC which is transmitted in 96-bit long frames as described with reference to fig. 2 f. As with the CRC circuit of FIG. 3, the generator polynomial is represented for a 4.8kbps rate by the following equation:

g(X)＝X⁸+X⁷+X⁴+X³+X+1 (2)

at initialization, all shift registers of circuits 62 and 64 are set to logic 1 by an initialization signal from logic 60. Additionally logic 60 places the switches of circuits 62 and 64 in the up position.

For data at a rate of 9.6kbps, the registers of circuit 62 are synchronized 172 times in a sequence of 172 bits of primary traffic bits, secondary traffic bits, or signaling bits, or a mixture of the former, along with the corresponding bits of the mode/format indicator as input to circuit 62. After synchronizing through 172 bits of circuit 62, logic 60 places the various switches of circuit 62 in the down position, and then the various registers of circuit 62 are additionally synchronized 12 times. As a result of the 12 additional synchronizations of circuit 62, 12 additional output bits are generated, the 12 additional bits being CRC bits. The CRC bits are appended to the end of the 172 bits as the output of circuit 62 for calculation purposes. It should be noted that from the 172-bit outputs of logic 60, these outputs are the outputs that are unchanged as they are by the calculation of the CRC bits by circuit 62, and thus the outputs from circuit 62 are identical in order and in magnitude to their inputs.

For a 9.6kbps rate, data bits are input to circuit 64 from logic 60 in the following order. For the primary traffic only case, the bits are input from logic 60 to circuit 64 in the order of one Mixed Mode (MM) bit followed by 171 primary traffic bits. For the "fuzzy and burst" case with primary traffic and signaling traffic, the bits are input to circuit 64 from logic 60 in the order of one MM bit, one Burst Format (BF) bit, Traffic Type (TT), a pair of traffic pattern (TM) bits, 80 primary traffic bits, one start of Message (MOS) bit, and 86 signaling traffic bits. For the "fuzzy and burst" case with primary and secondary traffic, the bits are input from logic 60 to circuit 64 in the order of one MM bit, one BF bit, a TT bit, a pair of TM bits, 80 primary traffic bits, and 87 signaling traffic bits. For the case of a "blank and burst" data format with only signaling traffic, the bits are input from logic 60 into circuit 64 in the order of one MM bit, one BF bit, TT bit, and 169 signaling traffic bits. For the "blank and burst" data format case with only secondary traffic, the bits are input from logic 60 to circuit 64 in the order of one MM bit, one BF bit, TT bit, and 169 signaling traffic bits.

Similarly for data at a rate of 4.8kbps, the registers of circuit 64 are synchronized 80 times for 80 bits of primary traffic data, or for 80 bits of access channel data. After synchronizing 80 bits through circuit 64, logic 60 places the switches of circuit 64 in the down position while the registers of circuit 64 are additionally synchronized 8 times. As a result of the 12 additional synchronizations of circuit 62, 12 additional output bits are generated as CRC bits. The CRC bits are also appended to the end of the 80 bits as the output of circuit 64 for calculation purposes. It should also be noted that the 80 bits output from logic 60, the CRC bits are computed by circuit 64 as is, and the output of these bits from circuit 64 is compared to its input, both in the same order and in the same magnitude.

The bits output by either of circuits 62 and 64 are provided to switch 60 under the control of logic 60. Also input to switch 66 are the 40 and 16 bit main traffic data outputs from logic 60 for the 2.4kbps and 1.2kbps data frames. The switch 66 selects between providing an output of input data (upper position) and providing a value of logic 0 ("0") (lower position). Generally, switch 66 is placed in an upper position to allow data from logic 60, and if present, from circuits 62 and 64, to be output from generator 20 to encoder 22 (FIG. 1). For data of 9.6kbps and 4.8kbps frames, after the bits of the CRC are checked through switch 66, logic 60 places the switch in the lower position for 8 clock cycles to produce 8 all-zero tail bits. Thus, for a 9.6kbps and 4.8kbps data frame, the data output to the encoder as the frame includes 8 additional tail bits following the CRC bits. Similarly for the 2.4kbps and 1.2kbps frame data, logic 60 switches to the next position for 8 clock cycles after the main traffic bits from logic 60 are synchronized by switch 66 to produce 8 all-zero tail bits again. Thus, for a 2.4kbps and 1.2kbps data frame, the data output to the encoder as the frame includes 8 additional tail bits following the main traffic bits.

Fig. 4 a-4 e show a series of flow charts of the operation of the microprocessor 18 and generator 20 to combine data into the disclosed frame format. It should be appreciated that there may be a wide variety of implementations for giving various traffic types and rate priorities for transmission. In an exemplary embodiment, when a signaling traffic message is to be sent, the "fuzzy and burst" format may be selected when vocoded data is present. The microprocessor 18 may generate a command to the vocoder to cause the vocoder to encode frames of voice samples at half the rate, regardless of whether the vocoder will normally encode the frames of samples at that rate. The microprocessor 18 then assembles the half-rate vocoder data and signaling traffic into 9.6kbps frames as shown in fig. 26. In this case, one limitation is the number of speech frames encoded at half rate to avoid deterioration of speech quality. In another arrangement, the microprocessor 18 may wait until a half-rate frame of vocoder data is received before combining the data into the "fuzzy and burst" format. In this case, to ensure timely transmission of the signaling signal, the maximum limit is to the number of non-half-rate consecutive frames that may be forced before a command is sent at half-rate to the vocoder for encoding. Secondary traffic may be transmitted in a similar manner in an "fuzzy and burst" format (fig. 2C).

This is similar for the "blank and burst" data format, as shown in fig. 2d-2 e. The vocoder may be commanded to not encode the voice samples or the vocoder data may be ignored by the microprocessor when constructing the data frames. The priority between the frame structures generated by the main traffic at multiple rates, the "fuzzy and burst" traffic and the "blank and burst" traffic is open for multiple possibilities.

Returning to FIG. 1, thus, 20ms frames of 9.6kbps, 4.8kbps, 2.4kbps, 1.2kbps data are output from generator 20 to encoder 22. In the exemplary embodiment, encoder 22 is preferably a conventional encoder of the type well known in the art. Encoder 22 preferably encodes the data using rate 1/3 as a convolutional code with a constraint length K of 9. As an example, the encoder 22 is configured with generator functions of g0 ═ 557 (octal), g1 ═ 663 (octal), and g2 ═ 711 (octal). As is known in the art, convolutional coding comprises a modulo-2 addition of a selected type of successively time-shifted delayed (time-shifted delayed) data sequence. The data sequence delay length is equal to K-1, where K is the constraint length of the code. Because the 1/3 code rate is utilized in the preferred embodiment, three code symbols, code symbols (C0), (C1), and (C2), are generated for each data bit and input to the encoder. The code symbols (C0), (C1), (C2) are generated by generator functions g0, g1 and g2, respectively. The code symbols are output from the encoder 22 to a data block interleaving circuit 24. The code symbols of the output code are supplied to the data block interleaving circuit 24 in the order that the code symbol (C0) precedes, the code symbol (C1) follows and the code symbol (C2) follows. When initialized, the state of encoder 22 is an all zero state. In addition, the tail bits utilized at the end of each frame provide for the encoder 22 to reset to an all-zero state.

The symbol output provided from encoder 22 to data interleaving circuit 24 provides a repetition of the code symbols under the control of microprocessor 18. The code symbols may be stored in a manner that achieves a code symbol repetition that varies with the data channel, using conventional Random Access Memory (RAM) as the symbol store is addressed by the microprocessor 18.

For a 9.6kbps data rate, the code symbols do not repeat. The code symbols are repeated once, i.e., twice per symbol, at a data rate of 4.8 kbps. This is repeated three times per code symbol at a data rate of 2.4kbps, i.e., four times per symbol. Each code symbol is repeated 7 times, i.e., each symbol occurs 8 times, at a data rate of 1.2 kbps. The repetition of the (9.6, 4.8, 2.4 and 1.2kbps) codes for all data rates results in a constant code symbol rate of 28800 code symbols per second as output data of the data block interleaving circuit 24. The code symbols repeated on the reverse traffic channel are not all transmitted multiple times, and due to the variable transmission duty cycle described in detail below, the code symbol repetitions are discarded prior to actual transmission. It will be appreciated that for purposes of describing the operation of the data block interleaving circuit, the use of code symbol repetition as an expedient method and a random generator of data bursts will be described in detail again below. It should be appreciated that the same objectives can be readily achieved and still be within the teachings of the present invention, as distinguished from various embodiments that utilize repetition schemes of code symbols.

All code symbols will be sent on the reverse traffic channel and the access channel interleaved before modulation and transmission. The block interleaving circuit 24 is constructed in a manner known in the art to provide an output of one code symbol in a 20ms period. Typically, the interleaved structure is a rectangular matrix of 32 rows and 18 columns, i.e., 576 cells. The code symbols are written repeatedly through the interleaving circuit with 9.6, 4.8, 2.4 and 1.2 data for each column to completely fill the 32 x 18 matrix. Fig. 5 a-5 d show the sequence of repeated code symbol write operations to write to the interleaving matrix for transmission at 9.6, 4.8, 2.4 and 1.2kbps data rates, respectively.

The reverse traffic channel code symbols are output from the data block interleaving circuit by rows. The microprocessor 18 also controls the address of the interleaving memory to output symbols in the proper order. The rows of the interleaving circuit are preferably output in the following order:

at 9.6 kbps:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

16 17 18 19 20 21 22 23 24 25 26 27 28

29 30 31 32

at 4.8 kbps:

1 3 2 4 5 7 6 8 9 11 10 12 13 15 14

16 17 19 18 20 21 23 22 24 25 27 26 28

29 31 30 32

at 2.4 kbps:

1 5 26 3 7 4 8 9 13 10 14 11 15 12

16 17 21 18 22 19 23 20 24 25 29 26 30

27 31 28 32

at 1.2 kbps:

1 9 2 10 3 11 4 12 5 13 6 14 7 15 8

16 17 25 18 26 19 27 20 28 21 29 22 30

23 31 24 32

the stored channel code symbols are also output from the interleaving circuit 24 by rows. The microprocessor 18 also controls the addressing of the interleaved memory to output the symbols in the appropriate order. The rows of code symbol interleaving circuits for the access channel at the 4.8kbps rate are output in the following order:

1 17 9 25 5 21 13 29 3 19 11 27 7 23

15 31 2 18 10 26 6 22 14 30 4 20 12

28 8 24 16 32。

it should be noted that convolutional codes using other coding rates, such as 1/2 rate, as well as various other symbol interleaving formats, can be readily implemented using the basic teachings of the present invention in the forward transmission channel.

Referring again to fig. 1, the interleaved code symbols are provided from the interleaving circuit 24 to the modulator 26. In the preferred embodiment, 64-matrix orthogonal signaling is utilized for modulation to only the CDMA channel. That is, one of 64 possible modulation symbols is transmitted for every 6 code symbols. The 64-matrix modulated symbol is preferably one of 64 orthogonal waveforms generated using walsh functions. These modulation symbols are given in fig. 6 and numbered from 0 to 63. These modulation symbols are selected according to the following formula:

modulation symbol number ═ C₀+2_C1+4C₂+8C₃+16C4+32C₅ (3)

Wherein C is₅Will represent the last or most recent sum C₀A binary value ("0" or "1") representing the first or oldest one of the code symbols of each set of six code symbols constituting a modulation symbol. The time period required to transmit a single modulation symbol is called a "walsh symbol" interval and is approximately equal to 208.333 mus. The time period associated with 1/64 of the modulation symbol is called the "walsh time slice" and is approximately 3.2552083333 … … μ s.

Each modulated or walsh symbol is output from the modulator 26 to one input of a modulo-2 adder, xor gate 28. The walsh symbols are output from the modulator at a 4800sps rate, which corresponds to a walsh chip rate of 307.2 kcps. The other input to gate 28 is provided from a long code generator 30, generator 30 operating in conjunction with a masking circuit 32 to produce a masked Pseudo Noise (PN) code called a long code sequence. From the long code sequence provided by generator 30 to a chip rate that is four times the walsh chip rate of modulator 26, i.e., a PN chip rate of 1.2288 Mcpc. Gate 28 combines the two input signals to provide a data output at a 1.2288Mcps time slice rate.

The long code sequence is of length 2⁴²-1 time of each time slice sequenceThe sum of the displacements is generated by a linear generator known in the art using the following polynomial:

P(X)＝X⁴²+X³⁵+X³³+X³¹+X²⁷+X²⁶+X²⁵+X²²+X²¹+X¹⁹+X¹⁸+X¹⁷+X¹⁶+X¹⁰+X⁷+X⁶+X⁵+X³+X²+X¹+1 (4)

fig. 7 depicts the generator 30 in more detail. Generator 30 is comprised of a generator sequence portion 70 and a mask portion 72. Section 70 consists of a shift register and modulo-2 adder, typically a sequence of exclusive or gates, coupled together to produce a 42-bit code according to equation (4). The long code is then generated by masking the variable output of the 42-bit state from the portion 70 with a 42-bit wide mask provided by the masking circuit 32.

Section 72 includes a series of input and gates 74 having mask bit inputs for receiving 42 bits wide₁-74₂₀. And gate 74₁-74₄₂Each other input terminal of which receives an output from a corresponding shift register in section 70. And gate 74₁-74₄₂The output of (a) is modulo-2 added by adder 76 to form a single bit output for each 1.2288MHz clock synchronization of the shift registers of section 70. Typically, the adder 76 is formed of a cascade arrangement of exclusive or gates, as is well known in the art. Thus, the actual PN sequence output is made up of all the masked output bits of the modulo-2 plus sequence generator 70 as shown in fig. 7.

The mask used for PN spreading will vary depending on the type of channel over which the mobile station is communicating. Referring to fig. 1, an initialization message is provided from microprocessor 18 to generator 30 and circuit 32. Generator 30 initializes the circuit in response to the initialization information. Masking circuit 32 also outputs a 42-bit mask in response to the initialization information indicating the type of mask to be provided. Thus, the masking circuit may be formed from a memory containing masking sequences for various communication channel types. Fig. 8 a-8C provide exemplary definitions of mask bits for each channel type.

In particular, when communicating on an access channel, the mask is defined in the manner as represented in fig. 8 a. Masking in access channel, masking bits M₂₄To M₄₁Set to "1", mask bit M₁₉To M₂₃Setting as the number for selecting the access channel; mask bit M₁₆To M₁₈Arranged as code channels for the associated paging channel, i.e. in general ranging from 1 to 7, with a mask bit M₀To M₁₅Set as a mask bit M for the current base station registration area₀To M₈Set to the pilot PN value for the current CDMA channel.

When communicating on the reverse traffic channel, the mask is defined as shown in fig. 8 b. The mobile station utilizes a common long code of the two long codes that is unique to the mobile station, i.e., an Electronic Serial Number (ESN) for the mobile station; and a unique long code for each mobile station's identification number (MIN), which is typically the mobile station's telephone number. In the public long code, the mask bit M₃₂To M₄₁Set to "0", and a mask bit M₆To M₃₁Set to the ESN value for that mobile station.

It is further contemplated that the unique code may be implemented in accordance with fig. 8C. The dedicated code will provide additional security, which is known only to the base station and the mobile station. The unique code will be transmitted opaque on the transmission medium. Masking bits M in a private code₄₀To M₄₁Set to "0" and "1", respectively; and mask bit M₀To M₃₉May be arranged according to a predetermined specified scheme.

Returning to fig. 1, the output of gate 28 is provided as one input to each of a pair of pair 2 adders, i.e., xor gates 34 and 36, respectively. The other inputs of gates 34 and 36 are provided by I and Q channel PN generators 38 and40 to generate PN sequences for the second and third I and Q channel "moment codes". The reverse access channel and the reverse traffic channel perform QPSK spreading on the signal before actual transmission. This de-aligned orthogonal spreading on the reverse channel utilizes the same I and QPN codes as the forward channel I and Q pilot PN codes. The length of the I and QPN codes generated by generators 38 and 40 is 2¹⁵And preferably a zero time detuned code with respect to the forward channel. For purposes of further understanding, a pilot signal is generated for each base station in the forward channel. The pilot signal of each base station is spread by I and QPN codes as just described. The I and QPN codes of the base stations are de-aligned from each other by shifting of the code sequence in order to provide differentiation of transmissions between base stations. The resulting function for the I and Q short PN codes will be expressed as follows:

P_I(X)＝X¹⁵+X¹³+X⁹+X⁸+X⁷+X⁵+1 (5)

P_Q(X)＝X¹⁵+X¹²+X¹¹+X¹⁰+X⁶+X⁵+X⁴+X³+1 (6)

generators 38 and 40 may be constructed in a manner well known in the art to provide an output sequence in accordance with equations (5) and (6).

The I and Q waveforms are output from gates 34 and 36, respectively, and provided as inputs to Finite Impulse Response (FIR) filters 42 and 44, respectively. FIR filters 42 and 44 are digital filters that limit the frequency band of the generated I and Q waveforms. These digital filters shape the I and Q waveforms so that the resulting spectrum is contained within a given spectral mask. The digital filter preferably has an impulse response as shown in table II below:

TABLE 2

Filters 42 and 44 may be constructed in accordance with known digital filter techniques and preferably provide a frequency response as shown in fig. 9.

The binary "0" and "1" inputs to the digital filters 42 and 44 resulting from the PN spreading function are converted to +1 and-1, respectively. The sampling frequency of the digital filter is 4.9152 MHz-4 × 1.2288 MHz. An additional "0" and "1" input sequence synchronized with the I and Q digital waveforms will be provided to each of the digital filters 42 and 44. This special sequence, called the mask sequence, is the output generated by the data burst randomizer. The mask sequence is multiplied by the I and Q binary waveforms to produce a ternary number (-1, 0 and +1) which is input to digital filters 42 and 44.

As described above, the data rate transmitted on the reverse traffic channel is one of the 9.6, 4.8, 2.4, or 1.2kbps rates and varies from frame to frame. Since the frames are fixed at 20ms length for the access channel and reverse traffic channel, the number of information bits per frame transmitted for a data rate of 9.6, 4.8, 2.4, or 1.2kbps, respectively, would be 192.96.48 or 24. As described above, the information is convolutionally encoded using the 1/3 rate, the code symbols would be repeated by factors of 1, 2, 4, and 8 for 9.6, 4.8, 2.4, or 1.2kbps rate data, respectively. Thus, the rate of the generated repetition code symbols is fixed at 28800 Symbols Per Second (SPS). this 28800SPS code stream is data block interleaved as described above.

Prior to transmission, the reverse traffic channel interleaving circuit output code stream is gated by a time filter to allow transmission of some of the interleaving circuit output symbols and removal of some other output symbols. Thus, the duty cycle of the transmission strobe is varied with the rate at which data is transmitted. This transmission strobe allows the output symbols of all of the interleaving circuits to be transmitted when the transmission rate is 9.6 kbps. When the rate of the transmission data is 4.8kbps, the transmission strobe allows half of the symbols output by the interleaving circuit to be transmitted, and so on. This gating operation is referred to as a power control group by dividing a 20ms frame into 16 equal lengths (i.e., 1.25 v). Some power control groups are controlled to be on (i.e., transmitting) while other groups are controlled to be off (i.e., not transmitting).

The arrangement of groups controlling on and off is called the function of the random generator of the data burst. The power control groups that control the power-on occur pseudo-randomly at their respective locations in the frame so that the actual traffic loading on the reverse CDMA channel is averaged, assuming a random distribution for each duty cycle frame. The function control groups of the control pass are arranged such that each code symbol entering the repetition process will be transmitted once without repetition. During the control period, the mobile station does not transmit energy, thereby reducing interference to other mobile stations operating on the same reverse CDMA channel. This gating occurs prior to transmit filtering.

When the mobile station is transmitting on the access channel, the transmission gating procedure is not utilized. When transmitting on the access channel, the code symbols are repeated once (twice per symbol) prior to transmission.

In a functional implementation of the data string randomizer, the data string randomizer logic 46 generates a "0" and "1" masking stream that randomly masks out the redundant data that is repeatedly generated by the code. The pattern of the mask stream is determined by the frame data rate and by the 14-bit data blocks taken from the long code sequence generated by generator 30. These mask bits are synchronized with the data stream and the data is selectively masked by these bits by the operation of digital filters 42 and 44. In logic 46, the 1.2288MHz long code sequence output from generator 30 is input into a 14-bit shift register that shifts at the 1.2288MHz rate. The contents of this shift register are loaded into the 14-bit latches of one power control group (1.25ms) exactly one before each reverse traffic channel frame boundary. Logic 46 uses this data, along with the data input from microprocessor 18, to determine a particular set or sets of power control groups, according to a predetermined algorithm, in which the data will be allowed to pass through filters 42 and 46 for transmission. Thus, the logic 46 outputs a "1" or "0" for each power control group depending on whether the data for the entire power control group is to be filtered ("0") or passed ("1"). In the corresponding receiver, the receiver also determines the appropriate power control group or groups in which the data is present using the same long code sequence and corresponding frame-determined rate.

The I-channel data output from filter 42 is provided directly to a digital-to-analog converter and anti-aliasing filter circuit 50. However, the Q channel data is output from the filter 44 to a delay element 48, which outputs Q channel data from the delay element 48 to a digital to analog converter (D/A) and anti-aliasing filter circuit 52. Circuits 50 and 52 convert the digital data to analog form and filter out the analog signal. The signals output from the circuits 52 and 50 are supplied to an offset quadrature phase shift keying (0QPSK) modulator 54, modulated in the modulator 54 and output to an RF transmitter circuit 56. Circuitry 56 amplifies, filters, and upconverts the signal for transmission. Signals from circuitry 56 are output to antenna 58 for communication with a base station.

It should be appreciated that the exemplary embodiments of this invention discuss data formatting for modulation and transmission with respect to a mobile station. It should be understood that the data formatting is the same for the base stations of the cell, however the modulation may be different.

The foregoing description of the preferred embodiments will suggest themselves to those skilled in the art or may be utilized with the present invention, and the general principles defined by the present invention may be applied to other embodiments not utilizing the technology of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown in the specification but is to be accorded the widest scope consistent with the principles and novel features disclosed in the specification.

Claims (10)

1. A subsystem for combining a data packet of a variable rate data packet with overhead data in a data frame in a digital communication system, wherein the variable rate data packet is transmitted in a data frame and the data capacity of the data packet is less than the data capacity of a data frame of the data frame for transmission, the subsystem comprising:

encoding means for receiving input data and encoding said input data at an encoding rate selected in accordance with a characteristic of said input data to provide said data packets;

input means for receiving said data packet and said additional data and combining said additional data in said data frame with said data packet in response to a control signal; and

control means for providing said control signal indicative of a combination format for combining said data packet with said additional data.

2. The system of claim 1 wherein said control means is responsive to a data rate signal.

3. The system of claim 1, wherein the data frame includes voice data and the additional data including signaling data.

4. The system of claim 1, wherein the data frame includes voice data and the additional data including second traffic data.

5. The system of claim 1, wherein the data frame further comprises at least one additional bit indicating a type of the additional data.

6. A subsystem for combining a data packet of variable length data packets with overhead data in a data frame in a spread spectrum communication system, wherein variable length data packets are transmitted in data frames and the data capacity of said data packets is less than the data capacity of a data frame of said data frames for transmission, said subsystem comprising:

encoding means for receiving input data and encoding said input data at an encoding rate selected in accordance with a characteristic of said input data to provide said data packets;

input means for receiving said data packet and said additional data and combining said additional data in said data frame with said data packet in response to a control signal; and

control means for providing said control signal indicative of a combination format for combining said data packet with said additional data.

7. The system of claim 6 wherein said control means is responsive to a data rate signal.

8. The system of claim 6, wherein said data packet contains voice data and said additional data containing signaling data.

9. The system of claim 6, wherein the data packet contains voice data and the additional data containing second traffic data.

10. The system of claim 6, wherein the data frame further comprises at least one additional bit indicating a type of the additional data.