HK1092941B - High voltage sensor device and method therefor - Google Patents

Description

High pressure sensor apparatus and method thereof

Technical Field

The present invention relates generally to electronics, and more particularly to methods of fabricating semiconductor devices and structures.

Background

The semiconductor industry in the past has used a variety of methods to form semiconductor devices that control high voltage systems, an example of which is a power supply controller operated by an input voltage of high voltage value. One problem with these prior art semiconductor devices is that the high voltage values cannot be detected in a continuous manner. Typically, an external circuit is used to provide a voltage representative of the high voltage value. For example, the controller may be operated by a voltage of several hundred volts, and the input voltage value may change over time. In order to operate efficiently, the controller may need to detect the voltage value when the voltage changes during the operation of the controller, and a device for detecting a high voltage cannot be provided on the semiconductor chip, resulting in the use of an external element, which increases the system cost.

Therefore, a semiconductor device capable of detecting a high voltage signal is required.

Disclosure of Invention

According to a first aspect of the present invention, there is provided a method for forming a high voltage detection component, the method comprising: providing a substrate of a first semiconductor material having a first conductivity type; forming a first doped region of a second conductivity type on a first portion of a substrate, including forming the first doped region to be operable to receive an input voltage, wherein the first portion of the first doped region is part of a J-FET and a second portion of the first doped region is part of a MOS transistor; forming an insulator overlying a portion of the first doped region, wherein a first thickness of the insulator is greater than a second thickness of a gate insulator of the MOS transistor; forming a first resistor overlying the insulator, wherein a first terminal of the first resistor is coupled to a first doped region to receive an input voltage; and coupling a first current carrier of the J-FET to receive the input voltage and coupling a second current carrier of the J-FET to the first current carrier of the MOS transistor.

According to a second aspect of the present invention, there is provided a high voltage component comprising: a substrate having a semiconductor material of a first conductivity type; a first transistor having a first doped region of a second conductivity type on a first portion of the substrate, wherein the first transistor is a J-FET; a MOS transistor formed on the substrate, wherein a portion of the first doped region forms a portion of the MOS transistor; an insulator covering a portion of the first doped region; and a first resistor formed overlying at least a portion of the insulator and a first portion of the first doped region, a first terminal of the first resistor being coupled to a first current carrier of the first transistor, and a second terminal of the first resistor not being connected to the current carrier of the first transistor.

According to a third aspect of the present invention, there is provided a method for forming a high voltage component of a semiconductor device, comprising: providing a substrate having a first semiconductor material of a first conductivity type; forming a first doped region of a second conductivity type on a first portion of a substrate; forming an insulator overlying at least a portion of the first doped region, wherein the insulator has a first thickness; forming a first resistor overlying the insulator; coupling a first terminal of a first resistor to receive a signal representative of a signal applied at a first doped region; and coupling a second terminal of the first resistor to circuitry external to the high-voltage component.

According to a fourth aspect of the present invention, there is provided a method for forming a high voltage component of a semiconductor device, comprising: providing a substrate of a first semiconductor material having a first conductivity type; forming a first doped region of a second conductivity type on a first portion of the substrate, wherein the first portion of the first doped region is part of a J-FET and a second portion of the first doped region is part of a MOS transistor; forming an insulator overlying at least a portion of the first doped region, wherein the insulator has a first thickness; forming a first resistor overlying at least a first portion of the insulator; coupling a first terminal of a first resistor to a first current carrier of the J-FET; and coupling the second current carrier of the J-FET to the first current carrier of the MOS transistor.

According to a fifth aspect of the present invention, there is provided a method for forming a high voltage component of a semiconductor device, comprising: providing a substrate of a first semiconductor material having a first conductivity type; forming a J-FET transistor having a first doped region on a first portion of a substrate; forming a MOS transistor on a substrate, wherein a portion of the first doped region forms a portion of the MOS transistor, and forming a first resistor overlying at least a portion of the active area of the J-FET transistor, wherein a first terminal of the first resistor is coupled to the J-FET transistor and a second terminal of the first resistor is not coupled to the J-FET transistor.

Drawings

Fig. 1 schematically illustrates a circuit diagram of an embodiment of a part of a high voltage semiconductor device according to the present invention;

FIG. 2 illustrates an enlarged plan view of an embodiment of a portion of the semiconductor device of FIG. 1 in accordance with the present invention;

FIG. 3 illustrates a cross-sectional portion of the embodiment of the semiconductor device of FIG. 2 in accordance with the present invention;

fig. 4 schematically illustrates a circuit diagram of another embodiment of a part of a high voltage semiconductor device according to the present invention;

fig. 5 illustrates an enlarged cross-sectional portion of another embodiment of a high voltage semiconductor device in accordance with the present invention;

fig. 6 schematically illustrates a circuit diagram of an embodiment of a portion of a high voltage semiconductor device according to the present invention as an alternative embodiment of the device of fig. 1;

FIG. 7 illustrates a partially enlarged plan view of the embodiment of the high voltage semiconductor device of FIG. 6 in accordance with the present invention;

fig. 8 schematically illustrates a circuit diagram of an embodiment of a portion of a system utilizing the high voltage semiconductor device of fig. 1 in accordance with the present invention.

Detailed Description

For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, with like reference numerals referring to like elements in different figures. Moreover, well-known descriptions and details are omitted for simplicity of the description. As used herein current carrying electrode means a unit of the device that carries current through the device, such as the source and drain of a MOS transistor, or the emitter and collector of a bipolar transistor, or the cathode and anode of a diode, and a control electrode means a unit of the device that controls current through the device. Such as the gate of a MOS transistor or the base of a bipolar transistor, although the device is illustrated herein with some sort of N-channel or P-channel, those skilled in the art will appreciate that complementary devices according to the present invention are also possible. For clarity of the drawing, the doped regions of the device structure are illustrated with straight edges and precise corners, however, those skilled in the art will appreciate that due to diffusion and activation of dopants, the doped regions are not generally straight lines and the corners are not precisely angled.

Fig. 1 illustrates schematically a circuit diagram of a preferred embodiment of a portion of a high voltage semiconductor device 10. The device 10 forms a low voltage sense signal representative of the input voltage at the high voltage level. The device 10 comprises a high voltage detection component 11 which receives the high voltage and generates a detection signal representative of the high voltage on a detection output 16. When the input voltage value changes, the detection signal also changes. Device 10 is formed to also flow a first output current on output 24 in response to a control signal applied to control input 25.

In one embodiment, component 11 is part of a high voltage transistor and detection device 28 in device 10, device 28 being formed as a merged transistor comprising a JFET transistor 18 and a Metal Oxide Semiconductor (MOS) transistor 19. Device 10 may also include a bias resistor 21 to provide a bias current to the gate of transistor 19. Those skilled in the art will recognize transistors such as transistors 18 and 19 in device 28. An example of a similar transistor 18 and 19 arrangement is disclosed in U.S. patent No. 5,477,175 to Tisinger et al, which is published at 19.12.1995 and incorporated herein by reference. In other embodiments, transistor 19 may be other transistor structures such as a J-FET or a bipolar transistor. In other embodiments, resistor 21 may be of other configurations, such as JEFT. Device 10 is formed to receive an input voltage at input 23 and to generate a sense signal on output 16.

In the past, it has been difficult to detect high voltage values on high voltage semiconductor devices. For example, in some worldwide line voltage applications, the input voltage may exceed 400 volts (400V), and in some cases, may be as high as 700 volts (700V). For example, a transformer flyback voltage for a mains power supply system may increase an input voltage of 400 volts to 700 volts.

As will also be seen hereinafter, the member 11 is constructed in a manner that facilitates receiving such high voltages and responsively forming a detection signal. In one embodiment, component 11 is a resistor divider connected between input 23 and the lowest voltage applied to the semiconductor device comprising component 11. The lowest voltage generally uses a ground reference voltage, although other values may be used. The resistor divider comprises a first resistor 12 in series with a second resistor 13, wherein a sense signal is generated at a common node at a common connection between the resistors. Only one end of resistor 12 is connected to a current carrying electrode or terminal of either of transistors 18 or 19. To facilitate the device receiving the sense signal, the other or low voltage terminal of resistor 12 is connected to output 16 instead of connecting transistors 18 and 19. And neither end of resistor 13 is connected to the current carriers of transistors 18 and 19. Thus, the low voltage terminal of component 11 is not connected to high voltage device 28 and transistors 18 and 19. Only one terminal is connected to device 28 and transistors 18 and 19, helping to ensure that the sense signal is low. To minimize the power loss of the component 11, the resistors 12 and 13 are made very large. In one exemplary embodiment, the total resistance of the series connection of resistors 12 and 13 is generally no less than about 15 megaohms, but may be other values in other embodiments.

To help provide the functionality of device 10, a drain of transistor 18 is commonly connected to input 23 and first terminal 15 of component 11. A first terminal of resistor 12 is connected to terminal 15 and a low voltage terminal of resistor 12 is connected to output 16. Connection terminal 14 of component 11 is connected to the lowest voltage point of device 28. A first terminal of resistor 13 is connected to output 16 and a second terminal thereof is connected to terminal 14. A source of transistor 18 is connected to a common node 20 and a drain of transistor 19. Transistor 19 has a gate connected to input 25 and to a first terminal of resistor 21, and a source connected to output 24. A second terminal of resistor 21 is connected to node 20. Fig. 2 will illustrate the transistor 18 gate connection in more detail.

A portion of one embodiment of device 10 depicted in fig. 1 is illustrated with an enlarged plan view of fig. 2. Fig. 3 illustrates a portion of device 10 along section line 3-3 in fig. 2, the description being in an enlarged cross-section with reference to fig. 2 and 3. Resistors 12 and 13 of component 11 are formed over a portion of J-FET18, and transistor 18 is substantially depleted of carriers during high voltage operation. The depletion region of transistor 18 allows component 11 to withstand the high voltage applied to device 10 and generate a detection signal on output 16.

In fig. 2, transistor 19 is generally identified by arrows and dashed lines. In general, semiconductors 18 and 19 form a closed geometry on the surface of semiconductor substrate 40, with a typical closed geometry having concentric centers and overlapping perimeters. In a preferred embodiment, the closed geometry is formed as concentric circles or arcs of circles having various radii. For clarity of illustration, the preferred embodiment has been used. However, those skilled in the art will recognize that other closed shapes, such as oval, square, pentagonal, hexagonal, interdigitated, etc., may be used instead of circular, and that transistors 18 and 19 may have different lengths and widths.

In a preferred embodiment, the closed geometry of transistor 18 is formed as concentric circles of increasing radius. The first part of the geometry of transistor 19 is formed as a circle and the second part as an arc of a circle with a radius larger than the radius of the circular part of transistor 18. A circular doped region 41 is formed on the surface of the substrate 40. In a preferred embodiment, the doping profile of the doped region 41 is not multi-layeredThe graded profile of the impurity regions is substantially constant in region 41. This non-graded doping profile simplifies manufacturing and reduces manufacturing costs. It should be understood that the doping concentration may vary with depth and normal longitudinal variation, but the resulting doping profile does not change substantially gradually from a high concentration at one location to a lower doping at a second location. The doping types of region 41 and substrate 40 are opposite. Preferably, substrate 40 is P-type and has a resistivity of about 80 ohm-cm, and region 41 is doped to a concentration of about 1E15 cm^-3To 2E15 cm^-3The N-type of (1). Region 41 is typically 7 to 8 microns thick. A portion of region 41 forms a portion of transistors 18 and 19. Drain contact 46 of transistor 18 is formed as a doped region at the surface of substrate 40 and within region 41. Contact 46 is shaped as a first hollow circle having a first radius centered at 47. Contact 46 is concentric with region 41 but has a smaller radius than region 41. Since the shape of the contact 46 is a hollow circle, a first circle of the interior of the region 41 is formed below the contact 46 (see fig. 3). This first portion forms the drain region of transistor 18. A second circular portion 42 of region 41 extends from an outer rim 44 of outer circumferential region 41 of contact 46 and forms a channel of transistor 18. The interface of substrate 40 and region 41 functions as the gate of J-FET transistor 18. A third portion of region 41, which is generally considered to be the source of transistor 18 and the drain of transistor 19, is immediately adjacent to edge 44 and is at least under a portion of gate conductor 54. Typically, substrate 40, and thus the gate of transistor 18, is connected to the lowest potential in the circuit in which device 10 is used. Thus, the drain and source of transistor 18 are formed in a closed geometry, with the source radius being very large compared to the drain. And the source and drain of transistor 18 and the drain of transistor 19 are formed with one doped region.

The source region 49 of the transistor 19 is formed as a doped region at the surface of the substrate 46 and is formed as a circular arc having a radius larger than the radius of the transistor drain. Typically, the interior of the source region 49 is below the gate conductor 54. A doped region is formed within source region 49 and serves as a source contact 50 for transistor 19. Note that at tap opening 70 (see fig. 2) of device 10, source region 49 and contact 50 are discontinuous, and thus, region 49 and contact 50 are arcs of a circle. Outside transistors 18 and 19, contact regions 63 are formed as doped regions in substrate 40. Contact area 63 is used to connect one end or terminal of resistor 13 to substrate 40. Body region 48 of transistor 19 is formed as a doped region on the surface of substrate 40 underlying gate conductor 54. Preferably, to form transistor 18 as an N-channel J-FET transistor and transistor 19 as an N-channel MOS transistor, substrate 40, body regions 48, and contact regions 63 are P-type material, while regions 41, source regions 49, and contacts 50 are N-type material.

A gate insulator 52 is formed on substrate 40 and covers region 48 and at least the inner edge of region 49. Typically, for transistor 19 to function better, insulator 52 is a thin layer of silicon dioxide, typically no more than 50 to 60(50-60) nanometers thick. A thicker insulator 53 is formed on the substrate, below the contact 61 and covering a portion 42. Typically, contact 61 is connected to terminal 23 in fig. 1, and generally, insulator 53 is at least 10 to 30 times thicker than insulator 52 to help provide a high breakdown voltage between resistors 12, 13 and the underlying silicon structure. The insulator 53 is typically no less than 1 to 2(1-2) microns thick. A gate conductor 54 is formed to cover at least a portion of the insulator 52. When the conductor 54 is formed, the material for the conductor 54 is also formed on the insulator 53 and patterned to form a spiral pattern as shown in fig. 2 and 3. The spiral pattern forms resistors 12 and 13. Typically, the material for conductor 54 is polysilicon. The doping of the polysilicon portion used to form resistors 12 and 13 may be the same as or different from conductor 54 in order to provide a desired value for the resistivity of resistors 12 and 13 and conductor 54. In one embodiment, the sheet resistance of the polysilicon used for resistors 12, 13 is not less than about 20 ohms/sq, or the material used for resistors 12, 13 may be formed separately from conductor 54. In order for the resistors 12, 13 to have a high resistance, the spiral pattern around the center 47 should have as many turns as possible. The use of at least a minimum pitch between adjacent portions of the spiral pattern reduces the electric field between adjacent portions of the pattern. In one embodiment, the spiral pattern has about 35 turns. Typical values for the spacing between adjacent turns of the spiral pattern are on the order of 1 to 2(1-2) microns. Other patterns may be used to form resistors 12 and 13. For example, the pattern may be formed as an ellipse, a square, a pentagon, a hexagon, etc., when the underlying region 41 has such a shape. Another insulator 57, such as an interlayer dielectric, is used to cover resistors 12, 13, conductor 54, and portions of substrate 40 that are external to transistors 18, 19. The use of a minimum spacing between adjacent portions of the spiral pattern also reduces the lateral electric field across the insulator 57, thus reducing the likelihood of breakdown, and increases the voltage value detectable by the component 11, the insulator 57 separating adjacent portions of the spiral pattern. Note that insulator 57 is not shown in fig. 2 for clarity of drawing. A conductor 35 is formed through an opening in the insulator 57 which is in electrical contact with the spiral pattern and patterned to form resistors 12 and 13. A further conductor 64 is formed through a further opening in the insulator 57 and is in electrical contact with the end or terminal of the spiral and connects the end or terminal of the resistor 13 to the substrate 40 via the contact area 63. Another conductor 59 is formed through an opening in insulator 57 which overlies contact 50 to form an electrical contact thereto to form a source conductor of device 10. Contact 61 may be formed as part of, or after, the formation of conductors 35, 59, and 64, it being noted that conductor 59 is not shown in fig. 2 for clarity of drawing.

Referring to fig. 2, where one turn of the spiral of device 11 passes through opening 70, conductor 35 is formed, which extends through conductor 54 and forms output 16 through opening 70. The output 16 may then be connected to a component (not shown) such as an operational amplifier or comparator formed on the substrate 40. Conductor 35 extends outside of transistor 19 for facilitating electrical contact with components external to device 10. A conductor 64 is formed in electrical contact with the end of the spiral and connects one end or terminal of the resistor 13 to the substrate 40 (fig. 3) through a contact area 63. A portion of the gate conductor 54 is formed to also extend through the opening 70 and form a tab 71 to facilitate contact with the gate conductor 54. Resistor 21 is also formed as a doped region on the surface of substrate 40 outside of device 28, with one end of resistor 21 extending below bond pad 71 (indicated by the dashed line) for making electrical contact with region 41 at edge 44 and node 20. The second end of the resistor 21 is connected to a connection pad 71 by a metal connection 72. To facilitate making the connection to the region 48, a portion of the region 48 extends through the opening 70. For clarity of drawing, the region 48 extends through the opening 70 and is not shown.

In operation, the J-FET function of transistor 18 serves to evenly distribute the high electric field voltage applied across region 41, and particularly between the drain and source of transistor 18 in region 42. Therefore, in the on or off state of the transistor 18, the influence of the high electric field voltage on the resistors 12 and 13 is negligible, and vice versa. The influence of the potential distributed evenly over the resistors 12 and 13 on the doped region of the transistor 18 lying below is also negligible. Typically, substrate 40 is connected to the lowest voltage of the system in which device 10 is used. When a high input voltage is applied to input 23, the large voltage difference between substrate 40 and region 41 causes transistor 18 to substantially deplete carriers. This depletion will be present in substrate 40 and portion 42 of transistor 18. The potential across portion 42 will generally cause region 42 to be substantially depleted as a result of the high input voltage, and transistor 18 will operate in a pinch-off state. The doping concentrations of substrate 40 and region 41 are selected to be so low as to provide substantial depletion at the voltage applied to input 23. In most embodiments, a voltage greater than about 5V, typically about 40 to 50 volts (40V-50V), is applied to input 23, and preferably about 400 to 700 volts (400-700V). The combined depletion effect of substrate 40 and region 42 can withstand such high voltages by simply extending their depletion region widths without exceeding the critical electric field of silicon, which is about 0.3 megavolts/cm.

The vertical potential between the component 11 and the top surface of the underlying region 42 is borne by the thickness of the insulator 53 at any given portion, although a small portion may be borne by the material of the component 11. Since a high voltage is applied to region 42 and a high voltage is applied to one terminal of resistor 12, only a modest difference in these voltages remains vertical between insulator 53 and device 11And (4) supporting. The majority of the vertical voltage is carried through the thickness of the insulator 53 while keeping the electric field well below the breakdown field of the material of the insulator 53. Typically, the material is silicon dioxide, which corresponds to an electric breakdown field of about 10 megavolts/cm. Due to the low resistivity of the material, the component 11 is subjected to only a small fraction of the vertical voltage. The material is typically doped polysilicon having a doping concentration of no less than about 1 x 10¹⁸To 1X 10¹⁹Electron/cm³. For example, when a voltage of about 700 volts (700V) is applied at input 23, the vertical voltage across member 11 and insulator 53 may be about 60 to 70 volts (60-70V). Of these 60 to 70 volt vertical voltages, typically less than about one volt drops vertically on the component 11, with the other voltage dropping on the insulator 53. In general, the potential at each point on the pattern of resistors 12 and 13 and the potential at the corresponding point in the underlying region 42 will track each other. This helps to minimize the amount of vertical electric field between them. The sustainable vertical voltage can be varied by adjusting the position of the two ends of the resistor 11 on the insulator 53 relative to the portions of the transistor 18 like the contact 46 and the edge 44. Region 41 provides isolation between substrate 40 and component 11, since at least portion 42 is substantially depleted of carriers. Therefore, the high electric field does not cause the substrate 40 to break down. Thus, region 41 and insulator 53 aid in the operation of component 11. Those skilled in the art will appreciate that under all operating conditions not all carriers are depleted from portion 42, but rather a substantial majority of the carriers are depleted, and that in such a case, the region is referred to as a carrier depletion region or substantially carrier depletion region. Those skilled in the art will also appreciate that the component 11 and corresponding resistors 12 and 13 may be formed to cover the depletion regions of other such, not just the depletion regions of the J-FETs.

Fig. 4 illustrates a circuit diagram of an embodiment of device 30, which is an alternative embodiment of device 10 in fig. 1. The device 30 includes a high voltage detection component 32 which is an alternative embodiment of the component 11. The component 32 receives the high voltage and forms a detection signal on the detection output 16. One terminal of the resistor 13 extends outside the active area of the device 28 and forms the connection terminal 14. Device 30 includes a power saving switch 22 for selectively switching terminal 14 to the lowest voltage applied to member 32. The switch 22 includes a switch control input 17 that is used to enable or disable the switch 22. For example, switch 22 is periodically enabled to form a sense signal on output 16, and then disabled after the sense signal is used. Disabling switch 22 reduces the power loss of the unit 32 and still allows component 32 to form a detection signal similar to component 11.

Fig. 5 illustrates an enlarged cross-sectional view of a portion of an embodiment of a semiconductor device 150 including a component 11. Device 150 is formed on a semiconductor substrate 140 similar to substrate 40 of fig. 2 and 3. A doped region 141 is formed on the surface of the substrate 140. The doping and insulating properties of region 141 are similar to those of region 41, forming contact 161 to receive a high input voltage. Node 161 is also formed to contact one terminal of resistor 12 and provide a connection to region 141 so that the high voltage received by contact 161 is applied at region 141. Contact region 163 is formed in substrate 140 similarly to region 63. A second end or terminal of resistor 13 extends through insulator 53 to make electrical contact with region 163. Similar to component 11, region 141 and insulator 53 are part of component 32. Device 150 may be part of a pulse width modulation (PMW) power supply controller or other type of device that may utilize component 11 to detect continuously changing values of a high voltage signal.

Fig. 6 illustrates a circuit diagram of an embodiment of a high voltage semiconductor device 80, which is an alternative embodiment of device 10. The component 11 comprises the resistor 12 but omits the resistor 13. Resistor 12 has one terminal connected to receive a high input voltage and a second terminal connected to output 16 to provide a low voltage sense signal. Similar to device 10, to minimize power losses of component 11, the value of resistor 12 is chosen to be large, typically no less than 15 megaohms.

Device 80 also includes a current mirror configured to receive the sense signal and responsively generate an output voltage on output 88 that is representative of the high input voltage received on input 23. The current mirror includes a clamping diode 81, a comparator transistor 84, and a current source 85. Output 88 is formed by connecting transistor 84 and current source 85. Diode 81 clamps the low voltage terminal of resistor 12 and the voltage at the base of transistor 84 to a fixed voltage. Terminal 86 of the current mirror is typically connected to receive the resulting operating voltage on output 24. As the value of the voltage on input 23 increases, the value of current 82 flowing through resistor 12 also increases. The increase in current 82 allows transistor 84 to conduct more current and decrease the voltage on output 88. Thus, when the high input voltage value on input 23 increases, the detection signal value on output 88 responsively falls and serves as a comparator output, switching state when the current through resistor 12 is greater than the current of current source 85. It will be appreciated that a resistor could be substituted for current source 85 and output 88 could produce an analog voltage representative of the value of the voltage received on input 23.

An enlarged plan view of a portion of the embodiment of device 80 depicted in fig. 6 uses fig. 7 to illustrate that this description makes reference to fig. 6 and 7. The portion of device 80 illustrated in fig. 7 omits the current mirror of device 80. Similar to device 10, resistor 12 is formed to overlie a portion of J-FET18 that is substantially depleted of carriers during operation of transistor 18. Since device 80 omits resistor 13, the pattern of resistor 12 generally extends to include the pattern used as resistor 13 in fig. 2 and 3. Note that one terminal of resistor 12 is connected to receive the high input voltage from input 23 and the other terminal of resistor 12 is connected to output 16 rather than to the current carrier of transistors 18 or 19.

Fig. 8 schematically illustrates a portion of one particular embodiment of a power control system 100. The control system regulates the value of the output voltage of system 100 using device 10, system 100 receiving the bulk input voltage between input terminals 110 and 111 and controlling power switch 105 to provide the output voltage between output terminals 112 and 113, device 10 receiving the bulk voltage on input 23 and providing a sense signal to output 16. The power control system 101 of system 100 has a PWM controller 103, a control circuit 102 and a device 10. Device 10 is also used to provide a start-up voltage for operation of controller 103 and circuit 102. Amplifier 104 receives the detection signal and amplifies it, and circuit 102 receives the amplified detection signal and processes it to provide control functionality for controller 103. Control functions may include, among other functions, brown-out detection and breaking, line over-voltage detection and breaking, input power detection and limiting, line feed-forward for current mode ramp compensation, power limiting, and/or backup operation. Those skilled in the art will appreciate that device 30, 80 or 150 may also be used in place of device 10.

In another embodiment, node 23 is connected to the drain of switch 105 in place of input 110, and when switch 105 is non-conductive, the amplified detection signal is useable by control circuit 102 to regulate the output voltage as a function of the flyback voltage of the transformer. When the switch 105 is not conducting, the control circuit 102 may also detect the flyback voltage to determine whether the transformer has energy stored at a certain point in time.

From the foregoing, it should be apparent that a new apparatus, method of forming the apparatus, and method of using the apparatus are disclosed. The invention includes, among other features, forming a high-voltage component overlying a doped region that may be substantially depleted of carriers during operation of the high-voltage component. The invention also includes forming a high voltage feature overlying a thick insulator, such as a field oxide, which overlies a portion of the doped region. For clarity of description, the word "connected" is used throughout, however, it has the same meaning as "coupled" throughout. Accordingly, "connected" should be understood as directly connected or indirectly connected.

Claims (10)

1. A method for forming a high voltage detection component, the method comprising:

providing a substrate of a first semiconductor material having a first conductivity type;

forming a first doped region of a second conductivity type on a first portion of a substrate, including forming the first doped region to be operable to receive an input voltage, wherein the first portion of the first doped region is part of a J-FET and a second portion of the first doped region is part of a MOS transistor;

forming an insulator overlying a portion of the first doped region, wherein a first thickness of the insulator is greater than a second thickness of a gate insulator of the MOS transistor;

forming a first resistor overlying the insulator, wherein a first terminal of the first resistor is coupled to a first doped region to receive an input voltage;

coupling a first current carrier of the J-FET to receive an input voltage and coupling the first current carrier of the J-FET to a first terminal of a first resistor and coupling a second current carrier of the J-FET to a first current carrier of the MOS transistor; and

a second terminal of the first resistor is coupled to a detection output of the high voltage detection component.

2. The method of claim 1, further comprising electrically coupling a first terminal of a second resistor to a second terminal of the first resistor.

3. A high voltage component comprising:

a substrate having a semiconductor material of a first conductivity type;

a first transistor having a first doped region of a second conductivity type on a first portion of a substrate, wherein the first transistor is a J-FET having a first current carrier coupled to receive an input voltage;

a MOS transistor formed on the substrate, wherein a portion of the first doped region forms a portion of the MOS transistor;

an insulator covering a portion of the first doped region; and

a first resistor formed overlying at least a portion of the insulator and a first portion of the first doped region, a first terminal of the first resistor coupled to a first current carrier of the first transistor and a second terminal of the first resistor not connected to the current carrier of the first transistor, wherein the second terminal of the first resistor is coupled to the detection output of the high voltage component.

4. The high voltage component of claim 3 further comprising a second resistor overlying the insulator, overlying the second portion of the first doped region, and coupled to the first terminal of the first resistor.

5. A method for forming a high voltage component of a semiconductor device, comprising:

providing a substrate having a first semiconductor material of a first conductivity type;

forming a first doped region of a second conductivity type on a first portion of a substrate;

forming an insulator overlying at least a portion of the first doped region, wherein the insulator has a first thickness;

forming a first resistor overlying the insulator;

coupling a first terminal of a first resistor to receive a signal representative of a signal applied at a first doped region; and

a second terminal of the first resistor is coupled to the detection output of the high voltage component.

6. The method of claim 5, further comprising coupling a first terminal of a second resistor to a second terminal of the first resistor.

7. The method of claim 6, further comprising coupling a second terminal of the second resistor to the substrate.

8. The method of claim 5, the step of forming the first doped region comprising forming the first doped region without a graded doping profile.

9. A method for forming a high voltage component of a semiconductor device, comprising:

providing a substrate of a first semiconductor material having a first conductivity type;

forming a first doped region of a second conductivity type on a first portion of the substrate, wherein the first portion of the first doped region is part of a J-FET and a second portion of the first doped region is part of a MOS transistor;

forming an insulator overlying at least a portion of the first doped region, wherein the insulator has a first thickness;

forming a first resistor overlying at least a first portion of the insulator;

coupling a first terminal of a first resistor to a first current carrier of the J-FET and coupling the first terminal of the first resistor to receive an input voltage;

coupling a second terminal of the first resistor to a detection output of the high voltage component; and

the second current carrier of the J-FET is coupled to the first current carrier of the MOS transistor.

10. A method for forming a high voltage component of a semiconductor device, comprising:

providing a substrate of a first semiconductor material having a first conductivity type;

forming a J-FET transistor having a first doped region on a first portion of a substrate;

forming a MOS transistor on a substrate, wherein a portion of the first doped region forms a portion of the MOS transistor, an

Forming a first resistor covering at least a portion of an active area of the J-FET transistor, wherein a first terminal of the first resistor is coupled to a first current carrier of the J-FET transistor and coupled to receive an input voltage, and wherein a second terminal of the first resistor is coupled to a detection output of the high voltage component and not coupled to the J-FET transistor.