HK1092604A - Extracting soft information in a block-coherent communication system - Google Patents

Description

Extracting soft information in a block coherent communication system

Technical Field

The present invention provides methods and apparatus for data communication over a block-coherent channel, and more particularly, methods and apparatus for joint demodulation and decoding for forward error detection and/or correction.

Background

Communication systems require non-coherent detection when their receivers cannot maintain a reliable estimate of instantaneous channel gain (amplitude and especially phase). Non-coherent communication systems include, for example, wireless multiple-access systems in which the mobile node has limited power and cannot transmit high power known symbols, such as pilots, to allow reliable channel estimation. A non-coherent communication channel may have some coherent properties. For example, a non-coherent communication channel may include coherent blocks, where coherent blocks are time intervals during which channel variations are negligibly small. Communication over such a channel is referred to as block coherent communication.

Block coherent communication may occur naturally in fast frequency hopping Orthogonal Frequency Division Multiplexing (OFDM) access systems. In such systems, information may be modulated onto a subset of available frequencies, calling tones, in each symbol time. To improve spectral efficiency and increase diversity gain, the tones used are sometimes skipped quickly over the entire used frequency band every L symbols, e.g., L consecutive symbols are mapped to one tone, followed by another L symbols mapped to a different tone, etc. When L is small, consecutive L symbols can be considered to experience the same channel gain. While the amplitudes of the gains of two consecutive groups of L symbols may be close, their phases are usually completely independent.

More specifically, a block coherent communication system may be defined as: for systems represented in the discrete time domain, the channel gain is an unknown complex random variable, generally remaining the same for every L consecutive symbols, but varying independently according to some distribution, e.g., the phase is uniformly distributed over [0, 2PI ], and the amplitude is Rayleigh (Rayleigh) distributed.

For block coherent communication, the nominal modulation scheme is differential M-ary phase shift keying (DMPSK). DMPSK carries information in the phase difference between two consecutive symbols on the coherent block. To illustrate, N × (L-1) MPSK information symbols s (i) are transmitted, each of N consecutive groups of the L-1 symbols, denoted by s (1), s (2),.., s (L-1), is differentially encoded into transmitted symbols t (0), t (1), t (2),.., t (L-1), where t (0) is set as a known symbol, and t (j) · t (j) × s (j), j · 1,. N-1.

Modulation schemes other than DMPSK are possible. For example, with known symbols inserted in a block, information symbols can be sent directly on other symbols without differentiation. This modulation scheme may be referred to as pseudo pilot modulation. Obviously, however, due to the phase uncertainty, a maximum of L-1 information symbols can be transmitted within a gap (dwell) of length L. We can therefore assume that a known symbol is present in each slot. Using the above illustrated notation, t (0) is set to a known symbol and the remaining transmitted symbols are t (j) ═ s (j), j ═ 1, ·, L-1.

With forward error correction coding, a block-coherent communication system will typically include an encoder (which inserts structured redundancy into the original data stream), a modulator, such as DMPSK, (which maps binary data bits into MPSK symbols), a demodulator (which extracts and feeds soft information to a decoder), and a decoder (which decodes the original message based on the soft information from the demodulator).

With block coherent reception, the relationship between the received symbols y (i) and the transmitted symbols t (i) is as follows:

y(i)＝αe^jθt(i)+n(i)

where θ is the unknown phase, α is the unknown (actual) channel gain, and n (i) is the additive noise component.

In most coding systems, receivers that apply iterative demodulation and decoding (hereinafter referred to as a turbo equalization scheme) have significant performance gains over non-iterative receivers. For example, the convolutional and/or turbo coded DMPSK system, studied in ieeprocessing communications 2000 by Shamai et al, "Iterative decoding for encoded non-coherent MPSK communications over phase-noise AWGN channel with phase interference," demonstrated turbo equalization performance within a channel capacity of 1.3dB, and 1dB better than the conventional scheme.

It has been shown that the code design takes into account the effects of iterative demodulation in order to make turbo equalization maximally effective. The importance of code design and the efficient way to achieve this is described in the article "design of Low-Density Parity-Check Codes in non-coherent communication" by Jin and Richardson published on International symposium on information the term 2002. The method therein improves the performance in a channel capacity of 0.7 dB.

While the performance of turbo equalization is important, for communication systems intended for practical use by various types of devices, such as user equipment, it is important that the turbo equalization be implemented at a reasonable cost. Thus, the ability to efficiently implement turbo equalization used by block coherent communication systems, e.g., in terms of hardware cost, can be an important factor.

From an implementation cost perspective, the practical challenges posed by turbo equalization are (i) the complexity of the soft-in-soft-out (SISO) demodulator and (ii) the necessary data interleaving at the transmitter and receiver.

One known method of implementing a SISO demodulator is to apply belief propagation (belief propagation), for example the Bahl-Cocke-Jelinek-raviv (bcjr) algorithm if DMPSK modulation is used. Such a demodulator requires considerable complexity. The BCJR algorithm runs on a trellis formed by quantizing the phase space (0, 2PI) to equidistant phase points. For example, 8 levels of quantization form 8 points, 0, 1/4PI, 7/4 PI. Thus, the unknown phase associated with the gap can only be one of those points, if no noise is added, as can the phase of the received symbol. The L symbols inside the slot comprise said trellis, each symbol being one of said eight states. The information symbols determine the transition from the current state to the next state. On the trellis, the BCJR algorithm returns a soft guess for the information symbol. The complexity of the BCJR algorithm is linear in the cardinality of the state space.

Implementing belief propagation demodulation of pseudo pilot modulation brings similar complexity that is linear in the base of the quantization interval.

Therefore, it is apparent that there is a need for a method and apparatus that addresses the complexity of soft-in soft-out demodulation. There is a need for a method and apparatus for low complexity demodulation that achieves good performance in a block communication system.

Description of the drawingsMing dynasty

Fig. 1 illustrates an exemplary communication system employing the methods and apparatus of the present invention, comprising an encoder, a first interleaver, a modulator, a communication channel, a demodulator, a deinterleaver, a second interleaver, and a decoder.

Fig. 2 shows an exemplary structure of joint demodulation and decoding using data interleaving and deinterleaving in an exemplary receiver according to the present invention.

Fig. 3 is an exemplary soft-in soft-out demodulator implemented in accordance with the present invention that may be used as the demodulator in fig. 2.

Fig. 4 is an example of an exemplary embodiment of a module implemented according to the present invention that generates updated independent phase estimates from independent phase estimates using known extrinsic rules.

Fig. 5 is a flow chart illustrating an exemplary method according to the present invention.

Fig. 6 shows a diagram of an exemplary set of information according to the present invention.

Disclosure of Invention

The present invention provides a method and apparatus for data communication over a block coherent channel. For simplicity, symbols transmitted in one coherence interval are referred to as gaps in this application. The length of the gap is L. A gap including L symbols is a unit for information transmission purposes.

Examples for explaining the present invention include the use of Gray mapped QPSK symbols with constellation points S0 ═ 1+ j, S1 ═ 1+ j, S2 ═ 1-j, and S3 ═ 1-j on the complex plane. A pair of two bits, also called dibit (dibit), is mapped to one QPSK symbol: dibit 00 maps to S0; dibit 01 maps to S1; dibit 11 is mapped to S2; and the dibit 10 is mapped to S3. Symbolically, we denote the mapped QPSK symbol for the dibit (c1c2) using S (c1c2), then S (00) is S0, and so on.

It will be appreciated that the techniques described in the application given in the QPSK exemplary context can be easily generalized and are well suited for higher order MPSK, as such an implementation is considered to be within the scope of the present invention.

Various features of the invention provide a method and apparatus for a low complexity SISO demodulator adapted to process pseudo pilot modulated information corresponding to each of one or more gaps. The low complexity method of the present invention provides good performance under turbo equalization.

In summary, this is achieved by first estimating the unknown phase independently based on each of L pairs of information, each pair comprising a received symbol y (i) and updated a priori information about the transmitted symbol t (i) fed back from the decoder. Which produces L independent estimates, one for each symbol's index i. Second, a new phase estimate for the ith symbol may be formed by averaging estimates of the other L-1 symbols, following "approximate Shannon limited error correction encoding and decoding" in Geneva, Switzerland, 5.1993 IEEEEEInternational Conference on Communications at page 1064 + 1070, A.Glavieux, P.Thitimajshima: turbo codes (Near Shannon limit error-correcting coding and Turbo codes) are non-inherent principles.

Finally, the new phase estimate can be used to generate soft information about the symbol (and thus the two bits associated therewith). This technique does not require quantization of the unknown phase and therefore requires little complexity.

In the exemplary SISO demodulation embodiment, for bits c (2i), c (2i +1) associated with QPSK symbol t (i), the decoder feeds the demodulator with soft messages, m (2i) and m (2i + 1). The soft message may take the form of a log-likelihood ratio, meaning the logarithm of the ratio of the probability that bit c is 0 to the probability that bit c is 1. The log-likelihood ratio of the two bits c (2i) and c (2i +1) can be processed to obtain the expected value of the symbol t (i):

E(t(i))＝(tanh(m(2i)/2)，tanh(m(2i+l)/2))，

and the expected value of the conjugate of s (i):

E(t(i)^*)＝(tanh(m(2i)/2)，-tanh(m(2i+l)/2))。

due to the special properties of the tangent-hyperbolic function, a simplification of this expected value by an approximation is possible with little performance degradation. For example, assuming that the soft message is quantized in ln (2) steps, an exemplary approximation is:

-3/4 when m < -10 [ ] -3/4

-1/2 when-10 < m < - > 6

-1/4 when-6 < m < -1

Equation (1) when-1 < ═ m < ═ 1 is 0 tan (m/2) < ═ 0

1/4 when 1 < m < 6

1/2 when m < 10 is 6 < ≦ m

3/4 when m > -10.

In this approximation, three bits are sufficient to represent the real and complex components of the expected value of the symbol t (i).

The known symbol t (0), which may be assumed to be 1+ j for the purpose of explaining a specific embodiment of the present invention, without loss of generality. There should be some special treatment in the gap. Its expected value E (t (0)) is known and is therefore set to t (0) ═ 1+ j, E (t (0)^*) Is set as t (0)^*1-j. It is equivalent to set tanh (m/2) ═ l. In other embodiments, the known symbol t (0) may be a different known value, and E (t (0)) and E (t (0)^*) May be set accordingly. Given y (i) ═ α e for each symbol in the same slot^jθt (i) + n (i), y (i) and E (t (i)^*) Multiplication yields alphae^jθIs referred to as T (i). T (0) is α e for a known symbol within the gap^jθIs estimated.

Thus, within a gap, we can obtain L independent estimates T (i) that include the unknown phase e^jθIndependent estimation of (a).These independent estimates can now form a new set of L estimates, containing a new estimate of the unknown phase, T' (i), following extrinsic principles.

Equation (2)

Thus, the conjugate multiplication of y (i) with T' (i) gives α²t (i) + α n (i); thus, soft messages for m (2i) and m (2i +1) will be proportional to the real and imaginary parts of y (i) T' (i). They are converted to the correct form of log-likelihood ratio by appropriately scaling with truncation and/or padding (puncturing) shifts.

In principle, the weighting coefficients "a" will be adaptively tuned during turbo equalization for best performance. In practice, however, setting the example constant of a-2 provides approximately the best performance in some implementations. When equation (1) is implemented in software or hardware, this simplifies implementation even further since constant multiplication can be incorporated into the mapping step.

Detailed Description

Fig. 1 illustrates an exemplary general communication system 10 in which the present invention may be implemented. In some embodiments, communication system 10 may be, for example, an OFDM communication system. The system 10 includes a transmitter 100 coupled by a communication channel 110 to a receiver 120. In other embodiments, transmitter 100 may be part of a wireless terminal and the receiver may be a base stationThe communication channel may be an uplink communication channel. In some embodiments, the transmitter 100 may be part of a base station and the receiver may be part of a wireless terminal, and the channel may be a downlink communication channel. Transmitter 100 includes data encoding circuitry such as encoder 101, interleaver 102, and modulator 103. The receiver includes a demodulator 121, a deinterleaver 122, an interleaver 123, a data decoder 124, and a synchronization signal generator 151. The decoder 124 may be a Turbo decoder, an LDPC decoder, or another type of decoder. The encoder 101 maps the input binary data stream a into a structured binary data stream X with redundancy₁. Interleaver 102 interleaves X₁To generate another data stream X₂. Modulator 103 converts binary stream X₂Transformed into a physical signal S, e.g. a QPSK signal, usable for the actual transmission. The communication channel 110 may be, for example, an airlink. After the modulated signal t is transmitted through the channel 110 to the receiver 120, it is received as signal Y. The demodulator 121, deinterleaver 122 and interleaver form a combined demodulation and interleaver device 150. The demodulator 121 and the data decoder 124 provide symbol timing and other information to the synchronization signal generator 151. The sync signal generator 151 generates a gap sync signal indicating alignment of the received symbols within the gap from the provided information. This information allows a device provided with the gap synchronization signal to determine which symbol within the gap is being processed at any particular point in time. On the receiver side, demodulator 121 extracts information X from the noisy distorted reception Y₂'. Deinterleaver 122 reorders the soft message X corresponding to the original order of the code structure₂' is X₁'. The decoder 123 attempts to decode the encoded data stream X produced by the demodulation by using it₂The redundancy that occurs in' restores the original binary data stream a. The output from the data decoder is a 'representing the recovery of the receiver's estimate of the original data stream a. The data path from data decoder 124 to demodulation 121 represents a feedback loop. The feedback path includes an interleaver 123. Corresponding to U₁Is interleaved by interleaver 123 to convert the order at the decoder to that at the modulator103 to produce an output corresponding to U₂The message of (2).

Fig. 2 is a diagram of an exemplary combined demodulation and interleaving apparatus 150' that may be used in place of the apparatus 150 of fig. 1. The exemplary demodulation and interleaving apparatus 150' shows a specific implementation of joint decoding and demodulation at the receiver side according to the present invention, where a data interleaving and deinterleaving control circuit 202 is coupled at the receiver side. From decoder corresponding to U₁Is stored in the soft output (from decoder) memory (block 200). The soft output is generated from the received signal Y and stored in a soft input (from channel) memory (block 208). The soft output from the decoder memory (block 200) and the soft input from the channel receiver memory (block 208) are considered to have the same configuration as the coded bits. Interleave control circuit 202 generates the correct addresses to access the soft outputs from decoder memory and the soft inputs from path memory in a gapped order, resulting in a corresponding U₂The message with Y is forwarded to the demodulator 204. Demodulator 204 extracts information X from the noisy distorted reception Y₂'. The same generated address generated by the interleaving control circuit 202 for accessing information input to the demodulator 204 is delayed by the delay introduced into the delay line 210. The output of the delay line 210 is used as a write address for controlling the information X to be output from the demodulator 204₂' the soft input is written into the decoder memory (block 206), and provided to the decoder as X₁′。

The write and read addresses provided to the memories 202, 206 may cause soft values corresponding to known signals, such as pilot signals or pseudo pilot signals, to be written to the dummy locations. These values are not important since known soft values corresponding to pilots or pseudo pilots may be used in place of them. However, it is important to use the actual address for the information corresponding to the data symbol, since such values are not fixed and it is important to recover the value for the data. Writing pilot or pseudo pilot related values to dummy addresses is performed in some embodiments to provide an easy way of maintaining time synchronization with the received symbol stream to be processed.

Fig. 3 illustrates an exemplary demodulator 204 that performs demodulation according to one embodiment of the invention. Demodulator 204 may be used as the exemplary demodulator in fig. 2. In the example of FIG. 3, the subscript x, for exemplary complex symbols, for example, denotes U₂、X′₂Y, IPE or UIPE, indicating the real part of the complex symbol, and subscript Y indicating the imaginary part of the complex symbol. Thus, in the example of FIG. 3, U_2xAnd U_2yRepresents U₂I and Q parts of (A), Y_xAnd Y_yI and Q moieties, X 'representing Y'_2xAnd X'_2yRepresents X'₂I and Q parts of (a).

In demodulator 300, mapping module 301 maps the soft messages m (2i) and m (2i +1) from the decoder, respectively associated with the real and imaginary parts of the symbol u (i), to three-bit values, respectively, according to equation (1). Submodule 311 AND U_xThe associated soft message m (2i) is mapped to a three-bit value and sub-module 313 maps the bit value with U_yThe associated soft message m (2i +1) is mapped to produce the other three bit values. The mapping module 301 also includes weighting coefficients "a" 319 that may be passed through a mapping submodule (311, 313) having known symbols, e.g., pseudo pilot symbols, e.g., as multipliers. In some embodiments, the weighting coefficient "a" (319) may be set to a constant value, e.g., 2. In other embodiments, the weighting coefficients "a" may be adaptively tuned, such as during turbo equalization. The mapping of said block 301 forms t (i)^*(conjugate of t (i)) to form t (i)^*Is calculated from the expected value of (c). The output from the mapping module 301 is soft bits corresponding to complex symbol values. In some embodiments, a look-up table may be used for the mapping. Based on the gap synchronization signal 323, the mapping modules 311, 313 may determine when known symbols, such as pseudo pilot symbols or pilot symbols, are being processed. Processing of known symbols, such as pseudo pilot symbols or pilot symbols, may include providing known values to the soft value input of mapping module 301 in place of soft values. Thus, the known symbols, e.g. dummy pilots or pilot symbols, may be performed differently than onMapping to data symbols. Likewise, based on the gap synchronization signal 323, the complex multiplier a303 may process values corresponding to known symbols, e.g., pseudo pilot symbols or pilot symbols, which are different from the symbols corresponding to data symbols. For example, first the complex multiplier 303 may define the multiplication of values in the case of known symbols, such as pseudo pilot symbols or pilot symbols, as a real number multiplication operation to avoid phase rotation, which may occur if the complex multiplication is performed on values corresponding to data symbols in the gaps. Complex multiplier A303 generates t (i)^*And the product of the received value y (i). The result is an Independent Phase Estimate (IPE) for each symbol in the gap. Production of Individual seeds (IPE)_x) And deficiency (IPE)_y) And (4) IPE. Module 305 processes the components of the complex IPE to produce an updated independent phase estimate (UEPE) that includes real and imaginary parts for each symbol in the gap. The module 305 uses known symbol information, e.g., pilot or pseudo-pilot symbol information, and knowledge of the gap structure in the process, e.g., from which the UIPE module 305 can determine where in the symbol sequence the pilot or pseudo-pilot will occur. The gap sync signal 323 is directly input to the module 305. The process of generating the UIPE may be implemented independently for each real and imaginary component. In FIG. 3, the extrinsic estimate/update submodule 315 handles IPEs_xTo produce UIPE_xRather than the intrinsic estimate/update submodule 317 handling IPEs_yTo produce UIPE_y。

The generated UIPE_xAnd UIPE_yTo conjugate circuit 306. Conjugation circuit 306 performs a conjugation operation on the signal provided to it. In various implementations, conjugation circuit 306 and complex multiplier B307 are combined into a single circuit.

Complex multiplier B307 then UIPE^*Multiplied by the received value y (i) to generate new soft messages m '(2 i) and m' (2i +1) up to the scaling constant. The received values y (i) may be from the same source as the input to block 303 and are delayed by a delay line block 309 which matches the pipeline delay in block 305It is late. The output from the complex multiplier B is X'₂(i)。

In a particular embodiment, module 305 generates a complex UIPE following known extrinsic rules. Fig. 4 illustrates a specific embodiment of a module 400 implemented using extrinsic rules, which may be used as the UIPE module 305 of fig. 3. In such an embodiment, the accumulator 401 produces a sum of all IPE T (i) in the slot. Accumulator 401 includes an addition module 403, a delay element 405 (with a delay corresponding to 1 time interval of one symbol being processed), and a feedback loop. The output of the summing block 403 is input to a delay element 405; the output of the delay element 405 is fed back as an input to the summing block 403 to be added to the IPE input signal. The output of delay element 405 is also coupled to an input of an add register 407. The sum of all IPEs inside the gap is locked, e.g. stored in an addition register 407, wherein the locking is controlled by a signal gap lock 409 indicating the boundaries of the gap. In the specific embodiment, it is assumed that there are L symbols in the gap. Reset signal 411 may be used to clear accumulator 401 and resume summing for subsequent slots. The add register 407 holds the locked sum value corresponding to the last gap and the accumulator 401 starts accumulating the sum corresponding to the new gap. The module 400 also includes a control module 415 that can generate the reset signal 411 and the clearance lock 409. Gap sync signal 323 is an input to control module 415 and can be used by the control module as a trigger to generate signals 411 and 409 at the appropriate time. Gap sync signal 323 is generated from sync signal generator 151 and is used to provide synchronization capabilities that facilitate identification of gap boundaries.

The module 400 further comprises a delay element 413 (having a delay corresponding to L time intervals of L symbols of the processed slot) and a subtraction module 415. Delay element 413 performs L delays on each IPE symbol received as input. Z_-L413 is a pipeline delay element capable of storing multiple IPE values. The delay 413 may be implemented as a series of L unit delay elements. Other implementations are possible. Subtraction module 415 receives as inputThe output of the delay element 413 and the gap sign and value locked in the addition register 407. The output of subtraction module 415 is the UIPE. Subtracting the IPE of the ith symbol from the sum of the gap groups comprising the ith symbol will result in the UIPE of the ith symbol, wherein the IPE is available by using a delay line. It should be understood that the IPE and the UIPE are complex-valued, and the process shown in fig. 4 is performed in parallel on each of the real and imaginary parts of the IPE. Thus, each illustrated element may be viewed as performing a separate processing operation on the complex values.

Fig. 5 shows a flow chart 500 of a particular method of operating a receiver implemented in accordance with the present invention to perform demodulation operations in accordance with the present invention. The method begins at step 502 where the receiver is powered on and initialized. Operation proceeds to step 504 where the receiver is operable to receive a first set of complex values, which are complex symbol values of a received signal transmitted over a channel, e.g., a wireless communications uplink channel. In some embodiments, the first set of complex symbol values is generated by an OFDM modulated communication system. The communication may be a block coherent communication system. In some embodiments, each set of complex values may correspond to seven received symbols. Other sizes of blocks are possible. In some embodiments, one of the received signals may be a known symbol, such as a pseudo pilot symbol or a pilot symbol. In step 506, the receiver is operated to store each of the first set of complex symbol values for a second predetermined time, the second predetermined time being longer than the first predetermined time. The second predetermined time is selected to be long enough so that the first set of values is available when the fourth set of values is generated. The value may be stored in the delay line. Operation proceeds to step 508. In step 508, a set of soft bits, e.g., generated from a decoder, is received. The received soft bits correspond to the complex symbol values. In some embodiments, each received complex symbol value has at least two soft bits. In other embodiments, each received complex symbol value has at least three soft bits.

In step 510, the multiplication module performs a complex multiplication operation on each of at least some of the first set of complex values to produce at least some elements of the second set of complex values, the multiplication operation performed on each complex value of said at least some of said first set of complex values comprising multiplying said each complex value by a complex value determined from at least some of said soft bits. Note that the multiplication may not be performed on known symbols, such as pilot or pseudo-pilot symbols, but instead outputs a predetermined value. In some embodiments, each complex multiplication operation is performed by performing two shift operations and one addition operation. In some embodiments, one of the received complex symbol values is not rotated, e.g., the phase is unchanged via a multiplication operation. In some embodiments, the complex symbol values that are not rotated occur in preselected locations within the set of received complex symbol values. The multiplication of complex symbol values that are not rotated may be known and independent of the soft bits. The complex symbol value that is not rotated may be a value representing a pilot symbol or a value representing a known symbol such as a pseudo pilot symbol. In step 512, the receiver is operative to store each generated second set of complex values for a first predetermined time. The first predetermined time in some embodiments is selected to be long enough to complete the generation of the third set of complex values.

Next, in step 514, the receiver is operative to add the complex values in the second set of complex values to produce a complex sum, the complex sum being a complex value. The receiver then operates to store the complex sum in step 516. Next, in step 518, a third set of complex values is generated by subtracting one of the stored second set of complex values from the stored complex sum to generate one of the third set of complex values, the third set of complex values having the same number of complex values as the first set of complex values. Each of the second set of complex values is separately subtracted from the sum. The subtraction may be performed sequentially or in parallel.

Next, in step 520, each element of the first set of complex values is multiplied by a conjugate of a complex value from the third set of complex values to produce a fourth set of complex values, the fourth set of complex values having the same number of elements as the first and second sets of complex values, the complex values in the fourth set being soft symbol values. Operation proceeds from step 520 to step 522.

In step 522, a soft-input soft-output decoding operation is performed on the soft symbol values to generate additional soft bits. In some embodiments, the soft-input soft-output decoding operation may be performed by a Low Density Parity Check (LDPC) decoder. In other embodiments, the soft-input soft-output decoding operation is performed by a turbo decoder.

Next, in step 524, the generated additional soft bits are used to process another set of complex symbol values. This may involve a repetition of steps 504 to 522. Operation terminates at step 526, for example, when there are no more complex values from the communication channel to process.

Fig. 6 illustrates a block diagram 600 of an exemplary set of information generated and processed in accordance with the present invention. Block 602 is an exemplary first set of complex symbol values. The first set of complex symbol values may be from a received set of block-coherent channel signals, e.g., seven symbols including one known symbol, e.g., a pseudo pilot signal or pilot symbol, and six symbols conveying user information. Block 604 is an exemplary set of soft bits from the decoder, e.g., soft bits corresponding to the received complex symbol values of block 602.

Block 606 is an exemplary second set of complex values that includes at least some elements that are the result of a complex multiplication operation between at least some elements of the first set of complex values 602 and complex values determined from at least some of the soft bits 604.

An exemplary complex sum 608 is generated from the second set of complex values 606.

Block 610 is an exemplary third set of complex values having the same magnitude as either the first or second set of complex values. Each element in the third set of complex values 610 results from a subtraction operation between the complex sum 608 and a member of the first set of complex values 602. Block 612 is an exemplary set of values that are the conjugates of the third set of complex values 610.

Block 614 is an exemplary fourth set of complex values, e.g., soft symbol values, that may be generated by a complex multiplication operation between the conjugates of the first set of complex values 602 and the third set of complex values 612. The additional soft bits 604' may be generated as a result of a soft-input soft-output decoding operation performed on the soft symbols 614. Additional soft bits 604 'may be used to process an exemplary other set of complex symbol values 602'.

In various ones of the above-described embodiments, the first complex multiplication performed by complex multiplier 303 in processing a known fixed value corresponding to, for example, a pilot value, does not cause rotation, e.g., a phase change. This generally applies in the case where the known value has no (e.g. zero) imaginary part. In other embodiments, where the known value has an imaginary component, the first complex multiplication operation may cause a phase change, e.g., a phase rotation, by a fixed predetermined amount.

Various features of the invention are implemented using modules. Such modules may be implemented using software, hardware, or a combination of software and hardware. Many of the above described methods or method steps can be implemented using machine executable instructions, such as software, included in a machine readable medium such as a storage device, e.g., RAM diskette, floppy disk, etc. to control a machine, e.g., general purpose computer with or without additional hardware, to implement all or portions of the above described methods, e.g., in one or more communication network nodes. Accordingly, the present invention provides, among other things, a machine-readable medium including machine executable instructions for causing a machine, e.g., processor and associated hardware, to perform one or more of the steps of the above-described method(s).

Many additional variations on the methods and apparatus of the present invention described above will be apparent to those skilled in the art in view of the above description of the invention. Such variations are to be considered within the scope of the invention. The methods and apparatus of the present invention in various embodiments may use CDMA, Orthogonal Frequency Division Multiplexing (OFDM), and/or various other types of communications techniques to provide wireless communications links between ingress nodes and mobile nodes. In some embodiments the access nodes are implemented as base stations which establish communications links with mobile nodes using OFDM and/or CDMA. In various embodiments the mobile nodes are implemented as notebook computers, Personal Data Assistants (PDAs), or other portable devices including receiver/transmitter circuits and logic and/or routines, for implementing the methods of the present invention.

Claims (27)

1. A method of operating a receiver device to generate soft values forming a set of complex values for transmission to the receiver device, the method comprising operating the device to perform the steps of:

a) receiving a first set of complex values, the first set of complex values being received complex symbol values obtained from a signal transmitted over a channel;

b) receiving a set of soft bits, the soft bits corresponding to the complex symbol values;

c) performing a complex multiplication operation on each of at least some of said first set of complex values to produce at least some elements of a second set of complex values, the multiplication operation performed on each of said set of at least some of said first set of complex values comprising multiplying said each complex value by a complex value determined from at least some of said soft bits;

d) adding the complex values in the second set of complex values to produce a complex sum, the complex sum being a complex value;

e) generating a third set of complex values by subtracting one of the second set of complex values from the complex sums, respectively, the third set having the same number of elements as the first set of complex values, each separate subtraction generating one of the third set of complex values; and

f) multiplying each element of said first set of complex values with a conjugate of a complex value from said third set to produce a fourth set of complex values, said fourth set of complex values having the same number of elements as said first and second sets, said complex values in said fourth set being the soft symbol values produced.

2. The method of claim 1, wherein said set of received soft values is generated from an output of a decoder.

3. The method of claim 1 wherein said individual subtractions performed in said step of generating a third set of complex values are performed sequentially.

4. The method of claim 1, wherein there are at least two soft bits for each received complex symbol value.

5. The method of claim 1, wherein there are at least 3 soft bits for each received complex symbol value.

6. The method of claim 1, wherein one of the received complex symbol values is unchanged in phase by said step of performing said complex multiplication operation on each of at least some of said first set of complex values.

7. The method of claim 6, wherein said complex symbol values with unchanged phase occur in preselected positions within said first set of received complex symbol values.

8. The method of claim 6, wherein said multiplication is known and independent of soft bits for said complex symbol values with unchanged phase.

9. The method of claim 6, wherein said complex symbol values whose phases have not been changed are pilot symbol values.

10. The method of claim 6, wherein said complex symbol values whose phases have not been changed are known symbol values representing pseudo pilot symbols.

11. The method of claim 1, further comprising:

a soft-input soft-output decoding operation is performed on the soft symbol values to generate additional soft bits.

12. The method of claim 11, further comprising:

processing another set of complex symbol values using the generated additional soft bits.

13. The method of claim 11, wherein said soft-input soft-output decoding operation is performed by a low density parity check decoder.

14. The method of claim 11, wherein said soft-input soft-output decoding operation is performed by a turbo decoder.

15. The method of claim 1, wherein said first set of complex symbol values is generated by an OFDM modulated communication system.

16. The method of claim 1, further comprising:

storing each of the generated second set of complex symbol values for a predetermined time, the subtracting using symbol values from the second set that have been stored for the predetermined time.

17. The method of claim 16, further comprising:

storing each of the first set of complex symbol values for a second predetermined time, the second predetermined time being longer than the first predetermined time; and

wherein the first complex symbol value multiplied by the third complex symbol value has been delayed by a second predetermined time.

18. The method of claim 5, wherein said complex multiplication operations on each of at least some of said first set of complex values are performed by performing at most two shift operations and at most one add operation.

19. The method of claim 1, wherein the communication signal is a block coherent communication signal.

20. The method of claim 1 wherein one of the received complex symbol values is phase-changed by a fixed preselected amount by said step of performing said complex multiplication operation on each of at least some of said first set of complex values.

21. The method of claim 20, wherein said complex symbol values that are phase-changed by a fixed preselected amount occur in preselected locations within said first set of received complex symbol values.

22. The method of claim 20 wherein said multiplication is known and independent of soft bits for a phase change of a fixed preselected amount of said complex symbol value.

23. An apparatus for generating soft values forming a set of complex values, the apparatus comprising:

a first complex multiplier comprising:

i) a first input for receiving a first set of complex values, the first set of complex values being received complex symbol values obtained from a signal transmitted over a channel;

ii) a second input for receiving a set of soft bits, said soft bits corresponding to said complex symbol values; and

iii) circuitry for performing a complex multiplication operation on each of at least some of said first set of complex values to produce at least some elements of a second set of complex values, the multiplication operation performed on each complex value of said set of at least some of said first set of complex values comprising multiplying said each complex value by a complex value determined from at least some of said soft bits;

an adder coupled to the first complex multiplier for adding the complex values in a second set of complex values to produce a complex sum, the complex sum being a complex value;

means for generating a third set of complex values by subtracting one of the second set of complex values from the complex sum, respectively, the third set having the same number of elements as the first set of complex values, each separate subtraction generating one of the third set of complex values; and

means for multiplying each element of said first set of complex values with a conjugate of a complex value from said third set to produce a fourth set of complex values, said fourth set of complex values having the same number of elements as said first and second sets, said complex values in said fourth set being the soft symbol values produced.

24. The apparatus of claim 23, further comprising:

a decoder to generate a soft output value, the decoder coupled to the first input of the first complex multiplier.

25. The apparatus of claim 23, wherein said means for generating a third set of complex values comprises a delay line for delaying complex values included in said second set of complex values, and a subtractor coupled to said delay line.

26. The apparatus of claim 23, wherein there are at least two soft bits for each received complex symbol value.

27. The apparatus of claim 23, wherein said means for multiplying each element of said first set of complex values by a conjugate of a complex value from said third set to produce a fourth set of complex values comprises:

a conjugate circuit; and

a second complex multiplier.