HK1091604A - Method and system of jitter compensation - Google Patents

Description

Method and system for jitter compensation

Field of the invention

The invention relates to a sigma-delta modulator (sigma delta modulator) and a phase locked loop. In particular, the invention relates to jitter compensation in sigma delta-controlled fractional-N synthesizers.

Background and description of the prior art

Many communication systems require stable and low noise frequencies for communication. Such exemplary communication systems are GSM, DCS 1800 and bluetooth. Stable frequencies that are flexible with respect to various reference oscillator frequencies can be obtained by a fractional-N synthesizer. A fractional-N synthesizer generates frequencies between two respective nominal frequencies determined from two rational numbers multiplied by a reference frequency. Typically, the rational number is derived by a frequency dividing circuit that changes between two integer divisors. By varying between rational numbers in a specified pattern, a desired frequency can be obtained for a series of reference oscillators. One problem with changing between frequencies (division ratio) is the introduction of phase noise. The synthesized frequency will include a series of frequency components of the output signal that are above or below the desired frequency. A sigma delta-controlled fractional synthesizer according to the prior art is shown in fig. 1.

Uk patent application GB2097206 describes a frequency synthesizer of the phase-locked loop type comprising a frequency divider with two switches. A compensation signal is generated and adaptively adjusted to reduce phase jitter. Phase jitter is caused by the output pulses of the variable divider not being regularly spaced. In one embodiment, the irregularities are suppressed before the signal is applied to the input of the phase compensator.

US patent US5834987 describes a frequency synthesizer system and method comprising a programmable frequency divider. The frequency divider is controlled to divide the frequency of the VCO output signal by a first or second integer ratio. The sigma delta modulator generates a divider control input in response to a modulation input. The fluctuating compensation signal is provided to the phase detector output.

US patent 4179670 discloses a fractional division ratio synthesizer with jitter compensation. Jitter compensation is inserted at the output of the phase comparator. The compensation signal is passed to the voltage controlled oscillator through a loop filter. For at the reference frequency f_rA fraction of the number of periods M, the nominal division ratio of M plus 1. The fraction is N/2ⁿWhere N may be used at f_rA clocked sigma delta modulator adds 1 on a cyclic basis.

US patent 4771196 describes an electronically variable active analog delay line using cascaded differential transconductance amplifiers with integrated capacitors.

US20020008557 presents a digital phase locked loop in which the output of a digitally controlled oscillator is fed to a multi-stage tapped delay line to provide a series of clock signals at different frequencies. A control signal representative of the timing error in the output signal determines the taps of the tapped delay line for output.

US5036294 discloses a switched capacitor phase locked loop.

None of the above cited documents discloses a method and system for frequency synthesis providing jitter compensation prior to phase detection of a phase locked loop or after generation of an oscillator signal of a phase locked loop, wherein the jitter compensation is introduced by means of a variable delay line.

Summary of The Invention

For phase locked loop frequency synthesizers, fast switching between different frequencies (e.g. in high rate extension to bluetooth) requires a large loop bandwidth. Prior art phase locked loops with large loop bandwidths typically suffer from too much out-of-band noise in many applications. The main part of the noise in the prior art is derived from the frequency divider when switching between different divisors.

It is therefore an object of the present invention to provide a method and system for jitter compensation to reduce out-of-band noise originating from a frequency divider circuit.

Furthermore, it is an object to reduce such noise/jitter before the jitter is further affected by phase detector non-linearities.

Another object is to accomplish jitter compensation by means of a variable delay circuit and a delay control circuit.

Yet another object is to accomplish the delay control by means of a sigma delta modulator.

Finally, it is also an object to implement a variable delay circuit by means of a controllable tapped delay line.

These objects are met by the invention of controlling a multi-stage tapped delay line.

Preferred embodiments of the invention are described below, by way of example, with reference to the accompanying drawings.

Brief Description of Drawings

Fig. 1 illustrates a sigma delta-controlled synthesizer according to the prior art.

Fig. 2 shows a first embodiment of compensation of sigma delta modulator induced jitter according to the invention.

Fig. 3 shows a first embodiment of compensation of the sigma delta modulator induced jitter with a digitally variable delay according to the invention.

Fig. 4 shows a generalized first embodiment of compensation of sigma delta modulator induced jitter according to the present invention.

Fig. 5 shows a second embodiment of compensation of sigma delta modulator induced jitter according to the invention.

Fig. 6 shows a third embodiment of compensation of sigma delta modulator induced jitter according to the invention.

Fig. 7 shows an embodiment of the delay control according to the invention.

Fig. 8 shows an embodiment of the variable delay implemented by a tapped delay line according to the invention.

Fig. 9 shows a first exemplary form of variable delay implemented by a tapped delay line comprising D flip-flops according to the present invention.

Fig. 10 shows a second exemplary form of variable delay implemented by a tapped delay line including D flip-flops according to the present invention.

Fig. 11 illustrates a 50% duty cycle clock frequency signal in accordance with the present invention.

Description of the preferred embodiments

Referring to fig. 1, the sigma delta-controlled synthesizer architecture includes a phase frequency detector PFD, a low pass loop filter LPF VCO, and a divider divide by N or N + 1. The frequency divider divide by N or N +1 by setting the input fraction by fraction at a frequency f_refAnd a sigma-delta modulator (sigma-delta modulator) for performing clock control. Frequency f_refReference clock signal f_refThe signal is input to a phase frequency detector and a frequency-divided output signal f of a voltage controlled oscillator VCO_oulA comparison is made. The average division factor N is obtained by the division factor Div ctrl modulated by a sigma delta modulator_a

N ≤N_a≤N+1。

The power spectral density of the division factor is smaller for low frequencies and smaller for aboutf_refFrequency of/2 is increased to a maximum, sigma delta modulator with f_refAnd performing clock control. The high frequency components are suppressed by a low pass loop filter LPF. However, the out-of-band noise level may still be too high for many applications. This is especially a problem for larger loop bandwidths. A larger loop bandwidth is necessary, for example, when fast switching between different frequencies is required, as is the case in high rate extensions, for example to bluetooth.

Some prior art solutions compensate for this noise by adding a compensation current at the input of the loop filter. However, this solution suffers from at least two disadvantages:

due to non-linearity in the phase detector, the phase noise will be converted from a higher frequency to a lower frequency (baseband). Once at baseband, it is difficult, if not impossible, to compensate for phase noise.

For digital implementations of sigma delta converters, which are more versatile than analog sigma delta converters, an analog digital-to-analog (D/a) converter is required in order to convert the compensation signal into an analog current. And the need for one or more D/a converters makes the manufacturing process more complex.

The present invention solves these problems by phase compensating the signal before it is input to the phase frequency detector PFD.

Fig. 2 shows a first embodiment of compensation of sigma delta modulator induced jitter according to the invention.

The variable delay unit Var delay delays the input signal to the phase detector PFD according to a control signal from a control unit delay calc which calculates the required jitter compensation. Preferably, the control unit is also controlled with a frequency f_refAnd performing clock control. The required jitter compensation is determined by the signal available from the sigma delta modulator. The delay control signal DCS is input to the variable delay unit Var delay.

The variable delay Var delay controls the instantaneous phase of the signal. Preferably, the controlled quantity is the instantaneous zero crossing of the signal fed to the input of the phase frequency detector PFD. The variable delay then controls the zero crossing condition.

Without compensation, as shown in FIG. 1, and assuming a locked loop, at time nT_ref(wherein n is an integer and T_ref＝1/f_ref) Time T between two zero crossings of signal sfb fed back to detector PFD_dCan be expressed as

T_d(mT_ref)＝N_aT_out+q(mT_ref)T_out

Wherein T is_out＝1/f_outAnd q (nT)_ref) Is a period jitter.

Assuming that the system starts at cycle 0, the phase jitter accumulated at cycle n is:

the variable Delay can be implemented fully digitally, as illustrated in detail in fig. 3, which also illustrates the clocking of the digital Delay "Dig Delay" C1k2 "in fig. 3. Preferably, the digital delay is output by the frequency signal f_outPerforming clock control. Output frequency signal f_outThe positive and negative wavefronts (flank) may be used to obtain as little as 0.5T for a 50% duty cycle output frequency signal_outStep size of (2). As in FIG. 2, the control units "delay calc" and ∑ Δ modulatorSigma-Delta modulator is preferably clocked with a reference frequency clock signal f_refClock control Clk 1.

In a generalized embodiment, the average division factor N is obtained by weighting_a. FIG. 4 illustrates a generalized first embodiment, in which a series of division factors, N_iE {. N-1, N +1, N +2, }, averaged by the following weighting:

wherein w_iAre weights such that

Similar generalizations apply to the second and third embodiments as well, as will be apparent to the reader.

Fig. 5 shows a second embodiment of compensation of sigma delta modulator induced jitter according to the invention. In fig. 5, the jitter is compensated before the division unit divide by N or N + 1. The frequency of the signal input to the variable delay Var/dig delay is much higher compared to the preferred embodiment of fig. 2. Also, the divisor of the division unit needs to be compensated. Reference frequency f used for delay calculator and sigma delta modulator_refClock control Clk 1. The variable delay Var/dig delay may be analog or digital. Preferred embodiments of analog and digital delays according to the present invention are illustrated in fig. 8-10. For the case of digital delay, a delay unit of variable delay Var/dig delay is preferably used that is equivalent to the input signal f_outThe clock signal Clk2 ofAnd (5) controlling a clock. Thus, the clock signal can be retrieved internally for variable delay Var/dig delay without a specific external clock signal input port. For the smallest step size, the delay elements of the digital variable delay are preferably triggered by the positive and negative flanks of the 50% duty cycle clock frequency signal. The clock signal Clk2 is not required for analog variable delay Var/dig delay.

Fig. 6 shows a third embodiment of compensation of sigma delta modulator induced jitter according to the invention. The output signal of the phase frequency detector PFD depends on the phase difference between its two input signals. This difference is the same whether the phase of the first input leads or the phase of the second input lags. The sign of the variable delay of the unit Var/dig delay is therefore reversed compared to the embodiment of fig. 2. In FIG. 5, the delay calculators "delay calc" and sigma-delta modulators are referenced to the frequency f_refClock control Clk 1. The variable delay Var/dig delay may be analog or digital. For the case of digital delay, the delay cells are clocked with the clock signal Clk 2. Preferably, a frequency signal f is output_outIt is used to clock the digital variable delay, as in the embodiment of figure 3. Output frequency signal f_outThe positive and negative wavefronts can be used to obtain as little as 0.5T for a 50% duty cycle output frequency signal_outStep size of (2). For analog variable delay Var/dig delay, the clock signal input Clk2 is not needed.

The embodiments of fig. 2-6 may be combined. The invention covers embodiments with more than one variable delay unit, for example.

Fig. 7 shows an embodiment of the delay control according to the invention. Accumulated phase jitter delta phi (mT)_ref) The estimate of (c) is obtained by integrating the error signal epsilon. The error signal is at a value corresponding to the desired fraction N_aAnd the output signal Div ctrl that controls the frequency dividing unit to divide by N or N + 1. Div ctrl is derived from a clock signal Cl0ckThe output of the clock controlled sigma delta modulator. The phase being substantially the frequency of the integral, and the error signal epsilon being integrated and scaled by 2 pi/N in delay calc_aMultiplied to obtain the estimated phase jitter. The variable delay and the delay control signal DCS correspond to this estimate for the embodiment of fig. 2. The delay calc is also clocked by the Clock signal Clock. The delay control signal for the embodiment of fig. 5 is as large as N_aThe variable delay is scaled accordingly in the delay unit Var/dig delay. The delay control signal of the embodiment of fig. 6 has the opposite sign or this sign is included in the delay unit Var/dig delay.

Fig. 8 shows an embodiment of an analog variable delay implemented by a tapped delay line according to the present invention. The tapped delay line is made up of a plurality of cascaded segments, each segment comprising: having a transconductance G_iThe amplifier of (a), illustrated as an inverter; having a capacitance C_iThe capacitor of (1); and switch S_i，i∈[0，n]Where n is the number of segments of the tapped delay line. The total delay of the tapped delay line is equal to having a closed switch S_iWherein the contribution of segment i with closed switch is proportional to G_i/C_iThe delay of (2). Various transconductances G can be obtained by varying the supply voltage and the bias current_i(depending on the transconductance circuitry).

The noisy variable delay itself may introduce more phase noise than the variable delay compensates for. For the tapped delay line shown in fig. 8, the noise level can be kept at a minimum if supplied from a stable supply voltage with low noise and by not using more delay than necessary. Deviations from the nominal value due to tolerances in the manufacturing process may also need to be taken into account. For most applications, no special low noise designed inverter is required. The embodiment of fig. 8 has the further advantage in jitter compensation that a separate multi-bit digital-to-analog (D/a) converter can be eliminated.

Given equal transconductance G for all inverters_iThe capacitor can then represent a binary value, i.e. C_i＝2ⁱC₀And i is greater than 0. Then switch S_iI ≧ 0, there can be their binary correspondence in the binary delay control signal (1 for closed switch and 0 for open switch). At least this is the case for the exact level desired, since as mentioned above, the noise generated by the delay line increases with the number of segments. However, the invention also covers other alternatives representing the delay.

The greatest advantage of the variable delay embodiment as shown in fig. 8 is that the capacitor can be realized by the gate-body capacitance of the CMOS transistor. Thus, variable delay can be implemented in well-known digital CMOS fabrication processes.

The tapped delay line may also be fully digital, as shown in fig. 9 and 10. These two figures show the combination of a D flip-flop D₀》，《D₁》，《D₂》，...，《D_nEmbodiments of variable delay implemented with tapped delay lines. D flip-flop D₀Optional. Each D flip-flop D₀》，...，《D_nThe file is clocked with Clock signal Clock. If the triggers are wavefront triggered on only one wavefront (positive or negative), each trigger represents a T_clockDelay step of (2), wherein T_clockIs the time period of the Clock signal Clock. Preferably, as shown in FIG. 11, the flip-flops are triggered on the positive and negative flanks of the 50% duty cycle clock signal, with the delay step reduced to T_clock/2. In fig. 11, the offset levels illustrate that the clock frequency signal may be NRZ (non return to zero) or RZ (return to zero). In FIGS. 9 and 10, switch S_iN, controlled by the delay control signal. In FIGS. 9 and 10, switch S is turned on and off at the same time₀》，《S₁》，...，《S_nOnly one switch is connected.

Fig. 9 shows a first exemplary form of an all-digital tapped delay line, and fig. 10 shows a second exemplary form.

The invention is not intended to be limited to only the embodiments described in detail above. Changes and modifications may be made without departing from the invention. The invention covers all modifications within the scope of the following claims.

Claims (34)

1. A method of jitter compensation in a phase locked loop frequency synthesizer by means of a variable delay, the method being characterized in that jitter is compensated before a signal being subjected to jitter is passed through a non-linear section, the jitter compensated variable delay being implemented by means of a tapped delay line.

2. The method of claim 1, wherein each divisor of the plurality of integer divisors is selected according to a fractional pattern representing fractional weighting of the integer divisor generated by a Σ Δ modulator from a fractional setting input.

3. A method according to claim 1 or 2, characterized in that the fractions of the first and second integers are determined by a binary fraction pattern for selecting the first and second integers, generated by the sigma delta modulator on the basis of a fraction setting input.

4. A method according to claim 2 or 3, characterized in that the tapped delay line is controlled by means of a control signal derived from a sigma delta modulator.

5. A method according to claim 4, characterized in that the control signal for controlling the tapped delay line is determined by integrating and scaling an error signal, which is the difference between the signal representing the fraction and the signal carrying the fractional pattern.

6. A method according to any of claims 1-5, characterized in that the tapped delay line comprises a plurality of capacitors having a capacitance proportional to successive powers of 2.

7. A method according to claim 5 or 6, characterized in that the control signal carries a binary number, the bit of which represents a capacitor connected or disconnected to the tapped delay line having a capacitance which each corresponds to a bit position of the binary representation.

8. A method according to any of claims 1-5, characterized in that the tapped delay line comprises a plurality of delay cells connected in series.

9. Method according to claim 5 or 8, characterized in that the control signal carries a representation of the delay elements for connecting or disconnecting the tapped delay line to the input or output of the tapped delay line.

10. A method according to claim 9, characterized in that the control signal carries a bit representation for connecting or disconnecting the output of the delay element to the output of the tapped delay line.

11. A method according to claim 9, characterized in that the control signal carries a bit representation for connecting or disconnecting the input of the delay element to the input of the tapped delay line.

12. A method according to any of claims 1-11, characterized in that the non-linear part is included in or is a phase detector or a frequency detector.

13. A method according to any of claims 1-12, characterized in that the output signal of the tapped delay line is input to a phase detector or a frequency detector.

14. A method according to any of claims 1-13, characterized in that at least one of the following signals is input to and delayed by a tapped delay line:

-a reference frequency signal, the reference frequency signal,

-a divided output signal of a voltage controlled oscillator,

-a frequency divided output signal of the frequency synthesizer.

15. A method according to any of claims 1-12, characterized in that the output signal of the tapped delay line is input to a frequency dividing circuit.

16. A method according to any of claims 1-12 and 15, characterized in that at least one of the following signals is input to and delayed by a tapped delay line:

-an output signal of a voltage controlled oscillator, an

-an output signal of the frequency synthesizer.

17. A phase locked loop frequency synthesizer with jitter compensation by means of variable delay, the frequency synthesizer being characterized by a tapped delay line which compensates for jitter before a signal being subjected to jitter is passed through a non-linear section.

18. The frequency synthesizer according to claim 17 c h a r a c t e r i z e d b y a sigma delta modulator for generating a fractional pattern representing fractional weighting of a plurality of integer divisors or a memory unit for pre-generated storing of a fractional pattern representing fractional weighting of a plurality of integer divisors, the fractional pattern selecting one integer divisor from the plurality of integer divisors at a time to be active.

19. The frequency synthesizer according to claim 17 or 18 c h a r a c t e r i z e d b y a sigma delta modulator for generating a binary fractional pattern for determining the fraction of the first and second integer numbers or a memory unit for pre-generated storing a binary fractional pattern for determining the fraction of the first and second integer numbers, the binary fractional pattern selecting the first or second integer number, the binary fractional pattern being generated or recovered from a fractional setting input.

20. A frequency synthesiser as claimed in claim 19 characterised in that the control means is arranged for controlling the tapped delay line by means of one or more control signals derived from the sigma delta modulator.

21. The frequency synthesizer according to claim 20 c h a r a c t e r i z e d i n that the integrator integrates and scales an error signal, said error signal being the difference between the signal representing the fraction and the signal carrying the binary fractional pattern, the integrator output signal being the signal for controlling the tapped delay line.

22. A frequency synthesizer according to any one of claims 17 to 21 wherein the tapped delay line comprises a plurality of capacitors having a capacitance proportional to successive powers of 2.

23. A frequency synthesiser as claimed in claim 21 or 22 characterised by switches for connecting or disconnecting the capacitors of the tapped delay line, wherein respective capacitances corresponding to bit positions of the binary representation of a binary number are connected or disconnected, the binary number being carried by the one or more control signals.

24. A frequency synthesizer according to any one of claims 17 to 21 wherein the tapped delay line comprises a plurality of delay cells connected in series.

25. A frequency synthesiser as claimed in claim 21 or 24 characterised by one or more switches for connecting or disconnecting the one or more delay elements to the input or output of the tapped delay line in accordance with a bit representation carried by the control signal.

26. The frequency synthesizer according to claim 25 wherein one or more switches each connect or disconnect the delay element output to the output of the tapped delay line.

27. A frequency synthesiser as claimed in claim 25 characterised by one or more switches each connecting or disconnecting the delay element input to the input of the tapped delay line.

28. A frequency synthesizer according to any one of claims 17-27 wherein the non-linear part is included in or is a phase or frequency detector.

29. A frequency synthesiser as claimed in any one of claims 17 to 28 characterised in that the output signal of the tapped delay line is input to a phase detector or frequency discriminator.

30. A frequency synthesiser as claimed in any one of claims 17 to 29 characterised in that at least one of the following signals is input to and delayed by the tapped delay line:

-a reference frequency signal, the reference frequency signal,

-a divided output signal of a voltage controlled oscillator,

-a frequency divided output signal of the frequency synthesizer.

31. A frequency synthesiser as claimed in any one of claims 17 to 28 characterised in that the output signal of the tapped delay line is input to the frequency dividing circuit.

32. A frequency synthesiser as claimed in any one of claims 17 to 28 and 31 characterised in that at least one of the following signals is input to and delayed by the tapped delay line:

-an output signal of a voltage controlled oscillator, an

-an output signal of the frequency synthesizer.

33. A radio communication system, characterized by means for carrying out the method according to any of claims 1-16.

34. A radio communication system, characterized by one or more frequency synthesizers according to any of claims 17-32.