HK1090443B - Reducing cpu and bus power when running in power-save modes - Google Patents

Description

Reducing CPU and bus power while operating in power-save mode

Technical Field

The present application relates to methods, apparatus and systems for reducing CPU and bus power while operating in a power saving mode.

Background

A device including a processor may have different modes of operation, the different modes representing different tradeoffs between power consumption and performance.

In one exemplary mode of operation ("performance" mode), internal resources of the device including the processor operate at high performance, which results in high power consumption.

In another exemplary mode of operation ("power save" mode), internal resources of the device including the processor operate at low power consumption while maintaining a predetermined performance of such mode of operation.

The processor may include a core defined to have a lowest core clock signal frequency no lower than a predetermined plurality of lowest bus clock signal frequencies of a bus coupled to the processor. This increases the lower limit to which the core clock signal frequency can be reduced in the power-save mode as higher bus clock signal frequencies become possible, thus preventing reduced power consumption in the power-save mode.

It would be beneficial to reduce power consumption while maintaining or improving performance when a device is operating in a power saving mode.

Disclosure of Invention

An apparatus for reducing power consumption in a power saving mode according to the present invention comprises: a processor core to receive a first clock signal, the first clock signal having at least one first clock frequency; a plurality of clock dividers for generating a plurality of second clock signals from a system clock signal, each second clock signal having one of a plurality of second clock frequencies, such that a fixed ratio between said first and second clock frequencies is maintained regardless of variations in said first or second clock signals; a bus interface coupled to the processor core to receive a plurality of second clock signals, wherein the bus interface generates and samples control, address, and data signals of a bus coupled to the bus interface with the plurality of second clock signals; and a frequency controller for changing the division factor of the plurality of clock dividers.

A method according to the present invention for reducing power in a power-saving mode by setting a core clock signal having a core clock frequency and a plurality of bus clock signals each having a bus clock frequency of a set of bus clock frequencies, the method comprising: the plurality of bus clock signals are generated such that a fixed ratio between the core clock frequency and the bus clock frequency is maintained regardless of changes in the core clock frequency or the bus clock frequency.

A system for reducing power consumption in a power saving mode according to the present invention comprises: a bus; an interface controller coupled to the bus, the interface controller having a plurality of first clock dividers for generating a plurality of first bus clock signals having the one or more bus clock frequencies, and the interface controller generating and sampling control, address, and data signals on the bus with the plurality of first bus clock signals; a processor coupled to the bus, the processor having a processor core operating according to one or more core clock frequencies, wherein a fixed ratio between the one or more core clock frequencies and the one or more bus clock frequencies is maintained regardless of variations in the one or more core clock frequencies or the one or more bus clock frequencies, the processor further having a bus interface for receiving one or more second bus clock signals having the one or more bus clock frequencies and using the second bus clock signals to generate and sample control signals, address signals, and data signals on the bus.

Drawings

The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

FIG. 1 is a simplified block diagram of an apparatus including a processing system according to some embodiments of the invention;

FIG. 2 is a simplified block diagram illustration of a processing system according to some embodiments of the inventions; and

FIG. 3 is a simplified block diagram illustration of a device including a processing system according to other embodiments of the present invention; and

FIG. 4 is a simplified block diagram illustration of a processor according to some embodiments of the inventions.

It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.

Detailed Description

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be understood by those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

It should be understood that embodiments of the invention may be used in any device having a processor. Although the present invention is not limited in this respect, the device may be a portable device powered by a battery. Non-limiting examples of such portable devices include laptop and notebook computers, mobile phones, Personal Digital Assistants (PDAs), and the like. Alternatively, the device may be a non-portable device, such as a desktop computer.

As shown in fig. 1, the apparatus 2 may include a processing system 4 and a power supply unit 6, according to some embodiments of the invention. The device 2 may optionally include an antenna 8. Well-known components and circuits of the apparatus 2 and processing system 4 are not shown in FIG. 1 so as not to obscure the invention.

The processing system 4 may include a processor 10 and an interface controller 20. Although the present invention is not limited in this respect, processor 10 may be, for example, a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a Reduced Instruction Set Computer (RISC), a Complex Instruction Set Computer (CISC), or the like. Further, the processor 10 may be part of an Application Specific Integrated Circuit (ASIC). Although the invention is not limited in this respect, interface controller 20 may be, for example, a bus bridge, a Peripheral Component Interconnect (PCI) Northbridge, a PCI southbridge, an Accelerated Graphics Port (AGP) bridge, a memory interface device, the like, or combinations thereof. Further, interface controller 20 may be part of an application specific integrated circuit or part of a chipset.

The processor 10 may include a core 12 and a core Phase Locked Loop (PLL) 14. Core PLL14 may generate one or more core clock signals 16 used by cores 12 from system clock signal 18.

Processor 10 and interface controller 20 may include a bus interface 13 and a bus interface 23, respectively, and may use them to generate and sample data, address and control signals on bus 30.

Processor 10 and interface controller 20 may include a bus PLL15 and a bus PLL25, respectively. Bus PLL15 and bus PLL25 may generate clock signal 17 and clock signal 27, respectively, using system clock signal 18. Bus interface 13 and bus interface 23 may generate and sample data, address, and control signals on bus 30 using clock signals 17 and 27, respectively.

Because they are derived from system clock signal 18, clock signals 16, 17, and 27 may maintain a fixed phase relationship with system clock signal 18 and, thus, with each other. In addition, the phase relationship between clock signals 16, 17, and 27 may be used to generate and sample data, address, and control signals on bus 30.

Those of ordinary skill in the art will appreciate that the performance of processing system 4 may be related to the performance of processor 10, that the performance of processor 10 may be related to the performance of cores 12, and that the cores may be related to the frequency of core clock signal 16. The performance of processing system 4 may also be related to the frequency at which data, address and control signals of bus 30 are generated and sampled. As a result, in the performance mode of operation, clock signals 16, 17, and 27 are expected to oscillate at a high frequency.

Conversely, in a power-saving mode of operation, it is desirable to have the core clock signal 16 oscillate at a low frequency so that the power consumption of the core 12 of the processor 10 is lower than in a performance mode of operation, while still supporting the predetermined performance of the processing system 4 for that mode of operation.

However, due to design constraints, the frequency of core clock signal 16 is constrained to be at least a predetermined multiple of the lowest frequency of clock signal 17. For example, core clock signals 16 may be constrained to oscillate at least six times the lowest frequency of clock signals 17, although the invention is not limited in this respect. If clock signal 17 were to oscillate at the same frequency in both performance mode and power-save mode, in power-save mode core clock signal 16 would be constrained to oscillate at frequencies that would cause core 12 to produce higher performance (and higher power consumption) than the predetermined performance of processing system 4 in support of being used in power-save mode.

Thus, to enable core clock signal 16 to oscillate at a lower frequency, clock signal 17 (and thus clock signal 27) may be generated at an even lower frequency, if possible, while still supporting the predetermined performance of processing system 4 for the power-save mode. If the frequency of clock signals 17 and 27 is reduced relative to the frequency they have in the performance mode, this will reduce the power consumption associated with bus interface 13, bus interface 23 and bus 30 relative to what is the case in the performance mode of operation.

For example, in one embodiment of the invention, system clock signal 18 may oscillate at a lower frequency in the power-save mode than in the performance mode. Since clock signals 16, 17, and 27 are derived from system clock signal 18, they are proportional to system clock signal 18. For example, system clock signal 18 may oscillate at 200MHz in the performance mode and 100MHz in the power-save mode. The lowest frequency of clock signal 17 may be 200MHz in the performance mode and 100MHz in the power-save mode, enabling core clock signal 16 to oscillate at frequencies as low as 600MHz in the power-save mode, using the example of the core clock signal being constrained to oscillate at a frequency no lower than six times the lowest frequency of the bus clock signal. However, in this embodiment, as processing system 4 changes from one mode to another, there is a period of time before core PLL18 and bus PLLs 15 and 25 are relocked to the new frequency of system clock signal 18, and thus bus 30 will be idle during that time. For example, during the relock time, the processor 10 may not be able to respond to interrupts and snoops. This may limit the timing at which switching between performance mode and power saving mode may be performed. Although the invention is not limited in this respect, the relock time of LL18, 15, and 25 may be about 5 to 30 microseconds in some cases.

In other embodiments of the present invention, described below with reference to FIG. 2, the frequency of system clock signal 18 does not change between the performance mode and the power-save mode.

The power supply unit 6 may supply power to the core 12 via power traces 61. Furthermore, the power supply unit 6 may supply power to the bus interface 13 and the bus interface 23 via the power supply trace 62.

Those of ordinary skill in the art will appreciate that the power consumption associated with core 12 of processor 10 increases with increasing voltage on power rail 61, and the power consumption associated with bus interface 13, bus 30, and bus interface 23 increases with increasing voltage on power rail 62. As a result, it is desirable to reduce the voltage on power traces 61 and 62 when device 2 is in a power-saving mode of operation. To enable voltage reduction on power trace 62, bus interface 13 and bus interface 23 may be designed to use a low voltage level for low frequency modes (such as power saving mode) and a high voltage level for high frequency modes (such as performance mode). Those of ordinary skill in the art will appreciate that the lower the frequency of core clock signal 16, power supply unit 6 may lower the voltage on power rail 61. Similarly, the lower the frequency of clock signals 17 and 27, the lower the voltage on power supply trace 62 can be reduced by power supply unit 6.

Those of ordinary skill in the art will appreciate that frequency variations in the clock signal involve some settling time. Thus, when the processor 10 changes the frequency of the clock signal 17 and the core clock signal 16 and instructs the interface controller; 20 change the frequency of clock signal 27, there is a period of time in which the frequency and phase of clock signals 16, 17 and 27 are not synchronized and therefore are not suitable for operation of bus 30. Although the invention is not limited in this respect, this time period may be a few system clock signals, equivalent to about 10 to 40 nanoseconds in some example processors. As a result, it is desirable to have handshaking between processor 10 and interface controller 20 when changing the frequency of clock signals 16, 17, and 27.

For example, processor 10 may send a signal to interface controller 20 to indicate a change from performance mode to power-save mode. This signal may be a new sideband signal from the processor 10 to the interface controller 20. Alternatively, existing signals from interface controller 20 to processor 10 may be made bi-directional to support the functionality of processor 10 indicating a mode change to interface controller 20. Further, both processor 10 and interface controller 20 may refrain from using bus 30 for a predetermined period of time after the indication to allow both processor 10 and interface controller 20 to complete internal changes and prepare to accept and send traffic in the new mode.

Fig. 2 is a simplified block diagram illustration of a processing system 4 according to some embodiments of the invention.

Clock signals 17 of processor 10 may include clock signal 17A, clock signal 17B, and clock signal 17C, which are used by bus interface 13, for example, to generate and sample control, address, and data signals, respectively, on bus 30.

Similarly, the clock signals of interface controller 20 may include clock signal 27A, clock signal 27B and clock signal 27C as used by bus interface 23 to generate and sample control, address and data signals, respectively, on bus 30.

Clock signals 17A, 17B and 17C have a fixed frequency relationship with each other. For example, clock signal 17C oscillates at twice the frequency of clock signal 17A. The clock signals 17A, 17B, and 17C have a fixed phase relationship with each other.

Similarly, clock signals 27A, 27B, and 27C may have a fixed frequency relationship with each other. For example, clock signal 27C may oscillate at twice the frequency of clock signal 27B, and clock signal 27B may oscillate at twice the frequency of clock signal 27A. Further, clock signals 27A, 27B, and 27C may maintain a fixed phase relationship with each other.

Bus PLL15 of processor 10 may include bus PLL core 150 and frequency dividers 151, 152, and 153. Bus PLL core 150 may receive system clock signal 18 as an input and may generate clock signal 154, which may maintain a fixed phase relationship with system clock signal 18 and core clock signal 16. Clock signal 154 may oscillate at the same frequency in performance mode and power-save mode so that bus PLL core 150 may remain locked to system clock signal 18. Frequency dividers 151, 152, and 153 may receive clock signal 154 and may divide it to generate clock signal 17A, clock signal 17B, and clock signal 17C, respectively. Thus, clock signal 154, which is generated from system clock signal 18 and divided to generate clock signals 17A, 17B, and 17C, may be considered an intermediate clock signal. Clock signal 154 may be internal to bus PLL15, although the invention is not limited in this respect. Clock signals 17A, 17B, and 17C may maintain a fixed phase relationship with clock signal 154, system clock signal 18, and core clock signal 16.

As an example, in performance mode, clock signal 154 may oscillate at 1600MHz, and frequency dividers 151, 152, and 153 may divide clock signal 154 by 8, 4, and 2, respectively, such that clock signals 17A, 17B, and 17C oscillate at frequencies of 200MHz, 400MHz, and 800MHz, respectively. Core clock signal 16 may oscillate at 3000MHz, which is greater than six times the frequency of clock signal 17A.

Core 12 may support the predetermined performance of processing system 4 in power-save mode when core clock signal 16 oscillates at 600MHz, and bus interface 13, bus 30, and bus interface 23 may support the predetermined performance of processing system 4 in power-save mode when clock signal 17A oscillates at 100 MHz.

Thus, in the power-saving mode, clock signal 154 can still oscillate at 1600MHz, and frequency dividers 151, 152, and 153 can divide clock signal 154 by 16, 8, and 4, respectively, so that clock signals 17A, 17B, and 17C oscillate at frequencies of 100MHz, 200MHz, and 400MHz, respectively. Core clock signal 16 may then oscillate at a frequency as low as 600MHz while still satisfying the constraint that the frequency of core clock signal 16 be at least six times the frequency of clock signal 17A.

Frequency control signal 156 of processor 10 may be coupled to frequency dividers 151, 152, and 153 and may be used to vary their frequency division between 8, 4, and 2 in performance mode and 16, 8, and 4 in power-save mode. Although the invention is not so limited, the idle time in which the digital divider changes may be on the order of 2-8 clock cycles of the system clock signal 18, which in some example processors is equivalent to about 1-20 nanoseconds.

Although the present invention is not limited in this regard, in the exemplary processing system of FIG. 2, the frequencies of clock signal 27A, clock signal 27B, and clock signal 27C may match the frequencies of clock signal 17A, clock signal 17B, and clock signal 17C, respectively, in both the performance mode and the power-save mode.

Bus PLL25 of interface controller 20 may include bus PLL core 250 and frequency dividers 251, 252, and 253. Bus PLL core 250 may receive system clock signal 18 as an input and may generate clock signal 254, which may maintain a fixed phase relationship with system clock signal 18. Clock signal 254 may oscillate at the same frequency in performance mode and power-save mode so that bus PLL core 250 may remain locked to system clock signal 18. Dividers 251, 252, and 253 may receive clock signal 254 and may divide it to generate clock signal 27A, clock signal 27B, and clock signal 27C, respectively. Thus, clock signal 254, which is generated from system clock signal 18 and divided to generate clock signals 27A, 27B, and 27C, may be considered an intermediate clock signal. Clock signal 254 may be internal to bus PLL25, although the invention is not limited in this respect. Clock signals 27A, 27B, and 27C may maintain a fixed phase relationship with clock signal 254, with system clock signal 18, and with clock signals 17A, 17B, and 17C of processor 10.

In performance mode, clock signal 254 may oscillate at 1600MHz and frequency dividers 251, 252, and 253 may divide clock signal 254 by 8, 4, and 2, respectively, such that clock signal 27A, clock signal 27B, and clock signal 27C oscillate at frequencies of 200MHz, 400MHz, and 800MHz, respectively.

In the power-saving mode, clock signal 254 may still oscillate at 1600MHz, and frequency dividers 251, 252, and 253 may divide clock signal 254 by 16, 8, and 4, respectively, such that clock signal 27A, clock signal 27B, and clock signal 27C oscillate at frequencies of 100MHz, 200MHz, and 400MHz, respectively.

Frequency control signal 256 of interface controller 20 may be connected to frequency dividers 251, 252, and 253 and may be used to change their frequency division between 8, 4, and 2 in performance mode and 16, 8, and 4 in power-save mode.

In an alternative embodiment of the present invention, frequency dividers 151, 152, and 153 may divide clock signal 154 by 8, 4, and 2, respectively, in both performance mode and power-save mode, such that clock signal 17A, clock signal 17B, and clock signal 17C oscillate at frequencies of 200MHz, 400MHz, and 800MHz, respectively, while clock signal 154 oscillates at 1600 MHz. In this alternative embodiment, the frequency control signal 156 is not required. In contrast, in the power-save mode, bus interface 13 may further divide clock signal 17A, clock signal 17B, and clock signal 17C to generate clock signals that oscillate at frequencies of 100MHz, 200MHz, and 400MHz, respectively. Alternatively, bus interface 13 may use masking logic to determine which edge of clock signals 17A, 17B, and 17C to use based on the mode to generate clock signals oscillating at 100MHz, 200MHz, and 400MHz frequencies in the power-save mode.

In this alternative embodiment, dividers 251, 252, and 253 may divide clock signal 254 by 8, 4, and 2, respectively, in both performance mode and power-save mode, such that clock signal 27A, clock signal 27B, and clock signal 27C oscillate at frequencies of 200MHz, 400MHz, and 800MHz, respectively, while clock signal 254 oscillates at 1600 MHz. In this alternative embodiment, the frequency control signal 256 is not required. In contrast, in power-save mode, bus interface 23 may further divide clock signal 27A, clock signal 27B, and clock signal 27C to generate clock signals that oscillate at frequencies of 100MHz, 200MHz, and 400MHz, respectively. Alternatively, bus interface 23 may use masking logic to determine which edge of clock signals 27A, 27B, and 27C to use based on the mode to generate clock signals oscillating at 100MHz, 200MHz, and 400MHz frequencies in the power-save mode.

When the oscillation frequency of system clock signal 18 is less than or equal to the oscillation frequency of clock signal 17A and clock signal 27A, it is not difficult to synchronize clock signal 17A and clock signal 27A to have a desired fixed phase relationship with each other.

However, when the oscillation frequency of system clock signal 18 is higher than the oscillation frequency of clock signal 17A and clock signal 27A, clock signal 17A and clock signal 27A have more than one way to maintain a fixed phase relationship with system clock signal 18. For example, system clock signal 18 may oscillate at 200MHz and, in power-save mode, clock signal 17A and clock signal 27A may oscillate at 100 MHz. Even though clock signal 17A and clock signal 27A each maintain a fixed phase relationship with system clock signal 18, there may be four different fixed phase relationships between clock signal 17A and clock signal 27A, namely 0, π/2, π and 3 π/2 radians. To set the fixed phase relationship between clock signal 17A and clock signal 27A as desired by processing system 4, processor 10 may send a signal (not shown) to interface controller 20 when changing the frequency of clock signal 17A. This signal may be part of the handshake described above.

As shown in fig. 3, apparatus 2 may include a processing system 4 including a processor 10 having a PLL35 for generating a core clock signal 16 and a clock signal 17 from a system clock signal 18, according to some embodiments of the invention. As shown in fig. 4, PLL35 may include PLL core 150 and frequency dividers 151, 152, and 153. As with the embodiment described above with reference to fig. 2, PLL core 150 may receive system clock signal 18 as an input and may generate clock signal 154, and frequency dividers 151, 152, and 153 may receive and divide clock signal 154 to generate clock signal 17A, clock signal 17B, and clock signal 17C, respectively. Unlike the embodiment described above with reference to fig. 2, PLL35 may also include a frequency divider 355 to receive clock signal 154 and divide it in order to generate a single core clock signal 16. If there is more than one core clock signal 16, PLL35 may include a corresponding number of frequency dividers to receive clock signal 154 and divide it to generate core clock signals 16.

As an example, in performance mode, clock signal 154 may oscillate at 4800MHz and divider 355 divides it by 1 so that core clock signal 16 oscillates at 4800 MHz. Frequency dividers 151, 152, and 153 may divide clock signal 154 by 24, 12, and 6, respectively, such that clock signals 17A, 17B, and 17C oscillate at frequencies of 200MHz, 400MHz, and 800MHz, respectively.

As an example, in power-save mode, clock signal 154 may still oscillate at 4800MHz, so PLL core 150 may remain locked to system clock signal 18, and frequency divider 355 may divide it by 8 to cause core clock signal 16 to oscillate at 600 MHz. Frequency dividers 151, 152, and 153 may divide clock signal 154 by 48, 24, and 12, respectively, to cause clock signals 17A, 17B, and 17C to oscillate at frequencies of 100MHz, 200MHz, and 400MHz, respectively.

Frequency control signal 156 of processor 10 may be coupled to frequency dividers 151, 152, and 153 and may be used to change their frequency division between 24, 12, and 6 in performance mode and 48, 24, and 12 in power-save mode. Similarly, frequency control signal 356 of processor 10 may be coupled to frequency divider 355 to change its frequency division between 1 in performance mode and 6 in power-save mode.

In an alternative embodiment of the present invention, frequency dividers 151, 152, and 153 may divide clock signal 154 by 24, 12, and 6, respectively, in performance mode and power-save mode, such that clock signals 17A, 17B, and 17C oscillate at frequencies of 200MHz, 400MHz, and 800MHz, respectively, when clock signal 154 oscillates at 4800 MHz. In this alternative embodiment, the frequency control signal 156 is not required. In contrast, in the power-save mode, bus interface 13 may further divide clock signals 17A, 17B, and 17C to form clock signals that oscillate at frequencies of 100MHz, 200MHz, and 400MHz, respectively. Alternatively, bus interface 13 may use masking logic to determine which edge of clock signals 17A, 17B, and 17C to use based on the mode to form clock signals that oscillate at 100MHz, 200MHz, and 400MHz frequencies in power-save mode.

While certain features of the invention have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that many modifications, substitutions, changes, and equivalents may be made. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Claims (16)

1. An apparatus for reducing power consumption in a power saving mode, comprising:

a processor core to receive a first clock signal, the first clock signal having at least one first clock frequency;

a plurality of clock dividers for generating a plurality of second clock signals from a system clock signal, each second clock signal having one of a plurality of second clock frequencies, such that a fixed ratio between said first and second clock frequencies is maintained regardless of variations in said first or second clock signals;

a bus interface coupled to the processor core to receive a plurality of second clock signals, wherein the bus interface generates and samples control, address, and data signals of a bus coupled to the bus interface with the plurality of second clock signals; and

a frequency controller for changing a division factor of the plurality of clock dividers.

2. The apparatus of claim 1, wherein the first clock frequency is limited to no less than a multiple of a lowest second clock frequency.

3. The apparatus of claim 1, comprising a phase locked loop to generate an intermediate clock signal from a system clock signal, wherein the plurality of clock dividers divide the intermediate clock signal to produce the plurality of second clock signals.

4. The apparatus of claim 3, comprising a core clock divider to divide the intermediate clock signal to generate the first clock signal.

5. The apparatus of claim 1, wherein the frequency controller is operative to vary the division factor in response to switching between a performance mode and a power saving mode of the apparatus.

6. A method of reducing power in a power-save mode by setting a core clock signal and a plurality of bus clock signals, the core clock signal having a core clock frequency, each of the plurality of bus clock signals having a bus clock frequency of a set of bus clock frequencies, the method comprising:

the plurality of bus clock signals are generated such that a fixed ratio between the core clock frequency and the bus clock frequency is maintained regardless of changes in the core clock frequency or the bus clock frequency.

7. The method of claim 6, wherein the fixed ratio comprises the core clock frequency not being less than a predetermined multiple of a lowest frequency of the set of bus clock frequencies.

8. The method of claim 6, wherein generating the plurality of bus clock signals comprises:

generating an intermediate clock signal from the system clock signal; and

dividing the intermediate clock signal to generate the plurality of bus clock signals.

9. The method of claim 6, wherein generating the plurality of bus clock signals comprises:

generating a first intermediate clock signal from a system clock signal;

dividing the first intermediate clock signal to produce one or more second intermediate clock signals; and

masking logic is used to select which edge of the one or more second intermediate clock signals to use to generate the plurality of bus clock signals.

10. The method of claim 8, comprising varying a division factor used to divide the intermediate clock signal in response to switching between a performance mode and a power saving mode of the system.

11. A system for reducing power consumption in a power saving mode, comprising:

a bus;

an interface controller coupled to the bus, the interface controller having a plurality of first clock dividers for generating a plurality of first bus clock signals having the one or more bus clock frequencies, and the interface controller generating and sampling control, address, and data signals on the bus with the plurality of first bus clock signals;

a processor coupled to the bus, the processor having a processor core operating according to one or more core clock frequencies, wherein a fixed ratio between the one or more core clock frequencies and the one or more bus clock frequencies is maintained regardless of variations in the one or more core clock frequencies or the one or more bus clock frequencies, the processor further having a bus interface for receiving one or more second bus clock signals having the one or more bus clock frequencies and using the second bus clock signals to generate and sample control signals, address signals, and data signals on the bus.

12. The system of claim 11, wherein one or more core clock frequencies are no less than a multiple of a lowest frequency of the one or more bus clock frequencies.

13. The system of claim 11, wherein the processor further comprises at least one second clock divider to generate one or more second bus clock signals having the one or more bus clock frequencies according to the fixed ratio.

14. The system of claim 13, wherein the processor further comprises a phase locked loop to generate an intermediate clock signal from a system clock signal, wherein the at least one second clock divider is to divide the intermediate clock signal to produce the one or more second bus clock signals.

15. The system of claim 14, wherein the system clock signal is divided to generate a core clock signal having a particular core clock frequency of the one or more core clock frequencies at a time.

16. The system of claim 13, wherein a division factor of the at least one second clock divider is changed according to the fixed ratio when switching between a performance mode and a power saving mode of the processor.