HK1089557B - Method of making a low profile packaged semiconductor device - Google Patents

Description

Method for manufacturing low profile highly packaged semiconductor device

Technical Field

The present invention relates generally to semiconductor devices and, more particularly, to semiconductor chips housed in low profile packages.

Background

There is a continuing need for electronic systems with higher functionality and smaller physical size. For example, successive generations of personal computers are specified to utilize ever-decreasing motherboards, while adding more components and operating at lower voltages but higher power consumption. Power requirements are often met by utilizing multiple local voltage regulators located at several locations on each motherboard.

Voltage regulators are typically implemented as switching regulators that include an integrated control circuit and, to accommodate high current levels, a plurality of parallel-connected, separate power switching transistors. One problem with this arrangement is that in each generation, multiple power switch transistors occupy a larger portion of the smaller motherboard, which reduces the area available for implementing other functions.

Some previous power transistors have utilized wire bonding to connect their semiconductor chips to package leads, but do not mount the semiconductor chips on the semiconductor chip attach flag. These devices have poor productivity and, ultimately, high cost because they are not sufficient to hold the semiconductor chip in place during the wire bonding operation. Problems can arise with semiconductor chips if they move when wire bonded connections are made.

Therefore, there is a need for a packaged semiconductor device having a small physical size and high efficiency so as to eliminate the above-mentioned problems.

Disclosure of Invention

The present invention provides a method of manufacturing a semiconductor device, characterized by the steps of: mounting a semiconductor chip having opposing first and second surfaces on an adhesive surface of a mounting tape over a hole in the tape, wherein the hole extends through the tape and the second surface covers the hole; drawing a vacuum through the hole to fix the semiconductor chip; connecting one end of a bonding wire to the first surface of the semiconductor chip while evacuating; and connecting the other end of the bonding wire to a lead disposed on the mounting tape.

The invention also provides a method for packaging semiconductor chips, which is characterized by comprising the following steps: providing a tape having an adhesive surface and an aperture extending through the tape; mounting a lead frame on the adhesive surface, wherein the lead frame has an opening and a lead, the opening surrounding the hole; mounting a semiconductor chip directly on the adhesive surface within the opening such that the semiconductor chip covers the hole; and drawing a vacuum through the hole to maintain the position of the semiconductor chip while wire bonding the semiconductor chip to the lead.

The present invention also provides a method of manufacturing a semiconductor device, characterized by the steps of: providing a mounting tape having an adhesive surface and an array of holes; attaching a leadframe substrate having a plurality of openings to an adhesive surface such that the plurality of openings are aligned with the array of holes; mounting a plurality of semiconductor chips to the adhesive surface, wherein each semiconductor chip covers a hole; forming a low voltage at the first hole while connecting the first bonding wire to the first semiconductor chip, wherein the step of forming the low voltage during the step of connecting the first bonding wire secures the first semiconductor chip to the mounting tape; forming a low voltage at the second hole while connecting the second bonding wire to the second semiconductor chip, wherein the step of forming the low voltage during the step of connecting the second bonding wire secures the second semiconductor chip to the mounting tape; forming a layer of molding material over portions of the leadframe substrate and the plurality of semiconductor chips while masking other portions of the leadframe substrate and the plurality of semiconductor chips with a tape to form a molded assembly; and dividing the molded assembly to form individual semiconductor devices.

Drawings

Fig. 1 is an exploded isometric view of a semiconductor device at a first stage of manufacture;

FIG. 2 is a side cross-sectional view of a semiconductor device and a portion of an assembly apparatus at a second stage of manufacture;

fig. 3 is an isometric view of the semiconductor device after completion of the entire operation;

fig. 4 is a bottom view of the semiconductor device; and

fig. 5 is a side cross-sectional view of a portion of an electrical system including a semiconductor device.

Detailed Description

In the drawings, like numbered elements have the same structure and functionality. Depending on the text, the same elements associated with a particular reference number may be described in a variety or general or in a single or specific sense.

Fig. 1 is an exploded isometric view of a semiconductor device 10, the semiconductor device 10 being assembled to a mounting tape 12 at a first stage of manufacture. The semiconductor device 10 is constructed using a leadframe or leadframe substrate 16 and one or more semiconductor chips 14. In one embodiment, the semiconductor chips 14 are substantially identical semiconductor substrates upon which standard semiconductor wafer processing is performed to produce a plurality of power transistors.

The mounting tape 12 comprises a standard semiconductor package mounting tape having an adhesive surface 11 for holding the mounted components in place during the mounting operation. An array of holes 18 is punched or otherwise formed in the strip 12 at predetermined locations determined by package size or other factors. The holes 18 may be formed in situ with computer controlled punching equipment prior to installation of the packaging components or may be purchased as drilled holes from the tape manufacturer or distributor. The mounting strap 12 is preferably made of a material that can withstand the temperatures required to complete the package assembly. For example, in one embodiment, the maximum temperature is generated during an encapsulation operation during which an epoxy-based or plastic molding compound is dispersed and cured at a temperature of about 180 ℃. In one embodiment, the mounting strip 12 is made of an acrylic adhesive coated onto polyester and formed with a plurality of holes 18 having a diameter of about 1500 μm. Alternatively, the mounting strap 12 may comprise a silicone and/or acrylic adhesive having a polyester, polyimide or Polytetrafluoroethylene (PTFE) backing. The mounting strip 12 may also be formed from an adhesive material applied to a metal foil, such as aluminum foil.

The leadframe substrate 16 has an x-y array defining individual leadframe regions and includes a leadframe 20, the leadframe 20 being integrally defined along cut lines 21-24 and used to form a plurality of packaged integrated circuits or transistors after assembly. In the embodiment of fig. 1, the leadframe substrate 16 is patterned such that, for example, a leadframe 20 is formed having leads 15 and 17 and an opening 19. The regions 29 between adjacent leadframes act as a kind of tie bar to maintain the position of the leads 15 and 17 relative to the openings 19 during assembly. In one embodiment, the leadframe substrate 16 is stamped or etched from a rolled copper sheet having a thickness in a range between 100 and 500 microns. And a typical thickness is about 200 microns. The lead frame substrate 16 is mounted on a region 27 of the adhesive surface 11 with the openings 19 aligned with regions 26 of the mounting tape 12, the regions 26 generally being centered about the holes 18. Thus, the leadframe substrate 16 is mounted directly on the adhesive surface 11 so that the holes 18 are exposed and visible through the openings 19.

The opening 19 has an area larger than the area of the semiconductor chip 14 so that the semiconductor chip 14 can be mounted directly on the adhesive surface 11 within the opening 19 and over the hole 18 using a standard pick and place equipment (not shown). The size of the opening 19 is selected in view of the semiconductor chip size, the requirements of the pick and place equipment, and any alignment tolerances required by the saw or other singulation tool in order to avoid damage to the semiconductor chip 14 during subsequent singulation operations.

Fig. 2 is a side cross-sectional view of semiconductor device 10 after a second stage of manufacture and illustrates the mounting tape 12 mounted on a portion of an assembly apparatus that includes a vacuum system 42.

A vacuum pump (not shown) draws a vacuum through the conduits of the vacuum system 42 in the direction indicated by arrow 40 to create a low pressure at each hole 18 that serves to fix the position of the semiconductor chip 14 and counteract the resiliency or movement of the mounting tape 12 during subsequent wire bonding. Once evacuated, the wire bonding machine secures the bonding wire 35 from the top surface 43 of the wire 17 to the top surface 32 of the semiconductor chip 14. Similar wire bonds are connected from leads 15 to top surface 32 as shown in fig. 2 and described below.

After wire bonding, semiconductor device 10 is placed on the bottom of a molding cavity (not shown) into which a molding material 49 such as plastic or thermosetting epoxy is introduced with tape 12 attached. Molding material 49 is formed as a continuum that encapsulates top surface 32 of semiconductor chip 14, top surfaces 43 of leads 17, and top surfaces of leads 15 (not shown in fig. 2). The mounting tape 12 is secured to the surface of the semiconductor device 10 to inhibit the molding material 49 from infiltrating the hole 18, thereby preventing the formation of mold flash on the bottom surface 31 of the semiconductor chip 14.

During wafer processing, the bottom surface 31 of the semiconductor chip 14 forms a solderable layer 72 for mechanical and conductive attachment to an external surface. Bottom surfaces 31, bottom surfaces 44 of leads 17, and bottom surfaces 54 of leads 15 (shown in fig. 3-4) are all connected to mounting tape 12 during a packaging or molding operation, and as a result, they are all masked by mounting tape 12 to prevent molding material 49 from covering them. Thus, bottom surfaces 31, 44 and 54 are exposed for making external electrical and mechanical connections after removal of mounting tape 12. If desired, semiconductor device 10 is subjected to a cleaning operation to remove any residue of mounting tape 12 or its adhesive material to ensure that bottom surfaces 31, 44 and 54 are all exposed and free of material that would prevent or reduce electrical contact with external surfaces.

It should be noted that the leadframe base 16 is subjected to half-etching or the like in order to form the mold locks 71, the mold locks 71 preventing the molding material 49 from being separated from the leads 15 and 17 during subsequent processing or when the semiconductor device 10 is used or handled. In one embodiment, the mold locks 71 have a generally rectangular reentrant shape as shown.

The leads 15 and 17, and in fact the lead frame base 16, are made to have a thickness less than that of the semiconductor chip 14. For example, in one embodiment, semiconductor chip 14 has a thickness of about 200 microns, and leads 15 and 17 have a thickness of about 125 microns. This thickness difference enables the bonding wire 35 to be formed with a small loop height in order to reduce the overall thickness or height of the semiconductor device 10. In one embodiment, in which semiconductor chip 14 has a thickness of 200 microns, the height of the ring is about 480 microns from the highest point of bonding wires 35-36 to top surface 32 of semiconductor chip 14, and the overall height of semiconductor device 10 is about 800 microns.

Fig. 3 is an isometric view of semiconductor device 10 after removal of mounting tape 12 and sawing along dicing lines 21-24 to complete the singulation process. In one embodiment, semiconductor die 14 is formed as a power transistor operating at a specified source-drain current greater than 1 amp and encased in a unitary package 70, which unitary package 70 includes leads 15 and 17, bonding wires 35 and 36, and molding material 49.

Semiconductor chip 14 has a gate electrode connected to gate bond pad 51 and a source electrode connected to a source bond pad 52, both of which are formed on top surface 32 of semiconductor chip 14. A solderable layer 72 is formed on the bottom surface 31 during wafer processing to function as a drain terminal. In one embodiment, solderable layer 72 and a titanium nickel silver alloy are formed. Bottom surface 31 is exposed, i.e., not encapsulated, by molding material 49, so solderable layer 72 allows bottom surface 31 to function as a package lead that can be reflowed with solder or otherwise connected for making external connections.

Where semiconductor device 10 includes a vertical power transistor, a plurality of bonding wires 35 are connected in parallel between source bonding pad 52 and top surface 43 of lead 17 to reduce on-resistance. The gate current is transient in nature and typically has a low amplitude, so a single bond wire 36 connected between gate bond pad 51 and lead 15 is typically sufficient to ensure high performance.

It should be noted that bottom surface 31 of semiconductor chip 14, bottom surface 44 of lead 17, and bottom surface 54 of lead 15 are all coplanar and exposed from molding material 49 to facilitate external connectivity.

Tabs 55-56 extend from leads 15 and 17, respectively, and are remnants of tie bars of region 29, while remaining on leads 15 and 17 as a saw or integrally worked article.

Exposing bottom surface 31 of semiconductor chip 14 and lowering the loop height of bonding wires 35-36 provides package 70 of semiconductor device 10 with a low profile. In one embodiment, semiconductor device 10 has an overall height of about 800 microns.

Fig. 4 is a bottom view of semiconductor device 10, and fig. 4 shows bottom surface 31 of semiconductor chip 14 when exposed for making external electrical connections with bottom surfaces 54 of leads 15 and bottom surfaces 44 of leads 17. Bottom surfaces 31, 44 and 54 are all coplanar.

Fig. 5 shows a cross-sectional side view of a portion of an electronic system including semiconductor device 10 mounted on a motherboard 60.

The motherboard 60 is formed with a trace 61 and a trace 62, the lead 17 is connected to the trace 61, and the trace 62 is for connection to the bottom surface 31 of the semiconductor chip 14. In one embodiment, leads 17 and bottom surface 31 are connected to traces 61-62 by reflow soldering.

Exposing the bottom surface 31 of the semiconductor chip 14 results in a low thermal resistance because heat does not flow through the bond pads of the semiconductor chip and their associated metallurgical bonds as in other packaged devices. This benefit is particularly apparent in an embodiment where most of the power is generated on the bulk of the semiconductor chip 14 rather than on the top surface 32.

Thermal resistance is further reduced by the low package profile height of semiconductor device 10 because of the short distance from semiconductor chip 14 to top surface 65 of molding material 49. In some applications, it may be advantageous to mount an external heat sink (not shown) to top surface 65 to help dissipate power. It should also be noted that the traces 62 are formed to extend outwardly from the semiconductor device 10. This mounting exposes a portion of trace 62 to ambient air flow to further facilitate removal of power P dissipated by semiconductor device 10_D。

Further, by mounting the bottom surface 31 of the semiconductor chip 14 directly onto the traces 62, the resistance is reduced because the vertical distance from the traces 62 to the bottom surface 31 is zero. In practice, the current flows directly from the bulk substrate of the semiconductor chip through solderable layer 72 onto trace 62. Thus, current flowing through the semiconductor device 10 does not hit the semiconductor chip attach flag and flows through a few metallurgical bonds, which results in a lower on-resistance than with other devices. Lower on-resistance further reduces dissipated power P_DWhile providing high performance and efficiency.

It can now be seen that the present invention provides a packaged semiconductor device having a low profile height and low electrical and thermal resistance. The lead has a first surface for wire bonding to the first surface of the semiconductor chip and a second surface substantially coplanar with the second surface of the semiconductor chip. The molding material encapsulates the first surface of the semiconductor chip and exposes the second surface of the semiconductor chip. The semiconductor chip and leads are disposed on the mounting tape to maintain their positions during the packaging assembly operation. The semiconductor chip is secured during the packaging operation by being positioned over one of the holes in the mounting tape and by drawing a vacuum through the hole so as to eliminate any movement or resiliency in the mounting tape while simultaneously applying pressure to the semiconductor chip during the wire bonding operation by the wire bonding tool.

The present invention provides a packaged semiconductor device having high reliability and low cost. Since the semiconductor chip is exposed to function as a kind of lead, there is no semiconductor chip connection pad, and thus, there is no need for a solder reflow semiconductor chip connection work. Thus, the semiconductor device can be assembled at various manufacturing sites and at a lower cost. Furthermore, there is less variation in component materials and therefore less variation in temperature expansion coefficients within the semiconductor device. Therefore, internal stress is reduced and reliability is increased. Finally, the semiconductor device can be constructed with smaller traces because there is no need to align and mount the semiconductor chip on the semiconductor chip connection pads, which are made larger to avoid the semiconductor chip protruding.

Claims (8)

1. A method of manufacturing a semiconductor device, characterized by the steps of:

mounting a semiconductor chip having opposing first and second surfaces on an adhesive surface of a mounting tape over a hole in the tape, wherein the hole extends through the tape and the second surface covers the hole;

drawing a vacuum through the hole to fix the semiconductor chip;

connecting one end of a bonding wire to the first surface of the semiconductor chip while evacuating; and

connecting the other end of the bonding wire to a lead disposed on the mounting tape.

2. The method of claim 1, further comprising the step of encapsulating the bonding wire, at least a portion of the lead, and at least a portion of the semiconductor chip.

3. The method of claim 2, wherein the step of encapsulating the leads and the semiconductor chip comprises coating the leads and the semiconductor chip so that surfaces thereof are exposed to provide the package leads.

4. The method of claim 1, further comprising the step of attaching a leadframe including the leads to the adhesive surface, wherein the second surface of the semiconductor chip is coplanar with the outer surfaces of the leads.

5. A method of packaging semiconductor chips, characterized by the steps of:

providing a tape having an adhesive surface and an aperture extending through the tape;

mounting a lead frame on the adhesive surface, wherein the lead frame has an opening and a lead, the opening surrounding the hole;

mounting a semiconductor chip directly on the adhesive surface within the opening such that the semiconductor chip covers the hole; and

a vacuum is drawn through the hole to maintain the position of the semiconductor chip while wire bonding the semiconductor chip to the leads.

6. The method of claim 5, further comprising the step of packaging the semiconductor chip and leads while connected to the tape.

7. A method of manufacturing a semiconductor device, characterized by the steps of:

providing a mounting tape having an adhesive surface and an array of holes;

attaching a leadframe substrate having a plurality of openings to an adhesive surface such that the plurality of openings are aligned with the array of holes;

mounting a plurality of semiconductor chips to the adhesive surface, wherein each semiconductor chip covers a hole;

forming a low voltage at the first hole while connecting the first bonding wire to the first semiconductor chip, wherein the step of forming the low voltage during the step of connecting the first bonding wire secures the first semiconductor chip to the mounting tape;

forming a low voltage at the second hole while connecting the second bonding wire to the second semiconductor chip, wherein the step of forming the low voltage during the step of connecting the second bonding wire secures the second semiconductor chip to the mounting tape;

forming a layer of molding material over portions of the leadframe substrate and the plurality of semiconductor chips while masking other portions of the leadframe substrate and the plurality of semiconductor chips with a tape to form a molded assembly; and

the shaped assembly is singulated to form individual semiconductor devices.

8. The method of claim 7, wherein the step of connecting the leadframe substrate includes connecting a leadframe substrate that is thinner than each of the plurality of semiconductor chips.