HK1088284B - Heater chip and method of operating the same, printhead, printer - Google Patents

Description

Heater chip, method of operating the same, printhead, and printer

Technical Field

The present invention relates to an inkjet printhead. In particular, the present invention relates to a heater chip thereof having a reduced size due to a narrow width power FET driven by an integrated voltage regulator having a trim capacitor.

Background

Techniques for printing images by ink jet techniques are well known. Typically, an image is produced by ejecting ink drops from an inkjet printhead at a precise moment so that they impact a print medium at a desired location. The printhead is supported by a movable print carriage in a device, such as an inkjet printer, and is caused to reciprocate relative to an advancing print medium and eject ink drops at such times pursuant to instructions of a microprocessor or other controller. The timing of the ink drop ejection corresponds to the pattern of image pixels being printed. In addition to printers, common devices that incorporate inkjet technology include, to name a few, fax machines, cell phones, photo printers, and plotters.

Conventionally, thermal inkjet printheads include a local or remote supply involving a color or monochrome ink, a heater chip, a nozzle or orifice plate attached to the heater chip, and an input/output connector, such as an automated tape bond circuit, for connecting the heater chip to a printer during use. The heater chip, in turn, typically includes a plurality of thin film resistors or heaters fabricated by deposition, masking and etching techniques on a substrate, such as silicon.

To print or eject a single drop of ink, individual resistive heaters are uniquely supplied with a small amount of current to rapidly heat a small volume of ink. This causes ink to evaporate in the local ink chamber (between the heater and the nozzle plate) and be ejected through and emitted by the nozzle plate towards the print medium.

The circuitry that drives the printing of a single drop typically includes a Field Effect Transistor (FET) source and a voltage source (typically +10.8 volts) connected to either end of the resistive heater. The control logic circuit sends a logic signal to the gate of the FET, and the resistive heater heats and ink is ejected upon actuation of the FET.

As a corollary to supplying a transistor logic (TTL) device of a control logic circuit with +5 volts of power, many FETs are driven by the same voltage. However, for today's CMOS ASICs, the voltage standard for the control logic is +3.3 volts. Thus, if the heater chip of an ink jet printer is to power its CMOS with one voltage and drive its FETs with another voltage while powering its resistive heaters with another voltage, then at least three different voltages are required to be transmitted from the printer to the heater chip and wiring (wiring) must be feasibly routed on the chip. This, therefore, increases circuit cost and complexity.

Accordingly, the inkjet printhead art desires a heater chip with optimal voltage control without the attendant chip cost.

Disclosure of Invention

The above and other problems are solved by the use of apparatus and method principles and techniques related to an inkjet printhead heater chip having a reduced size as described hereinafter.

In one embodiment, the heater chip has an integral voltage regulator that will derive two output voltages from a single voltage input into the chip. One of the two output voltages supplies power for the control logic circuit and the other output voltage supplies power for the FET driver. Preferably, the input voltage comprises +10.8 volts, and the output voltage comprises a line of +3.3 volts for the control logic and +7.5 volts for the FET drivers. Vgs of the FET is approximately +7.5 volts, which may cause the FET to have approximatelyA zone width of 400 microns and a zone length of about 42 microns (1/1600)^thInches). The output of the control circuit provides an input to the FET driver. A resistive heater for ejecting ink is connected between the drain of the FET and the chip input voltage. Preferred FET drivers include logic AND gates or logic NAND gates with inverters.

In another aspect of the invention, a voltage regulating capacitor is present on the heater chip in parallel with any or all of the input voltages and each of the output voltages. Preferred capacitors have a gate oxide layer and a polysilicon layer overlying a substrate and may or may not have a region of n-well doping in the substrate beneath the gate oxide layer. The positive capacitor electrode is attached to the polysilicon layer. The negative capacitor electrode is attached to an electrically grounded substrate.

Printheads containing the heater chips and printers containing the printheads are also disclosed.

These and other embodiments, aspects, advantages, and features of the present invention will be set forth in the description which follows, and in part will become apparent to those of ordinary skill in the art by reference to the following description of the invention and referenced drawings and by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

Drawings

FIG. 1 is a perspective view of a thermal inkjet printhead according to the present technique;

FIG. 2 is a perspective view of an ink jet printer in accordance with the present technique;

FIG. 3 is a schematic diagram of a circuit capable of having narrow size power FETs in a heater chip of an inkjet printhead in accordance with the present technology;

FIG. 4 is a schematic diagram of a portion of a reduced size heater chip with narrow size power FETs in accordance with the present technique;

FIG. 5 is a schematic diagram of an overall voltage regulator in accordance with the present technique;

FIG. 6 is a schematic diagram of a heater chip having multiple voltage regulating capacitors in accordance with the present technique;

FIG. 7A is a schematic diagram of a first embodiment of an independent voltage regulating capacitor in accordance with the present technique; and

FIG. 7B is a schematic diagram of a first embodiment of an independent voltage regulating capacitor in accordance with the present technique.

Detailed Description

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments having various process, electrical, mechanical, chemical or other changes may be utilized without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.

In accordance with the present invention, we will hereinafter describe an inkjet printhead heater chip having reduced size due to narrow width power FETs driven by an integral voltage regulator having a regulating capacitor.

Referring to fig. 1, an ink jet print head of the present invention is shown generally at 10. The printhead 10 has a housing 12 made of any suitable material for containing ink. Its shape may vary and is generally dependent on the external device that carries or houses the printhead. The housing has at least one compartment 16 therein to accommodate an initial or refill supply of ink. In one embodiment, the compartment has a single chamber and contains a black supply ink, a photo supply ink, a cyan supply ink, a magenta supply ink, or a yellow supply ink. In other embodiments, the compartment has multiple chambers and contains three supplies of ink. Preferably, cyan, magenta and yellow inks are included. In still other embodiments, the compartment contains multiple inks of black, photo, cyan, magenta, or yellow ink. It should be understood, however, that while the compartment 16 is shown as being partially incorporated into the housing 12 of the printhead, it may alternatively be connected to a remote ink source and receive a supply of ink, for example, from a tube.

A portion 19 of the automated taping circuit 20 is adhered to one surface 18 of the housing 12. Another portion 21 of the TAB circuit 20 is adhered to another surface 22 of the housing. In this embodiment, the two surfaces 18, 22 are arranged perpendicular to each other with respect to the edge 23 of the housing.

The TAB circuit 20 supports thereon a plurality of input/output (I/O) connectors 24 for electrically connecting the heater chip to an external device, such as a printer, facsimile machine, copier, photo printer, plotter, uniset, etc., during use. A plurality of electrical conductors 26 are present on the TAB circuit 20 to electrically connect or short the I/O connectors 24 to the input terminals (bond pads 28) of the heater chip 25. Various techniques are known for simplifying the connection. For simplicity, we show only eight I/O connectors 24, eight electrical conductors 26, and eight bond pads 28, but today's printheads have a larger number and any number is equally encompassed herein. In addition, it will be understood by those of ordinary skill in the art that while the number of connectors, electrical conductors, and bond pads are the same as one another, actual printheads may have different numbers.

The heater chip 25 contains four rows (rows a-D) of a plurality of resistive heater elements (or simply heaters) for ejecting ink from the compartment 16 during use. For simplicity, the plurality of heaters in rows A through D are shown as rows of six dots,but in practice may include a length along the path at 1/600^thInch 1/1200^thInch 1/2400^thHundreds of heaters equally spaced in inches. Many processes for forming the vias are known. The process comprises the following steps: grit blasting or etching such as wet etching, dry etching, reactive ion etching, deep reactive ion etching, and the like. An aperture in a nozzle plate (not shown) is aligned with each heater to facilitate firing of the ink during use. The nozzle plate may be attached by an adhesive or epoxy or may be fabricated as a thin film layer.

Referring to fig. 2, an external device in the form of an inkjet printer containing the printhead 10 is shown generally as 40. The printer 40 includes a carriage 42 having a plurality of slots 44 for receiving one or more printheads 10. As is well known in the art, the motive force supplied to the drive belt 50 causes the carriage 42 to reciprocate along the shaft 48 over the print zone (in accordance with the output 59 of the controller 57). The reciprocation of the carriage 42 occurs relative to a print medium (such as a sheet of paper) 52, which paper 52 advances in the printer 40 along a paper path from an input tray 54 through the print zone 46 to an output tray 56.

While in the print zone, the carriage 42 reciprocates in a reciprocating direction generally perpendicular to the paper 52 advancing in the advance direction, as indicated by the arrow. Ink drops from the compartment 16 (fig. 1) are ejected from the heater chip 25 at the times indicated pursuant to instructions from the microprocessor or other controller 57. The timing of the ink drop ejection corresponds to the pattern of image pixels being printed. Oftentimes, the pattern is generated in a device that is electronically connected to the controller 57 (via ext. input), which is external to the printer, and includes, but is not limited to, a computer, scanner, camera, video display unit, personal data assistant, and the like.

To print or eject a single drop of ink, a heater (dot rows A-D, FIG. 1) is uniquely supplied with a small amount of current to rapidly heat a small amount of ink. This causes ink to evaporate in the local ink chamber between the heater and the nozzle plate and be ejected through and emitted by the nozzle plate towards the print medium. The trigger pulse required to eject the ink drop may be embodied as a single or a split trigger pulse.

A control panel 58 having a user selection interface 60 is also accompanied by a number of printers, such as an input 62 for the controller 57, to provide additional printer capability and stability.

Referring to fig. 3, the reduced size heater chip 25 of the present invention has an integral voltage regulator 330. Input terminals (such as bond pads 28)₁) The heater chip is supplied with a separate input voltage, preferably +10.8 volts. Input voltage line 332 is connected to an input terminal to provide an electrical path for the input voltage supplied to the voltage regulator at node 331. During use, the voltage regulator takes at least two output voltages supplied at nodes 333, 335 from separate input voltages. Preferably, the +10.8 volt input becomes approximately +3.3 volts on output voltage signal line 336 and approximately +7.5 volts on output voltage signal line 338. Figure 5, described below, illustrates one embodiment of a voltage regulator for use in connection with the present invention.

The control logic circuit 340 is in turn electrically connected to the input terminal bond pads 28 of the printer₂、28₃、28₄A logical input is received. The outputs (terminals) of the control logic (shown as four representative outputs (terminals) 342-1, 342-2, 342-3, 342-4) are connected as inputs to a plurality of drivers 350, which drivers 350 either drive or do not drive the switches 360. As shown, the switch is embodied as a power FET having a gate connected to the output of driver 350, a resistor R connected to the ground path_GAnd connected to the resistive heater element R_HThe resistive heater element R, the resistive heater element R_HFor heating the ink and ejecting it through the nozzle holes (dotted lines) under the actuation of the switches to which they are connected. Since other resistances may be present at the input terminal and the resistive heater element R_HIn the path between, and thus shows an auxiliary resistance R between them_L。

In a preferred embodiment, the output (terminal) 342 of the control logic circuit includes the original, address lines and extended address lines for accessing a particular driver 350, as well as a trigger pulse line. In other embodiments, the lines may include more, fewer, or other signals.

With respect to control logic 340, driver 350 and resistive heater element R_HThe first and second output voltage lines 336, 338 of the voltage regulator 330 supply voltage to the control logic circuit and the driver, respectively, from the input terminal 28₁Supplies voltage to the resistive heater. In this manner, the control logic circuit may receive one voltage for the COMS-based logic device, while the driver may receive another voltage at the same time when only one voltage is being supplied to the heater chip. In a preferred embodiment, the voltage on line 336 is approximately +3.3 volts and the voltage on line 338 is approximately +7.5 volts. Then, when the output of any independent driver 350 activates its respective FET, the Vgs (gate-source voltage) of the FET may become as large as +7.5 volts.

Referring to the table below, one of ordinary skill will note that the resistance of the 400 micron wide FET Region (RFET) with a Vgs of approximately +7.5 volts is equivalent to the same resistance of the 500 micron wide FET Region (RFET) of the prior art with a Vgs of approximately +5 volts.

Vgs (volt)	RFET(Ω)	FET region width (microns)
			3.3	7.0	500
5	4.5	500
			7.5	4.0	500
3.3	8.0	400
			5	4.9	400
7.5	4.5	400

Table: characterization of 400 and 500 micron wide FET area and 42 micron FET area length at room temperature and 320mA rated current

Thus, referring to fig. 4, since the FET width d2 may decrease with increasing Vgs and still maintain a leakage current suitable for firing ink from the resistive heater element, the overall width d3 of the heater chip may decrease accordingly. This saves silicon costs. As a manifestation of silicon savings, a practical wafer product having multiple heater chips as described above, equivalent to a 6% reduction in FET width, has increased the die-per-wafer yield (die-per-wafer) from 199 to 212 per wafer.

Since the illustrated chip embodies a single via 32 with left and right rows of FETs each narrowing from 500 microns to 400 microns, the distance d3 of the heater chip may be correspondingly narrow by about 200 microns. In addition, if the heater chip has a plurality of vias and a plurality of left and right rows of power FETs, the width of the heater chip can be narrowed by a larger distance.

As another significant improvement over the prior art, since the input terminals of the heater chip currently require only one input voltage, the TAB circuit 20 may have a corresponding reduction in electrical conductors and/or I/O connectors and the printer need only supply one input voltage, for example.

With respect to the distance d1 between adjacent FETs, this value preferably corresponds to the vertical pitch distance between the resistive heater elements. Likewise, the present invention contemplates 1/300 because pitch generally corresponds to printer resolution in terms of Dots Per Inch (DPI)^thInch 1/1200^thInch 1/2400^th1/600 inches or others^thThe distance of (c).

Referring to fig. 5, one embodiment of the overall or on-chip voltage regulator 330 includes three sub-circuits, specifically a voltage reference circuit 500 and first and second regulator circuits 510, 520, the first and second regulator circuits 510, 520 being used to derive first and second output voltages (+3.3 and 7.5 volts) from an input voltage (in the following embodiment +10.8 volts).

In general, voltage reference circuit 500 includes a voltage divider formed by a pair of series-connected resistors R6 and R7. The ratio of these two resistors is chosen such that the desired reference voltage is obtained at node 1 between them. In a preferred embodiment, R6 is a 150K ohm resistor, R7 is a 66K ohm resistor, and since the input voltage is approximately 10.8 volts, a reference voltage of approximately 3.3 volts is obtained. Additionally, a capacitor C3 may be provided to help stabilize the voltage. One preferred value of C3 is 200 pF.

With respect to regulator circuit 510, it includes an operational amplifier 512, wherein the inverting input (-) of operational amplifier 512 is connected to reference voltage node 1. The non-inverting input (+) is connected to the drain of the p-channel mos transistor 514. During use, a p-channel metal-oxide-semiconductor transistor is used as a pass device between the input voltage at node 331 and the output voltage at node 333. The operational amplifier 4 is constructed for unity gain by setting the feedback resistor R2 to a large value (100K ohms in one embodiment) and having no resistance in the path between the non-inverting input (-) of the operational amplifier and the node 333. Likewise, in this configuration the op-amp will vary the voltage at the output of op-amp 512 so as to maintain the voltage at node 333 at the same value as the inverting input (-), i.e., 3.3 volts. Resistor R1 (13.2K ohms in one embodiment) is used to force constant current 250A through pass device 514 to aid stability. A capacitor C1 (preferably 2nF) at the output node 333 of the regulator circuit 510 provides additional circuit stability.

The regulator circuit 520 is similar to the regulator circuit 510 except that a resistor R4(125K ohms) is added between the non-inverting input (-) of the operational amplifier 522 and the drain of the pass device 524. And the amplifier gain is increased so that the output of op-amp 522 attempts to maintain the voltage at node 335 at a constant 7.5 volts. The value of the load resistor R5(30K ohms) has been changed in order to provide the same constant current 250A.

Referring to fig. 6, to ensure a relatively smooth voltage waveform on the heater chip, a plurality of capacitors C are arranged electrically in parallel with the input voltage Vin on line 332 and the output voltages V1, V2 on lines 336, 338. In a preferred embodiment, a total of about 10 to 15 capacitors exist on the heater chip 25 and are dispersed over about the entire heater chip for each of the input voltage Vin and the output voltages V1, V2.

It should be understood that with reference to fig. 7A and 7B, which illustrate two embodiments of the capacitor C, the heater chip includes multiple thin film layers on a semiconductor substrate. In both embodiments, a gate oxide layer 702 and a polysilicon layer 704 overlie the substrate 700. The positive capacitor electrode is attached to the polysilicon layer and the negative capacitor electrode is attached to an electrically grounded substrate. In fig. 7A, an n-well region 706 of dopant is located under the gate oxide layer and is electrically coupled to the grounded substrate. It should be understood that the substrate is preferably a P-type, 100-orientation wafer, and preferred embodiments of the dopant include phosphorus and arsenic. The preferred thickness of the gate oxide layer is about 185 angstroms +/-about 15%, while the preferred thickness of the polysilicon layer is about 4500 angstroms +/-about 10%.

It will be understood by those of ordinary skill in the art that the structure shown in fig. 7A and 7B illustrates the result of a substrate that has been processed through a series of growth, deposition, masking, photolithography, and/or etching or other process steps. Likewise, preferred deposition techniques include, but are not limited to, any kind of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), epitaxial growth, evaporation, sputtering, or other similar known techniques. Preferred CVD techniques include Low Pressure (LP) types, but may also include Atmospheric Pressure (AP) types, Plasma Enhanced (PE) types, high density plasma types, and the like. Preferred etches include, but are not limited to, any type of dry or wet etch, reactive ion etch, deep reactive ion etch, and the like. Preferred photolithography steps include, but are not limited to, exposure to ultraviolet or x-ray light sources, etc., while the photomask includes photomask islands and/or photomask apertures. As those terms are readily understood in the art, the specific embodiment of the islands or apertures depends on whether the structure of the mask is a clear-view or dark-view mask.

In a preferred embodiment, substrate 700 comprises a P-type, 100-oriented silicon wafer having a resistivity of 5-20 ohms/cm. The starting thickness is preferably any of 525+/-20 microns M1.5-89, 625+/-20 microns M1.7-89, or 625+/-15 microns M1.13-90 for respective wafer diameters of 100+/-0.50mm, 125+/-0.50mm, and 150+/-0.50 mm.

Finally, the foregoing description is for the purpose of illustrating and describing various aspects of the invention only. However, the description is not intended to be exhaustive or to limit the invention to the precise form disclosed. For example, the input and output voltages of the voltage regulator may be any value other than those disclosed as 10, 10.8, 3.3, and 7.5 volts. Instead of the power FET shown, the switch may be any switch other than a transistor, such as an npn, pnp, bipolar transistor, n-channel, p-channel, or double-channel JFET, MOSFET, IGFET, or the like. Instead of the bonding pads shown, the input terminals of the heater chip may include wires, bumps, and the like. In contrast to the AND350 shown, the driver may be embodied as a logical NAND with an inverter, or the like. Instead of the top-ejection type, the inkjet printhead 10 may be embodied as a side-ejection type. The resistive heater may be embodied as a piezoelectric transducer or other transducer. The embodiments described above were therefore chosen to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally and equitably entitled.

Claims (29)

1. A heater chip for an inkjet printhead, comprising:

an input terminal for receiving an input voltage;

a voltage regulator connected to the input terminal, the voltage regulator having first and second output voltage lines, wherein a voltage thereon during use is derived from the input voltage;

a driver connected to one of the first and second output voltage lines for receiving a supply voltage;

a control logic circuit coupled to the driver and to the other of the first and second output voltage lines for receiving a supply voltage;

a transistor connected to the driver; and

a resistive heater element connected to the transistor and to the input terminal for receiving a supply voltage from the input voltage.

2. The heater chip of claim 1, wherein during use, one of the first and second output voltage lines is 3.3 volts and the other of the first and second output voltage lines is 7.5 volts.

3. The heater chip of claim 1, wherein the input voltage is 10.8 volts during use.

4. The heater chip of claim 1, wherein the input terminals are bond pads.

5. The heater chip of claim 1, wherein the transistor has a region width of 400 microns.

6. A heater chip for an inkjet printhead, comprising:

a voltage regulator having an input voltage and first and second output voltages from the input voltage;

a driver having an input and an output, the driver receiving a supply voltage from one of the first and second output voltages;

a control logic circuit having an output connected to said input of said driver, said control logic circuit receiving a supply voltage from the other of said first and second output voltages;

a transistor having a gate, a source, and a drain, the gate connected to the output of the driver; and

a resistive heater element connected to the drain and operable to heat upon actuation of the transistor, the resistive heater element receiving a supply voltage from the input voltage.

7. The heater chip of claim 6, wherein said transistor has a zone width of 400 microns.

8. A heater chip for an inkjet printhead, comprising:

a bond pad for receiving a 10.8 volt input voltage;

a voltage regulator electrically coupled to the bond pad, the voltage regulator having first and second output voltage lines, wherein first and second output voltages thereon are from the input voltage during use, the first output voltage is 3.3 volts, and the second output voltage is 7.5 volts;

a plurality of drivers each having a plurality of input terminals and an output terminal, the plurality of drivers receiving a supply voltage from the second output voltage line;

a control logic circuit having a plurality of outputs coupled to the plurality of inputs of the driver, the control logic circuit receiving a supply voltage from the first output voltage line;

a plurality of transistors each having an area width of 400 μm and having a gate, a source, and a drain, each of the gates being connected to the output terminal of each of the drivers; and

a plurality of resistive heater elements, each of the resistive heater elements connected between one of the drains and the input voltage.

9. A heater chip for an inkjet printhead, comprising:

a voltage regulator having at least two output voltage lines;

a driver connected to receive a supply voltage from one of the output voltage lines; and

a field effect transistor having a gate connected to the driver, the field effect transistor having a region width of 400 microns.

10. The heater chip of claim 9, wherein the field effect transistor receives an output signal from the driver such that a gate-source voltage of the field effect transistor is 7.5 volts.

11. The heater chip of claim 9, further comprising an input voltage line connected to the voltage regulator.

12. The heater chip according to claim 11, further comprising a resistive heater element connected to a drain of the field effect transistor and to the input voltage line.

13. A heater chip for an inkjet printhead, comprising:

an input voltage line;

a voltage regulator connected to the input voltage line, the voltage regulator having at least two output voltage lines;

a driver connected to receive a supply voltage from one of the output voltage lines;

a switch connected to the driver; and

a resistive heater element connected to the switch and the input voltage line.

14. The heater chip of claim 13, further comprising a logic control circuit connected to the driver and to the other of the output voltage lines for receiving a supply voltage.

15. The heater chip of claim 13, having a plurality of capacitors in parallel with each of the at least two output voltage lines.

16. An inkjet printhead comprising:

supplying ink;

a plurality of I/O connectors; and

a heater chip electrically connected to the plurality of I/O connectors, the heater chip having:

a voltage regulator connected to one of the plurality of I/O connectors for receiving an input voltage and having first and second output voltage lines;

a driver connected to receive a supply voltage from one of the first and second output voltage lines;

a control logic circuit connected to the driver, the control logic circuit connected to receive a supply voltage from the other of the first and second output voltage lines;

a switch connected to the driver; and

a resistive heater element connected to one of the plurality of I/O connectors and the switch, the resistive heater element for ejecting an ink drop from the supply ink upon actuation of the switch.

17. An ink jet printer comprising the ink jet print head of claim 16.

18. The inkjet printer of claim 17, wherein only one voltage source is connected to said plurality of I/O connectors.

19. The inkjet printhead of claim 16, wherein said heater chip further comprises a plurality of bond pads connected to said plurality of I/O connectors.

20. An inkjet printhead according to claim 16, further comprising automated tape bonding circuitry for supporting the I/O connectors.

21. A method for manipulating a heater chip of an inkjet printhead, comprising:

supplying an input voltage to a voltage regulator;

obtaining at least first and second output voltages from said input voltage, said obtaining voltage step being performed by said voltage regulator;

supplying one of the first and second output voltages to a driver;

driving a switch connected to the driver by an output of the driver; and

supplying the input voltage to a resistive heater element connected to an output of the switch.

22. The method according to claim 21, further comprising: the other of the first and second output voltages is supplied to a control logic circuit whose output is connected to the driver.

23. The method of claim 21, wherein the switch is a field effect transistor, and wherein the step of driving the switch further comprises supplying the output of the driver such that the gate-source voltage of the field effect transistor is 7.5 volts.

24. The method of claim 21, wherein the step of deriving at least first and second output voltages further comprises generating a first voltage of 3.3 volts and a second voltage of 7.5 volts.

25. The method of claim 21, wherein the step of supplying an input voltage further comprises supplying 10.8 volts from an inkjet printer.

26. A method for manipulating a heater chip of an inkjet printhead, comprising:

supplying an input voltage to a voltage regulator;

deriving at least first and second output voltages from said input voltage, said deriving voltage steps being performed by said voltage regulator;

supplying one of the first and second output voltages to a driver;

supplying the other of said first and second output voltages to a control logic circuit having an output connected to an input of said driver;

driving a transistor connected to the driver by an output of the driver;

supplying the input voltage to a resistive heater element connected to an output of the switch;

heating the resistive heater element; and

ink is ejected from the print head.

27. A heater chip for an inkjet printhead, comprising:

an input voltage line;

a voltage regulator having first and second output voltage lines; and

at least one capacitor in parallel with the input voltage line and the first and second output voltage lines, the at least one capacitor comprising:

a substrate;

a gate oxide layer on the substrate; and

a polysilicon layer on the gate oxide layer.

28. The heater chip of claim 27, wherein said substrate has a well of n-type dopant beneath said gate oxide layer.

29. The heater chip of claim 28, wherein said dopant is one of phosphorous and arsenic.