HK1087192B - Conductive bus structure for interferometric modulator array - Google Patents

Abstract

Embodiments of an interferometric modulator are disclosed having various enhancements and features including a conductive bus. In certain embodiments, the interferometric modulator has a first conductive layer suspended over a second electrode layer. In certain embodiments, a second conductive layer is provided over the first conductive layer. One of the first and/or second conductive buses may further connect to the first electrode layer and/or the second electrode layer. Other disclosed features can be incorporated into embodiments of the interferometric modulator to improve response time, power consumption, and image resolution.

Description

Conductive bus structure for interferometric modulator array

Technical Field

The technical field of the invention relates to microelectromechanical systems (MEMS), and more particularly, to electrical connection architectures for arrays of MEMS elements.

Background

Microelectromechanical Systems (MEMS) include micromechanical elements, actuators, and electronics. Micromechanical elements may be created using deposition, etching, or other micromachining processes that etch away parts of substrates and/or deposited material layers or that add layers to form electrical and electromechanical devices. One type of MEMS device is known as an interferometric modulator. An interferometric modulator may comprise a pair of conductive plates, one or both of which may be partially transparent and capable of relative motion upon application of an appropriate electrical signal. One of the plates may comprise a stationary layer deposited on a substrate and the other plate may comprise a metal diaphragm suspended from the stationary layer.

In some display configurations, an array of independently actuatable interferometric light modulators are used as display elements. The light modulators are electrically connected to provide control voltages or signals for individually actuating the individual light modulators.

Disclosure of Invention

The system, method and apparatus of the present invention have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this invention, its more prominent features will now be discussed briefly. After reviewing this discussion, and particularly after reading the section entitled "detailed description of certain embodiments" one will understand how the features of this invention provide advantages over other display devices.

In certain embodiments, a light modulator includes a substrate, a first electrode layer located on the substrate, and a second electrode layer located on the substrate. The light modulator further includes a reflective surface substantially parallel to the first electrode layer and coupled to the second electrode layer. The reflective surface is movable in a direction substantially perpendicular to the reflective surface between a first position and a second position. The first position is a first distance from the first electrode layer, and the second position is a second distance from the first electrode layer. The light modulator further includes a conductive bus layer, at least a portion of the conductive bus layer being electrically coupled to at least one of the first electrode layer and the second electrode layer. The reflective surface moves between the first position and the second position in response to a voltage applied across the conductive bus layer.

In some embodiments, a method is used to control a light modulator. The method includes providing a substrate and providing a first electrode layer on the substrate. The method further includes providing a second electrode layer on the substrate, and providing a reflective surface substantially parallel to the first electrode layer and coupled to the second electrode layer. The reflective surface is movable in a direction substantially perpendicular to the reflective surface between a first position and a second position. The first position is a first distance from the first electrode layer, and the second position is a second distance from the first electrode layer. The method further includes applying a voltage to a conductive bus layer, wherein at least a portion of the conductive bus layer is electrically coupled to at least one of the first electrode layer and the second electrode layer. The method further includes moving the reflective surface between the first position and the second position in response to an applied voltage.

In certain embodiments, a device comprises means for supporting an interferometric modulator. The device further includes means above the supporting means for conducting a first electrical signal. The device further includes means above the supporting means for conducting a second electrical signal. The device further comprises means for reflecting light substantially parallel to the means for conducting the first electrical signal and coupled to the means for conducting the second electrical signal, the means for reflecting light being movable in a direction substantially perpendicular to the means for reflecting light and movable between a first position at a first distance from the means for conducting the first electrical signal and a second position at a second distance from the means for conducting the first electrical signal. The apparatus further includes means for electrically coupling to at least one of the means for conducting the first electrical signal and the means for conducting the second electrical signal, wherein the means for reflecting light moves between the first position and the second position in response to a voltage applied across the means for electrically coupling.

Drawings

FIG. 1 is an isometric view depicting a portion of one embodiment of an interferometric modulator display in which a movable reflective layer of a first interferometric modulator is in a released position and a movable reflective layer of a second interferometric modulator is in an actuated position.

FIG. 2 is a system block diagram illustrating one embodiment of an electronic device including a 3 × 3 interferometric modulator display.

FIG. 3 is a diagram of movable mirror position versus applied voltage for one exemplary embodiment of an interferometric modulator of FIG. 1.

FIG. 4 is a schematic diagram of a set of row and column voltages that may be used to drive an interferometric modulator display.

Fig. 5A and 5B show an exemplary timing diagram for row and column signals that may be used to write a frame of display data to the 3 x 3 interferometric modulator display of fig. 3.

Fig. 6A is a cross-sectional view of the device of fig. 1.

FIG. 6B is a cross-sectional view of an alternative embodiment of an interferometric modulator.

FIG. 6C is a cross-sectional view of another alternative embodiment of an interferometric modulator.

FIG. 7A schematically illustrates an exemplary 3 × 3 interferometric modulator display having a conductive bus located above the second electrode layer and electrically coupled to the first electrode layer.

FIG. 7B shows a cross-sectional view of the 3 × 3 interferometric modulator display of FIG. 7A.

FIG. 7C is a view taken from one post support of the 3 × 3 interferometric modulator display of FIG. 7A, in which the conductive bus to the second electrode layer connection line is shown in circular dashed lines.

FIG. 8A schematically illustrates an exemplary 3 × 3 interferometric modulator display having a conductive bus located over and electrically coupled to the second electrode layer.

FIG. 8B shows a cross-sectional view of the 3 × 3 interferometric modulator display of FIG. 8A.

FIG. 9A schematically illustrates an exemplary 3 × 3 interferometric modulator display having a conductive bus located between the second electrode layer and the first electrode layer and electrically coupled to the first electrode layer.

FIG. 9B shows a cross-sectional view of the 3 × 3 interferometric modulator display of FIG. 9A.

FIG. 9C schematically illustrates an exemplary 3 × 3 interferometric modulator display having a conductive bus located on and electrically coupled to the first electrode layer.

FIG. 9D shows a cross-sectional view of the 3 × 3 interferometric modulator display of FIG. 9C.

FIG. 9E shows a cross-sectional view of another embodiment of the 3 × 3 interferometric modulator display of FIG. 9C having a mask material aligned with the conductive bus and located between the conductive bus and the viewing side of the 3 × 3 interferometric modulator display.

FIG. 10A schematically illustrates an exemplary 3 × 3 interferometric modulator display having a first conductive bus over the second electrode layer and electrically coupled to the first electrode layer, and a second conductive bus over the first conductive bus and electrically coupled to the second electrode layer.

FIG. 10B shows a cross-sectional view of the 3 × 3 interferometric modulator display of FIG. 10A.

Fig. 11(a) -11(Q) schematically illustrate a series of exemplary process steps for forming a conductive bus structure over the second electrode layer.

FIG. 12 shows a cross-sectional view of an embodiment of an interferometric modulator having an additional dielectric layer within the optical stack.

FIG. 13 shows a cross-sectional view of an embodiment of an interferometric modulator having a cavity within a dielectric layer.

FIG. 14 shows one embodiment of a patterned electrode having a reduced electrically active area.

FIG. 15 is a cross-sectional view of an interferometric modulator corresponding to FIG. 14 in a plane through the active and inactive regions.

FIG. 16 is another cross-sectional view of an interferometric modulator corresponding to FIG. 14 in a plane passing through only the active area.

FIG. 17 shows an alternative embodiment of a patterned electrode.

FIG. 18 is a cross-sectional view of an interferometric modulator corresponding to FIG. 17.

FIG. 19 shows an embodiment of an interferometric modulator having regions responsible for the electrostatic forces decoupled from the reflective surface layer.

FIG. 20 shows an embodiment of the interferometric modulator of FIG. 19 in the "ON" state.

FIG. 21 shows a perspective view of an embodiment of an interferometric modulator having a spring design for the second electrode layer.

FIG. 22 shows a floor plan of a pixel comprising a 3 × 3 array of interferometric modulators.

FIG. 23 shows a cross-sectional view of one embodiment of a red interferometric modulator taken from the array in FIG. 22.

FIG. 24 shows a cross-sectional view of one embodiment of a green interferometric modulator from the array in FIG. 22.

FIG. 25 shows a cross-sectional view of one embodiment of a blue interferometric modulator taken from the array in FIG. 22.

FIGS. 26A and 26B are system block diagrams illustrating one embodiment of a visual display device comprising a plurality of interferometric modulators.

Detailed Description

An exemplary embodiment of an interferometric light modulator comprises a substrate, a first electrode layer located on the substrate, a second electrode layer located on the substrate, and a conductive bus layer. At least a portion of the conductive bus layer is electrically coupled to at least one of the first electrode layer and the second electrode layer. The reflective surface moves between a first position and a second position in response to a voltage applied across the conductive bus layer. The conductive bus layer provides an electrical path having a significantly lower electrical resistance than a configuration in which the columns of interferometric modulators are electrically connected only through the first electrode layer or the rows of interferometric modulators are electrically connected only through the second electrode layer.

The following detailed description is directed to certain specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways. In the description, reference is made to the drawings wherein like parts are designated with like numerals throughout. As will be apparent from the following description, the invention may be implemented in any device that is configured to display an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or pictorial. More specifically, the invention may be implemented in or associated with a wide variety of electronic devices such as, but not limited to: mobile telephones, wireless devices, Personal Data Assistants (PDAs), handheld or portable computers, GPS receivers/navigators, cameras, MP3 players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and/or displays, camera scene displays (e.g., a rear view camera display for a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., a display of images on a piece of jewelry). MEMS devices of similar structure to those described herein can also be used in non-display applications such as in electronic switching devices.

One interferometric modulator display embodiment comprising an interferometric MEMS display element is shown in FIG. 1. In these devices, the pixels are in either a bright or dark state. In the bright ("on" or "open") state, the display element reflects a large portion of incident visible light to the user. When in the dark ("off" or "closed") state, the display element reflects little incident visible light to the user. Depending on the embodiment, the light reflectance properties of the "on" and "off" states may be reversed. MEMS pixels can be configured to reflect predominantly at selected colors, allowing for a color display in addition to black and white.

FIG. 1 is an isometric view depicting two adjacent pixels in a series of pixels of a visual display, wherein each pixel comprises a MEMS interferometric modulator. In certain embodiments, an interferometric modulator display comprises a row/column array of these interferometric modulators. Each interferometric modulator includes a pair of reflective layers positioned at a variable and controllable distance from each other to form a resonant optical cavity with at least one variable dimension. In one embodiment, one of the reflective layers is movable between two positions. In the first position, referred to herein as the released state, the movable layer is positioned relatively far from a fixed partially reflective layer. In the second position, the movable layer is positioned closer to the partially reflective layer. Incident light that reflects from the two layers interferes constructively or destructively depending on the position of the movable reflective layer, producing either an overall reflective or non-reflective state for each pixel.

The portion of the pixel array shown in FIG. 1 includes two adjacent interferometric modulators 12a and 12 b. In the interferometric modulator 12a on the left, a movable highly reflective layer 14a is illustrated in a released position at a predetermined distance from a fixed partially reflective layer 16 a. In the interferometric modulator 12b on the right, a movable highly reflective layer 14b is illustrated in an actuated position adjacent to a fixed partially reflective layer 16 b.

The fixed layers 16a, 16b are electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more layers each of chromium and indium tin oxide on a transparent substrate 20. The layers are patterned into parallel strips and may form row electrodes in a display device, as will be described further below. The movable layers 14a, 14b may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes 16a, 16 b) deposited on top of posts 18 and an intervening sacrificial material deposited between the posts 18. After the sacrificial material has been etched away, the deformable metal layers are separated from the fixed metal layers by a defined air gap 19. The deformable layers may use a highly conductive and reflective material, such as aluminum, and the strips may form column electrodes in a display device.

When no voltage is applied, the cavity 19 remains between the layers 14a, 16a and the deformable layer is in a mechanically relaxed state as shown by the pixel 12a in FIG. 1. However, after application of a potential difference to a selected row and column, the capacitor formed at the intersection of the row and column electrodes at the corresponding pixel becomes charged, and electrostatic forces pull the electrodes together. If the voltage is high enough, the movable layer deforms and is forced against the fixed layer (a dielectric material (not shown in this figure) may be deposited on the fixed layer to prevent shorting and control the separation distance), as shown in the right pixel 12b in FIG. 1. The behavior is the same regardless of the polarity of the applied potential difference. Thus, row/column actuation that can control the reflective vs. non-reflective pixel states is analogous in many ways to that used in conventional LCD and other display technologies.

FIGS. 2-5 illustrate one exemplary process and system for using an array of interferometric modulators in a display application. FIG. 2 is a system block diagram illustrating one embodiment of an electronic device that may embody aspects of the invention. In the exemplary embodiment, the electronic device includes a processor 21, which may be any general purpose single-or multi-chip microprocessor, such as an ARM, Pentium, or other microprocessor、Pentium II、PentiumIII、Pentium IV、PentiumPro、805 1、MIPS、Power PC、ALPHAOr any special purpose microprocessor such as a digital signal processor, microcontroller, or programmable gate array. As is conventional in the art, the processor 21 may be configured to execute one or more software modules. In addition to executing an operating system, the processor may be configured to execute one or more software applications, including a web browser, a telephone application, an email program, or any other software application.

In one embodiment, the processor 21 is further configured to communicate with an array controller 22. In one embodiment, the array controller 22 includes a row driver circuit 24 and a column driver circuit 26 that provide signals to a pixel array 30. The cross-sectional view of the array shown in FIG. 1 is shown by line 1-1 in FIG. 2. For MEMS interferometric modulators, the row/column actuation protocol may take advantage of the hysteresis properties of these devices shown in FIG. 3. It may require, for example, a 10 volt potential difference to cause a movable layer to deform from the released state to the actuated state. However, when the voltage is reduced from this value, the movable layer will retain its state as the voltage drops back below 10 volts. In the exemplary embodiment of FIG. 3, the movable layer does not release completely until the voltage drops below 2 volts. Thus, in the example shown in FIG. 3, there is a range of voltage, approximately 3-7 volts, within which there exists a window of applied voltage within which the device is stable in either the released or actuated state. This is referred to herein as the "hysteresis window" or "stability window". For a display array having the hysteresis characteristics of FIG. 3, the row/column actuation protocol can be designed to apply a voltage difference of about 10 volts to the pixels to be actuated in the selected pass and a voltage difference of approximately 0 volts to the pixels to be released during row strobing. After the strobe, the pixels are exposed to a steady state voltage difference of about 5 volts such that they remain in whatever state the row strobe put them in. After being written, each pixel sees a potential difference within the "stability window" of 3-7 volts in this example. This feature makes the pixel design shown in fig. 1 stable under the same applied voltage conditions in either an actuated or released pre-existing state. Since each pixel of the interferometric modulator, whether in the actuated or released state, is essentially a capacitor formed by the fixed and moving reflective layers, this stable state can be held at a voltage within the hysteresis window with almost no power dissipation. Essentially no current flows into the pixel if the applied potential is constant.

In typical applications, a display frame may be created by asserting the set of column electrodes in accordance with the desired set of actuated pixels in the first row. A row pulse is then applied to the row 1 electrode, actuating the pixels corresponding to the asserted column lines. The asserted set of column electrodes is then changed to correspond to the desired set of actuated pixels in the second row. A pulse is then applied to the row 2 electrode, actuating the appropriate pixels in row 2 in accordance with the asserted column electrodes. The row 1 pixels are unaffected by the row 2 pulse, and remain in the state they were set to during the row 1 pulse. The above steps may be repeated for the entire series of rows in a sequential manner to form the frame. Typically, the frames are refreshed and/or updated with new display data by continually repeating the process at some desired number of frames per second. A wide variety of protocols for driving row and column electrodes of pixel arrays to produce display frames are also well known and may be used in conjunction with the present invention.

Fig. 4 and 5 show one possible actuation protocol for forming a display frame on the 3 x 3 array of fig. 2. Figure 4 shows a possible set of row and column voltage levels that may be used for pixels having the hysteresis curves of figure 3. In the embodiment of FIG. 4, actuating a pixel includes setting the corresponding column to-V_biasAnd sets the corresponding row to + av-which may correspond to-5 volts and +5 volts, respectively. Releasing the pixel is then performed by setting the corresponding column to + V_biasAnd sets the corresponding row to the same + av, thereby creating a 0 volt potential difference across the pixel. In those rows where the row voltage is held at 0 volts, the pixels are stable in the state they were originally in, being at + V with the column_biasOr is-V_biasIs irrelevant.

FIG. 5B is a timing diagram showing a series of row and column signals applied to the 3 × 3 array of FIG. 2, which will result in the display arrangement of FIG. 5A, where actuated pixels are non-reflective. Prior to writing the frame shown in FIG. 5A, the pixels can be in any state, in this example, all the rows are at 0 volts, and all the columns are at +5 volts. Under these applied voltages, all pixels are stable in their existing actuated or released states.

In the frame shown in FIG. 5A, pixels (1, 1), (1, 2), (2, 2), (3, 2) and (3, 3) are activated. To accomplish this, during a line time for row 1, columns 1 and 2 are set to-5 volts, and column 3 is set to +5 volts. This does not change the state of any pixels, as all pixels remain within the 3-7 volt stability window. Thereafter, row 1 is strobed with a pulse that rises from 0 volts to 5 volts and then falls back to 0 volts. Thereby actuating the pixels (1, 1) and (1, 2) and releasing the pixels (1, 3). No other pixels in the array are affected. To set row 2 as desired, column 2 is set to-5 volts, and columns 1 and 3 are set to +5 volts. Thereafter, applying the same strobe to row 2 will actuate pixel (2, 2) and release pixels (2, 1) and (2, 3). Again, no other pixels in the array are affected. Similarly, row 3 is set by setting columns 2 and 3 to-5 volts, and column 1 to +5 volts. The row 3 strobe sets the row 3 pixels to the state shown in FIG. 5A. After writing the frame, the row potentials are 0, while the column potentials can remain at either +5 or-5 volts, and the display will thereafter be stable in the arrangement shown in FIG. 5A. It will be appreciated that the same procedure can be used for arrays consisting of tens or hundreds of rows and columns. It will also be appreciated that the timing, sequence, and levels of voltages used to perform row and column actuation can be varied widely within the general principles outlined above, and the above example is exemplary only, and any actuation voltage method can be used with the present invention.

The detailed structure of interferometric modulators that operate in accordance with the principles set forth above may vary widely. For example, fig. 6A to 6C show three different embodiments of the moving mirror structure. FIG. 6A is a cross-sectional view of the embodiment of FIG. 1, wherein a strip of metal material 14 is deposited on orthogonally extending supports 18. In FIG. 6B, the moveable reflective material 14 is attached to supports at the corners only, on tethers 32. In FIG. 6C, the moveable reflective material 14 is suspended from a deformable layer 34. This embodiment has several advantages because the structural design and materials used for the reflective material 14 can be optimized with respect to the optical properties, and the structural design and materials used for the deformable layer 34 can be optimized with respect to the desired mechanical properties. The production of various types of interference devices is described in a number of published documents, including, for example, U.S. published application No. 2004/0051929. The above-described structures may be fabricated using a variety of well-known techniques, including a series of material deposition, patterning, and etching steps.

The response time to discharge and charge an interferometric modulator depends in part on an RC (resistance-capacitance) time constant of the voltage circuit connected to the interferometric modulator. This response time of the interferometric modulator has an effect on the display quality of the interferometric modulator array. If the time between input scan pulses received by a given interferometric modulator is shorter than the response time of the interferometric modulator, the moving layer cannot be synchronized with the input scan pulses. Under such conditions, the state of the interferometric modulator is not responsive to all of the scan pulses, thus resulting in degradation of the displayed image. It is therefore desirable to provide an interferometric modulator having a reduced response time to achieve faster scan and refresh rates.

Voltage circuits connected to an interferometric modulator include the electrodes of the interferometric modulator, as well as contacts, leads, and other conductive elements that provide electrical connections between the electrodes and row/column drive electronics. In certain embodiments, the material and geometry of the electrodes of the interferometric modulator may affect the RC time constant of the voltage circuit. In certain array configurations, electrodes of adjacent interferometric modulators are coupled together in series to connect adjacent interferometric modulators with the drive electronics, which makes the RC time constant higher. For other array configurations, electrical connections may be made between the row and column drivers and the electrodes of the interferometric modulators using wires or other electrical connectors, which have an effect on the RC time constant of the interferometric modulators.

FIGS. 7A, 7B, and 7C schematically illustrate an exemplary 3 × 3 portion of an interferometric modulator display of embodiments described herein. Portions of the display that are larger or smaller than the 3 x 3 portion shown in fig. 7A are also compatible with the embodiments described herein. As shown in the cross-sectional view of fig. 7B, each modulator includes a substrate 1106, a first electrode layer 902 located on the substrate 1106, and a second electrode layer located on the substrate 1106. The modulator further comprises a reflective surface 901 substantially parallel to the first electrode layer 902 and coupled to the second electrode layer 1302. The reflective surface 901 is movable between a first position and a second position. The first position of the reflective surface 901 is a first distance from the first electrode layer 902. The second position of the reflective surface 901 is a second distance from the first electrode layer 902.

As shown in FIG. 7B, in certain embodiments, the first electrode layer 902 of each modulator is stationary and positioned proximate to the substrate 1106. The first electrode layers 902 of the array are arranged in rows. These rows are not shown in fig. 7A, but they correspond to the three row modulator shown in fig. 7A. The first electrode layers 902 of each row are electrically connected to each other, but are electrically insulated from the first electrode layers 902 of the other rows.

In certain embodiments, the second electrode layer 1302 of each modulator includes at least a portion of a moving layer located above the first electrode layer 902. In the embodiment schematically illustrated in FIG. 7A, the second electrode layer 1302 comprises the entire moving layer. In certain embodiments, the second electrode layers 1302 of the array are patterned to separate the second electrode layers 1302 of each column of modulators from the second electrode layers 1302 of adjacent columns of modulators. Thus, the second electrode layers 1302 of the array are arranged in columns. For example, in the embodiment schematically illustrated in FIG. 7A, the second electrode layer 1302 has strips or tethers 1300 at the four corners of the second electrode layer 1302 of each modulator. The tethers 1300 mechanically couple the second electrode layer 1302 to the support posts 202 located at the corners of the modulator. The tethers 1300 also mechanically couple the second electrode layers 1302 of adjacent modulators within a column, while the second electrode layers 1302 are electrically isolated from the second electrode layers 1302 of other columns. Other second electrode layers 1302 compatible with embodiments described herein use spring structures in place of the tethers 1300 in FIG. 7A.

As schematically illustrated in fig. 7A and 7B, in some embodiments, the reflective surface 901 of each modulator is mechanically coupled to the second electrode layer 1302 of the corresponding modulator by a support member 1200. Certain other embodiments include a plurality of support members that mechanically couple the reflective surface 901 to the second electrode layer 1302. Thus, when the modulator is actuated, the reflective surface 901 moves relative to the first electrode layer 902 between a first position and a second position along a direction 903 substantially perpendicular to the reflective surface 901.

In some embodiments, each modulator in the array further comprises a conductive bus layer. At least a portion of the conductive bus layer is electrically coupled to at least one of the first electrode layer 902 and the second electrode layer 1302. The reflective surface 901 moves between a first position and a second position in response to a voltage applied to the conductive bus layer.

The conductive bus layer 600 of some embodiments includes a conductive material including, but not limited to, metals, composites, and alloys. Exemplary conductive materials for the conductive bus layer 600 include, but are not limited to, titanium, chromium, nickel, and aluminum. In certain embodiments, the conductive bus layer 600 has a thickness in a range from about 0.1 microns to about 2 microns measured in a direction parallel to the direction 903 in fig. 7B. Other thicknesses are also compatible with the embodiments described herein.

As shown in fig. 7A, in some embodiments, the conductive bus layer 600 is positioned above the second electrode layer 1302. The conductive bus layer 600 of the modulator constitutes a plurality of conductive bars, which in the exemplary embodiment shown in FIG. 7A are located above the second electrode layer 1302. The conductive bars of each row are electrically connected to each other and electrically insulated from the conductive bars of the other rows. In certain embodiments, each conductive bar provides an electrical connection between a row driver and the first electrode layer 902 of a corresponding modulator row. In certain embodiments, the conductive bars arranged along the rows have a width, measured in a direction perpendicular to direction 903 in FIG. 7B, in a range between about 4 microns and about 10 microns. Other widths are also compatible with embodiments described herein.

In the exemplary embodiment shown in FIGS. 7A-7C, the conductive bus layer 600 of a modulator is electrically coupled to the first electrode layer 902 of the modulator through a conductive portion of one or more support posts 202 of the modulator. The support posts 202 provide structural support for the mobile layer and the second electrode layer 1302. As shown in fig. 7B, in some embodiments, the conductive portions of the support posts 202 are electrically coupled to both the conductive bus layer 600 and the first electrode layer 902, but are electrically insulated from the second electrode layer 1302 by the insulating material 603.

FIG. 7C schematically illustrates a post 202 of a 3 × 3 portion of the interferometric modulator display of FIG. 7A compatible with the embodiments described herein. The tether 1300 is mechanically coupled to the support posts 202, but is electrically insulated from the conductive bus layer 600 and the conductive portions 700 of the support posts 202. The conductive portion 700 of the support posts 202 electrically couples the conductive bus layer 600 to the first electrode layer 902. As shown in fig. 7C, the conductive portion 700 of the post 202 has a generally annular shape, as indicated by the dashed center line. In certain other embodiments, the conductive portion 700 has other cross-sectional shapes (e.g., square). In certain embodiments, the conductive portion 700 is cylindrical, or solid. Embodiments of the conductive portion 700 may have a uniform or non-uniform cross-section between the conductive bus layer 600 and the first electrode layer 902.

For the embodiment schematically shown in FIGS. 7A, 7B, and 7C, the conductive bus layer 600 is preferably positioned above the second electrode layer 1302 and away from the optical path of light entering or reflected from the interferometric modulator. Thus, the conductive bus layer 600 of such embodiments does not interfere with the optical properties of the interferometric modulators. In addition, the conductive bus layer 600 advantageously provides an electrical path between the row drive electronics and the first electrode layer 902 of the interferometric modulator array that is significantly less resistive than other electrical paths of other configurations (e.g., the first electrode layer 902 of a row of interferometric modulators connected in series with each other), thus advantageously reducing the RC time constant relative to these other configurations.

The conductive bus layer 600 of some embodiments is positioned at a different location relative to other portions of the interferometric modulator display. As schematically shown in fig. 7A, in some embodiments, the conductive bus layer 600 is located above the second electrode layer 1302. As described below, in certain other embodiments, the conductive bus layer 600 is positioned within or adjacent to the first electrode layer 902 or between the first electrode layer 902 and the second electrode layer 1302. The conductive bus layer 600 may also be located below the first electrode layer 902 or in substantially the same plane as the second electrode layer 1302. Other configurations of the conductive bus layer 600 are also compatible with the embodiments described herein.

FIG. 8A schematically illustrates an exemplary 3 × 3 portion of an interferometric modulator display in which interferometric modulators have conductive bus layers 800 overlying second electrode layers 1302 and electrically coupled to the second electrode layers 1302. FIG. 8B shows a cross-sectional view of the 3 × 3 portion of the interferometric modulator display of FIG. 8A. As shown in FIG. 8A, in some embodiments, the conductive bus layers 800 of a column of modulators of a display are coupled together to form a plurality of conductive bars. The conductive bars of each column electrically connect the second electrode layers 1302 of the column to each other, and the conductive bars of each column are electrically insulated from the conductive bars of the other columns.

In some embodiments, each conductive bar provides an electrical connection between a column driver and the second electrode layer 1302 of a corresponding column of modulators. In some embodiments, each conductive bus layer 800 is electrically connected to a corresponding second electrode layer 1302 at one or more locations. As shown in fig. 8B, the conductive bus layer 800 is connected to the second electrode layer 1302 over the support posts 202. In certain embodiments, the conductive bars arranged along the columns have a width, measured in a direction perpendicular to direction 903 in FIG. 8B, in a range between about 4 microns and about 10 microns. Other widths are also compatible with embodiments described herein. The conductive bus layer 800 advantageously provides a circuit path between the column driver electronics of the interferometric modulator array that has a significantly lower resistance than other electrical paths of other configurations, such as the second electrode layers 1302 of a column of interferometric modulators connected in series with each other, thereby advantageously reducing the RC time constant relative to other configurations.

FIG. 9A schematically illustrates an exemplary 3 × 3 portion of an interferometric modulator display in which interferometric modulators have conductive bus layers 900 located between first electrode layers 902 and second electrode layers 1302. FIG. 9B shows a cross-sectional view of the 3 × 3 portion of the interferometric modulator display of FIG. 9A. In the exemplary embodiment shown in FIG. 9A, the conductive bus layer 900 is located below the second electrode layer 1302 and is a conductive portion of the support posts 202. In the embodiment schematically illustrated in FIG. 9B, each conductive bus layer 900 is electrically coupled to each first electrode layer 902 of one interferometric modulator row and is electrically isolated from the first electrode layers 902 of other interferometric modulator rows.

The conductive bus layer 900 of some such embodiments electrically connects a row driver with the first electrode layer 902 of a corresponding row of interferometric modulators. The row driver selectively applies voltages through the conductive bus layer 900 to the first electrode layers 902 of the interferometric modulators in a row of the display. The conductive bus layer 900 provides an electrical path having a resistance significantly lower than a configuration in which rows of interferometric modulators are electrically connected only through the first electrode layer 902.

FIG. 9C schematically illustrates an exemplary 3 x 3 portion of an interferometric modulator display having interferometric modulators with conductive bus layers 1000 adjacent to and electrically coupled to first electrode layers 902 of a corresponding row of interferometric modulators. FIG. 9D shows a cross-sectional view of the 3 × 3 portion of the interferometric modulator display of FIG. 9C. The conductive bus layer 1000 of some such embodiments electrically connects a row driver with the first electrode layer 902 of a corresponding row of interferometric modulators, thereby providing an electrical path between the row driver and the interferometric modulators that is significantly less resistive than other configurations in which rows of interferometric modulators are electrically connected only through the first electrode layer 902. In the exemplary embodiment shown in fig. 9D, the conductive bus layer 1000 is positioned between the support posts 202 and near the outer edge of an underlying first electrode layer 902. The conductive bus layer 1000 is electrically coupled to the underlying first electrode layer 902.

The material of the conductive bus layer 1000 is selected to increase the conductivity across the first electrode layer 902. In certain embodiments, the conductive bus layer 1000 includes aluminum or other conductive material. Unlike the first electrode layer 902 of some embodiments, the material selected for the conductive bus layer 1000 may be opaque. In some embodiments, the width of the conductive bus layer 1000 measured in a direction perpendicular to the direction 903 in fig. 9D is in a range between about 4 microns and about 10 microns.

In some embodiments, a dielectric layer 906 is located between the conductive bus layer 1000 and the reflective surface layer 901. The dielectric layer 906 of certain such embodiments may advantageously prevent contact between the conductive bus layer 1000 and the reflective surface layer 901 of the interferometric modulator.

In certain embodiments, disposing the conductive bus layer 1000 below the reflective surface layer 901 can adversely affect the optical performance of the interferometric modulator by blocking at least a portion of incident reflected light of the interferometric modulator. To reduce the visual impact of the conductive bus layer 1000 on the optical performance of the interferometric modulator, a smaller width of the conductive bus layer 1000 measured along a direction perpendicular to the direction 903 in FIG. 9D may be utilized.

FIG. 9E shows a cross-sectional view of another embodiment of the 3 × 3 portion of the interferometric modulator display of FIG. 9C. The interferometric modulators of the display of FIG. 9E have a mask material 1002 that is substantially aligned with the conductive bus layer 1000 of the interferometric modulator and is located between the conductive bus layer 1000 and the viewing side of the 3 x 3 interferometric modulator display. The mask material 1002 is typically an opaque and optically absorptive material that is wide enough to block incident light from impinging on the conductive bus layer 1000. In the embodiment shown in FIG. 9E, the masking material 1002 is typically mixed with a light transmissive material (e.g., SiO) in the layer 1004₂) Coplanar, the light transmissive material is transmissive to incident light incident to the modulator and reflective light reflected from the modulator.

FIG. 10A schematically illustrates an exemplary 3 × 3 portion of an interferometric modulator display having interferometric modulators, in which a first conductive bus layer 1100 is located over the second electrode layer 1302 and a second conductive bus layer 1102 is located over the first conductive bus layer 1100. FIG. 10B shows a cross-sectional view of the 3 × 3 interferometric modulator display of FIG. 10A. The first conductive bus layer 1100 is electrically coupled to the first electrode layers 902 of a row of interferometric modulators by a conductive portion of at least one support post 202. The second conductive bus layer 1102 is electrically coupled to the second electrode layers 1302 of a column of interferometric modulators. The first conductive bus layer 1100 is electrically isolated from the second conductive bus layer 1102 by the insulating portion 605 of the support posts 202.

In fig. 10B, the first conductive bus layer 1100 is electrically coupled to the first electrode layer 902 through a conductive portion of the one or more support posts 202. The second conductive bus layer 1102 is electrically coupled to the second electrode layer 1302 at a location above the one or more support posts 202.

In some embodiments, the less resistive path provided by the conductive bus layer may advantageously reduce the RC time constant of the circuit. Exemplary RC times for a plurality of interferometric modulators having their first electrode layers 902 electrically coupled in series may vary in the range of 5 microseconds to 100 microseconds, depending on the number of interferometric modulators. The same plurality of interferometric modulators may have a resistance of up to 30-50 ohms/square. The use of conductive bus layers to electrically connect the row and column drivers to the corresponding first electrode layers 902 and second electrode layers 1302 of the plurality of interferometric modulators can reduce the resistance of the circuit, thereby reducing the RC time constant.

Method for manufacturing conductive bus on mechanical layer

FIGS. 11(A) -11(Q) schematically illustrate a series of example process steps for forming a conductive bus structure over a second electrode layer 1302. Fig. 11(a) shows the deposition of a black mask 1800 on a substrate 1106. In certain embodiments, the black mask 1800 comprises molybdenum.

Fig. 11(B) the black mask 1800 is patterned and etched to form islands on top of the substrate 1106. FIG. 11(C) shows depositing an oxide layer 1802 over the black mask 1800 and the substrate 1106, and depositing a metal layer 904 and a first electrode layer 902 over the oxide layer 1802. In certain embodiments, the metal layer 904 comprises chromium and the first electrode layer 902 comprises Indium Tin Oxide (ITO).

FIG. 11(D) shows the first electrode layer 902 and the metal layer 904 patterned and etched to form electrodes and interferometric modulators compatible with columns, rows, or other effective configurations, according to the design of the display. In the exemplary embodiment shown in fig. 11(a) -11(Q), the first electrode layer 902 may serve as a column electrode.

As shown in fig. 11(D), a dielectric (e.g., silicon oxide) layer 906 is formed over the metal layer 904, the first electrode layer 902, and the oxide layer 1802.

FIG. 11(E) shows the formation of a sacrificial layer 1804. The sacrificial layer 1804 determines the size of the cavity over which the reflective surface 901 is suspended. The interference characteristics of the cavity are directly affected by its depth. Some embodiments with colored interferometric modulators are constructed with modulators with different cavity depths to provide the resultant static colors of red, green, and blue. To produce these varying cavity sizes, a different thickness of the sacrificial layer 1804 is deposited for each different color interferometric modulator.

For example, in some embodiments, a first sacrificial layer is deposited, masked, and patterned such that the first sacrificial layer defines a first modulator region. A second sacrificial layer is then deposited and patterned to define the combined area of the first modulator and a second modulator defined above. The combined thickness of the first and second sacrificial layers in the area of the first interferometric modulator is greater than the thickness of the second sacrificial layer in the area of the second interferometric modulator. Subsequently, in certain embodiments, a third sacrificial layer is formed over the second sacrificial layer to define a combined area of the first, second, and third interferometric modulators for each set of color interferometric modulators. In certain embodiments, the third sacrificial layer need not be patterned, as its thickness will be included in all three modulators of the set of color interferometric modulators.

The three different sacrificial layers described herein may have different thicknesses. In this manner, the first modulator of the set of color interferometric modulators will have a cavity with a depth equal to the combined thickness of the three sacrificial layers. The second modulator of the set of color interferometric modulators will have a cavity with a depth equal to the combined thickness of two of the three sacrificial layers. The third modulator of the set of color interferometric modulators will have a cavity with a depth equal to the thickness of one of the three sacrificial layers. After removal of the sacrificial layers, the size of the cavity will vary for different combined thicknesses of the three sacrificial layers, thereby producing three different colors, e.g., red, green, and blue.

FIG. 11(F) shows the deposition of a reflective surface layer 1901 over the dielectric layer 906. In fig. 11(G), the reflective surface layer 1901 is patterned and etched to form islands of the reflective surface layer 1901.

FIG. 11(H) shows the deposition of a sacrificial layer 1810 over the reflective surface layer 1901 and the dielectric layer 906. In certain embodiments, the sacrificial layer 1810 comprises molybdenum.

In fig. 11(I), the sacrificial layer 1810 is patterned and etched to form conductive bus holes 1812 and reflective surface layer holes 1814. The conductive bus holes 1812 extend through the sacrificial layer 1810 and the intermediate layer to the first electrode layer 902. The reflective surface layer holes 1814 extend through the sacrificial layer 1810 to the reflective surface layer 1901.

In fig. 11(J), a conductive layer 1816 is deposited over the sacrificial layer 1810 and in the conductive bus holes 1812 and the reflective surface layer holes 1814. The conductive layer 1816 is electrically coupled to the first electrode layer 902 through the conductive bus hole 1812. The conductive layer 1816 is also electrically coupled to the reflective surface layer 1901 through the reflective surface layer holes 1814.

In FIG. 11(K), the conductive layer 1816 is patterned and etched to form a conductive bus structure 1820 and reflective surface layer connectors 1818. The reflective surface layer connector 1818 shown in FIG. 11(K) is electrically isolated from the conductive bus structure 1820.

In fig. 11(L), a dielectric layer 1824 is deposited. In fig. 11(M), the dielectric layer 1824 is patterned and etched to remove portions of the dielectric layer 1824 in the region between the conductive bus structure 1820 and the reflective surface layer connector 1818.

FIG. 11(N) shows the deposition of a sacrificial layer 1826. In FIG. 11(O), the sacrificial layer 1826 is patterned and etched to form landing areas 1828 for a second electrode layer 1302. In fig. 11(P), the second electrode layer 1302 is deposited, patterned and etched. In FIG. 11(Q), the sacrificial layers 1804, 1810, 1826 are removed, thereby forming an interferometric modulator having a bus structure 1820.

The capacitance of the interferometric modulator may be reduced alone or in combination with the above characteristics. Reducing the capacitance of the circuit reduces the RC time constant.

Refresh rate

The time required to charge and discharge the first electrode layer 902 and the second electrode layer 1302 or to change the voltage applied across them affects the refresh rate of the display. For example, shortening the response time of the second electrode layer 1302 to changing the applied voltage may allow the display to be refreshed in a shorter amount of time. A faster refresh display may provide a less noticeable transition between successive frames.

Image resolution

In certain embodiments, gray scale display techniques may be improved using a conductive bus structure that includes complex routing lines arranged along the backside of an interferometric modulator array. Techniques for displaying a gray scale image include subdividing the pixel into a plurality of interferometric modules or smaller sub-pixels. By including more sub-pixels in each pixel, deeper gray levels can be obtained. However, increasing the number of sub-pixels increases the complexity of the circuitry required for the row and column drivers arranged around the display array.

In some embodiments, gray scale display may be improved using a conductive bus structure. In temporal modulation, each interferometric modulator of a gray scale image is pulsed or rapidly refreshed, so that the viewer perceives the display to exhibit a change in brightness level. In certain embodiments, the refresh or modulation rate of an interferometric modulator is increased upon incorporation of one or more of the improvements described above. The refresh rate may be calculated according to the following calculation:

T_line＝T_rc+T_interferometric modulator

wherein T _ line is the time required to update 1 line;

t _ RC is the RC time of the line;

the T _ interferometric modulator is the mechanical response time of the interferometric modulator.

Thus:

T_refresh＝n_rows×T_line

wherein T _ refresh is the time required to update the entire screen;

n _ rows is the number of rows on the display.

Thus:

screen Refresh Rate (Screen Refresh Rate) 1/T _ Refresh

Where the Screen Refresh Rate (Screen Refresh Rate) is the Refresh Rate of the entire display, typically in Hz.

Since T _ rc is shortened using the conductive bus, T _ line is shortened and T _ refresh is shortened. As T refresh is shortened, the screen refresh rate increases and the temporal modulation improves.

Referring back to fig. 7A and 7B, the first electrode layer 902 has an intrinsic conductivity that depends on the material selected for the first electrode layer 902. Using a higher conductivity material for the first electrode layer 902 may reduce the circuit resistance of the interferometric modulator. In certain embodiments, the material selected for the first electrode layer 902 comprises zinc tin oxide (ZnTO) which has a higher conductivity than Indium Tin Oxide (ITO).

The thickness of the first electrode layer 902 may vary. In certain embodiments, the thickness measured in a direction parallel to direction 903 in fig. 7B may be between 300 angstroms and 2,000 angstroms. Other thicknesses of the first electrode layer 902 may also be used.

A material having a low dielectric constant may be selected for the oxide layer or the dielectric material 906 separating the first electrode layer 902 and the second electrode layer 1302. The dielectric material electrically insulates the second electrode layer 1302 from the first electrode layer 902 to store a charge or voltage between the first and second electrode layers. The dielectric layer 906 further allows the voltage or charge to create an electrostatic force that acts on the second electrode layer 1302. A material with a low dielectric constant advantageously reduces the RC time constant of the circuit. For example, a low dielectric constant (K) material may have a lower dielectric constant than a dielectric material fabricated using silicon oxide (3.8). In certain embodiments, the dielectric constant of the dielectric layer 906 is as low as 2.0.

Reduction of capacitance

Different and additional materials may be added to reduce the capacitance of the circuit. In some embodiments, the material selected for the dielectric layer 906 may reduce the capacitance of the circuit. These materials include spin-on glass, silicon nitride, silicon dioxide, aluminum dioxide, and composites of one or more of these materials.

In some embodiments, a second dielectric layer 104 is provided between the metal layer 904 and the first electrode layer 902. As shown in fig. 12, in some embodiments, the second dielectric layer 104 is located between the metal layer 904 and the first electrode layer 902. The additional dielectric layer 104 is added on the basis of the dielectric or oxide layer 906. In such embodiments, the dielectric layer 104 serves to separate the optically functional device from the electrically functional device of the first electrode layer 902. In some embodiments, this configuration does not adversely affect the image quality of the display.

In certain embodiments of interferometric modulators, the decrease in capacitance due to the addition of the second dielectric layer 104 varies with the thickness of the dielectric layer 906 and the second dielectric layer 104 when the reflective surface 901 is in the "near" position. In certain embodiments, the two dielectric layers 906, 104 comprise the same material, while in other embodiments, the two dielectric layers comprise different materials. When the dielectric layer 906 and the second dielectric layer 104 are the same material, the capacitance of an interferometric modulator can be approximated using the following equation.

Capacitance (area of reflective surface 901) x (dielectric constant) x (permittivity constant)/(thickness of top dielectric layer 906 + thickness of bottom dielectric layer 104)

In certain embodiments, the thickness of the dielectric layer 906 may vary. As shown in fig. 13, the dielectric layer 906 includes one or more air gaps 1900 embedded within the dielectric layer 906.

FIGS. 14 and 17 show an array of adjacent interferometric modulators arranged in rows and columns, each modulator having a central portion of the first electrode layer 902 electrically isolated from a peripheral portion of the first electrode layer 902. In some embodiments, a groove within the first electrode layer 902 separates the central portion from the peripheral portion. In certain such embodiments, the area of the portion of the first electrode layer 902 participating in the driving of the interferometric modulator is reduced, thereby reducing the capacitance of the circuit.

In some embodiments, only the peripheral portion may provide an electrically active area of the first electrode layer 902. In some such embodiments, the peripheral portion is electrically connected to a conductive bus structure. In certain other embodiments, only the central portion may provide an electrically active area of the first electrode layer 902. In some such embodiments, the central portion is electrically connected to a conductive bus structure. FIGS. 15 and 16 are cross sections taken from FIG. 14 of two adjacent interferometric modulators having an electrically active central portion 902(a) that is electrically isolated from a peripheral portion 902(b) of the two interferometric modulators.

FIG. 17 shows an array of interferometric modulators 112 arranged in rows and columns, each interferometric modulator 112 having a first electrode layer 902, the column portion 902(c) of the first electrode layer 902 being electrically isolated from the two peripheral portions 902(d), 902(e) of the first electrode layer 902. In certain embodiments, one or more of the peripheral portions 902(c), 902(d), 902(e) may provide an electrically active area of the first electrode layer 902, and one or more of the peripheral portions 902(c), 902(d), 902(e) do not provide an electrically active area of the first electrode layer 902. FIG. 18 is a cross-sectional view of the two interferometric modulators 112 taken from FIG. 17, the interferometric modulator 112 having electrically active peripheral portions 902(d), 902(e) that are electrically isolated from the electrically inactive column portions 902(c) of the two interferometric modulators.

FIGS. 19 and 20 show an embodiment of an interferometric modulator having a first electrode layer 902 comprising more than two electrically active areas 404(a) - (e). The electrically active areas 404(a) - (e) together with the second electrode layer 1302 generate an electrostatic force that pulls the second electrode layer 1302 towards the electrically active areas 404(a) - (e). As the second electrode layer 1302 moves toward the electrically active areas 404(a) - (e), the reflective surface 901 moves a corresponding distance relative to the substrate 1106 and the metal layer 904. Movement of the reflective surface 901 transitions the interferometric modulator to an "ON" or "OFF" state, as described above. By decoupling these two functions, the area of the electrically active portion of the optical layer (or mechanical layer) can be reduced to less than the area of the optical portion of the optical layer (or mechanical layer).

Reducing power consumption

Another benefit of reducing the resistance and capacitance of the circuit is a reduction in power consumption. For example, to charge and discharge an array of interferometric modulators, column and row drivers require power to charge and discharge the interferometric modulators. By reducing the capacitance of the individual interferometric modulators, the row and column drivers may apply a lower voltage when activating each interferometric modulator. In certain embodiments, the reduction in actuation voltage may be achieved by changing the mechanical stiffness of the interferometric module and/or affecting the strength of the electrostatic force within the interferometric modulator.

For example, geometric variations of the interferometric module may reduce the mechanical stiffness of the second electrode layer 1302. Example geometric changes include increasing the spacing between adjacent support posts 202 or changing the shape of the second electrode layer 1302. In some embodiments, increasing the nominal spacing between the support posts 202 increases the flexibility of the attached second electrode layer 1302. This increase in flexibility enables the second electrode layer 1302 and the reflective surface 901 to change states in response to a column or row driver applying a lower activation voltage.

As shown in fig. 21, in some embodiments, the geometry of the second electrode layer 1302 can be altered to simulate a mechanical spring. The mechanical spring design may decouple the reflective surface 901 from the second electrode layer 1302. Tethers 120 constitute a spring portion as the reflective surface 901 moves up and down. In some embodiments, the reflective surface 901 comprises a portion of a rigid body (e.g., a reflective surface layer). In this way, tethers 120 and reflective surface 901 are decoupled in that movement of one does not substantially affect the other.

The material selection of the second electrode layer 1302 can affect the activation voltage. Selecting a more compliant material increases the flexibility of the second electrode layer 1302. In this way, in some embodiments, the row and column drivers apply a lower actuation voltage and still achieve the desired reflective surface layer displacement. In some embodiments, the second electrode layer 1302 comprises a more compliant material (e.g., aluminum) to enable the reflective surface layer 901 to respond to a lower activation voltage than the second electrode layer 1302 comprising nickel. Other example materials that may be used for the second electrode layer 1302 include, but are not limited to, chromium, copper, composites made of oxides and metals (e.g., silicon nitride clad with aluminum), metal-reinforced organic films (e.g., photoresist plated with any of the metal examples). The mechanical stiffness of the second electrode layer 1302 can be further reduced by reducing the thickness of the second electrode layer 1302. In some embodiments, the second electrode layer 1302 has a thickness of about 500 angstroms.

In some embodiments, another technique for reducing the activation voltage is to vary the strength of the electric field formed between the first electrode layer 902 and the second electrode layer 1302. This technique increases the electric field strength by patterning the first electrode layer 902 to reduce the size of the electrically active area. In this manner, the area of the interferometric modulator forming the electrically active portion may be reduced. Patterning the electrode by narrowing the electrically active area as shown in fig. 14-18 has the effect of increasing the actuation voltage, assuming all other parameters remain the same.

In certain embodiments, the activation voltage may be further reduced by selecting a material for the one or more dielectric layers 906 that has a higher dielectric constant. First, the relationship between the dielectric constant and the excitation voltage is:

V～1/(K^1/2)

the voltage is inversely proportional to the square root of the dielectric constant. Therefore, as the constant increases, the voltage required to pull the second electrode layer 1302 toward the first electrode layer 902 decreases. The material having a higher dielectric constant may increase the electrostatic attraction force generated between the first electrode layer and the second electrode layer.

One possible pixel configuration 602 for some embodiments is shown in fig. 22. This view is seen by an observer from the front side of the substrate 106 and consists of nine elements, three for each of the colors red, green and blue. As shown, modulators 1400(a), 1400(b), 1400(c) may correspond to red, 1400(d), 1400(e), 1400(f) may correspond to green, and 1400(g), 1400(h), 1400(i) may correspond to blue. In the embodiment schematically illustrated in FIG. 22, the array of interferometric modulators is arranged in an N matrix to provide an image display surface.

In certain embodiments, three different colors (red, green, and blue) can be obtained by varying the distance between the mirror and the optical stack. When a voltage is applied across the modulators, all of the modulators may move a same distance or different distances toward the electrodes. In fact, all nine modulators may traverse the entire cavity and move to a close position where they are in direct contact with the substrate 106. The dimensions of the cavity in the at rest state are shown as vertical dimensions 1500, 1600, and 1700 in fig. 22, 23, and 25, respectively. In one embodiment, vertical dimensions 1500, 1600, and 1700 are 4000 angstroms, 3000 angstroms, and 2000 angstroms, respectively.

Interferometric modulators are small, typically 25-60 microns (400-1,000 dots per inch) on one side. Thus, in certain embodiments, multiple interferometric modulator elements may be combined and driven together as a pixel or sub-pixel in a monochrome, color, or grayscale display. For example, each interferometric modulator may correspond to a display pixel in a monochrome display. For color or gray scale displays, the color or intensity of each interferometric modulator in some embodiments depends on the size of the air gap between the optical and mechanical layers. Multiple sub-elements with different intensities or colors may form a gray scale or color pixel. To fabricate a flat panel display, a large array of interferometric modulators (e.g., 5 inch full color VGA) is fabricated in a desired format.

In certain embodiments, the reflective surface 901 of the modulator 1400(a) may have a back support, a flex layer, and post interfaces designed to stabilize the reflective surface 901 at a distance 1500. In some embodiments, the reflective surface 901 of the modulator 1400(d) may have back supports, a flex layer, and post interfaces designed to stabilize the reflective surface layer at a distance 1600, which is less than distance 1500. Finally, in some embodiments, the reflective surface layer 901 of the modulator 1400(g) may have a back support, a flex layer, and post interfaces designed to stabilize the reflective surface layer at a distance 1700 that is less than 1600 a. In this manner, the result of controlling the mechanical properties and/or physical limitations of the support in some embodiments is the formation of three different cavity sizes, and thus three different pixel colors.

Alternatively, different characteristics of the flexible layer and the support may be manipulated to cause the reflective surface layer 901 to move different distances when the same voltage is applied. Alternatively, all modulators may have the same structure but with different voltages applied to achieve different colors.

FIGS. 26A and 26B are system block diagrams illustrating one embodiment of a display device 2040. The display device 2040 can be, for example, a cellular or mobile telephone. However, the same components of display device 2040, or slight variations thereof, are also illustrative of various types of display devices, such as televisions and portable media players.

The display device 2040 includes a housing 2041, a display 2030, an antenna 2043, a speaker 2045, an input device 2048, and a microphone 2046. The housing 2041 is typically made by any of a number of manufacturing processes well known to those skilled in the art, including injection molding and vacuum forming. Further, the housing 2041 may be made from any of a wide variety of materials, including but not limited to plastic, metal, glass, rubber, and ceramic, or a combination thereof. In one embodiment, the housing 2041 includes removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.

The display 2030 of exemplary display device 2040 may be any of a wide variety of displays, including a bi-stable display as described herein. In other embodiments, the display 2030 comprises a flat panel display, such as a plasma, EL, OLED, STN LCD, or TFT LCD as described above, or a non-flat panel display, such as a CRT or other tube device, as is well known to those skilled in the art. However, for purposes of describing the present embodiment, the display 2030 includes an interferometric modulator display, as described herein.

FIG. 26B schematically illustrates components in one embodiment of an exemplary display device 2040. The exemplary display device 2040 shown includes a housing 2041 and can include other components at least partially enclosed therein. For example, in one embodiment, the exemplary display device 2040 includes a network interface 2027, the network interface 2027 including an antenna 2043 coupled to a transceiver 2047. The transceiver 2047 is connected to the processor 2021, which processor 2021 is in turn connected to conditioning hardware 2052. Conditioning hardware 2052 may be configured to condition (e.g., filter) a signal. Conditioning hardware 2052 is coupled to a speaker 2045 and a microphone 2046. The processor 2021 is also connected to an input device 2048 and a driver controller 2029. The driver controller 2029 is coupled to a frame buffer 2028 and to the array driver 2022, which in turn is coupled to a display array 2030. A power supply 2050 provides power to all components as required by the design of the particular exemplary display device 2040.

The network interface 2027 includes the antenna 2043 and the transceiver 2047 so that the exemplary display device 2040 can communicate with one or more devices over a network. In one embodiment, the network interface 2027 may also have some processing capabilities to reduce requirements for the processor 2021. The antenna 2043 is any antenna known to those skilled in the art for transmitting and receiving signals. In one embodiment, the antenna transmits and receives RF signals according to the IEEE802.11 standard, including IEEE802.11 (a), (b), or (g). In another embodiment, the antenna transmits and receives RF signals according to the Bluetooth (BLUETOOTH) standard. In the case of a cellular telephone, the antenna is designed to receive CDMA, GSM, AMPS or other conventional signals used to communicate in a wireless cellular telephone network. The transceiver 2047 pre-processes the signals received from the antenna 2043 so that they may be received by and further processed by the processor 2021. The transceiver 2047 also processes signals received from the processor 2021 so that they may be transmitted from the exemplary display device 2040 via the antenna 2043.

In an alternative embodiment, the transceiver 2047 may be replaced by a receiver. In yet another alternative embodiment, the network interface 2027 can be replaced by an image source, which can store or generate image data to be sent to the processor 2021. For example, the image source can be a Digital Video Disc (DVD) or a hard-disc drive that contains image data, or a software module that generates image data.

The processor 2021 generally controls the overall operation of the exemplary display device 2040. The processor 2021 receives data, such as compressed image data, from the network interface 2027 or an image source and processes the data into raw image data or into a format that is readily processed into raw image data. The processor 2021 then sends the processed data to the driver controller 2029 or to frame buffer 2028 for storage. Raw data generally refers to information that can identify the image characteristics at each location within an image. For example, the image characteristics may include color, saturation, and gray-scale level.

In one embodiment, the processor 2021 includes a microcontroller, CPU, or logic unit to control operation of the exemplary display device 2040. Conditioning hardware 2052 typically includes amplifiers and filters for sending signals to the speaker 2045, and for receiving signals from the microphone 2046. Conditioning hardware 2052 may be discrete components within the exemplary display device 2040 or may be incorporated within the processor 2021 or other components.

The driver controller 2029 takes the raw image data generated by the processor 2021 either directly from the processor 2021 or from the frame buffer 2028 and reformats the raw image data appropriately for high speed transmission to the array driver 2022. In particular, the driver controller 2029 reformats the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning the display array 2030. The driver controller 2029 then sends the formatted information to the array driver 2022. Although a driver controller 2029, such as an LCD controller, is typically associated with the system processor 2021 as a stand-alone Integrated Circuit (IC), such controllers may be implemented in a number of ways. It may be embedded in the processor 2021 as hardware, embedded in the processor 2021 as software, or fully integrated in hardware with the array driver 2022.

Typically, the array driver 2022 receives the formatted information from the driver controller 2029 and reformats the video data into a parallel set of waveforms that can be applied many times per second to the hundreds and sometimes thousands of leads coming from the display's x-y array of pixels.

In one embodiment, the driver controller 2029, array driver 2022, and display array 2030 are appropriate for any of the types of displays described herein. For example, in one embodiment, the driver controller 2029 is a conventional display controller or a bi-stable display controller (e.g., an interferometric modulator controller). In another embodiment, the array driver 2022 is a conventional driver or a bi-stable display driver (e.g., an interferometric modulator display). In one embodiment, a driver controller 2029 is integrated with the array driver 2022. Such embodiments are common in highly integrated systems such as cellular phones, watches, and other small area displays. In yet another embodiment, the display array 2030 is a typical display array or a bi-stable display array (e.g., a display including an array of interferometric modulators).

The input device 2048 enables a user to control the operation of the exemplary display device 2040. In one embodiment, input device 2048 includes a keypad (e.g., a QWERTY keyboard or a telephone keypad), a button, a switch, a touch-sensitive screen, a pressure-or heat-sensitive membrane. In one embodiment, the microphone 2046 is an input device for the exemplary display device 2040. When the microphone 2046 is used to input data to the device, voice commands may be provided by a user to control operation of the exemplary display device 2040.

The power supply 2050 can include a variety of energy storage devices, as are well known in the art. For example, in one embodiment, power supply 2050 is a rechargeable battery, such as a nickel-cadmium battery or a lithium ion battery. In another embodiment, power supply 2050 is a renewable energy source, a capacitor, or a solar cell, including plastic solar cells and solar-cell paint. In another embodiment, power supply 2050 is configured to receive power from a wall outlet.

In some implementations control programmability resides, as described above, in a driver controller, which can be located in several places in the electronic display system. In some cases, control programmability exists in the array driver 2022. Those skilled in the art will recognize that the above-described optimization may be implemented in any number of hardware and/or software components and in different configurations.

While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the art without departing from the spirit of the invention. Methods of combining the above-described features with interferometric modulators will be readily apparent to those of ordinary skill in the art. In addition, one or more of such features can be modified to be suitable for use with any of the embodiments and other interferometric modulator configurations. It will be recognized that the present invention may be embodied within a form that does not provide all of the features and benefits set forth herein, as some features may be used or practiced separately from others.

Claims (39)

1. A device for use in a microelectromechanical system, comprising:

a substrate;

an array of microelectromechanical devices formed on the substrate and arranged in rows and columns;

a first electrode layer on the substrate, the first electrode layer electrically connecting the micro-electromechanical devices in a row;

a second electrode layer on the substrate, the second electrode layer electrically connecting the micro-electromechanical devices in a column;

a reflective surface substantially parallel to the first electrode layer and coupled to the second electrode layer, the reflective surface movable in a direction substantially perpendicular to the reflective surface, the reflective surface movable between a first position a first distance from the first electrode layer and a second position a second distance from the first electrode layer; and

a conductive bus layer electrically coupled to the first or second electrode layers at two or more locations, wherein a bond between the conductive bus layer and the electrode layers to which it is coupled provides an electrical path between row drive electronics of the array and the first electrode layer or between column drive electronics of the array and the second electrode layer, the electrical path having a lower resistance than if the micro-electromechanical devices in a row or a column were connected only through the first or second electrode layers, wherein the reflective surface moves between the first position and the second position in response to a voltage applied across the conductive bus layer.

2. The device of claim 1, wherein the conductive bus layer is electrically connected to the first electrode layer.

3. The device of claim 1, wherein the conductive bus layer is electrically connected to the second electrode layer.

4. The device of claim 1, wherein the conductive bus layer is positioned over the second electrode layer.

5. The device of claim 1, wherein the conductive bus layer is positioned adjacent to the first electrode layer.

6. The device of claim 1, wherein the second electrode layer comprises the reflective surface.

7. The device of claim 1, further comprising a reflective layer coupled to the second electrode layer, wherein the reflective layer comprises the reflective surface.

8. The device of claim 1, wherein the conductive bus layer comprises a conductive metal.

9. The device of claim 1, wherein the conductive bus layer comprises a composite alloy.

10. The apparatus of claim 1, wherein the conductive bus layer comprises aluminum, chromium, titanium, or nickel.

11. The device of claim 1, wherein the conductive bus layer has a thickness between 0.1 and 2 microns.

12. The device of claim 1, wherein the conductive bus layer has a width between 4 and 10 microns.

13. The device of claim 1, wherein the first electrode layer has a thickness between 300 angstroms and 2,000 angstroms.

14. The device of claim 1, further comprising:

a display;

a processor in electrical communication with the display, the processor configured to process image data; and

a storage device in electrical communication with the processor.

15. The device of claim 14, further comprising:

a drive circuit configured to send at least one signal to the display.

16. The device of claim 15, further comprising:

a controller configured to send at least a portion of the image data to the drive circuit.

17. The device of claim 14, further comprising:

an image source module configured to send the image data to the processor.

18. The device of claim 17, wherein said image source module comprises at least one of a receiver, transceiver, and transmitter.

19. The device of claim 14, further comprising:

an input device configured to receive input data and to communicate the input data to the processor.

20. The device of claim 1, wherein the conductive bus layer is configured to reduce a resistance-capacitance time constant between a driver and a device having serially connected electrode layers relative to the device.

21. The device of claim 1, wherein the conductive bus layer is configured to avoid interference with an optical performance of the device.

22. The device of claim 1, wherein the conductive bus layer is electrically coupled to the first electrode layers of one row of interferometric modulators and the conductive bus layer is electrically isolated from the first electrode layers of other rows of interferometric modulators.

23. A method of fabricating a light modulator, comprising:

providing a substrate;

providing a first electrode layer on the substrate, the first electrode layer electrically connecting the micro-electromechanical devices in a row;

providing a second electrode layer on the substrate, the second electrode layer electrically connecting the micro-electromechanical devices in a column;

providing a reflective surface substantially parallel to the first electrode layer and coupled to the second electrode layer, the reflective surface being movable in a direction substantially perpendicular to the reflective surface, the reflective surface being movable between a first position and a second position, the first position being a first distance from the first electrode layer, the second position being a second distance from the first electrode layer; and

providing a conductive bus layer electrically coupled at two or more locations to the first or second electrode layers, wherein the bonding between the conductive bus layer and the electrode layers to which it is coupled provides an electrical path between the array of row drive electronics and the first electrode layer or between the array of column drive electronics and the second electrode layer that has a lower resistance than if the micro-electromechanical devices in a row or in a column were connected only through the first or second electrode layers, wherein the reflective surface moves between the first position and the second position in response to a voltage applied across the conductive bus layer.

24. The method of claim 23, wherein the conductive bus layer is electrically coupled to the first electrode layer.

25. The method of claim 23, wherein the conductive bus layer is electrically coupled to the second electrode layer.

26. The method of claim 23, wherein the conductive bus layer is positioned over the second electrode layer.

27. The method of claim 23, wherein the conductive bus layer is positioned adjacent to the first electrode layer.

28. The method of claim 23, wherein the reflective surface is located on the second electrode layer.

29. The method of claim 23, further comprising providing a reflective layer coupled to the second electrode layer, wherein the reflective layer comprises the reflective surface.

30. A device for use in a microelectromechanical system, comprising:

means for supporting an interferometric modulator;

means for conducting a first electrical signal over the support means, the means for conducting a first electrical signal electrically connecting the micro-electromechanical devices in a row;

means for conducting a second electrical signal over the support means, the means for conducting a second electrical signal electrically connecting the microelectromechanical devices in a column;

means for reflecting light substantially parallel to said means for conducting said first electrical signal and coupled to said means for conducting said second electrical signal, said means for reflecting light being movable in a direction substantially perpendicular to said means for reflecting light and between a first position at a first distance from said means for conducting said first electrical signal and a second position at a second distance from said means for conducting said first electrical signal; and

means for electrically coupling to the means for conducting the first electrical signal or the means for conducting the second electrical signal at two or more locations, wherein the coupling means and the conductive means to which it is coupled provide an electrical path between row drive electronics of the array and the means for conducting a first electrical signal or between column drive electronics of the array and the means for conducting a second electrical signal, the electrical path has a lower resistance than if the micro-electromechanical devices in a row or the micro-electromechanical devices in a column were connected only by the means for conducting the first electrical signal or the means for conducting the second electrical signal, wherein the means for reflecting light moves between the first position and the second position in response to a voltage applied to the coupling means.

31. The apparatus of claim 30, wherein the coupling means is electrically connected to the means for conducting the first electrical signal.

32. The apparatus of claim 30, wherein the coupling means is electrically connected to the means for conducting the second electrical signal.

33. The apparatus of claim 30, wherein the coupling means is positioned above the means for conducting the second electrical signal.

34. The apparatus of claim 30, wherein the coupling means is positioned adjacent to the means for conducting the first electrical signal.

35. The apparatus of claim 30, wherein the support member comprises a substrate.

36. The apparatus of claim 30, wherein the means for conducting the first electrical signal comprises an electrode.

37. The apparatus of claim 30, wherein the means for conducting the second electrical signal comprises an electrode.

38. The apparatus of claim 30, wherein the reflective member comprises a reflective surface.

39. The apparatus of claim 30, wherein the coupling member comprises a conductive bus.