HK1084507B - Chip-scale schottky device - Google Patents

Description

Chip-scale schottky device

Technical Field

The invention relates to a semiconductor device, in particular to a chip-scale Schottky device.

Background

Conventional semiconductor devices, such as Surface Mount Devices (SMDs), typically include a semiconductor die, a lead frame having external leads, and a housing that may be molded from a plastic material. In these conventional devices, the external leads serve not only to support the device, but also to provide electrical connections to the semiconductor die, while the casing provides protection to the semiconductor die by encapsulating it. Of course, to package a semiconductor die, the housing itself must be larger than the semiconductor die. At the same time, the external leads typically extend laterally from the case, further increasing the area occupied by the device.

As the demand for higher performance portable devices (e.g., cellular phones, portable computers, personal digital assistants, etc.) increases, the demand for semiconductor devices that can provide high power densities while occupying less space on circuit boards is increasing in order to improve performance while reducing size. To fulfill the demand for miniaturization, chip scale devices for semiconductor switching dies (switching die) such as MOSFETs (metal oxide semiconductor field effect transistors) have been proposed. Chip scale packages have or approximate the size of a semiconductor die and thus occupy less area on a circuit board than conventional semiconductor packages. To ensure that the chip scale device has, or approximately has, the dimensions of a semiconductor die, the electrodes of the die are provided on only one surface so that the die can be connected to conductive pads (conductive pads) of, for example, a printed circuit board, by, for example, appropriately placed solder bumps. This structure is conventionally referred to as a flip chip. An example of a flip chip device is disclosed in U.S. patent No. 4,250,520. However, the flip chip device proposed by U.S. patent No. 4,250,520 is not a chip scale device because the substrate on which the semiconductor die is formed occupies a relatively larger area than the die itself.

Schottky diodes are components that are widely used in electronic circuits. It is therefore desirable to have a chip-scale schottky package in order to achieve miniaturization of electronic circuits.

Disclosure of Invention

A schottky diode according to the prior art includes an anode disposed on one major surface of a die and a cathode disposed on an opposite major surface of the die. Therefore, in order to package a conventional schottky diode, a lead structure must be provided to fit the surface mount package.

According to one aspect of the present invention, a schottky device is provided that includes a schottky die having a first portion that is low doped with a dopant of a first conductivity type and a second portion that is highly doped with a dopant of the first conductivity type. A first portion of the die is disposed over a second portion thereof and includes a major surface on which the schottky barrier layer is disposed. An electrode, which may be an anode, is disposed over and electrically connected to the schottky barrier layer. The first portion of the die further includes a sinker (sinker) extending from the major surface of the first portion toward the second portion. The sinker is highly doped with a dopant of the first conductivity type. An electrode, which may be a cathode, is disposed over and electrically connected to the sinker region. Further, a passivation layer is disposed over the cathode and the anode. The solder bumps are connected to the cathode and anode through respective openings in the passivation layer.

According to one embodiment of the invention, the anode electrode covers a substantial extent of the main surface of the first portion of the die and surrounds at least one cathode electrode also arranged on the same main surface of the die. In this embodiment, a guard ring is formed in the first portion of the die around the perimeter of the cathode electrode. The guard ring is a diffusion region of opposite polarity to the polarity of the first and second portions of the die.

According to another embodiment of the invention, the anode covers a substantial extent of the main surface of the first portion of the die and is surrounded by at least one cathode also arranged on the same main surface of the die. In this embodiment, a guard ring is formed in the first portion of the die around the perimeter of the anode electrode. The guard ring is a diffusion region of opposite polarity to the polarity of the first and second portions of the die.

In accordance with yet another embodiment of the present invention, the semiconductor die includes side edges that define lateral boundaries for a semiconductor device package.

Other features and advantages of the present invention will become more apparent from the following description of the present invention with reference to the accompanying drawings.

Brief description of the drawings

Fig. 1 is a perspective view of a device according to a first embodiment of the invention;

fig. 2 is a top view of a device according to a first embodiment of the invention;

FIG. 3 is a cross-sectional view taken along line 3-3 of FIG. 2, viewed in the direction of the arrows;

FIG. 4 shows a device according to the invention mounted on a printed circuit board;

fig. 5 shows a top view of a device according to a second embodiment of the invention;

fig. 6 shows a top view of a device according to a third embodiment of the invention;

fig. 7 shows a top view of a device according to a fourth embodiment of the invention;

FIG. 8 graphically depicts forward voltage (V)_F) As a function of charge in the anode region;

fig. 9 shows, in diagrammatic form, V of an example of a device according to the embodiment shown in fig. 1 to 7_FExperimental measurement results of (a);

FIG. 10 shows V of an example of a device according to the embodiment shown in FIGS. 1-7_FAnd a plot of experimental measurements of leakage current.

Detailed description of the drawings

Fig. 1 shows a first embodiment of a device 10 according to the invention. Device 10 is preferably a schottky diode having two cathodes 12 and one anode 14, wherein the cathodes and the anode are disposed on only one major surface 16 of die 20. In the first embodiment according to the present invention, two solder bumps 18 are provided on the anode 14, and the solder bumps 18 are disposed on and electrically connected to the respective cathodes 12. Preferably, the solder bumps 18 are spaced apart from each other and arranged to form a support structure when the device 10 is mounted on a circuit board as described below.

Referring to fig. 2 and 3, anode 14 is disposed over and electrically connected to schottky barrier layer 22. A schottky barrier layer 22 is disposed over and ohmically connected to the major surface 16 of the die 20. The die 20 includes a first portion 24 disposed over a second portion 26. First portion 24 of die 20 is low doped and second portion 26 is highly doped. In a preferred embodiment of the present invention, second portion 26 of die 20 is a silicon substrate highly doped with N-type dopants, and first portion 24 of die 20 is an epitaxially grown silicon layer lowly doped with N-type dopants.

Cathode electrode 12 in device 10 is also ohmically connected to major surface 16 of die 20. A sinker 28 extends between cathode 12 and second portion 26 of die 20. Sinker 28 is a highly doped region that is doped with an N-type dopant in the preferred embodiment.

The device 10 further includes a passivation layer 30. A passivation layer 30 is disposed over cathode 12 and anode 14. The passivation layer 30 includes openings through which the solder bumps 18 are connected to the respective electrodes.

In the embodiment shown in fig. 2 and 3, a first guard ring 32 is disposed around the perimeter of cathode electrode 12 in first portion 24 of die 20. Likewise, a second guard ring 34 is disposed around the outer periphery of the anode electrode 14 in the first portion 24 of the die 20. Guard rings 32 and 34 are diffusions of dopants of opposite conductivity to the dopants in first portion 24 of die 20 and thus are P-type in this preferred embodiment of the invention. Each cathode 12 is insulated from the anode 14 by a combination of a gap 36 and an insulating layer 38 disposed along its periphery.

In this preferred embodiment of the invention, the schottky barrier layer 22 is comprised of molybdenum, while the cathode 12 and anode 14 are comprised of a suitable aluminum or aluminum-silicon alloy. Of course, any other suitable material may be used to compose the schottky barrier layer 22, the cathode 12, and the anode 14. The schottky barrier layer 22 may be composed of, for example, vanadium or palladium (palladium). Also, in order to improve adhesion (adhesion), it is preferable that a nickel film 40(nickel plating) be disposed between the solder bump 18 and the electrode in connection therewith if the electrode is composed of, for example, an aluminum silicon alloy. The passivation layer 30 is preferably composed of silicon nitride or other suitable material.

Fig. 4 shows device 10 mounted on circuit board 42. The circuit board 42 includes conductive pads 44, and the solder bumps 18 are connected to the conductive pads 44. When device 10 is in operation, current flows between cathode 12 and anode 14 through the body of die 20.

Fig. 5, 6 and 7 show top views of devices 46, 48 and 50 according to second, third and fourth embodiments of the present invention, respectively. Referring first to fig. 5, a device 46 according to a second embodiment of the present invention includes all of the features of the device 10 according to the first embodiment except that the device 46 does not have two cathodes, the device 46 including a single cathode 12 surrounding an anode 14.

Thus, in accordance with one aspect of the invention, the respective areas of anode 14 and cathode 12 may be varied to alter the operating characteristics of the device to achieve the desired performance of the device. For example, V can be made by varying the respective areas of the cathode and anode in a device according to the invention_FThe forward voltage is optimized. FIG. 8 shows V as the anode region covers more of the active region_FThis is a desirable result. According to fig. 8, V is when the anode area is about 80% of the active region_FAt a minimum.

Fig. 9 graphically illustrates the results of electrical testing of 60 mil devices 10, 46, 48 and 50 in accordance with various examples of the first, second, third and fourth embodiments of the present invention as compared to standard 60 mil and 36 mil devices. As shown in fig. 9, the device according to the invention exhibits a V_FThe value is comparable to 36 mil standard device, and has slightly higher V compared with 60 mil standard device_FThe value is obtained.

Although increased size can achieve the same performance as a standard 36 mil device, a device in accordance with the present invention will eventually occupy less space on the circuit board, as shown by the data presented in table 1.

Flip chip and surface mount

Referring to fig. 10, experimental results show that the leakage currents of the devices 10, 46, 48 and 50 according to the first, second, third and fourth embodiments of the present invention fall within the same general range. However, as shown in table 2, experimental measurements show that the device 10 according to the first embodiment of the present invention exhibits a higher avalanche energy (avalanche energy) than the other embodiments.

Avalanche testing

Average

39,6

35,3

34,4

46,8

TABLE 2

A device according to the invention may be made by depositing or growing an oxide or other insulating layer on a major surface of a die. At least one window may then be opened in the insulating layer to expose selected areas of the major surface over which the insulating layer is disposed. Sinker 28 may then be formed in first portion 24 of die 20 by implantation and subsequent diffusion driving. Next, a second window may be opened in the insulating layer to expose a preselected area of the major surface of the die 20. A schottky barrier layer 22 may then be deposited on the selected areas exposed by the second window. The cathode 12 and anode 14 are then formed, followed by the passivation layer 30. Next, an opening that exposes portions of the cathode 12 and the anode 14 is formed above the cathode 12 and the anode 14. A nickel film is then applied to the portions of cathode 12 and anode 14 exposed by the openings in passivation layer 30. Next, solder bumps 18 are formed in the openings in the passivation layer 30.

Preferably, a plurality of devices according to the present invention are formed in a single wafer. The wafer is diced (dice) after the formation of the solder bumps 18 to obtain a plurality of devices according to the present invention. Since the electrical contacts of the anode and the cathode are arranged on a common surface in the device according to the invention, no backgrinding or back metal sputtering is necessary as is the case for vertically conducting devices.

While the present invention has been described with respect to specific embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

Claims (14)

1. A semiconductor device package comprising:

a semiconductor die having a first major surface;

a Schottky structure disposed over and in ohmic contact with a portion of the first major surface;

a first electrode electrically connected to the schottky structure;

a second electrode electrically connected to the first major surface of the semiconductor die but electrically insulated from the first electrode;

a plurality of solder pads, at least one of the solder pads connected to one of the first electrode and the second electrode;

wherein the first electrode surrounds the second electrode or the second electrode surrounds the first electrode, and a guard ring is formed in the semiconductor die at least partially disposed between the first electrode and the second electrode.

2. The semiconductor device package of claim 1, further comprising a passivation layer disposed over the first and second electrodes, wherein the plurality of solder bumps are disposed over a free surface of the passivation layer and extend through openings in the passivation layer to the first and second electrodes.

3. The semiconductor device package of claim 1, wherein the schottky structure is a molybdenum layer.

4. The semiconductor device package of claim 1, wherein the first electrode is an anode and the second electrode is a cathode.

5. The semiconductor device package of claim 1, wherein the semiconductor die comprises a first low-doped portion and a second high-doped portion, wherein the first low-doped portion is disposed above the second high-doped portion, and further comprising a sinker extending from a major surface of the first low-doped portion toward the second high-doped portion, wherein the second electrode is electrically connected to the sinker.

6. The semiconductor device package of claim 5, wherein the sinker comprises a highly doped region within the first lowly doped portion.

7. The semiconductor device package of claim 1, further comprising a nickel layer disposed between at least one of the plurality of solder bumps and its associated electrode.

8. The semiconductor device package of claim 1, wherein the schottky structure comprises a palladium layer.

9. The semiconductor device package of claim 1, wherein the schottky structure comprises a layer of vanadium.

10. The semiconductor device package of claim 1, wherein the first electrode comprises aluminum.

11. The semiconductor device package of claim 1, wherein the second electrode comprises aluminum.

12. The semiconductor device package of claim 2, wherein the passivation layer comprises silicon nitride.

13. The semiconductor device package of claim 1, wherein the semiconductor die comprises a second major surface opposite the first major surface, the second major surface being free of any electrical connections.

14. The semiconductor device package of claim 1, wherein the semiconductor die comprises side edges that define lateral boundaries for the semiconductor device package.