HK1083930A - A method for reading a passive matrix-addressable device and a device for performing the method - Google Patents

Description

Method for reading a passive matrix-addressable device and device for performing the method

Technical Field

The invention relates to a method for reading a passive matrix-addressable device, in particular a memory device or a sensor device having individually addressable cells for storing a logic value given by a charge value set in the cell, wherein the device comprises an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the device comprises a first and a second electrode arranged by parallel electrodes forming word lines and bit lines, respectively, in the device, wherein the word line electrode and the bit line electrode are arranged perpendicular to each other and contact the polarizable material at their opposing surfaces, such that each cell of the device includes a capacitor-like structure defined at a volume of polarizable material in or at the intersection between the word line and the bit line, wherein the cell is addressed by applying a coercive voltage V between the word line and the bit line of the addressed cell that is greater than the polarizable material._cVoltage V of_sThe cell in the device can be set to one of two polarization states or switched between these polarization states, wherein each bit line is connected to a detection means, wherein the method comprises a voltage pulse protocol with a read cycle, wherein during the read cycle each detection means detects the charge flowing between its associated bit line and the cells connected to the bit line; and the invention relates to a device for performing a read of a passive matrix-addressable device, in particular a memory device or a sensor device having individually addressable cells for storing a logic value given by a charge value set in the cell, wherein the device comprises an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the device comprises a memory cell arranged with parallel electrodes forming word lines and bit lines, respectively, in the deviceFirst and second electrodes disposed in a manner such that the word line electrode and the bit line electrode are disposed perpendicular to each other and contact the polarizable material at their opposing surfaces, such that each cell of the device includes a capacitor-like structure defined by a volume of polarizable material in or at an intersection between the word line and the bit line, wherein the cell is addressed by applying a coercive voltage V between the word line and the bit line that is greater than the polarizable material_cVoltage V of_sThe cell in the device can be set to one of two polarization states or switched between these polarization states, wherein each bit line is connected to a detection means, wherein the method comprises a voltage pulse protocol with a read cycle, wherein during the read cycle each detection means detects the charge flowing between its associated bit line and the cells connected to the bit line.

As mentioned above, the invention relates in particular to a method for reading all cells connected between a selected word line and parallel intersecting bit lines, so-called full row reading. This is known from other us patent No.6157578, which relates to a method and device for accessing rows of data in a semiconductor memory device in a single operation, in other words in parallel.

Background

As an example of the state of the art concerning active matrix addressable devices, reference will be made to IEEE proceedings 5/2000, volume 88, section 5, page 667-689 by "surfey of circuit innovations in Ferroelectric Random-access Memories" of a.sheikholslami and p.glenn Gulak, which paper discloses active memory devices and their addressing methods, and in particular a class of active Ferroelectric memory devices, in which each cell is built as a capacitor-like structure connected in series with a so-called access transistor controlling the access to the capacitor. The material in the capacitor-like structure is a ferroelectric material that can be polarized and exhibits hysteresis. Such an active memory cell connected to a transistor is called a 1T-1C cell, but such an active memory device may also comprise two transistors and two capacitors, etc. It is also possible that a larger number of n capacitors are connected to a single transistor, so that the active memory cell is represented as a 1T-nC type cell. When the latter are not addressed, it is desirable to disconnect the capacitor of the memory cell and thus not be affected by matrix parasitic capacitances which cause voltage disturbances and sneak currents when addressing other cells of the matrix.

Thus, matrix-addressable devices with active cells have obvious advantages but also disadvantages. The use of access transistors or switching transistors correspondingly increases power consumption and leads to lower integration density, among other things, reducing storage density in memory devices.

In a passive matrix-addressable memory device, all cells, e.g. memory cells of a memory matrix, will always be connected in a network formed by electrodes, word lines and bit lines, usually called matrix, each cell being arranged at or between a word line or an intersecting bit line and thus forming a capacitor structure. Such a single passive cell is addressed by applying a voltage on said word line and/or bit line such that a potential difference is obtained over the memory cell between these electrodes. Depending on the potential difference, the polarization state of the cell can be influenced, for example by providing a permanent positive polarization in the cell or a permanent negative polarization in the cell. By applying voltages corresponding to the voltage difference V_sA sufficiently large potential difference which must be greater than the coercive voltage V of the ferroelectric material_cIt is possible to change from one polarization state to another.

Writing of data in such a cell involves polarizing the original, i.e. unpolarized cell, to one of two permanent polarization states, or by switching it from a permanent positive polarization state to a permanent negative polarization state or reversing the polarization characteristics already set in the cell, or vice versa. In reading, the polarization state of the cell is detected in a corresponding manner, e.g. by setting the word line to a voltage level V_sWhile simultaneously connecting the corresponding bit linesHeld at zero potential. Depending on the polarization state, whether the polarization characteristics of the cell are maintained or switched, either a low charge current or a high charge current is generated on the bit line. The charging current is detected as a current value, and the logic state of the cell may be read as logic 0 or logic 1, respectively, for example. This practically already indicated only feasible read-out method is destructive, in the sense that the original data content stored in a cell is destroyed when the polarization state of the cell is switched to a polarization state of opposite polarity. The above provides a reliable detection of the logic value, but it also means that the initial logic value in this state has to be rewritten to the cell by performing a write operation as described above.

Relatively large potential differences are required both in writing cells and in reading from cells, and in passive matrices such addressing of individual cells generates disturbing voltages and sneak currents in the passive network of cells and thus influences their polarization state. This problem is exacerbated by disturbances in passive matrix-addressable networks and further exacerbated for large matrices, such as matrices having millions of cells, if several cells, such as all cells connected to a particular word line, are addressed in parallel.

Disclosure of Invention

It is therefore an object of the present invention to avoid the problems arising from the non-destructive readout of cells in passive matrix-addressable devices, and in particular to eliminate disturbing voltages and sneak currents affecting unaddressed cells in passive matrix-addressable devices during read operations. Further, it is an object of the invention to perform the reading of several cells in parallel, in particular to perform a so-called full row read, thus enabling the reading of all cells connected to a word line in parallel with minimal disturbance of the remaining unaddressed cells in a passive matrix-addressable device.

Finally, it is an object of the present invention to avoid the corresponding problems associated with such cells being written into a passive matrix-addressable network, in particular subsequently rewritten after a read operation in order to read the cells, so that the initial polarization state is restored or the stored logic or data values are reset to their initial values prior to the reading of these cells.

The above objects and other features and advantages are obtained according to the present invention by a method, characterized in that: the potentials on all word lines and bit lines are controlled in a time-adjusted manner according to a voltage pulse protocol comprising a clock sequence of the potentials on all word lines and bit lines, whereby a word line is activated at least during a part of a read cycle by an applied potential corresponding at least to a voltage V relative to the potentials of all intersecting bit lines_sAnd the logic value stored in each cell connected to the activated word line is determined by detecting the charge value in the detecting means.

In the method according to the invention it is considered advantageous to use a sense amplifier as the detection means.

In the method according to the invention, it is also considered to use four different voltage values and preferably 0, V in the control of the potential_s/3、2V_s/3 and V_sCorresponding voltage values are advantageous.

The above objects, together with further features and advantages, are also obtained according to the present invention by a device, characterized in that: the word lines and the bit lines are connected to control means which control the potentials on all word lines and bit lines in a time-adjusted manner and which implement a voltage pulse protocol comprising a clock sequence of the potentials on all word lines and bit lines, said control means being adapted to activate a word line during at least part of a read cycle so as to apply to the word line a potential which corresponds at least to a voltage V with respect to the potentials of all intersecting bit lines_s。

In the device according to the invention it is considered advantageous that the polarizable material is a ferroelectric polymer.

It is also considered advantageous that the detection means in the device according to the invention are sense amplifiers.

Drawings

The invention will now be explained in detail by discussing the conventional background art for implementing passive matrix-addressable devices and how it is addressed in accordance with the invention, in connection with a discussion of exemplary embodiments, all with reference to the accompanying drawings, in which

Figure 1 shows a hysteresis loop of a polarizable material in the case of a ferroelectric memory material,

figure 2 is a schematic diagram of a passive matrix-addressable device,

FIG. 3 is a first embodiment of a voltage pulse protocol with successive rewrite/refresh cycles for a full row read, an

FIG. 4 is a second embodiment of a voltage pulse protocol with successive rewrite/refresh cycles for a full row read.

Detailed Description

Fig. 1 shows a hysteresis loop of a polarizable material. Typically, both ferroelectric materials and dielectrics have this type of hysteresis loop. In the hysteresis loop, -P_rAnd + P_rRespectively representing positive and negative remanent polarization, with P shown on the y-axis_sIs the so-called saturation polarization. On the X axis-V_cAnd + V_cRespectively represent a positive coercive voltage and a negative coercive voltage, and V is_sGreater than constant voltage V representing selection_cAnd 1/3V according to the invention_sThe values of (a) represent the divided voltage levels as part of the voltage pulse protocol used, as will be discussed further below. If it is assumed that the polarizable material is initially unpolarized, it is applied by applying a voltage substantially greater than V, for example_cAnd preferably with V_sCorresponding toThe voltage is polarized. Then the polarization is shifted from 0 until it reaches the point Pc on the hysteresis loop_s. This point shows the ferroelectric saturation polarization P of the material_sOr dielectric saturation polarization P_sThen the increased voltage is no longer effective. When the applied voltage is removed, i.e. now 0 potential above the polarizable material, the polarization P will return along the hysteresis loop to the remanent or permanent polarization P where the hysteresis loop intersects the y-axis_r. Accordingly, a large negative voltage V for polarizing the material can be applied_sTo polarize the material to a remanent polarization state-P_r. By applying a voltage-V_sThe polarization state can be from + P_rTransformation to-P_rAnd by applying a correspondingly large positive voltage + V_sPolarization state-P_rIs accordingly converted into + P_r. This corresponds to the protocol of writing and reading in passive matrix-addressable devices comprising a polarizable material of this type, and in order to implement the above-mentioned read-write protocol it is clear that the potential difference across the cell, i.e. the capacitor-like structure, must correspond to the applied voltage level + V_sor-V_sBy setting the word line to this voltage and holding one or more bit lines at 0, the desired (something) can be obtained. If only one of the cells connected to the activated word line is to be written to or read from, care must be taken that the potential of the remaining bit lines contacting the unaddressed cells remains at the same voltage as the activated word line, so that the potential difference across these cells thus becomes equal to 0.

Fig. 2 shows an exemplary embodiment of a passive matrix-addressable device. The first electrode group is constituted by parallel electrodes WL forming word lines in a matrix. For example, the first electrode group may be m such word lines WL. The second electrode group is constituted by parallel electrodes BL perpendicularly crossing the word lines WL. The former is the bit lines BL of the matrix and is arranged in a number n, so that an mn matrix is obtained. Each electrode set is disposed in a respective parallel plane and the polarizable material is provided as a unitary layer sandwiched between the electrode sets, it is possible to provide the polarizable material over the electrode sets if the word lines WL and bit lines BL are arranged in a bridge arrangement with intervening layers insulated from each other in the intersections. Thus, a matrix-addressable device is obtained, wherein each single cell is now defined by the active material located in the intersection or cross-point between the word line WL and the bit line BL. Thus, the passive addressable matrix becomes a matrix with mn addressable elements (which of course may be square such that m ═ n). Both the word lines and the bit lines are connected to a common sensing device and to driving and control circuitry for selection and addressing. These are not shown but are known to those skilled in the art to be used in active and passive matrix-addressable devices and are therefore omitted from figure 2. Furthermore, the detection means associated with each bit line may in fact be advantageously implemented as a sense amplifier SA.

In addressing, a word line is selected and a certain voltage is applied thereto. This word line is shown as the activated word line AWL in FIG. 2, while all of the remaining word lines WL are represented as the deactivated word lines (IWL). If there is now a potential difference between the activated word line AWL and the bit line BL crossing it, an addressing operation is performed on the memory cell which is at the crossing point between the word line AWL and the bit line BL. In so-called global row addressing (full row read) the same potential difference will occur over all cells connected to the active word line AWL, so that for read the charge flowing in the bit line is detected by the respective detection means or sense amplifier SA.

In a preferred embodiment of the device according to the invention for performing the method, the polarizable material is a ferroelectric polymer material. Various ferroelectric polymer materials may be employed including, but not limited to, polyvinylidene fluoride (PVDF). As further examples, polyamides (nylon), cyano polymers, copolymers of vinylidene fluoride (VDF) and trifluoroethylene (TrFE), polyureas, polythioureas, biopolymers such as polypeptides and cyanoethylcellulose can be mentioned. The ferroelectric polymer film can be deposited using well known methods such as spin coating, for example, VDF-TrFE (75/25) copolymer from a suitable solvent such as Dimethylformamide (DMF), cyclohexanone or Methyl Ethyl Ketone (MEK).

Different embodiments of the method according to the invention will now be discussed. The first embodiment is illustrated by the graph of fig. 3, fig. 3 showing a graph with 0 and V_sVoltage pulse protocol of voltage levels in between and time stamps from 0 to 6 count points at the time points and at the upper edge as shown. According to the voltage pulse protocol in fig. 3, when no addressing operation is generated, i.e. when no cell in the matrix is read or written, all word lines WL and bit lines BL of the device are kept at a static voltage equal to 0. During a read cycle, the voltage V between time markers 1 and 2_sIs applied to the activated word line AWL while the inactivated word line IWL is held at 0 potential. In a state of remanent polarization + P_rIn the cell (2), a large positive voltage + V is applied_sWithout causing any substantial change in the polarization state of the cell, and in other words no charge flow in the bit line BL, there may be only one polarization P represented in saturation as shown in fig. 1_sAnd remnant polarization + P_rThe small charge of the difference between. Conversely, if the cell is in the remanent polarization state-P_rThen the current polarization state according to the protocol is switched to + P_rAnd a large charging current is obtained on the bit line BL and a high output signal is output to the sensing means. If positive polarization state + P_rE.g. representing a logical 0, it does not have to have any refresh or overwrite, but is in the negative remanent polarization state-P_rIn the cell (b), the read-out will result in a switch to the positive remanent polarization state + P_rAnd the logical value of the cell must be restored by rewriting the memory cell. This is done by holding the activated word line at 0 and setting the bit line at the potential indicated to apply a voltage to the cell equal to-V_sTo be implemented. During a write cycle, all inactive wordlines IWL remain at 2V_s/3 and the inactive bit line remains at V_s/3. Therefore, only the potential difference between the activated bit line AWL and the bit line BL activated for refresh is equal to V_sWhile all the inactive word lines IWL are held at the same potential, e.g., 2V_s/3 and all inactive bit lines correspond to the potential V_s/3. Thus, it is possible to provideThe potential difference between the inactive word line and the active bit line is substantially less than V_sAnd this is advantageous for reducing disturbing voltages or capacitive coupling etc. in the matrix during the addressing operation of the overwrite.

It should be observed that four voltage levels, i.e., 0, V, are employed in the voltage pulse protocol of FIG. 3_s/3、2V_s/3 and V_s. Voltage V_sIs a voltage division level of V_s/3 and 2V_sThe/3 is derived from the so-called voltage selection law or pattern for modifying the state of polarization of the memory cell with values between 0 and V in order to reduce disturbing voltages and sneak currents and other situations which can affect the polarization state of the memory cell in a detrimental way_sA pulse protocol between/3 for selecting voltage values. In the present case, the selection law used is the so-called 1/3 selection. Can show V_sAnd/3 is the minimum average voltage level that can exist on all word and bit lines in the matrix during an addressing operation.

In view of the theoretical background of the use of voltage pulse protocols and voltage selection rules, reference may be made to the pending norwegian patent No.312699, which establishes a voltage pulse protocol and the theory to use them, independent of whether individual cells or several cells are addressed in parallel, which cells are located in large passive matrix-addressable memory devices with ferroelectric or dielectric memory material.

Fig. 4 shows another voltage pulse protocol according to the invention with corresponding identification of the time points. This likewise uses a pressure of from 0 to V_sAnd the so-called 1/3 selection rule, but unlike the protocol in fig. 3, when no cell in the matrix is read or written, all word lines and bit lines are currently held at a quiescent voltage V_s/3. This has the advantage that during an addressing operation for reading or writing, the voltage level which in any case has to be applied to, for example, an activated word line AWL or an activated bit line BL is substantially less than V_sE.g. up to 2V_sA/3, and also results in a network ofThe disturb voltage and sneak current while reducing access time. Thus, activating the wordline in the read cycle of the protocol is from V at identification 2_s3 switching to V_sAnd the bit line is from V_sThe/3 is switched to 0 voltage. At the same time, the inactive word line IWL is also set to a 0 voltage so that there is no potential difference between the inactive word line IWL and the inactive bit line BL. After performing the read cycle in parallel, by setting all word lines and bit lines back to the quiescent voltage V_sA refresh is generated and in a period for rewriting or refreshing, 0 voltage is applied to the active word line AWL and the active bit line BL is set to the potential V_sThe active bit line BL addresses the memory cell to be reset or refreshed, the potential V being such that, in order to generate a true reset_sOf course with the appropriate polarity. The inactive bit lines, i.e. those contacting cells that will not produce a refresh, are held at V_s/3 while inactive word line IWL is set to 2V_s/3. Thus, the potential difference between an inactive word line and an inactive bit line will be V_s/3 and the potential difference between the inactive word line and the active bit line is likewise V_s/3, and the potential difference for rewriting between the activated word line and the activated bit line becomes obviously equal to V at present_s(may be-V)_s). The potential difference between the activated word line AWL and the inactivated bit line where no further writing occurs is V_s/3。

The voltage pulse protocol in the embodiment shown in fig. 3 provides a very simple reading of a matrix-addressable device and this means that it is not shown for word lines and bit lines WL; the BL driver circuit is made relatively simple and the slightly more complex voltage pulse protocol shown in the embodiment of fig. 4 requires that the potentials on all the word lines and bit lines be changed according to the protocol, but at the same time the immunity of the device to disturb voltages and sneak currents is greatly improved. It will be appreciated that during a write cycle, the actual potential on the activated bit line may be positive and negative depending on the logic value that should be written and the initial state of the respective cell after the destructive read operation. It should also be noted that the figures are shown forThe time identity of the clock sequence can be chosen relatively freely and it can for example be the case that the time intervals 2-1 and 4-3 in fig. 4 can be 0 or negative, as the time value will depend on the dynamic properties of the polarizable material, for example the time constant of the hysteresis loop of the chosen material. It should also be understood that the absolute value of the voltage levels and the number of voltage levels themselves according to the pulse protocol may be chosen arbitrarily, as long as the conditions for performing a so-called full row read, i.e. the potential V over each cell of the activated word line, are obtained_sAnd a 0 voltage over unaddressed cells on the inactive word line IWL. For activating the cells, it is also possible to provide substantially more than V_sOtherwise, the remanent polarization state of the memory material is affected. It should also be noted in this context that phenomena such as fatigue, i.e. a gradual decrease of the remanent polarization value of the memory cell, may aggravate and create reading problems for the respective cell. Furthermore, a so-called "imprint" will be evident, i.e. a cell that has been in a particular polarization state for a long time will be in a situation where this polarization state is maintained, whereby a high voltage or a long voltage pulse is required when performing a possible addressing operation.

Thus, when all bit lines BL in the passive matrix are read during the same read cycle using a suitable voltage pulse protocol, a full row read is performed. During the same time period that all n bit lines are activated, only one of the m word lines is activated. To obtain this structure, each bit line in the matrix must be connected to a sense amplifier. When the matrix is divided into a plurality of sub-matrices for some reason, full row reading may be employed. The concept of full row read is therefore meant to include the case where all cells on an entire word line in the sub-matrix are read during the same read cycle. Full row read provides more advantages than partial row read or single cell read-out, i.e.

a) During a read cycle, all unaddressed cells apply a 0 potential, which reduces the number of disturb signals that can generate a loss of data content (logic value) and eliminates all disturbs that can generate background currents during a read operation.

b) The data slew rate will be the maximum rate allowed by the number of bit lines in the matrix or sub-matrix;

c) the read voltage V can be selected to be higher than the coercive voltage_sWithout causing local switching on unaddressed cells, which means that the switching speed will be the highest switchable speed for the polarized material of the respective cell; and

d) the readout mode is compatible with large matrices and matrix sets.

To read data, the potential difference between the activated word line AWL and the bit line BL is set to a potential V_sIt creates a flowing charge from each cell and to the contacting bit line. The charge value (or current) depends on the polarization state of each cell and is detected by a sense amplifier, one for each bit line. By using suitable measurement circuitry, the logic state of each cell can thus be determined.

As mentioned above, in the introduction of the present application, a passive matrix-addressable device may be a memory device and may be applied for storage of data such that the polarization state in each cell represents either a logical 1 or a logical 0. It is also possible to use a corresponding device as a sensor device, whereby the logic value stored in each cell is assigned to the value of each sensor element of the sensor device. However, in this application or other applications, there is in principle no difference in the way they are used to read and refresh the data stored in the cells.

Claims (7)

1. A method for reading a passive matrix-addressable device, in particular a memory device or a sensor device having individually addressable cells for storing a logic value given by a charge value set in a cell, wherein the device comprises an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the device comprises a first and a second electrode arranged by parallel electrodes forming a word line and a bit line, respectively, in the device, wherein the word line electrode (WL) and the bit line electrode (BL) are arranged perpendicularly to each other and at their opposite surfacesContacting the polarizable material such that the cells of the device include a capacitor-like structure defined by a volume of polarizable material in or at the intersection between word lines and bit lines, by applying a coercive voltage (Vl) greater than the polarizable material between the Word Lines (WL) and Bit Lines (BL) of an addressed cell_cVoltage V of_sThe cell in the device can be set to one of two polarization states or switched between these polarization states, wherein each Bit Line (BL) is connected to detection means, wherein the method comprises: a voltage pulse protocol having a read cycle such that during the read cycle each sensing means senses the charge flowing between its associated Bit Line (BL) and the cells connected to the bit line, and wherein the method is characterized by:

the potentials on all word lines and bit lines are controlled in a time-adjusted manner according to a voltage pulse protocol comprising a clock sequence of the potentials on all word lines and bit lines, so that at least during a part of a read cycle a word line is activated by an applied potential which corresponds at least to a voltage V relative to the potentials of all intersecting bit lines_sAnd the logic value stored in each cell connected to the activated word line is determined by detecting the charge value in the detection means.

2. The method according to claim 1,

a sense amplifier is used as the detection means.

3. The method according to claim 1,

four different voltage values are used in the control of the potential.

4. A method according to claim 3,

the voltage values used are 0 and V respectively_s/3、2V_s/3 and V_s。

5. A device for performing a method of reading a passive matrix-addressable device, in particular a memory device or a sensor device having individually addressable cells for storing a logic value given by a charge value set in the cell, wherein the device comprises an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the device comprises a first and a second electrode arranged by parallel electrodes forming word lines and bit lines, respectively, in the device, wherein the word line electrode (WL) and the bit line electrode (BL) are arranged perpendicular to each other and contact the polarizable material at their opposite surfaces, such that each cell of the device includes a capacitor structure defined by a volume of polarizable material in or at the intersection between the word line and the bit line, wherein the cell is addressed by applying a coercive voltage V between the Word Line (WL) and the Bit Line (BL) of the addressed cell that is greater than the polarizable material._cVoltage V of_sThe cell in the device can be set to one of two polarization states or switched between these polarization states, wherein each Bit Line (BL) is connected to detection means, wherein the method comprises: -a voltage pulse protocol having a read cycle such that during the read cycle each detection means detects the charge flowing between its associated Bit Line (BL) and the cells connected to this bit line, characterized in that:

the word lines and bit lines (WL; BL) are connected to control means which control the potentials on all word lines and bit lines in a time-regulated manner and which implement a voltage pulse protocol comprising a clocked sequence of the potentials on all word lines and bit lines, said control means being adapted to activate a Word Line (WL) during at least part of a read cycle so that the potential with respect to all intersecting bit lines will correspond at least to a voltage VV_sIs applied to the word line (AWL).

6. The device according to claim 5,

the polarizable material is a ferroelectric polymer.

7. The device according to claim 3,

the detection means (SA) is a sense amplifier.