HK1081738B - Lc oscillator with wide tuning range and low phase noise - Google Patents

Description

LC oscillator with wide tuning range and low phase noise

Technical Field

The present invention relates generally to the field of wireless communications, and more particularly to a voltage controlled oscillator for a phase locked loop.

Background

Phase Locked Loops (PLLs) have found wide application in, for example, wireless communication systems and other product areas. In many applications, PLLs have very stringent performance requirements. In a typical wireless system, there may be more than one PLL circuit 110, 120. For example, an exemplary block diagram 100 of a receiver using a super-heterodyne architecture is shown in FIG. 1. Those skilled in the art will readily recognize the various blocks and their functions and, therefore, the details of such blocks will not be further described herein.

PLLs used in wireless communication systems provide a highly stable carrier signal for modulation and demodulation processes. The carrier signal should be of sufficient spectral purity (typically manifested as phase noise characteristics of a Voltage Controlled Oscillator (VCO) in the PLL) and to support the required channel spacing within the required frequency band. For example, cellular phone standards in korea include the IS-95 standard for Code Division Multiple Access (CDMA) digital services at approximately 900MHz and 1700 MHz. The cellular telephone standards in europe include the global system for mobile communications (GSM) operating in the 900MHz band and the Defense Communications System (DCS) in the 1800MHz range. Although the occupied frequency bands are similar, the channel spacing required for the PLL varies according to a specific standard. For example, the IS-95 standard requires a channel spacing of 1.25MHz and a channel raster of 10 KHz. On the other hand, the GSM and DCS standards require a channel spacing of 200KHz in a specified frequency band. Since the PLL in a wireless communication transceiver generates an appropriate Very High Frequency (VHF) signal with high accuracy, the PLL can use a highly stable voltage controlled temperature compensated crystal oscillator (VCTXO) as a reference clock.

Fig. 2 shows a generic block diagram of a PLL typically used in a wireless communication device. As shown, the PLL includes a reference divider 202, a feedback divider 210, a Voltage Controlled Oscillator (VCO)208, a Phase Frequency Detector (PFD)204, a charge pump circuit (not shown), and a Loop Filter (LF) 206. The PFD204 compares the phase of the divided reference clock signal and the divided output of the VCO 208. Depending on the magnitude and polarity of the phase error, the charge pump circuit generates an UP or DOWN signal at its output, where the width of the pulse is proportional to the detected phase error. The charge pump circuit generates an amount of charge equal to the error signal. The net charge is accumulated on LF206 as a control signal for VCO 208. The simple form of LF206 is a serial combination of a resistor and a capacitor (e.g., a first order filter). However, in modern PLL designs, higher order loop filters can be used to obtain better performance in phase noise and spurious responses. The resulting voltage from LF206 is connected to the frequency control terminal of VCO 208. The PLL of fig. 2 obtains a stable output frequency due to the negative feedback loop. When the net charge of the loop filter 206 voltage becomes zero, there will be a state where the output frequency is stable. At this point, the frequency and phase of VCO208 generally do not change. In this locked state, the frequency of VCO208 can be simply expressed as:

wherein f is_vcoVCO frequency, feedback divider, reference divider, f_refThe reference frequency. In equation (1) above, the coefficients of the feedback divider may be integers, and in some applications may also include a fractional part.

There are many factors in designing a PLL circuit for a particular application. Common factors are circuit area, cost and power consumption. Performance characteristics such as lock time and phase noise depend on the system using the PLL. Depending on system requirements, design parameters such as division factor, loop bandwidth and circuit design will be affected. For example, in GSM applications, a channel spacing of 200KHz, a reference frequency of 13MHz, and a lock on time of a few milliseconds are required. Thus, an integer-N frequency synthesizer and conventional loop bandwidth may be used to meet the requirements. However, in General Packet Radio Service (GPRS) applications, the normal integer N frequency synthesizer cannot be used because the lock time is required to be less than 150 μ s. In this case, fractional-N synthesizers or sigma-delta based synthesizers are typically used.

In other applications, the required frequency resolution in the PLL is 10KHz, even with a channel spacing of 1.25 MHz. This is of reason. First, the most common reference frequency in IS-95 applications IS 19.2MHz, which IS not a multiple of 1.25 MHz. Second, when a PLL is used in a superheterodyne transceiver, the required frequency resolution depends on the choice of Intermediate Frequency (IF) signal. The common IF frequency in receive mode is 85.38MHz, and the frequency resolution in local oscillator should be 10 KHz. Third, compatibility with older standards such as Advanced Mobile Phone Service (AMPS) requires a 10KHz frequency resolution in generating the Local Oscillator (LO) signal.

The performance of the related art PLL is limited by the performance of the VCO208, and important characteristics of the VCO208 include phase noise performance. The remaining components, such as the PFD204 and the dividers 202 and 210, also contribute to the overall noise performance of the PLL output. Phase noise is typically defined as the ratio of the carrier power at a particular offset frequency of 1Hz from the carrier to the sideband power. The unit of the phase noise is dBc/Hz. VCO208 is a sensitive device whose phase noise performance characteristics may be greatly affected by environmental conditions such as power supply variations, temperature, and noise. The factor representing the sensitivity of VCO208 is its gain, usually denoted as K_vco(MHz/V). For low noise PLL applications, the VCO208 may have a relatively low gain and thus a low sensitivity. The low gain of VCO208 reduces the effects of external noise by minimizing modulation from AM to FM.

Since the phase noise requirements are very stringent in mobile phone applications, the types of VCOs that are allowed to be used are limited, and LC oscillators are commonly used. The LC oscillator consists of a resonant tank and some active devices to compensate for the energy loss in the tank. Since the tank is a band-pass filter, the phase noise performance of the LC oscillator is superior to other types of oscillators. The nominal frequency of the LC oscillator is expressed as follows:

in equation 2, f_vcoThe nominal frequency of the VCO, L inductance,c is capacitance. There are two possibilities to control the VCO frequency. However, variable capacitance can be used to control the frequency of the VCO, since it is not easy to make a variable inductance.

VCOs are usually designed using a separate tank circuit, some passive components and active devices. This approach results in a larger circuit area and higher cost. There has been a recent trend to integrate those functional modules into a monolithic form. The most difficult factor in designing a fully integrated LC oscillator is to ensure stable operation during processing and environmental changes. In the worst case, the capacitance or inductance grown on the silicon wafer varies by more than 10%. Referring to equation (2), it can be seen that the percentage of operating frequency change in this case is also 10%. The total operating range of the VCO should therefore include this frequency translation as well as the required frequency range. However, a wide tuning range is in conflict with the small gain design goal to obtain low phase noise characteristics.

The balance between the low phase noise and the wide tuning range described above is addressed by various discrete tuning methods. Fig. 3 shows a schematic diagram of a VCO according to the related art. LC tank 310 controls the frequency of oscillator 300. LC circuit 310 includes a capacitor 312, an inductor 314, varactors 316 and 320, and a switch 318. In operation, when no lock is achieved in the PLL, the varactor diode 316 is selectively switched to control the frequency of the VCO. When the operating frequency of the VCO exceeds the desired frequency, more switches are closed to reduce the operating frequency of the VCO and vice versa. In the related art circuit of fig. 3, the size of the capacitor 312 is not important due to the capacitance of the varactors 316 and 320.

The LC circuit of the related art VCO has various disadvantages. For example, referring to fig. 3, there is no DC current path in the off state of switch 318. Thus, the bias voltage of the floating terminal of the corresponding diode 316 is unknown and very sensitive to leakage. When the initial bias condition of such a floating terminal is too high or too low, the reliability of the device will be greatly affected.

Fig. 4, 5A and 5B show a similar related art VCO in another differential embodiment, in which an equal value capacitance is used in place of each varactor. As shown in fig. 4, all switches except SW (1) and SWB (1) are closed, so we focus on the states of floating nodes NSC (1) and NSCB (1). Where the initial bias voltage of the floating terminal is assumed to be equal to the oscillator's normal mode voltage, the waveform of the floating terminal is nearly the same as the waveform of the oscillator output and there is little or no degradation in performance.

However, fig. 5A shows the situation where some positive charge is stored on the plate of the capacitor connected to NSC (1) and some negative charge is stored on the other plate of capacitor SCB (1) just after switch SW (1) is turned off. Since there is no DC current path in the off state, there is a positive offset voltage between the NSC (1) node and the OUT node. Wherein when the offset voltage is excessive, the switch may be damaged and the reliability of the VCO may be degraded.

Fig. 5B shows another undesirable situation. When an NMOS switch is used to control the switchable capacitance, the drain node is forward biased. Since the quality factor of such a parasitic connection is very poor, the phase noise performance will be severely degraded in this case.

Other problems and disadvantages exist, as will be appreciated by those skilled in the art. Examples of related art systems are presented in U.S. patent nos. 6,137,372 and 5,739,730.

The above references are incorporated herein by reference as appropriate for teachings of additional or alternative details, features and/or technical background.

Disclosure of Invention

As set forth and broadly described herein, there are provided an apparatus and method that overcome the above-mentioned drawbacks of the prior art. Accordingly, an embodiment of the present invention provides a system, including: at least one regulating circuit operably connected to an oscillator, wherein the regulating circuit comprises: a resistor; a reactive element; and a first switch, wherein the first switch is in series with the reactive element and connects or disconnects the reactive element and the oscillator output, and wherein the resistance provides a bias voltage to the reactive element such that the reactive element has the bias voltage when the first switch is open.

Furthermore, an embodiment of the present invention provides an apparatus, including: an active oscillator, wherein the active oscillator comprises a first output node and a second output node; an inductor, wherein the inductor connects the first output node and the second output node; and at least one capacitive circuit connected to the first output node or the second output node, each capacitive circuit comprising: a capacitor; a resistor; and a first switch, wherein said resistor provides a bias voltage to said capacitor when said first switch is open, and said first switch is in series with said capacitor and connects or disconnects said capacitor from the oscillator output.

Further, an embodiment of the present invention provides a method for tuning an oscillator circuit, the method including: providing a bias voltage to the reactive element through the resistor such that the reactive element has a bias voltage when the first switch is open; and connecting or disconnecting the reactive element and the oscillator using the first switch, thereby adjusting the frequency of the oscillator.

Additional advantages, objects, and features of the invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following.

Drawings

The present invention will hereinafter be described in detail with reference to the appended drawings, wherein like reference numerals denote like elements, and wherein:

fig. 1 is a block diagram of a superheterodyne receiver in accordance with the related art;

FIG. 2 is a block diagram of a related art lock-directed ring;

fig. 3 is a schematic diagram of a related art voltage controlled oscillator;

fig. 4 is a schematic diagram of the operation of a related art voltage controlled oscillator in accordance with a first mode of operation;

fig. 5A is a schematic diagram of the operation of a related art voltage controlled oscillator in accordance with a second mode of operation;

fig. 5B is a schematic diagram of the operation of a related art voltage controlled oscillator in accordance with a third mode of operation;

fig. 6 is a schematic diagram of a voltage controlled oscillator according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a voltage controlled oscillator according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a voltage controlled oscillator according to an embodiment of the present invention; and

fig. 9 is a schematic diagram of a voltage controlled oscillator according to an embodiment of the present invention.

Detailed Description

Fig. 6 is a block diagram illustrating an embodiment of the present invention. Oscillator circuit 600 includes an oscillator 610 and at least one conditioning circuit 620 operably coupled to oscillator 610. The regulating circuit includes a bias resistor 622, a reactive element 624 (e.g., a capacitor), and a first switch 626. The first switch 626 selectively connects or disconnects the reactive element 624 from the oscillator circuit 600. Bias resistor 622 provides a bias voltage V to reactive element 624_ASo that the reactive element 624 has a bias voltage when the first switch 626 is open.

As will be discussed in detail below, the bias voltage V may be provided to the reactive element in a variety of configurations_A. For example, the bias voltage V may be applied to the bias resistor 622_AWith a bias switch 628 placed therebetween. The bias switch 628 selectively connects the bias resistor 622 and the bias voltage when the first switch 626 is disconnected from the reactive element 624. When the first switch 626 connects the reactive element 624 with the oscillator circuit 600Bias switch 628 selectively opens bias resistor 622 and bias voltage V_A. Alternatively, the bias resistor 622 (e.g., high resistance value) may be customized as desired to enable stable biasing of the voltage V_AIs connected to a bias resistor and biases the voltage V when the first switch 626 is closed_AThe operating characteristics of the regulating circuit are not substantially changed.

Bias voltage V_AMay be connected to ground, to the supply voltage or to the common mode voltage of the oscillator output. Furthermore, a bias voltage V_AMay be variable and may be selected in a range from ground voltage to power supply voltage. In addition, switches 626 and 628 may be semiconductor switching devices, such as transistors and the like.

As shown in fig. 6, the regulating circuit 620 is part of a resonant circuit 630. Those skilled in the art will appreciate that resonant circuit 630 may include additional elements such as inductors, capacitors, and resistors. When the first switch 626 is opened or closed, the reactive element 624 is removed or added, respectively, from the resonant circuit 630. Accordingly, the first switch 626 may alter the characteristics of the resonant circuit 630, thereby altering the frequency of the VCO. Also, additional regulation circuitry may be added to the resonant circuit 630 to extend the range of control. And those skilled in the art will appreciate that the adjustment circuit of fig. 6 may be used for a single terminal or different types of oscillators, since an extended tuning range and improved phase noise performance are advantageous for both oscillators.

Fig. 7 is a schematic diagram illustrating a voltage controlled oscillator according to an embodiment of the present invention. As shown in fig. 7, the circuit preferably includes an active oscillator circuit 702. The circuit shown in fig. 7 is a differential embodiment with output nodes OUT706 and OUTB 708. The inductor 704 is preferably connected to the output nodes OUT706 and OUTB 708. Two or more circuits having capacitors 722 in series with switches 718 are also connected to OUT 706. Capacitor 722 is connected to output node 706 and switch 718. Switch 718 is preferably a transistor switch that is connected to a reference voltage, which may be a ground voltage as shown in fig. 7. In addition, the circuit preferably comprises a resistor and a switch connected in series, for example a transistorAn explicit resistor 710 in series with 714 is switched off. One terminal of explicit resistor 710 is connected to a common node of capacitor 722 and transistor switch 718, and transistor switch 714 is connected to the other terminal of resistor 710 and bias voltage V_AIn the meantime. Similar components and connections are also preferably made at the output node OUTB 708. For example, a capacitor 722 is preferably connected in series with the transistor switch 720, with the other terminal of the capacitor 722 connected to the output node OUTB 708. Also, the other end of the transistor switch 720 is grounded. Furthermore, there is preferably an explicit resistor 712 connected in series with a transistor switch 716, such that resistor 712 is connected to a common node of capacitor 722 and transistor switch 720, with the other terminal of transistor switch 716 connected to a bias voltage V_A. Those skilled in the art will appreciate that capacitors 722 may have the same or different values. Also, the associated resistors and switches may be determined to be the same or different values depending on the particular design requirements of each application.

The operation of the circuit shown in fig. 7 will now be described. The values of resistors 710 and 712 are preferably determined or optimized for optimal phase noise performance in the off state. Since the resistance values are typically high (e.g., in excess of several kilo-ohms), the low on-resistance of the transistor switches 714 and 716 is not required. Thus, the size of the transistor switches 714 and 716 can be very small. In addition, the additional parasitic capacitance of the transistor switches 714 and 716 is also small. Also, since the resistors 710 and 712 are designed to include most of the resistance in the off state, the characteristics of the transistor switches 714 and 716 do not change significantly. Bias voltage V_AThe common voltage in the off state is determined and may have any value from ground to supply voltage. Therefore, the bias voltage V_AMay be generated by a simple bias voltage source, such as a resistor divider. V_ABut also the ground voltage or the supply voltage itself.

Fig. 8 is a schematic diagram illustrating a Voltage Controlled Oscillator (VCO) according to an embodiment of the present invention. VCO800 preferably includes an active oscillator circuit 802. VCO800, as shown in fig. 8, is a differential embodiment having output nodes OUT806 and OUTB 808. The inductor 804 is preferably connected between the output nodes OUT806 and OUTB 808. A series circuit comprising a capacitor 822, a resistor represented as an explicit resistor 810 and a switch 814 or the like (e.g., a transistor) is preferably connected to the output node OUT806 via one terminal of the capacitor 822 and one terminal of the transistor switch 814, i.e., the opposite terminal of the series circuit. In addition, a switch 818 or the like (e.g., a transistor) is preferably connected between a reference voltage at ground and a common node of the capacitor 822 and the resistor 810. Similar circuitry may also be connected at the output node OUTB 808. For example, a series circuit including the capacitor 822, the resistor 812, and the transistor switch 816 may be connected to the output node OUTB808 with one terminal of the capacitor 822 and one terminal of the transistor switch 816 in the series circuit therebetween. Transistor switch 820 is preferably connected between ground and the common node of capacitor 822 and resistor 812. Those skilled in the art will appreciate that the capacitors 822 may have the same or different values. Also, the associated resistors and switches may be determined to be the same or different values depending on the particular design requirements of each application.

In the embodiment shown in fig. 8, no additional biasing circuitry is required in the off state. Instead, the common mode voltage of the active circuit in the LC oscillator provides an appropriate DC bias to the other end of the capacitor that is not connected to the oscillator output. Also, in VCO800, the size of transistor switches 814 and 816 can be very small. Therefore, the additional parasitic capacitance of the transistor switches 814 and 816 is also not significant.

Fig. 9 is a schematic diagram showing a voltage controlled oscillator according to an embodiment of the present invention. VCO900 as shown in fig. 9 preferably includes an active oscillator circuit 902. VCO900 of fig. 9 is also a differential configuration with output nodes OUT906 and OUTB 908. The inductor 904 is preferably connected between the output nodes OUT906 and OUTB 908. Further, preferably, a capacitor 922 is connected in series with a switch 918 (e.g., a transistor), the other terminal of the capacitor 922 is connected to the output node OUT906, and the other terminal of the transistor switch 918 is connected to ground. Preferably, an explicit resistor, as resistor 910, is connected between the common node of capacitor 922 and transistor switch 918, and the bias voltage V_AIn the meantime. Similar circuitry is also preferably connected at OUTB 908. For example, a capacitor 922 is preferably connected in series with transistor switch 920, with the other end of capacitor 922 connected to the inputThe node OUTB908 and the other terminal of the transistor switch 920 are coupled to ground. Preferably, an explicit resistor 912 is connected to the bias voltage V_AAnd between capacitor 922 and the common node of transistor switch 920. Those skilled in the art will appreciate that the capacitors 922 may have the same or different values. Also, the associated resistors and switches may be determined to be the same or different values depending on the particular design requirements of each application.

In the embodiment shown in fig. 9, the bypass switches (e.g., switches 814 and 816 in fig. 8) are eliminated, reducing or limiting performance loss. This is because the impedances of explicit resistors 910 and 912 are selected so that they do not significantly change the operating characteristics during the closing of switches 918 and 920. Those skilled in the art will appreciate that appropriate values for resistors 910 and 912 are empirically determined for a given oscillator design (e.g., capacitance, frequency range, etc.). When switches 918 and 920 are opened to reduce capacitance, the other end of them not connected to the oscillator output preferably has a DC bias substantially equal to the common mode voltage of oscillator 902.

The above-described embodiments can be used in the receiver and PLL circuit described in the related art. Moreover, those skilled in the art will appreciate that embodiments of the present invention may be used in any device that uses or may use a PLL or VCO. For example, embodiments of the invention may include a PLL, receiver, transmitter, transceiver, wireless communication device, base station, or mobile station (e.g., cellular telephone, PDA, pager, etc.).

As described above, the preferred embodiment and method of the VCO circuit has various advantages. The preferred embodiment provides an extended tuning range for the PLL. Moreover, the preferred embodiments reduce or eliminate problems associated with the on and off states of the VCO tuning circuit. Furthermore, the size of the transistor switch can be reduced.

Furthermore, those skilled in the art will appreciate that the method disclosed in the foregoing description is for tuning a device having an oscillator circuit. For example, the method includes providing a bias voltage to the reactive element via a bias resistor such that the reactive element has the bias voltage when the first switch is open, connecting or disconnecting the reactive element and the oscillator circuit using the first switch, and connecting the bias resistor and the bias voltage using the second switch. Also, the method may include opening the second switch if the first switch is closed and closing the second switch if the first switch is open. The method may be applied to a variety of devices such as PLLs, receivers, transmitters, transceivers, wireless communication devices, base stations, and/or mobile stations.

The foregoing embodiments and advantages are merely representative and are not intended to limit the present invention thereto. As will be appreciated by those skilled in the art, the present invention may also be applied to other types of apparatuses. Further alternatives, modifications and variations will be apparent to those skilled in the art.

Claims (50)

1. A system, comprising:

at least one regulating circuit operably connected to an oscillator, wherein the regulating circuit comprises:

a resistor;

a reactive element;

a first switch, wherein the first switch is in series with the reactive element and connects or disconnects the reactive element and the oscillator output, and wherein the resistor provides a bias voltage to the reactive element such that the reactive element has the bias voltage when the first switch is open; and

a second switch, wherein the second switch connects the resistance to the bias voltage when the first switch disconnects the reactive element, and the second switch disconnects the resistance to the bias voltage when the first switch connects the reactive element.

2. The system of claim 1, wherein said reactive element is a capacitor.

3. The system of claim 1, wherein the bias voltage is at least one of a voltage generated by a resistor divider, a ground voltage, a supply voltage, and a common mode voltage of an oscillator output.

4. The system of claim 3, wherein the bias voltage generated by the resistor divider ranges between ground voltage to a supply voltage.

5. The system of claim 1, wherein the resistance is customized as needed to enable constant coupling of the bias voltage to the resistance and the bias voltage does not change the operating characteristics of the at least one regulating circuit when the first switch is closed.

6. The system of claim 1, wherein said first switch is a semiconductor device.

7. The system of claim 1, wherein the first switch is a transistor and the second switch is a smaller transistor than the first switch.

8. The system of claim 1, further comprising a plurality of conditioning circuits connected in parallel with the output of the oscillator.

9. The system of claim 8, wherein each reactive element in each of the conditioning circuits is a capacitor, and wherein the capacitance value of each capacitor is the same.

10. The system of claim 1, wherein the system is at least one of an active oscillator circuit, a PLL, a receiver, a transmitter, a transceiver, a wireless communication device, a base station, and a mobile station.

11. An apparatus, comprising:

an active oscillator, wherein the active oscillator comprises a first output node and a second output node;

an inductor, wherein the inductor connects the first output node and the second output node; and

at least one capacitive circuit connected to the first output node or the second output node, each capacitive circuit comprising: a capacitor; a resistor; and a first switch, wherein the resistor provides a bias voltage to the capacitor when the first switch is open, and the first switch is in series with the capacitor and connects or disconnects the capacitor from the oscillator output, wherein the capacitor connects the first switch to a first or second output node, the first switch connects the capacitor to ground, and the resistor is connected to the capacitor and the first switch at a common node of the capacitor and the first switch.

12. The apparatus of claim 11, wherein the bias voltage is at least one of a voltage generated by a resistor divider, a ground voltage, a supply voltage, and a common mode voltage of an oscillator output.

13. The apparatus of claim 11, wherein each capacitive circuit includes a second switch that connects and disconnects the resistor to the bias voltage.

14. The apparatus of claim 13, wherein the second switch and the resistor are in series, and wherein the bias voltage is a common-mode voltage of the oscillator output.

15. The apparatus of claim 13, wherein each capacitive circuit is configured to:

closing the second switch if the first switch is open; and

if the first switch is closed, the second switch is opened.

16. The apparatus of claim 11, wherein the apparatus is at least one of a PLL, a receiver, a transmitter, a transceiver, a wireless communication device, a base station, and a mobile station.

17. A method for adjusting an oscillator, the method comprising:

providing a bias voltage to a reactive element via a resistor, such that the reactive element has the bias voltage when the first switch is open;

connecting and disconnecting the reactive element to an output of the oscillator using a first switch based on a control signal, thereby adjusting a frequency of the oscillator;

when the first switch disconnects the reactance element, the resistance and the bias voltage are connected through a second switch; and

when the first switch connects the reactive element, the resistance and the bias voltage are disconnected via the second switch.

18. A system, comprising:

at least one regulating circuit operably connected to an oscillator, wherein the regulating circuit comprises:

a resistor;

a reactive element;

a first switch, wherein the first switch is electrically connected in series with the reactive element and connects or disconnects the reactive element and the output of the oscillator, and wherein the resistor provides a bias voltage to the reactive element such that the reactive element has a bias voltage when the first switch is open, wherein the bias voltage is generated by a resistor divider, the bias voltage ranging from ground voltage to a supply voltage.

19. The system of claim 18, further comprising:

a second switch;

wherein the second switch connects the resistance and the bias voltage when the first switch disconnects the reactive element and the second switch disconnects the resistance and the bias voltage when the first switch connects the reactive element.

20. The system of claim 18, wherein the resistance is customized on demand so that a bias voltage can be constantly coupled to the resistance and the bias voltage does not change the operating characteristics of the regulating circuit when the first switch is closed.

21. An apparatus, comprising:

an active oscillator, wherein the active oscillator comprises a first output node and a second output node;

an inductor, wherein the inductor connects the first output node and the second output node; and

at least one capacitive circuit connected to the first output node or the second output node, the at least one capacitive circuit comprising: a capacitor; a resistor; and a first switch for controlling the operation of the switch,

wherein the resistor provides a bias voltage to the capacitor when the first switch is open, wherein the first switch is electrically connected in series with the capacitor and connects or disconnects the capacitor from the oscillator output based on a control signal, and wherein the at least one capacitor circuit comprises a second switch that connects and disconnects the resistor from the bias voltage.

22. The apparatus of claim 21, wherein the second switch and the resistor are in series, wherein the bias voltage is a common-mode voltage of the oscillator output.

23. The apparatus of claim 21, wherein the at least one capacitive circuit is configured to:

closing the second switch if the first switch is open; and

if the first switch is closed, the second switch is opened.

24. The apparatus of claim 21, wherein the second switch connects and disconnects the resistor to the bias voltage based on the control signal.

25. An apparatus, comprising:

at least one reactive element;

a first switching circuit for selectively connecting said reactive element to an oscillator output based on a control signal;

a bias resistor for connecting the reactive element to a bias voltage when the first switch circuit disconnects the reactive element from the oscillator output, wherein the reactive element is tuned to the output frequency of the oscillator output when the first switch connects the reactive element to the oscillator.

26. The apparatus of claim 25, wherein a second switching circuit connects the reactive element to the bias voltage through at least one resistive element.

27. The apparatus of claim 25, wherein a second switching circuit disconnects the reactive element from the bias voltage when the first switching circuit connects the reactive element to the oscillator output.

28. The apparatus of claim 25, wherein the first switching circuit is coupled between the reactive element and a reference potential.

29. The apparatus of claim 28, wherein the reference potential is ground.

30. The apparatus of claim 25, wherein said bias voltage is lower than a voltage stored in said reactive element when said first switching circuit disconnects said reactive element from said oscillator output.

31. The apparatus of claim 25, wherein said bias voltage is higher than a voltage stored in said reactive element when said first switching circuit disconnects said reactive element from said oscillator output.

32. The apparatus of claim 25, wherein the bias voltage at least partially discharges the voltage stored in the reactive element when the first switching circuit disconnects the reactive element from the oscillator output.

33. The apparatus of claim 25, wherein the bias voltage is a reference potential.

34. The apparatus of claim 33, wherein the reference potential is ground.

35. The apparatus of claim 25, wherein the bias voltage is a supply potential.

36. The apparatus of claim 25, wherein the bias voltage is a common mode voltage of an oscillator.

37. The apparatus of claim 25, wherein the bias voltage is between a range of reference potentials and supply potentials.

38. The apparatus of claim 25, wherein a second switching circuit connects and disconnects the reactive element to the bias voltage based on the control signal.

39. A method, comprising:

operating a first switching circuit to connect a reactive element to an output of an oscillator based on a control signal;

operating a second switching circuit to connect the reactive element to a bias voltage when the first switching circuit disconnects the reactive element from the oscillator output, wherein the reactive element is tuned to the oscillator output frequency when the reactive element is connected to the oscillator.

40. The method of claim 39, wherein said second switching circuit connects the reactive element to the bias voltage through at least one resistive element.

41. The method of claim 39 wherein the second switching circuit disconnects the reactive element from the bias voltage when the first switching circuit connects the reactive element to the oscillator output.

42. The method of claim 39, wherein the first switching circuit is coupled between the reactive element and a reference potential.

43. The method of claim 42, wherein the reference potential is ground.

44. The method of claim 39, wherein said bias voltage is lower than a voltage stored in said reactive element when said first switching circuit disconnects said reactive element from said oscillator output.

45. The method of claim 39, wherein said bias voltage is higher than a voltage stored in said reactive element when said first switching circuit disconnects said reactive element from said oscillator output.

46. The method of claim 39, wherein the bias voltage at least partially discharges the voltage stored in the reactive element when the first switching circuit disconnects the reactive element from the oscillator output.

47. The method of claim 39 wherein the bias voltage is a reference potential.

48. The method of claim 47, wherein the reference potential is ground.

49. The method of claim 39, wherein the bias voltage is a supply potential.

50. The method of claim 39, wherein the bias voltage is a common-mode voltage of an oscillator.