HK1081325B - Vertical gate semiconductor device with a self-aligned structure - Google Patents

Description

Vertical gate semiconductor device with self-aligned structure

Background of the invention

The present invention relates generally to semiconductor devices and more particularly to vertical gate transistors.

There is a continuing need for semiconductor devices with higher performance levels and lower manufacturing costs. For example, manufacturers of switching regulators require more efficient power MOSFET transistors to switch the inductor current that produces the regulated output voltage. Higher efficiency is obtained by using transistors with shorter channels to provide a higher frequency response that reduces the switching losses of the regulator.

However, most, if not all, previous high frequency power transistors require advanced lithographic equipment capable of resolving small feature sizes in order to provide the shorter channels necessary to reduce switching losses. Some previous high frequency transistors were fabricated with vertical gate structures in which the channel length was determined by the thickness of the deposited gate electrode, rather than by the feature size of the lithographic apparatus. This approach reduces the need for expensive lithographic equipment, which reduces the cost of device fabrication. Previous vertical gate devices require a large number of masking steps and a complex sequence of processing steps that reduce die yield and thus increase device manufacturing costs.

Therefore, there is a need for a semiconductor device with a short channel that operates at high frequency and high efficiency and can be fabricated with a simple sequence of processing steps to avoid the need for expensive fabrication equipment.

Brief description of the drawings

Fig. 1 is a cross-sectional view of a semiconductor device after a first fabrication step;

fig. 2 is a cross-sectional view of the semiconductor device after a second fabrication step;

fig. 3 is a cross-sectional view of the semiconductor device after a third fabrication step;

fig. 4 is a cross-sectional view of the semiconductor device after a fourth fabrication step; while

Fig. 5 is a top view of a semiconductor device showing features of the device layout.

Detailed description of the drawings

In the various figures, elements having the same reference number have similar functions. As used herein, the term current carrying or conducting electrode refers to a device element that carries current through the device, such as the source or drain of a field effect transistor or the emitter or collector of a bipolar transistor.

Fig. 1 is a cross-sectional view of a cell of a semiconductor device 10 formed with a semiconductor substrate 12 after a first stage of processing. In one embodiment, semiconductor device 10 is used as a switching metal oxide semiconductor field effect transistor operating at currents above 1 amp.

The base layer 14 is formed to a thickness of about 250 microns. In one embodiment, base layer 14 is heavily doped to have n-type conductivity and a resistivity of about 0.01 ohm-cm to provide low on-resistance for semiconductor device 10. In one embodiment, base layer 14 comprises single crystal silicon.

Epitaxial layer 16 is grown on base layer 14 to a thickness of about 3 microns. In one embodiment, epitaxial layer 16 comprises single crystal silicon doped to n-type conductivity at a doping concentration of about 3.0 x 10 per cubic centimeter¹⁶An atom.

A blanket n-type implant is applied to substrate 12 to create region 17, where region 17 has a doping concentration of about 1.0 x 10 per cubic centimeter¹⁷Atoms in order to prevent low voltage breakdown caused by drain pinch-off. In one embodiment, region 17 is formed to a depth of about 0.5 microns.

A gate dielectric layer 18 is formed on the epitaxial layer 16 to a thickness of about 350 angstroms. In one embodiment, dielectric layer 18 is formed of thermally grown silicon dioxide.

Dielectric layer 19 is formed on dielectric layer 18 to a thickness of about 1500 angstroms. In one embodiment, dielectric layer 19 comprises silicon nitride.

Dielectric layer 20 is formed on dielectric layer 19 to a thickness of about 6000 angstroms. In one embodiment, dielectric layer 20 is formed by a tetraethyl orthosilicate (TEOS) process to form deposited silicon dioxide.

A conductive semiconductor layer 21 is deposited on dielectric layer 20 to a thickness of about 1800 angstroms. In one embodiment, semiconductor layer 21 comprises heavily doped polysilicon to provide low resistance. Semiconductor layer 21 may include a film of platinum, tungsten, or titanium silicide or similar materials to provide even lower resistance.

A dielectric layer 22 is formed on the semiconductor layer 21 to a thickness of about 4000 angstroms. In one embodiment, dielectric layer 22 is formed as deposited silicon dioxide from a TEOS process.

Surface 29 of substrate 12 is patterned in a first photoresist step that masks a series of standard etch steps that sequentially remove exposed portions of dielectric layer 22, semiconductor layer 21, and dielectric layers 19 and 18 to form raised pedestal structure 24. The recessed region 34 adjacent the base structure 24 is defined by vertical walls or surfaces 28 that are typically separated by a distance in the range of about 2-3 microns depending on the subsequent film thickness and the desired breakdown voltage.

Vertical walls 28 are used to mask or define an implant into body region 31 of substrate 12, which inverts to form a channel of semiconductor device 10, as described below. Thus, body region 31 is self-aligned to vertical wall 28.

An isotropic silicon nitride etch is then performed to undercut dielectric layer 19 such that its vertical surfaces 32 are recessed relative to vertical walls 28. Recessing surface 32 in this manner ensures that the channel (not shown) formed in body region 31 extends to the boundary or edge 33 of body region 31, enabling channel current to flow into epitaxial layer 16. Recessing vertical surface 32 also increases the operating voltage of semiconductor device 10 by increasing its channel length. In one embodiment, dielectric layer 19 is recessed a distance of about 0.1 microns.

As shown, a semiconductor layer 35 is deposited on the substrate 12 to a thickness of about 4000 angstroms. Semiconductor layer 35 is typically doped to have the same conductivity type and low resistance as semiconductor layer 21. Note that the semiconductor layers 21 and 35 are electrically coupled to each other along the vertical wall 28.

Fig. 2 is a cross-sectional view of semiconductor device 10 after a second stage of fabrication. Semiconductor layer 35 is anisotropically etched to form a liner adjacent pedestal structure 24 that serves as vertical gate 40. A vertical gate refers to a control electrode formed of a gate material deposited on a first surface to control a conductive channel formed on a second surface perpendicular to the first surface. In the case of semiconductor device 10, channel 50 is formed at surface 48 of body region 31, which is considered a horizontal surface. The control electrode film, i.e., semiconductor layer 35, is deposited along walls 28 perpendicular to surface 48 and thus referred to as vertical walls 28. As a result, the channel length is determined by the film thickness of vertical gate 40. Thus, a control signal applied to vertical gate 40 inverts body region 31 at the top surface to form channel 50 having a length approximately equal to the thickness of semiconductor layer 35.

Once vertical gates 40 are formed, a thin thermal oxide is grown on the exposed semiconductor surfaces to prevent contamination or static charge from accumulating through the surfaces of vertical gates 40 during subsequent processing. In one embodiment, this process step results in approximately 100 angstroms of silicon dioxide being grown on vertical gate 40.

Note that a bipolar transistor can be made with vertical gate 40 serving as the base electrode by etching dielectric layer 18 to deposit semiconductor layer 35 directly on body region 31 by omitting the etching step of recessed dielectric layer 19. After anisotropically etching the semiconductor layer 35, the vertical gates 40 are electrically coupled to the body regions 31 so as to form the base of the bipolar transistor. Subsequent processing is described below with the source and drain acting as the emitter and collector, respectively, of the bipolar transistor.

In a second photoresist step, dielectric layer 22 is patterned and etched as shown to form gate contact 54.

A blanket implant is then performed to semiconductor device 10 to form source regions 45 defined by vertical gates 40, i.e., self-aligned to vertical gates 40. This blanket implant also dopes the gate contact 54 to reduce its contact resistance. In one embodiment, the source region has n-type conductivity and a doping concentration of about 10 per cubic centimeter¹⁹-10²⁰An atom.

Note that source region 45 defines one end of channel 50 and boundary 33 of body region 31 defines the other end. Since boundary 33 is self-aligned to vertical wall 28 and source region 45 is self-aligned to vertical gate 40, the length of channel 50 is substantially determined by the film thickness of vertical gate 40. In one embodiment, the effective length of the channel 50 is about 0.4 microns, and the minimum feature size for the photolithographic process used herein may be as large as about 3 microns. Thus, a short channel is formed with a less expensive lithographic apparatus, thereby providing high frequency performance at a reduced cost. Moreover, the performance is more consistent since the film thickness can be controlled more precisely than the dimensions of the surface features determined by the masking method.

Fig. 3 shows a cross-sectional view of integrated circuit 10 after a third stage of fabrication. A dielectric material is deposited on semiconductor substrate 12 and anisotropically etched to produce dielectric liner 55 adjacent sidewalls 49 of vertical gates 40. The dielectric material is preferably deposited to a film thickness greater than the thickness of semiconductor layer 35 to ensure that thinning of dielectric liner 55 during the profile step does not result in exposing vertical gates 40 during the anisotropic etch step. For example, in an embodiment where the thickness of the semiconductor layer 35 is about 4000 angstroms, the dielectric material used to form the liner 55 may have a thickness of about 5000 angstroms. The anisotropic etch also removes dielectric material from the exposed portions of dielectric layer 18 to define source contacts 56 on source regions 45 that are self-aligned to dielectric liner 55.

As shown, liner 55 is also used to mask the p-type blanket implant step that creates enhancement region 47 under source region 45. Enhancement region 47 provides a low resistance path that keeps body region 31 at a constant potential in all regions of semiconductor device 10. In an alternative embodiment, enhancement regions 47 may be formed in selected regions of surface 48 using an additional photomasking step to block the source implant from entering the selected regions.

Fig. 4 is a cross-sectional view of semiconductor device 10 after a fourth stage of fabrication.

A standard semiconductor metal film is deposited on the surface of substrate 12. In one embodiment, a thin layer of platinum is deposited and annealed to form a platinum silicide layer that provides a low resistance electrical connection to the semiconductor material exposed in gate contact 54 and source contact 56. The titanium layer was formed to a thickness of 120 angstroms followed by an 800 angstroms titanium nitride barrier layer. Finally, an aluminum layer with a thickness of 3-4 microns is deposited.

A third photoresist step is used to pattern the metal film to form a source terminal 60 and a gate terminal 62. A similar blanket metal film is deposited on the bottom surface 63 of the substrate 12 to form a drain terminal 64 having a thickness of 3-4 microns.

A passivation layer (not shown) is deposited and patterned to produce the finished device. Note that additional masking steps may be included to provide additional or different features. For example, by patterning the drain electrode and/or terminal on the same surface as the source electrode/terminal, an additional photomasking step may be used to form semiconductor device 10 as a lateral or planar device rather than a vertical device. As another example, for high voltage applications, additional photomasks may be used to pattern the field shaping region around semiconductor device 10.

The vertical structure of the semiconductor device 10 can be understood with reference to its standard mode of operation. Assume that the source terminal 60 operates at a potential V of 0V_SThe gate terminal 62 receives a control voltage V that is greater than the conduction threshold of the semiconductor device 10_G2.5V and drain terminal 64 operates at a drain potential V_D5.0V. V_GAnd V_SIs such that body region 31 is inverted under vertical gate 40 to form channel 50, electrically connecting source region 45 to epitaxial layer 16. Device current I_SGenerally shown as a dashed line 65, from source terminal 60, bypasses through source region 45, channel 50, region 17, epitaxial region 16, and base layer 14 to drain terminal 64. Thus, current I_SFlows vertically through the substrate 12, resulting in a low on-state resistance. In one embodiment, I_S＝1.0A。

Fig. 5 illustrates a simplified top view of semiconductor device 10 showing some selected features of a vertical gate transistor layout. In this embodiment, the pedestal structure 24 is formed over a majority of the central region of the substrate 12 having source contacts 56 arranged in a plurality of rows for contacting source terminals 60 in a large area at the center of the substrate 12 to provide low on-resistance. Gate terminal 62 is formed to surround source terminal 60 as shown and contacts semiconductor layer 21 at gate contact 54 in order to maintain vertical gate 40 at a constant potential.

In embodiments where semiconductor device 10 is a high voltage device, a field stop structure is formed around a peripheral portion of substrate 12 using an additional photomask step. The field stop structure shapes the electric field caused by the high voltage applied to drain terminal 64 to prevent local breakdown, which may degrade the specified performance of semiconductor device 10.

In summary, the present invention provides a semiconductor device having a vertical gate to provide fast switching speed and high frequency performance. A pedestal structure is formed on a top surface of the substrate. The conductive material is disposed along a side surface of the pedestal structure as an edge of a source electrode of the self-aligned semiconductor device. A dielectric liner is formed along a side surface of the conductive material as a contact region for the self-aligned source electrode. The base structure is formed with a single photomasking step and the gate, source, and source contacts are sequentially self-aligned to the side surfaces, i.e., vertical walls, of the base structure. Thus, in embodiments where the transistor is fabricated as a vertical power device with a drain terminal on the bottom surface of the substrate, the transistor can be fabricated with only 4 photomasking steps including forming the gate contact, metallization, and passivation layers. One or more masking steps may be added to form a field termination or top surface drain terminal for high voltage operation to form a transistor as a planar device.

Claims (10)

1. A transistor, comprising:

a substrate having a top surface for forming a pedestal structure;

a conductive material disposed along a side surface of the base structure to define an edge of the first conductive electrode within the substrate; and

a dielectric liner formed along a side surface of the conductive material to define a contact region for the first conductive electrode,

wherein the first conductive electrode refers to an element that carries current through the transistor.

2. The transistor of claim 1, wherein the substrate comprises:

a semiconductor layer; and

a first dielectric layer formed on the semiconductor layer to support the pedestal structure, the conductive material, and the dielectric liner.

3. The transistor of claim 2 wherein the side surface of the dielectric liner defines a window in the first dielectric layer that exposes the semiconductor layer to form a contact region.

4. The transistor of claim 1 wherein the substrate is formed with a body region having an edge defined by a side surface of the pedestal structure.

5. The transistor of claim 4 wherein the conductive material inverts the body region to form a channel at the top surface of the substrate.

6. The transistor of claim 5, further comprising a transistor another conductive electrode formed at a surface of the substrate opposite the top surface.

7. The transistor of claim 1, wherein the base structure comprises:

a second dielectric layer formed on the top surface of the substrate;

a third dielectric layer formed on the second dielectric layer; and

a conductive layer formed of a conductive material on the third dielectric layer.

8. The transistor of claim 7, wherein the conductive material comprises polysilicon.

9. A semiconductor device, comprising:

a substrate having a top surface for doping source regions within the substrate and forming a channel of a semiconductor device;

a dielectric base formed on the top surface;

a control electrode formed along a side surface of the dielectric base so as to define an edge of the source region; and

a dielectric liner formed along a side surface of the control electrode to define a contact region of the source region.

10. A semiconductor device, comprising:

a substrate;

a first conductive material disposed on the first surface so as to define a conductive electrode of the semiconductor device at a second surface within the substrate perpendicular to the first surface; and

a dielectric liner formed on a surface of the first conductive material extending parallel to the first surface so as to define a contact area for the conductive electrode,

wherein the conductive electrode refers to an element that carries current through the semiconductor device.