HK1081381A

HK1081381A - Multi-layer circuit assembly and process for preparing the same

Info

Publication number: HK1081381A
Application number: HK06101196.4A
Authority: HK
Inventors: C. 奥尔森 K.; E. 王 A.
Original assignee: Ppg工业俄亥俄公司
Priority date: 2002-11-08
Filing date: 2003-11-07
Publication date: 2006-05-12

Description

Multi-layer circuit assembly and method of making the same

no marking

Cross Reference to Related Applications

This application is a continuation-in-part of U.S. patent application serial No.09/901,373, filed on 7, 9, 2001; it is a continuation-in-part of U.S. patent application Ser. No.09/851,904, filed on 9.5.2001, and it is a continuation-in-part of U.S. patent application Ser. No.09/802,001, filed on 8.3.2001, which are all incorporated herein by reference.

Background

I. Field of the invention

The present invention relates to the field of electronic circuitry, and more particularly to multilayer circuit assemblies, such as chip scale packages, and methods for their preparation.

Technical considerations

Electronic components, such as resistors, transistors, and capacitors, are typically mounted on a circuit board structure, such as a printed circuit board. Circuit boards typically comprise a generally flat sheet of dielectric material with electrical conductors disposed on a major, flat surface of the sheet, or on both major surfaces. The conductors are typically formed of a metallic material such as copper and serve to interconnect the various electronic components mounted on the circuit board. When conductors are disposed on both major surfaces of the board, the board may have via conductors that extend through holes (or "vias") in the dielectric layer to interconnect the conductors on the two opposing surfaces. Multilayer circuit board assemblies have heretofore been fabricated which employ multiple stacked circuit boards having additional layers of dielectric material for separating conductors on mutually facing surfaces of two adjacent boards in the stack. These multi-layer assemblies typically incorporate interconnections extending between conductors on the various circuit boards in the stack to provide the required electrical interconnections, as desired.

In microelectronic circuit packages, circuits and cells are fabricated at the packaging level in larger sizes. In general, the smallest size package level is typically a semiconductor chip that houses many microcircuits and/or other components. Such chips are typically made of ceramic, silicon, etc. An intermediate package level (i.e., a "chip carrier") comprising a multi-layer substrate may have attached thereto a plurality of small-scale chips housing a number of microelectronic circuits. Likewise, these intermediate package levels themselves can be attached to larger sized circuit cards, motherboards, etc. The intermediate package level serves several functions throughout the circuit assembly including structural support, transitional integration of smaller scale microcircuits and circuits on larger scale boards, and dissipation of heat from the circuit assembly. Substrates used in common intermediate package levels include a variety of materials, such as ceramics, glass fiber reinforced polyepoxy compounds, and polyimides.

The above-described substrates, while sufficiently rigid to provide structural support for the circuit assembly, typically have a coefficient of thermal expansion that is significantly different from the coefficient of thermal expansion of the microelectronic die to which they are attached. As a result, damage to the circuit assembly after repeated use may be at risk due to failure of the adhesive joints between the various layer assemblies.

Likewise, the dielectric materials used on the substrates must meet several requirements, including conformability (conformability), flame resistance, and compatible thermal expansion properties. Common dielectric materials include, for example, polyimides, polyepoxides, phenolic resins, and fluorocarbons. These polymer dielectrics typically have a coefficient of thermal expansion that is much higher than the coefficient of thermal expansion of the adjacent layers.

There is a growing demand for circuit board structures that provide high density, complex interconnections. Such a need can be addressed by multilayer circuit board structures, however, the manufacture of multilayer circuit assemblies has serious drawbacks.

Typically, multilayer boards are manufactured by providing single and double sided circuit boards that include appropriate conductors. The plates are then laminated one on top of the other with one or more layers of uncured or partially cured dielectric material, commonly referred to as "prepregs" disposed between adjacent plates of each pair. This stack is typically cured under heat and pressure to form a unitary member. After curing, holes are typically drilled in the stack locations where electrical connections between different boards are required. The formed holes or "vias" are then coated or filled with a conductive material, often by plating the interior of the holes to form plated vias. It is difficult to drill holes at high depth to diameter ratios and therefore the holes used in such assemblies must be large and consume a large amount of space in the assembly.

US patent No.6,266,874B 1 discloses a method of manufacturing a microelectronic element: providing a conductive substrate or "core"; providing a photoresist at selected locations on the conductive core; and electrophoretically depositing an uncured dielectric material on the conductive core except at locations covered by the photoresist. The document suggests that the electrophoretically deposited material can be a cationic acrylic-type or cationic epoxy-type composition known in the art and commercially available. The electrophoretically deposited material is then cured to form a conformal dielectric layer, and the photoresist is removed, whereby the dielectric layer has vias extending to the conductive core at locations covered by the photoresist. The holes formed and extending to the coated substrate or "core" are commonly referred to as "blind" holes. In one embodiment, the structural conductive element is a metal sheet containing continuous through holes or "vias" extending from one major surface to the opposite major surface. When the dielectric material is applied electrophoretically, the dielectric material is deposited at a uniform thickness over the conductive element surfaces and pore walls. It has been found, however, that the electrophoretically deposited dielectric materials proposed by this document are flammable and therefore do not need to meet typical flame retardancy requirements.

US patents 5,224,265 and 5,232,548 disclose methods of making multilayer thin film wiring structures for use in circuit assemblies. The dielectric material applied to the core substrate is preferably a fully cured and annealed thermoplastic polymer such as polytetrafluoroethylene, polysulfone, or polyimide-siloxane, preferably applied by lamination. Such dielectrics do not necessarily function as conformal coatings and do not have a low enough dielectric constant or dissipation factor to accommodate the high frequency circuitry currently designed for today's electronics market. In addition, the dielectric properties of conventional dielectric coatings are known to decrease at high frequencies.

Although the above identified documents disclose through holes ("vias") in the wiring structure, there is no recognition in the document of the need for higher via densities. High via density allows for a larger number of chip connections, which is required in highly functional chip scale packages for applications such as mobile phones and the like.

It should be noted that high via density in the circuit layer is critical to the operation of circuitry with a high number of chip connections; however, high via density also causes crosstalk. Therefore, circuit packages designed with high via density need to be fabricated using very efficient dielectrics that do not degrade at high frequencies.

US patent 5,153,986 discloses a method of manufacturing a metal core layer for a multilayer circuit board. Suitable dielectrics include vapor-depositable conformal polymer coatings. The method uses a solid metal core and the document describes the circuit design of the substrate in broad, generic terms. Intermediate packaging level circuit designs are often made by applying a positive or negative photoresist to a metal plated substrate, followed by exposure, development, and stripping to obtain the desired circuit pattern. Photoresist compositions are typically applied by lamination, spraying, or dipping. The applied photoresist layer may have a thickness of 5 microns to 50 microns.

In addition to the above-mentioned ceramic, glass fiber reinforced polyepoxides and polyimides, common substrates used in intermediate package levels further include solid metal sheets as disclosed in U.S. Pat. No.5,153,986. These solid substrates must be perforated during the manufacturing process of the circuit assembly to provide through holes for alignment purposes. Also, although this document discloses vias in the circuit layer, the need for higher via density is not recognized to accommodate highly functionalized chips.

In view of the state of the art methods, it would be desirable to provide a method of making a multi-layer circuit assembly that overcomes the disadvantages of the prior art. That is, it is desirable to provide a method of fabricating a multi-layer circuit assembly having a high via density to accommodate highly functionalized elements by using a highly efficient dielectric that does not degrade at high frequencies and meets additional requirements including conformality and flame resistance.

Summary of the invention

According to the present invention, there is provided a method of manufacturing a multi-layer circuit assembly comprising the steps of:

(a) providing a substrate having at least one area comprising a plurality of vias, the area having a via density of 500 to 10,000 holes per square inch (75-1550 holes per square centimeter);

(b) applying a dielectric coating to all exposed surfaces of the substrate to form a conformal coating; and

(c) a metal layer is applied to the entire surface of the substrate.

The present invention also relates to a method of manufacturing a multi-layer circuit assembly comprising the steps of:

(b) applying a photoresist on a predetermined position of a substrate;

(c) applying a dielectric coating to the entire surface of the substrate of step (b) except for the locations covered by the photoresist;

(d) removing the photoresist on the predetermined position; and

(e) applying a metal layer over the entire surface of the substrate of step (d).

Further, the present invention relates to a method of manufacturing a multi-layer circuit assembly comprising the steps of:

(b) applying a dielectric coating to all exposed surfaces of the substrate to form a conformal coating thereon;

(c) removing the dielectric coating over the predetermined pattern to expose portions of the substrate;

(d) applying a layer of metal over the entire surface to form metallized vias therethrough and/or to the conductive core;

(e) applying a photoresist on the metal layer to form a photosensitive layer;

(f) imaging the photoresist on the predetermined location; and

(g) developing the photoresist to expose selected areas of the metal layer; and

(h) the exposed areas of the metal are etched to form circuit patterns connected by the metallized vias.

In another embodiment, the present invention is directed to a multilayer circuit assembly comprising:

(a) a substrate having at least one area comprising a plurality of vias, the area having a via density of 500 to 10,000 holes per square inch (75-1550 holes per square centimeter);

(b) a dielectric coating applied to all exposed surfaces of the substrate;

(c) a metal layer applied to the entire surface of the substrate of step (b); and

(d) a photosensitive layer applied on the metal layer.

Detailed description of the invention

Other than in the operating examples, or where otherwise indicated, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and attached claims are approximations that may vary depending upon the desired properties to be obtained by the present invention. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of the claims, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

Also, it should be understood that any numerical range recited herein is intended to include all sub-ranges subsumed therein. For example, a range of "1 to 10" is intended to include all sub-ranges between and including the recited minimum value of 1 and the recited maximum value of 10, i.e., having a minimum value equal to or greater than 1 and a maximum value of equal to or less than 10.

As noted above, in one embodiment the present invention is directed to a method of making a multi-layer circuit assembly comprising the steps of: (a) providing a substrate having at least one area comprising a plurality of vias, the area having a via density of 500 to 10,000 holes per square inch (75-1550 holes per square centimeter); (b) applying a dielectric coating to all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a metal layer over the entire surface of the substrate.

The substrate (or "core") includes any of a variety of substrates. The substrates used in the process for making the multi-layer circuit assembly of the present invention are typically conductive substrates, particularly metal substrates, such as untreated or galvanized steel, aluminum, gold, nickel, copper, magnesium, or alloys of any of the foregoing, as well as materials having a conductive carbon coating. Also, the core has two major surfaces and edges and can have a thickness of from 10 to 100 microns, typically from 25 to 100 microns.

In one embodiment of the invention, the substrate comprises a metal substrate selected from the group consisting of copper foil, iron-nickel alloys, and combinations thereof. In one embodiment of the invention, the substrate comprises a perforated substrate comprised of any of the above-described metals or combinations thereof.

In one embodiment of the invention, the substrate comprises a perforated copper foil. In another embodiment, the substrate comprises a nickel-iron alloy. A preferred iron-nickel alloy is INVAR, (a trademark owned by imphys.a., 168 Rue de Rivoli, Paris, France) comprising about 64 wt% iron and 36 wt% nickel. This alloy has a low coefficient of thermal expansion, comparable to that of the silicon material used to prepare the chip. This property is desirable to prevent the destruction of adhesive joints between successive larger or smaller scale layers of a chip scale package due to thermal cycling during normal use.

As previously described, at least one region of the substrate comprises a plurality of vias, the region having a via density of 500 to 10,000 holes per square inch (75-1550 holes per square centimeter), and typically at least 2500 holes per square inch (387.5 holes per square centimeter). That is, the substrate can be a sheet of any of the above-described substrate materials, wherein only some regions are perforated and some regions are unperforated; alternatively, the substrate can be a "perforated substrate" of any of the aforementioned substrate materials. All that is required for the purposes of the present invention is that at least one region of the substrate have a specified via density.

"perforated" substrate refers to a web having a plurality of apertures at regular intervals. Typically the holes (or vias) are of uniform size and shape. When the holes are circular, which is typical, the diameter of the holes is about 8 mils (203.2 microns). The pores may be larger or smaller, as desired, provided that the pores are large enough to accommodate the various layers applied in the method of the invention but not so large as to become clogged. The pitch of the holes is about 20 mils (508 microns) center-to-center, but may be larger or smaller as desired.

A layer of metal (usually copper) may be applied to the substrate to ensure optimum conductivity prior to application of the dielectric coating in step (b) as described below. This metal layer, as well as layers applied in subsequent metallization steps, can be applied by conventional methods, such as by electroplating, metal vapor deposition techniques, and electroless plating. The metal layer typically has a thickness of 1-10 microns.

As previously discussed, the application of the dielectric coating to all exposed surfaces of the substrate forms a conformal coating. As used herein in the specification and in the claims, a "conformal" film or coating refers to a film or coating having a substantially uniform thickness that conforms to the topography of the substrate including surfaces within the pores (but, preferably, not obstructing the pores). The dielectric coating film thickness can be no more than 50 microns, usually no more than 25 microns, and typically no more than 20 microns. Lower film thicknesses are desirable for a variety of reasons. For example, dielectric coatings with low film thickness allow for smaller scale circuits.

The dielectric coating can have a dielectric constant of no more than 4.00, sometimes no more than 3.50, often no more than 3.30, often no more than 3.00, and typically no more than 2.80. Also, the cured film typically has a dielectric loss factor of less than or equal to 0.02, often less than or equal to 0.15, and can be less than or equal to 0.01. Also, coatings with low dielectric constants make it possible to obtain dielectric coatings with lower film thicknesses and the attendant advantages, as well as minimizing capacitive coupling between adjacent signal traces.

The dielectric material is a non-conductive substance or insulator. "dielectric constant" is an index or measure of the ability of a dielectric material to store charge. The dielectric constant is proportional to the capacitance of the material, which means that if the dielectric constant of the material is reduced, the capacitance will be reduced. Low dielectric materials are desirable for high frequency, high speed digital applications where the capacitance of the substrate and coating is critical for reliable function of the circuit. For example, computer operation is currently limited by the coupling capacitance between the circuit paths on the multi-layer assembly and the integrated circuits, as the computational speed between the integrated circuits is reduced by this capacitance and the power required for operation is increased. See Thompson, Larry F. et al, Polymers for Microelectronics, published on the 203rd National Meeting of the National institute of chemistry (the 203rd National Meeting of American Chemical Society), 4.4.10.1992.

"dielectric dissipation factor" is the power dissipated by a dielectric material when the friction of the molecules of the dielectric material resists the molecular motion generated by an alternating electric field. See, i.e., gilleo, Ken, handbook of flex Circuits, page 242, Van nonstrand Reinhold, New York (1991). For a detailed discussion of the dielectric materials and dielectric constants, see also James J. Licari and Laura A. Hughes, Handbook of Polymer Coatings for electronics, p.114-118, second edition, Noyes Publication (1990).

For the present invention, the dielectric constant of the dielectric coating is determined at a frequency of 1 megahertz using electrochemical impedance spectroscopy as follows. The coating samples were prepared by applying the dielectric coating composition to a steel substrate followed by subsequent drying or curing of the coating to provide a dielectric coating having a film thickness of 0.85 mils (20.83 microns). A 32 cm square unlined film of dielectric coating was placed into an electrochemical cell with 150 ml of electrolyte solution (1M NaCl) and allowed to equilibrate for one hour. The impedance was measured from a frequency range of 1.5 mhz to 1 hz with 100mV of AC potential applied to the sample. The method uses a platinum/niobium expanded mesh counter electrode and a single junction silver/silver chloride reference electrode. The dielectric constant of the coating can be determined by calculating the capacitance at 1 megahertz, 1 kilohertz, and 63 hertz and solving the following equation for E.

C＝E_oEA/d

Where C is the capacitance (Faraday) measured at a discrete frequency; e_oPermittivity of free space (8.854187817)¹²) (ii) a A is the sample area (32 square centimeters); d is the coating thickness; and E is the dielectric constant. It should be noted that the value of the dielectric constant used in the specification and claims is the dielectric constant measured at a frequency of 1 mhz as described above. Likewise, the value of the dielectric loss factor is determined as the difference between the dielectric constant measured at a frequency of 1 megahertz as described above and the dielectric constant measured at a frequency of 1.1 megahertz for the same material.

The dielectric coating may be formed from any of a variety of coating compositions, as will be discussed below. The dielectric coating can be formed from a thermoplastic composition in which, once applied, the solvent (i.e., organic solvent and/or water) is driven off or evaporated, thereby forming a film of dielectric coating on the substrate. The dielectric coating can also be formed from a curable or thermoset composition, wherein once the composition is applied to a substrate and cured, a cured film of the dielectric coating is formed. The dielectric coating can be any coating applied by any paint application technique, provided that the resulting coating is a conformal coating having a sufficiently low dielectric constant to ensure adequate insulation properties and fire resistance as determined by IPC-TM-650, "Test Methods Manual, Number 2.3.10," flexibility of amine ", revision B, available from the Institute of Interconnecting and Packaging electronic circuits, 2215 Sanders Road, thnoise, Illinois.

The dielectric coating used in the method of the present invention may be applied by any suitable conformal coating method including, for example, dip coating, vapor deposition, electrodeposition and auto-electrophoretic deposition.

Examples of dielectric coatings applied by vapor deposition include poly (p-xylylene) (including substituted and unsubstituted poly (p-xylylene)); silsesquioxanes such as those disclosed in US patent nos. 5,711,987 and 6,144,106; polybenzocyclobutene and polyimide.

Examples of dielectric coatings applied by electrodeposition include anodic and cathodic acrylic, epoxy, polyester, polyurethane, polyimide or oleoresin compositions, as are known to those skilled in the art. The dielectric coating can also be formed by electrodeposition of any of the electrodepositable photosensitive compositions described below.

In a particular embodiment of the invention, the dielectric coating is applied to the substrate by electrodeposition of an electrodepositable coating composition comprising a resinous phase dispersed in an aqueous medium, wherein the resinous phase has a covalently bonded halogen content of at least 1 weight percent, based on the total weight of resin solids present in the resinous phase. Such electrodepositable coating compositions and methods of application of the compositions are described in detail in pending US patent application serial nos. 10/184,192 and 10/184,195.

Any of the foregoing electrodepositable coating compositions can be electrophoretically applied to a conductive substrate (or a substrate that has been rendered conductive, such as by metallization). The applied voltage for electrodeposition can vary and can be, for example, as low as 1 volt up to several thousand volts, but is typically between 50 and 500 volts. The current density is typically between 0.5 and 5 amps per square foot (0.5-5 milliamps per square centimeter) and tends to drop during electrodeposition, indicating the formation of an insulating conformal coating film over the entire exposed surface of the substrate. After the coating has been applied by electrodeposition, it is typically cured, usually at an elevated temperature of 90-300 ℃ for 1-40 minutes, to form a conformal dielectric coating on all exposed surfaces of the substrate.

Generally, autophoresis, also known as chemiphoresis, is a coating process that deposits an organic coating on a metal surface from an acidic aqueous coating composition in a dip tank. The method comprises the controlled release of metal ions from the surface of the substrate due to the low pH of the aqueous composition, thereby destabilizing the polymer dispersed in the aqueous phase in the immediate vicinity of the substrate to be coated. This causes agglomeration of the polymer particles and deposition of the agglomerated polymer on the substrate surface. As the coating thickness increases, the deposition slows, resulting in an overall uniform coating thickness. See, r.lambourne et al, Paint and Surface Coatings, William Andrew Publishing, second edition, volume 12, page 510. Examples of compositions suitable for use as an autophoretically applied dielectric coating include those described in detail in US patent nos. 4,310,450 and 4,313,861.

After application of the dielectric coating, the dielectric coating can be removed at one or more predetermined locations to expose one or more portions of the substrate surface. The dielectric coating can be removed by various methods, such as by ablation techniques. The ablation is typically performed using a laser or by other conventional methods, such as mechanical drilling and chemical or plasma etching techniques.

Metallization is typically performed after the removal step by applying a layer of metal over the entire surface such that metallized vias (i.e., vias) are formed through the substrate and/or metallized vias (i.e., blind vias) are formed to (but not through) the substrate or core. Alternatively, the metallization can be performed before the removal step, after which additional metallization can be performed if necessary. The metal applied in this metallization step can be any of the aforementioned metals or alloys, as long as the metal or alloy has sufficient conductive properties. Typically, the metal applied in the above-described metallization step is copper. The metal applied in any of the metallization steps used in the method of the present invention may be applied by conventional electroplating, seed electroplating, metal vapor deposition, or any other method as described above that provides a uniform layer of metal. The thickness of the metal layer is typically about 5 to 50 microns.

To enhance the adhesion of the metal layer to the dielectric coating, the entire surface is treated with an ion beam, electron beam, corona discharge or plasma bombardment prior to the metallization step, followed by the application of an adhesion promoter layer on the entire surface. The adhesion promoter layer can have a thickness of 50-5000 angstroms and is typically a metal or metal oxide selected from chromium, titanium, nickel, cobalt, cesium, iron, aluminum, copper, gold, tungsten, and zinc, and alloys and oxides thereof.

Also, the substrate surface may be pretreated or otherwise treated prior to application of the dielectric coating in preparation for application of the dielectric material. For example, cleaning, rinsing, and/or treatment with an adhesion promoter prior to application of the dielectric is suitable.

After metallization, a photosensitive layer (formed from a "photoresist" or "photoresist" composition) is applied to the metal layer. Optionally, the substrate metallized prior to application of the photosensitive layer can be cleaned and pretreated; for example, treatment with an acid etchant removes oxidized metal. The photosensitive layer can be positive or negative type photosensitive. The photosensitive layer typically has a thickness of about 2 to 50 microns and can be applied by any method known to those skilled in the art of photolithographic processing. Additives or printed circuit processing methods may be used to create the desired circuit pattern.

Suitable positive photosensitive resins include any of those known to those skilled in the art. Examples include dinitrobenzyl-functional polymers such as those disclosed in U.S. Pat. No.5,600,035, columns 3-15. Such resins are highly photosensitive. In one embodiment, the resinous photosensitive layer is a composition comprising a dinitrobenzyl functional polymer, typically applied by a spray coating process. Nitrobenzyl functional polymers known to those skilled in the art are also suitable.

In a separate embodiment, the photosensitive layer is an electrodepositable composition comprising a dinitrobenzyl functional polyurethane and an epoxy-amine polymer, as described in examples 3-6 of US patent No.5,600,035.

Negative photoresists include liquid or dry film type compositions. The liquid composition may be applied by a roll coating technique, curtain coating, or electrodeposition. Preferably, the liquid photoresist is applied by electrodeposition, more preferably cationic electrodeposition. The electrodepositable composition comprises an ionic polymeric material, which may be cationic or anionic, and may be selected from polyesters, polyurethanes, acrylics, and polyepoxides. An example of a photoresist applied by anionic electrodeposition is given in US patent 3,738,835. Photoresists applied by cationic electrodeposition are described in US patent 4,592,816. Examples of dry film photoresists include those disclosed in US patents 3,469,982, 4,378,264, and 4,343,885. Dry film photoresists are typically laminated to a surface by the application of heated rollers.

It should be noted that after application of the photosensitive layer, the multi-layer substrate can be packaged at this point for ease of transport and handling for any subsequent steps at a remote location.

In a particular embodiment, the present invention is directed to a method of making a multi-layer circuit assembly comprising the steps of: (a) providing a substrate (such as any of the substrates described in detail above) having at least one area comprising a plurality of vias, the area having a via density of 500 to 10,000 holes per square inch (75-1550 holes per square centimeter) and typically at least 2500 holes per square inch (387.5 holes per square centimeter); (b) applying a photoresist (such as any of the photoresist compositions described in detail above) on the substrate at the predetermined locations; (c) applying a dielectric coating (such as any of the dielectric coatings described in detail above) to all surfaces of the substrate of step (b) except where covered by the photoresist; (d) removing the photoresist at the predetermined locations (e.g., by any of the methods described above); and (e) applying a layer of metal (e.g., copper) over the entire surface of the substrate of step (d).

In any of the methods of the present invention, after the photosensitive layer is applied, a photomask having the desired pattern is placed over the photosensitive layer, and the laminated substrate is then exposed to a sufficient level of a suitable source of actinic radiation. The term "sufficient level of actinic radiation" as used herein refers to a level of radiation dose that polymerizes these monomers in the radiation-exposed regions for negative-tone photoresists, or that promotes depolymerization or renders the polymer more soluble for positive-tone photoresists. This results in a solubility difference between the radiation exposed areas and the radiation shielded areas.

The photomask may be removed after exposure to the radiation source and the laminated substrate developed using a common developer to remove the more soluble portions of the photosensitive layer and expose selected areas of the underlying metal layer. The exposed metal in this step is then etched using a metal etchant that converts the metal to a water-soluble metal complex. The soluble complex may be removed by water spraying.

The photosensitive layer protects any metal that is under it during the etching step. The remaining photosensitive layer, which is unaffected by the etchant, is then removed by a chemical lift-off process to provide a circuit pattern connected by the metallized vias formed as described above.

The total thickness of the multilayer circuit assembly after removal of the photosensitive layer is typically about 25-360 microns, preferably 35-210 microns.

In yet another embodiment, the present invention is directed to a method of making a multi-layer circuit assembly comprising the steps of: (a) providing a substrate (such as any of the substrates described in detail above) having at least one area comprising a plurality of vias, the area having a via density of 500 to 10,000 holes per square inch (75-1550 holes per square centimeter) and typically at least 2500 holes per square inch (387.5 holes per square centimeter); (b) applying a dielectric coating (such as any of those described in detail above) to all exposed surfaces of the substrate to form a conformal coating; (c) removing the dielectric coating (by any of the removal methods described above) in a predetermined pattern to expose portions of the substrate; (d) applying a layer of metal (by any of the metallization techniques described above) on all surfaces to form a metallized via through and/or to the conductive core; (e) applying a photoresist (any of the photosensitive compositions described above) to the metal layer to form a photosensitive layer; (f) imaging the photoresist (as described above) at the predetermined locations; (g) developing the photoresist (as described above) to expose selected areas of the metal layer; and (h) etching (as described above) the exposed areas of the metal to form circuit patterns connected by the metallized vias.

It should be understood that any of the methods of the present invention can include one or more additional steps without departing from the scope of the present invention. Likewise, the order in which the various steps are performed may be changed as desired without departing from the scope of the invention.

The present invention also relates to a multi-layer circuit assembly made by any of the foregoing methods. In one embodiment, the present invention is directed to a multilayer circuit assembly comprising: (a) a substrate (such as any of the substrates described in detail above) having at least one area comprising a plurality of vias, the area having a via density of 500 to 10,000 holes per square inch (75-1550 holes per square centimeter) and typically at least 2500 holes per square inch (387.5 holes per square centimeter); (b) a dielectric coating (such as any of the dielectric coatings described previously) applied to all exposed surfaces of the substrate; (c) a layer of any of the foregoing metals (typically copper) suitable for metallization; and (d) a photosensitive layer (e.g., any of the aforementioned photosensitive compositions). Application of the dielectric coating, metal layer, and photosensitive layer can be performed by any of the various application methods described in detail above.

After preparation of the circuit pattern on the multilayer substrate, other circuit elements may be attached in one or more subsequent steps to form a circuit assembly. Additional components can include one or more of a multi-layer circuit assembly prepared by any of the methods of the present invention, components of smaller size grades such as semiconductor chips, interposers, circuit cards or motherboards of larger size grades, and active or passive components. It should be noted that the interposer used in the preparation of the circuit assembly may be prepared by using the appropriate steps of the method of the present invention. These components may be attached using common adhesives, surface mount techniques, wire bonding or flip chip techniques.

The high via density in the multi-layer circuit assembly prepared according to the present invention allows for more electrical interconnections in the assembly from highly functionalized chips to packages.

Those skilled in the art will recognize that changes can be made to the embodiments without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A method of making a multi-layer circuit assembly comprising the steps of:

(b) applying a dielectric coating to all exposed surfaces of the substrate to form a conformal coating thereon; and

(c) a metal layer is applied to the entire surface of the substrate.

2. The method of claim 1, further comprising, as step (e), applying a photosensitive layer to the metal layer.

3. The method of claim 1, further comprising, prior to applying the metal layer of step (c), removing the dielectric coating at one or more predetermined locations to expose one or more portions of the surface of the substrate.

4. The method of claim 1, further comprising, prior to applying the metal layer of step (c), applying a photoresist at predetermined locations on the dielectric coating applied in step (b).

5. The method of claim 1, wherein the substrate comprises a conductive substrate.

6. The method of claim 5, the substrate comprising a metal substrate selected from the group consisting of copper foil, iron-nickel alloys, and combinations thereof.

7. The method of claim 5, the substrate comprising a perforated metal substrate.

8. The method of claim 7, wherein the substrate comprises a perforated copper foil.

9. The method of claim 6, wherein the metal substrate comprises a nickel-iron alloy.

10. The method of claim 5, wherein a layer of copper metal can be applied to the substrate prior to the application of the dielectric coating in step (b).

11. The method of claim 1, wherein the dielectric coating is applied by vapor deposition.

12. The method of claim 11, wherein the dielectric coating is poly (p-xylylene).

13. The method of claim 1, wherein the dielectric coating is applied by electrodeposition.

14. The method of claim 1, wherein the dielectric coating is applied by an automated electrophoresis method.

15. The method of claim 13, wherein the dielectric coating comprises a photosensitive composition.

16. The method of claim 1, wherein prior to step (d) the entire surface is treated with ion beam, electron beam, corona discharge or plasma bombardment followed by application of an adhesion promoter layer over the entire surface.

17. The method of claim 16, wherein the adhesion promoter layer comprises a metal or metal oxide selected from one or more of chromium, titanium, nickel, cobalt, cesium, iron, aluminum, copper, gold, zinc, and oxides thereof.

18. The method of claim 1, wherein the metal layer applied in step (c) comprises copper.

19. The method of claim 2, wherein the photosensitive layer comprises a positive photosensitive layer applied by electrodeposition.

20. The method of claim 1, wherein at least one area of the substrate comprises a plurality of vias, the area having a via density of at least 2500 holes per square inch (387.5 holes per square centimeter).

21. A method of making a multi-layer circuit assembly comprising the steps of:

(b) applying a photoresist on a predetermined position of a substrate;

(d) removing the photoresist on the predetermined position; and

22. The method of claim 21, wherein the substrate comprises a conductive substrate.

23. The method of claim 22, the substrate comprising a metal substrate selected from the group consisting of copper foil, iron-nickel alloys, and combinations thereof.

24. The method of claim 23, wherein the substrate comprises a perforated copper foil.

25. The method of claim 23, wherein the substrate comprises a nickel-iron alloy.

26. The method of claim 21, wherein the dielectric coating is applied by vapor deposition.

27. The method of claim 21, wherein the dielectric coating is applied by electrodeposition.

28. The method of claim 27, wherein the dielectric coating comprises a photoresist composition.

29. The method of claim 21, wherein the dielectric coating is applied by an automated electrophoresis method.

30. The method of claim 21, wherein the metal layer applied in step (c) comprises copper.

31. The method of claim 21, wherein at least one area of the substrate comprises a plurality of vias, the area having a via density of at least 2500 holes per square inch (387.5 holes per square centimeter).

32. A method of making a multi-layer circuit assembly comprising the steps of:

(c) removing the dielectric coating at the predetermined locations to expose portions of the substrate;

(d) applying a layer of metal over the entire surface to form a metallized via through and/or to the conductive core;

(e) applying a photoresist to the metal layer to form a photosensitive layer thereon;

(f) imaging the photoresist on the predetermined location;

(g) developing the photoresist to expose selected areas of the metal layer; and

33. The method of claim 32, further comprising, as step (i), stripping the remaining resinous photosensitive layer.

34. The method of claim 32, further comprising the steps of: one or more circuit elements are attached.

35. The method of claim 34, wherein the assembly is packaged after step (e) for ease of transport and subsequent processing steps at a remote location.

36. The method of claim 32, wherein the substrate comprises a conductive substrate.

37. The method of claim 36, wherein the substrate comprises a perforated metal substrate having a via density of at least 2500 holes per square inch (387.5 holes per square centimeter).

38. The method of claim 36, wherein the perforated metal substrate comprises a metal substrate selected from the group consisting of perforated copper foil, iron-nickel alloys, and combinations thereof.

39. The method of claim 38, wherein the metal substrate comprises a nickel-iron alloy.

40. The method of claim 39, wherein a layer of copper metal can be applied to the metal substrate prior to application of the dielectric coating.

41. The method of claim 32, wherein the dielectric coating is applied by vapor deposition.

42. The method of claim 41, wherein the dielectric coating comprises poly (p-xylylene).

43. The method of claim 32, wherein the dielectric coating is applied by electrodeposition.

44. The method of claim 43, wherein the dielectric coating comprises a photosensitive composition.

45. The method of claim 32, wherein the dielectric coating is applied by an automated electrophoresis method.

46. The method of claim 32, wherein prior to step (d) the entire surface is treated with ion beam, electron beam, corona discharge or plasma bombardment followed by application of an adhesion promoter layer over the entire surface.

47. The method of claim 46 wherein the adhesion promoter layer comprises a metal or metal oxide selected from one or more of chromium, titanium, nickel, cobalt, cesium, iron, aluminum, copper, gold, zinc, and oxides thereof.

48. The method of claim 32, wherein the metal layer applied in step (d) comprises a copper layer.

49. The method of claim 32, wherein the photoresist is applied in step (e) by electrodeposition.

50. A multi-layer circuit assembly made by the process of claim 1.

51. A multi-layer circuit assembly made by the process of claim 32.

52. A multi-layer circuit assembly comprising:

(b) a dielectric coating applied to all exposed surfaces of the substrate;

(d) a photosensitive layer applied on the metal layer.

53. The multi-layer circuit assembly of claim 52, wherein the substrate comprises a conductive substrate.

54. The multi-layer circuit assembly of claim 52, wherein the dielectric coating is removed at predetermined locations prior to application of the metal layer (c).

55. The multi-layer circuit assembly of claim 53, wherein the conductive substrate comprises a metal substrate selected from the group consisting of a perforated copper foil, an iron-nickel alloy, and combinations thereof.

56. The multi-layer circuit assembly of claim 55, wherein the substrate comprises a nickel-iron alloy.

57. The multi-layer circuit assembly of claim 56, further comprising an intervening layer of copper metal between the metal substrate and the dielectric coating.

58. The multi-layer circuit assembly of claim 52, wherein the dielectric coating is applied by vapor deposition.

59. The multi-layer circuit assembly of claim 58, wherein the dielectric coating is poly (p-xylylene).

60. The multi-layer circuit assembly of claim 52, wherein the dielectric coating is applied by electrodeposition.

61. The multi-layer circuit assembly of claim 60, wherein the dielectric coating comprises a photosensitive composition.

62. The multi-layer circuit assembly of claim 52, wherein the dielectric coating is applied by an automated electrophoresis process.

63. The multi-layer circuit assembly of claim 52, further comprising an adhesion promoter layer applied to all surfaces prior to application of the metal (c) layer.

64. The multi-layer circuit assembly of claim 63, wherein the adhesion promoter layer comprises a metal or metal oxide selected from one or more of chromium, titanium, nickel, cobalt, cesium, iron, aluminum, copper, gold, zinc, and oxides thereof.

65. The multi-layer circuit assembly of claim 52, wherein the metal layer (c) comprises a copper layer.

66. The multi-layer circuit assembly of claim 52, wherein the photosensitive layer (d) comprises a positive photosensitive layer applied by electrodeposition.

67. The multi-layer circuit assembly of claim 52, wherein the substrate comprises a perforated metal substrate having a via density of at least 2500 holes per square inch (387.5 holes per square centimeter).