HK1081013B - History based measured power control response - Google Patents

Description

History-based measured power control response

RELATED APPLICATIONS

This application claims priority to prior provisional application 60/398,264 filed on 23/7/2002.

I. Field of the invention

The present invention relates to the field of wireless communications, and more particularly, to a method and apparatus for responding to power control commands received on a channel reverse link in the case of queuing and batching received transmission frames.

II. background of the invention

Advances in satellite communications and related technology have led to rapid growth in Mobile Satellite Services (MSS) in recent years. While economic factors slow the growth of these systems, tens of thousands of user terminals are currently in use, providing important services in many areas as compared to no communication service.

In addition to user terminals, the delivery of mobile satellite services typically involves the provision of space vehicles, i.e., satellites, and a number of gateways, also referred to as base stations. The satellite acts as a "relay" between the gateway and the user terminal.

Power control is typically employed to manage the exchange of signals between the user terminal and the gateway via one or more satellites. In particular, the power control commands are in the form of, for example, power control bits, which are typically included in transmission frames received on the reverse link of a channel (also referred to as the return link of the channel).

In the context of an MSS, a channel corresponds to an assigned frequency. In a multiple access environment, such as in the case of Time Division Multiple Access (TDMA), a channel is divided into multiple time slots, with each user terminal being assigned one or more time slots. The sum of these slots plus some overhead data bits corresponds to one transmission frame. Similarly, in the case of code division multiple access, a channel is shared among multiple simultaneous users by encoding each user's transmission with an orthogonal or near-orthogonal spreading code.

The increase in the number of users and the usage of users results in increased data traffic, which in turn increases the amount of transmission from the user terminals and the processing performed by the gateway. To facilitate handling the increased throughput, some gateways may wish to queue transmission frames received on the channel reverse link and process them in batches.

Power control is important in CDMA systems for optimum capacity, so each transmission frame of user traffic (e.g., voice or data) typically carries a power control command (typically a single bit, indicating power increase or decrease of one) for the transmitter at the other end of the communication link. If it responds in the same manner in a queued/batch processing environment as it responds to power control instructions in a real-time non-queued/non-batch processing environment, it may result in excessive consecutive identical power control commands being generated due to the delay inserted in the power control loop by queuing. The overly continuous issuance of the same power control commands in turn results in a loss of the channel or communication link.

Thus, an improved method of responding to power control commands when transmission frames are queued or processed in batches is desired.

Disclosure of Invention

Briefly, the present invention provides a method and apparatus to slow the response or rate of response to power control commands determined or generated by a receiver for an opposite or corresponding transmitter over a communication link and included in each frame received over a channel-link. If the receiver determines that the relative or corresponding received transmission is too weak, it may include a power-on command proposal for each received frame, and vice versa.

Under operating conditions, a first set of frames received on a link is queued for later batch processing. To slow down the response to the power control instructions included in the received frame, the instructions or commands are examined and a running history of a predetermined length is maintained. A second set of frames sent on the link in the opposite direction of the channel are also queued for later batch processing. Power control instructions are generated for inclusion within the queued frames to be transmitted based at least in part on the maintained or maintained history in order to achieve a desired slowing down of the response to the incoming power control instructions.

In accordance with one aspect of the invention, for a typical communication system or link, the power control commands and responses are in the form of power control bits, and the predetermined length of the history is on the order of 2 bits. The m "zero" value power control bits and the n "one" value power control bits generated for inclusion in a frame to be transmitted depend on the 2-bit historical bit pattern, and the two values may be the same or differ by, for example, 1 regardless of whether the second set of frames contains an even or odd number of frames.

The method and apparatus of the hold and generate operation may be performed within a gateway of a wireless communication system or within a simulation gateway and gateway simulator of a wireless communication test system.

In a further aspect, a wireless communication system gateway uses a transceiver to receive a first set of frames on a link of a channel, and to queue the first set of frames for batch processing, each frame including a power control instruction, and to output the power control instruction included in each of the first set of frames. A processing subsystem coupled to the transceiver processes or examines information in the queued first set of frames to receive power control commands and generates a second set of frames on the channel for a reverse link, which frames may also be queued before being processed in the transceiver. The processing subsystem: a continuous history of verified power control instructions included within the first set of frames is maintained until a predetermined length of time, and power control commands are generated for the second set of frames based at least in part on this maintained or maintained continuous history in a manner that slows a response or rate of response to the power control instructions.

In other aspects of the gateway, the processing subsystem is configured to generate m "zero" value power control bits and n "one" value power control bits for each batch formed by the second set of frames, the number depending on whether there are an even number of frames or an odd number of frames, and the information bit value of the control command.

In a further embodiment, the wireless communication device has a gateway emulator configured to emulate receipt of a first set of frames in a channel link direction, and to group or queue the first set of frames for batch processing, the frames including or accompanied by power control instructions. The gateway emulator provides power control instructions with each of the first set of frames. A gateway simulator coupled to the gateway simulator processes the queued first set of frames in a batch form and receives or detects values of power control instructions processed by the gateway simulator and generates a second set of frames for the reverse link of the channel that are also queued before being processed in a batch form by the gateway simulator. The gateway simulator maintains a continuous history of a predetermined length for power control instructions included within the first set of frames and generates corresponding power control commands for the second set of frames based at least in part on the maintained continuous history in a manner that slows responses to the power control instructions. The gateway simulator is designed to generate m "zero" value power control bits and n "one" value power control bits for each batch formed by a subset of the second set of frames, as desired.

In a further embodiment, an apparatus is provided for achieving the advantages and features of the present invention having means for maintaining a continuous history of a predetermined length for power control commands included in a first set of frames received in a direction on a communication channel link, the first set of frames being grouped prior to processing thereof, and means for generating power control commands for a second set of frames transmitted in a reverse direction on the channel link based at least in part on the maintained continuous history in a manner that slows down responses to incoming power control commands, the second set of frames also being grouped for subsequent processing in batches for transmission.

The operations of the present invention may be implemented in a machine-readable medium having stored thereon machine-executable instructions that, when executed, implement a method comprising: maintaining a continuous history of a predetermined time or length for power control commands included within a first set of frames received on a link of a channel, the first set of frames being grouped prior to processing thereof; and generating power control commands for a second set of frames transmitted in a reverse direction on the channel link based at least in part on the detected and maintained continuous history, the generating being capable of slowing a response or rate of response to received power control instructions, the second set of frames also being grouped for processing by a subsequent batch for transmission.

Drawings

Examples of the invention are illustrated by way of example in the accompanying drawings. However, these drawings do not limit the scope of the present invention. Like reference symbols in the various drawings indicate like elements.

FIG. 1 illustrates a method of the present invention in accordance with one embodiment;

FIG. 2 illustrates further detailing the history-based power control generation of FIG. 1, in accordance with an embodiment;

FIG. 3 illustrates an exemplary gateway in which the present invention may be implemented in an embodiment;

FIG. 4 illustrates a satellite-based wireless communication system in which the example gateway of FIG. 3 may be used in an embodiment;

FIG. 5 illustrates an example gateway emulator and an example gateway simulator in which the present invention may be implemented in an embodiment;

FIG. 6 illustrates a wireless communication test system in which the example gateway emulator and simulator of FIG. 5 may be used in an embodiment;

FIG. 7 illustrates one embodiment of a hardware system for implementing various embodiments; and

FIG. 8 illustrates one embodiment of a machine-readable medium to hold executable instructions to implement various embodiments.

Detailed Description

Various embodiments of methods and apparatus for slowing down a response to a power control command will now be described for reducing the likelihood of issuing excessive consecutive power control commands that may result in a loss of a channel or communication link in wireless communications to a wireless communication system or device.

Various aspects of these embodiments will be described in the following description. It will be apparent, however, to one skilled in the art that the present invention may be practiced with only some or all aspects of these embodiments. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the present invention. However, it will also be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known features are omitted or simplified in order not to obscure the present invention.

Reference herein to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, operation, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.

General examples

Referring now to FIG. 1, there is shown a block diagram illustrating a general embodiment of the present invention. This general embodiment specifically includes the bulk logic 104 and the power control command generator/filler 118, both of which are included in the principles of the present invention. This embodiment also includes a storage location, element or device 110. In addition, this embodiment also includes batch processing logic 108 and a frame generator 114. These elements are operatively coupled to each other as shown.

Transmission frames 102 received on a channel-link, such as a reverse or Return Link (RL) where signals are transmitted from a transmitter in a user terminal to a receiver in a gateway, are queued or grouped or batched using batching logic 104 into batches of frames 106 for subsequent batching by, for example, batching logic 108. Furthermore, it is arranged to output the power control commands R comprised by the received transmission frames 102, such that a continuous history of comprised power control commands of a predetermined length or time period can be maintained or maintained.

For one embodiment, the memory 110 is used to store, contain, or maintain a continuous history of a predetermined length. As described in detail below, the continuous history is employed in generating power control responses or commands that are used to slow down the response behavior or response to power control commands, thereby reducing the likelihood of issuing overly continuous power control commands that could result in channel loss.

The batch processing logic 108, as the name implies, is used to process batches of frames 106. The essential nature of the processing performed is not relevant to the implementation of the invention and can be understood by those skilled in the art of the system.

Frame generator 114 is used to organize traffic/signals to be transmitted over a channel-link, such as the Forward Link (FL) where the signals are transmitted from a transmitter in a gateway to a receiver in a user terminal, into a plurality of frames 116. The manner in which traffic/signals are transmitted is also not relevant to the implementation of the present invention and will be understood by those skilled in the art of the particular communication system employed.

The power control command generator/stuffer 118 is operative to generate and insert power control commands P into frames 116 to be transmitted on the channel forward link. For this embodiment, it also queues frames 116 into batches of frames 120, which are then processed in batches or groups by a general transceiver subsystem (not shown).

Thus, operationally, upon receipt of a transmission frame 102 on the reverse or return link of the channel, the transmission frame 102 is queued or organized by the batching logic 104 into RL batch frames 106 for subsequent batching, such as by batching logic 108. At the same time, a continuous history of included power control instructions is maintained in memory 110, the continuous history being a predetermined length or period of time for subsequent use in slowing down the response to power control instructions.

After the transmit traffic and signals 112 are organized into transmission frames 116 by the frame generator 114 for transmission on the channel forward link, the generated frames 116 are also provided to the power control response generator/stuffer 118 for generation and insertion of the power control response for transmission with the transmission frames 116.

According to the described embodiment, the generator/stuffer 118 generates the power control response based at least in part on the continuous history maintained in the memory 110. More specifically, as described above, it generates power control commands based at least in part on the maintained continuous history in a manner that slows down the response to power control instructions, thereby reducing the likelihood of over-issuing continuous power control commands, which may result in channel loss. For example, issuing an excessive power down command may cause the channel to fall below a useful power level to maintain the link or connection, or increase reception errors. Also, over-issuing power increase commands can cause user terminals to use excessive power and cause interference to other user terminals or signals and unnecessarily consume valuable power resources.

For this embodiment, at least some selected transmission frames 102 include power control instructions in the form of power control bits. These power control bits are output by the batching logic 104 when the batching logic 104 queues the received frames 102 and batches them into batched frames 106. The power control bits are examined and their values or provided control information are continuously stored in a queue in memory 110. An exemplary queue has a queue length on the order of 2 bits. However, other queue lengths may be employed as desired, depending on the amount of command information to be saved.

The generator/populator 118 generates power control commands based at least in part on a continuous history (here, 2 bits) maintained in the queue. More specifically, for one embodiment, it generates power control commands based at least in part on the maintained continuous 2-bit history in a manner that slows responses to power control instructions to an approximate batch processing rate, as described in more detail with reference to FIG. 2.

The batch logic 104, batch process 108, and frame generator 114 all represent a broad range of these elements known in the art, except that one copy or version of the power control instructions is added for historical purposes. Thus, they will not be described in detail. Implementation of the output power control commands while batching the received frames is well understood by those skilled in the art and need not be described in detail herein.

Power control command generation

Fig. 2 illustrates an operational flow of relevant aspects of the power control command generator/filler 118 of fig. 1, in accordance with an embodiment. This embodiment assumes that the power control instruction R and the command P are in the form of power control bits, and maintains a continuous 2-bit history of the power control bits included within the received frame.

As shown, in the associated components, the generator/populator 118 determines whether the 2-bit history has a bit pattern of "01" or "10" in a step or processing stage 202. If it is determined that the 2-bit history has either of these two bit patterns, the generator/stuffer 118 generates an approximately equal number of "zero" value and "one" value power control command bits, i.e., m "zero" value power control response bits and n "one" value power control response bits, m and n differing by at most 1 and both being integers, at step 204.

If there are an even number of frames, the number of "zero" and "one" power control command bits, i.e., m and n, generated are then equal. If there are odd number of frames, the batch is changed, and the number of "zero" value power control command bits (m) generated is 1 greater than the number of "one" value power control response bits (n) generated.

In one embodiment, m of the batches occupying odd ordinal positions of the batch generation may be greater than 1 than n, and n of the batches occupying even ordinal positions of the batch generation may be greater than 1 than m.

In another embodiment, the order may be arranged such that n of batches occupying odd ordinal positions of the batch generation may be greater than 1 and m of batches occupying even ordinal positions of the batch generation may be greater than 1.

If it is determined at step or stage 202 that the 2-bit history does not have either of the "01" or "10" bit patterns, the generator/stuffer 118 further determines whether the 2-bit history has a bit pattern of "11". If it is determined that the 2-bit history has a bit pattern of "11", then in step 208, the generator/stuffer 118 alternately generates a "one" value power control command bit and a "zero" value power control command bit, depending on whether there are odd or even frames in a batch, so that there are one or two additional "one" value power control command bits.

When there are odd number of frames in a batch, the batch naturally carries an extra one value power control command bit. When there are even numbers of frames in a batch, the generator/stuffer 118 also generates the last bit as a one value power control bit, thereby making the last two power control command bits a one value bit. Thus, the number of "one" value power control command bits generated may exceed the number of "zero" value power control bits by more than 2.

If it is determined in step or processing stage 204 that the 2-bit history does not have an "11" bit pattern, nor the other patterns discussed above, then the 2-bit history by default has a "00" bit pattern. At step 210, the generator/stuffer 118 alternately generates a "zero" value power control command bit and a "one" value power control response bit, and one or two additional "zero" value power control command bits, depending on whether there are odd or even frames within a batch.

When there are odd number of frames in a batch, the batch naturally has an extra "zero" value power control command bit. When there are an even number of frames in a batch, the generator/stuffer 118 also generates the last bit as a "zero" value power control command bit, thereby bringing the last two power control command bits to a "zero" value bit. Thus, the number of "zero" value power control command bits generated may exceed the number of "one" value power control bits by more than 2.

Gateway embodiments

Referring now to fig. 3, there is shown a block diagram illustrating a gateway embodiment of the present invention. The terms gateway, hub and base station are sometimes used interchangeably in the art, with the gateway being considered a private base station that directs communications through satellites and the base station directing communications within a surrounding geographic area using terrestrial antennas. The phrase "ground station" is sometimes used interchangeably with "gateway" in this field.

Similar to the general embodiment shown in fig. 1, the gateway 300 includes the batch logic 104 and the power control command generator/filler 118 described above, both of which are incorporated into the principles of the present invention. This embodiment also includes a storage element, location or device 110. Thus, this embodiment also includes batch processing logic 108 and a frame generator 114.

For the gateway embodiment, batch logic 104 is a component of transceiver subsystem 302, while batch 108, memory 110, frame generator 114, and power control command generator/stuffer 118 are components of frame processing subsystem 304.

These elements are operatively coupled to each other as shown. Also, these elements are used in combination with each other as described above.

In particular, in embodiments where the power control command is in the form of a power control bit, the memory 110 maintains a 2-bit continuous history in the form of a queue as described above, and the generator/stuffer 118 generates a slow response to the power control bit in the manner described above with reference to FIG. 2.

These elements are well known in the art, except for the inventive principles incorporated in the transceiver subsystem 302 and frame processing 304, and therefore will not be described further.

Application of gateway embodiment

Fig. 4 illustrates an MSS in which a gateway 300 with a slowed or slower power control response of the present invention may be employed. As shown, the MSS includes user terminals 430, 440 and a gateway 300, bridged by a communication satellite 420. First, a user terminal or terminal device 430 receives a transmission from the communication satellite 420 via a forward link of a first channel of a first beam 435 and transmits to the communication satellite 420 on a reverse link of the first channel. Second terminal device 440 receives transmissions from communication satellite 420 via the forward link of the second channel of second beam 445 and transmits to communication satellite 420 on the reverse link of the second channel.

This example contemplates satellite 420 providing multiple beams within at least one "site," the multiple beams being directed to cover separate, generally non-overlapping geographic areas. Typically, multiple beams at different frequencies, also referred to as CDMA channels (when CDMA is used), "sub-beams" or FDM signals, frequency field points, or channels, can be used to overlap the same region. However, it is readily understood that the beam coverage areas or service areas of different satellites, or the antenna patterns of terrestrial cell sites, may overlap completely or partially within a given area, depending on the communication system design and the type of service provided.

To establish the forward or reverse link, information may be subdivided into time slots, as used by TDMA-type communication systems or signals, or into code channels, as used by CDMA-type communication systems or signals, with each terminal communicating over an assigned code channel. These and other combinations are well known for establishing links within the channels discussed herein.

The terms reverse link and forward link are as described above. The terms reverse link and return link are sometimes used interchangeably in the art to refer to the communication path through which signals travel from a terminal device to a satellite, and from the satellite to a ground station. In terrestrial communication systems, they propagate directly from the terminal to the base station. The forward link refers to the communication path through which signals travel from the ground station to the satellite, and from the satellite to the terminal device. In terrestrial communication systems, they propagate directly from the base station to the terminal. Furthermore, the term "reverse direction" is used to refer to signal transmission on a communication link in a direction (RL or FL) opposite to the direction (FL or RL) in which the signal was received. As is well known to those skilled in the art.

User terminals or terminal devices 430 and 440 each have or include a wireless communication device such as, but not limited to: a cellular telephone, a data transceiver, or a transmission device (e.g., a computer, a personal data assistant, a facsimile machine). Generally, these units are either hand-held or vehicle-mounted, as desired. While these user terminals are discussed above as being mobile, it will be appreciated that the principles of the invention may be applied to fixed units or other types of terminals where long-range wireless service is desired. The latter type of service is particularly suited for establishing communication links in most remote areas of the world using satellite repeaters. User terminals, terminal devices are also sometimes referred to as wireless devices, access terminals, subscriber units, mobile stations, or simply as "users," "mobiles," and "subscribers" in some communication systems, depending on preference. These terms are well known in the art.

Gateway 300 transmits forward channel data to terminal devices 430, 440 via communication satellite 420 and also receives reverse channel data from terminal devices 430, 440 via communication satellite 420.

The backchannel data may include power control instructions, particularly in the form of power control bits. Gateway 300 having the principles of the present invention is capable of batching received backchannel data while reducing the likelihood of issuing overly-continuous power control commands and losing the channel by slowing the response to power control commands.

The remaining elements, other than the inventive principles embodied within gateway 300, are also well known in the art and will not be further described.

Gateway emulator and simulator embodiments

As will be appreciated by those skilled in the art, the development of MSS requires extensive testing. Testing in the field or live is often expensive. Thus, in a simulation and/or emulation environment, a number of tests are conducted in a development laboratory.

Figure 5 illustrates a gateway emulator and simulator embodiment of the present invention. Also similar to the general embodiment shown in FIG. 1, the simulator and simulator pairs 502 and 504 include the batch logic 104 and the power control response generator/filler 118 described above, both of which are incorporated within the principles of the present invention. This embodiment also includes a memory 110. In addition, this embodiment also includes batch processing logic 108 and a frame generator 114.

For this embodiment, the batch logic 104 is a component of the simulator 502, while the batch 108, memory 110, frame generator 114, and power control response generator/populator 118 are components of the simulator 304.

These elements are operatively coupled to each other as shown. Also, these elements may be used in combination with each other as described above.

In particular, in embodiments where the power control command is in the form of a power control bit, the memory 110 maintains a 2-bit continuous history in the form of a queue as described above, and the generator/stuffer 118 generates a slow response to the power control bit as described above with reference to FIG. 2.

In addition to the inventive principles incorporated within gateway emulator 502 and simulator 504, these elements may include other components, such as networking and other interfaces for interfacing with each other and other elements, such as user terminals and the like. The actual composition of simulator 502 and simulator 504 is not necessary to practice the present invention and is therefore not further described.

Application of gateway emulator and simulator embodiments

Fig. 6 illustrates an MSS test environment in which an emulator and simulator 502-504 with the slow power control response of the present invention may be employed. For this embodiment, the MSS test environment 600 includes a user terminal 606 and a Mobile Communications Subsystem (MCS)608 in addition to the emulator and simulator pair 502-504.

Simulator 502 includes, inter alia, a plurality of networking interfaces such as an ethernet interface, a Radio Frequency (RF) interface, and a Timing and Frequency Unit (TFU) (all not shown), and simulator 504 includes a networking interface and a diagnostic monitor (also not shown).

The emulator 502 and the simulator 504 are coupled to each other via a networked connection and exchange commands and data with each other over the networked connection in order to enable the simulator 504 to drive the emulator 502 for the purpose of testing the MSS.

The user terminal 606 communicates with the MCS608 over one or more Radio Frequencies (RF) and with the gateway simulator 504 over a UT-DMI (diagnostic monitor interface) to cause the gateway simulator 504 to drive it for testing purposes.

MCS608 in turn communicates with emulator 502: via the networking interface for control commands, RF for user data, and TFU connections for timing and frequency information.

Likewise, the actual composition and operation of the remaining elements, other than the inventive principles embodied within the gateway emulator and simulator 502-504, is not critical to implementing the present invention to slow the speed or response rate to power control commands, particularly in a batch transmission frame environment.

Implementation of

Aspects of the invention may be implemented in a circuit-based solution, including possible implementation on a single integrated circuit. It will be apparent to those skilled in the art that various functions of the circuit elements may also be implemented by processing operations in a software program. Such software may be employed in, for example, a digital signal processor, a microcontroller, or a general purpose computer.

Various embodiments of the present invention use computing resources to implement the above-described functionality. FIG. 7 illustrates one embodiment of a hardware system for representing a broad class of computer systems, such as personal computers, workstations, and/or embedded systems. In the illustrated embodiment, the hardware system includes a processor 710 coupled to a high speed bus 705, which high speed bus 705 is coupled to an input/output (I/O) bus 715 through a bus bridge 730. I/O device 750 is also coupled to bus 715. The I/O devices 750 may include a display device, a keyboard, one or more external network interfaces, and so forth.

Particular embodiments may include additional components, may not require all of the above components, or may combine one or more components. For example, temporary memory 720 may be integrated into processor 710. Alternatively, permanent memory 740 may be deleted and temporary memory 720 replaced with an Electrically Erasable Programmable Read Only Memory (EEPROM), wherein the software routines are executed instead from the EEPROM. Some implementations may employ a separate bus to which all of the components are coupled, or one or more additional buses and bus bridges to which various other components may be coupled. Those skilled in the art will be familiar with a variety of alternative internal networks, including, for example, internal networks based on a high speed system bus with a memory controller hub and an I/O controller hub. Other components may include other processors, CD ROM drives, other memory, and other peripheral components known in the art.

In one embodiment, the present invention is implemented using one or more hardware systems, such as the hardware system of FIG. 7, as described above. When more than one computer is used, the systems may be coupled to communicate over an external network, such as a Local Area Network (LAN), an Internet Protocol (IP) network, or the like. In one embodiment, the invention is implemented as software routines executed by one or more execution units within a computer. For a given computer, the software routines may be stored on a storage device, such as persistent storage 740.

Alternatively, as shown in FIG. 8, the software routines may be machine executable instructions 810 stored using any machine readable storage medium 820, such as a cassette, CD-ROM, tape, Digital Versatile Disk (DVD), compact disk, ROM, flash memory, and the like. The series of instructions need not be stored locally but may be received from a remote storage device, such as a server on a network, a CD ROM drive, a floppy disk, etc., via, for example, I/O device 750 of fig. 7.

From whichever source, the instructions may be copied from the storage device into temporary memory 720 and then accessed and executed by processor 710. In one implementation, these software routines are written in the C programming language. It will be appreciated, however, that these routines may be implemented in any of a variety of programming languages.

In alternative embodiments, the invention is implemented in discrete hardware or firmware. For example, one or more Application Specific Integrated Circuits (ASICs) may be programmed to have one or more of the functions of the invention described above. In another example, one or more of the functions of the present invention may be implemented in one or more ASICs on other circuit boards, which may be plugged into the computer described above. In another example, a Field Programmable Gate Array (FPGA) or a Static Programmable Gate Array (SPGA) may be used to implement one or more functions of the present invention. In yet another example, a combination of hardware and software could be used to implement one or more functions of the present invention.

Conclusion

Thus, a history-based method and apparatus implemented in an MSS application has been described that slows the response to power control commands.

One advantage of the present invention is that it reduces the likelihood of over issuing consecutive power control commands that may result in loss of a channel or communication link, particularly when transmission frames are organized together, queued, or processed in batches.

Although the present invention is described primarily in terms of wireless satellite-based communications, the present invention is applicable to other types of communication channels, including digital, electrical or optical, wireless or wired/optical, etc., where signal delay is an element of the communication link that one wishes to compensate for.

It is to be understood that the present invention is not limited to the embodiments described above, but encompasses any and all embodiments within the scope of the following claims.

Claims (32)

1. A method for providing a power control response, comprising:

maintaining a continuous history of predetermined lengths for power control instructions included within a first set of frames received in one direction on a channel link, the first set of frames being queued prior to processing; and

generating power control commands for a second set of frames to be transmitted in a return direction of the channel based at least in part on the maintained continuous history, the generating being in a manner to slow a response to incoming power control instructions, the second set of frames also being batched for subsequent processing in batched form for transmission, the generating comprising: if the two-bit continuation history is equal to a selected one of "01" and "10", generating m "zero" value power control bits and n "one" value power control bits for each batch formed with the subset of the second set of frames, where m and n differ by at most 1, m and n being integers;

wherein the power control instructions and commands are in the form of power control bits, and the predetermined length is equal to two bits.

2. The method of claim 1, wherein m and n are equal if each batch of the subset of the second set of frames contains an even number of frames.

3. The method of claim 1, wherein m and n differ by 1 if each batch of the subset of the second set of frames contains an odd number of frames.

4. The method of claim 3 wherein m is greater than 1 for batches having an odd number of positions in the forming sequence and n is greater than 1 for batches having an even number of positions in the forming sequence.

5. The method of claim 3 wherein m is greater than 1 for batches having an even number of positions in the forming sequence and n is greater than 1 for batches having an odd number of positions in the forming sequence.

6. The method of claim 1, wherein the generating comprises: if the two consecutive frames are equal to "11", then a "one" value power control bit and a "zero" value power control bit are alternately generated for each batch formed with a subset of the second set of frames, with the last frame or two frames selected to receive the "one" value power control bit.

7. The method of claim 6 wherein the last frame receives a one value power control bit if there are odd numbers of frames in each batch and the last two frames receive a one value power control bit if there are even numbers of frames in each batch.

8. The method of claim 1, wherein the generating comprises: if the two consecutive frames are equal to "00", then a "zero" value power control bit and a "one" value power control bit are alternately generated for each batch formed with a subset of the second set of frames, with the last frame or two frames selected to receive the "zero" value power control bit.

9. The method of claim 8 wherein the last frame receives a "zero" value power control bit if there are an odd number of frames in each batch and the last two frames receive a "zero" value power control bit if there are an even number of frames in each batch.

10. The method of claim 1, wherein the maintaining and generating operations are performed within a gateway of a wireless communication system.

11. The method of claim 1, wherein the maintaining and generating operations are performed within a simulation gateway and a gateway simulator of a wireless communication test system.

12. A gateway of a wireless communication system, comprising:

a transceiver for receiving a first set of frames on a first link of a channel and batching the first set of frames for batching, each of the first set of frames including a power control instruction, the transceiver outputting the power control instruction included within each of the first set of frames;

a processing subsystem coupled to the transceiver for batch processing the batched first set of frames and receiving power control instructions for the first set of frames output by the transceiver and for generating a second set of frames for a second link of the channel, the second set of frames also being batched prior to batch processing by the transceiver, wherein the processing subsystem:

maintaining a continuous history of predetermined lengths for power control instructions included within the first set of frames, an

Generating power control commands for the second set of frames based at least in part on the maintained continuity history, the generating in a manner that slows down a response to incoming power control instructions,

the processing subsystem is further designed to generate m "zero" value power control bits and n "one" value power control bits for each batch formed with a subset of the second set of frames if the two-bit continuation history is equal to a selected one of "01" and "10", where m and n differ by at most 1, m and n being integers;

wherein the power control instruction is in the form of a power control bit and the predetermined length is equal to two bits.

13. The gateway of claim 12, wherein the processing subsystem is designed to: if each batch of the subset of the second set of frames contains an even number of frames, then the "zero" value power control bit and the "one" value power control bit are generated such that m equals n.

14. The gateway of claim 12, wherein the processing subsystem is designed to: if each batch of the subset of the second set of frames contains an odd number of frames, then the "zero" value power control bit and the "one" value power control bit are generated such that m and n differ by 1.

15. The gateway of claim 14, wherein the processing subsystem is designed to: for batches with an odd number of positions in the forming sequence, the "zero" value power control bit and the "one" value power control bit are generated such that m is greater than n by 1, and for batches with an even number of positions in the forming sequence, the "zero" value power control bit and the "one" value power control bit are generated such that n is greater than m by 1.

16. The gateway of claim 14, wherein the processing subsystem is designed to: for batches having an even number of positions in the forming sequence, the "zero" value power control bit and the "one" value power control bit are generated such that m is greater than n by 1, and for batches having an odd number of positions in the forming sequence, the "zero" value power control bit and the "one" value power control bit are generated such that n is greater than m by 1.

17. The gateway of claim 12, wherein the processing subsystem is designed to: if the two consecutive frames are equal to "11", then a "one" value power control bit and a "zero" value power control bit are alternately generated for each batch formed with a subset of the second set of frames, with the last frame or two frames selected to receive the "one" value power control bit.

18. The gateway of claim 17, wherein the processing subsystem is designed to: if there are odd number of frames in each batch, the last frame is generated with a 'one' value power control bit, and if there are even number of frames in each batch, the last two frames are generated with a 'one' value power control bit.

19. The gateway of claim 12, wherein the processing subsystem is designed to: if the two consecutive frames are equal to "00", then a "zero" value power control bit and a "one" value power control bit are alternately generated for each batch formed with a subset of the second set of frames, with the last frame or two frames selected to receive the "zero" value power control bit.

20. The gateway of claim 19, wherein the processing subsystem is designed to: if there are odd number of frames in each batch, the last frame is generated with a power control bit with "zero" value, and if there are even number of frames in each batch, the last two frames are generated with a power control bit with "zero" value.

21. A wireless communication test system, comprising:

a gateway emulator for emulating a gateway, including receiving a first set of frames in one direction on a channel link, each of the first set of frames including a power control instruction, and queuing the first set of frames for batching, the gateway emulator outputting the power control instruction included within each of the first set of frames;

a gateway simulator coupled to the gateway simulator for batching a first set of frames in groups and receiving power control instructions for the first set of frames output by the gateway simulator, and for generating a second set of frames for transmission on the opposite direction on the channel link, the second set of frames also being batched prior to batching by the gateway simulator, wherein the gateway simulator:

maintaining a continuous history of predetermined lengths for power control instructions included within the first set of frames, an

Generating power control commands for the second set of frames based at least in part on the maintained continuity history, the generating in a manner that slows down a response to incoming power control instructions,

the gateway simulator is further designed to: if the two-bit continuation history is equal to a selected one of "01" and "10", generating m "zero" value power control bits and n "one" value power control bits for each batch formed with the subset of the second set of frames, where m and n differ by at most 1, m and n being integers;

wherein the power control instructions and commands are in the form of power control bits, and the predetermined length is equal to two bits.

22. The wireless communication test system of claim 21, wherein the gateway simulator is designed to: if each batch of the subset of the second set of frames contains an even number of frames, then the "zero" value power control bit and the "one" value power control bit are generated such that m equals n.

23. The wireless communication test system of claim 21, wherein the gateway simulator is designed to: if each batch of the subset of the second set of frames contains an odd number of frames, then the "zero" value power control bit and the "one" value power control bit are generated such that m and n differ by 1.

24. The wireless communication test system of claim 23, wherein the gateway simulator is designed to: for batches with an odd number of positions in the forming sequence, the "zero" value power control bit and the "one" value power control bit are generated such that m is greater than n by 1, and for batches with an even number of positions in the forming sequence, the "zero" value power control bit and the "one" value power control bit are generated such that n is greater than m by 1.

25. The wireless communication test system of claim 23, wherein the gateway simulator is designed to: for batches having an even number of positions in the forming sequence, the "zero" value power control bit and the "one" value power control bit are generated such that m is greater than n by 1, and for batches having an odd number of positions in the forming sequence, the "zero" value power control bit and the "one" value power control bit are generated such that n is greater than m by 1.

26. The wireless communication test system of claim 21, wherein the gateway simulator is designed to: if the two consecutive frames are equal to "11", then a "one" value power control bit and a "zero" value power control bit are alternately generated for each batch formed with a subset of the second set of frames, with the last frame or two frames selected to receive the "one" value power control bit.

27. The wireless communication test system of claim 26, wherein the gateway simulator is designed to: if there are odd number of frames in each batch, the last frame is generated with a 'one' value power control bit, and if there are even number of frames in each batch, the last two frames are generated with a 'one' value power control bit.

28. The wireless communication test system of claim 21, wherein the gateway simulator is designed to: if the two consecutive frames are equal to "00", then a "zero" value power control bit and a "one" value power control bit are alternately generated for each batch formed with a subset of the second set of frames, with the last frame or two frames selected to receive the "zero" value power control bit.

29. The wireless communication test system of claim 28, wherein the gateway simulator is designed to: if there are odd number of frames in each batch, the last frame is generated with a power control bit with "zero" value, and if there are even number of frames in each batch, the last two frames are generated with a power control bit with "zero" value.

30. An apparatus for providing a power control response, comprising:

means for maintaining a continuous history of predetermined lengths for power control instructions included in a first set of frames received on a first link of a channel, said first set of frames being grouped prior to processing thereof; and

means for generating power control commands for a second set of frames to be transmitted on a second link of the channel based at least in part on the maintained continuity history, the generating in a manner that slows responses to incoming power control instructions, the second set of frames also being grouped for subsequent batching for transmission, the means for generating power control commands further configured to: if the two-bit continuation history is equal to a selected one of "01" and "10", generating m "zero" value power control bits and n "one" value power control bits for each batch formed with the subset of the second set of frames, where m and n differ by at most 1, m and n being integers;

wherein the power control instructions and commands are in the form of power control bits, and the predetermined length is equal to two bits.

31. An apparatus for controlling a system for providing a power control response when the apparatus is coupled to the system, the apparatus comprising:

a control module for controlling the system to maintain a continuous history of predetermined lengths for power control instructions included in a first set of frames received on a first link of a channel, the first set of frames being grouped prior to processing thereof; and

a control module for controlling the system to generate power control commands for a second set of frames to be transmitted on a second link of the channel based at least in part on the maintained continuous history, the generation being in a manner that slows responses to incoming power control instructions, the second set of frames also being grouped prior to subsequent batching for transmission, wherein further configured to: if the two-bit continuation history is equal to a selected one of "01" and "10", generating m "zero" value power control bits and n "one" value power control bits for each batch formed with the subset of the second set of frames, where m and n differ by at most 1, m and n being integers;

wherein the power control instructions and commands are in the form of power control bits, and the predetermined length is equal to two bits.

32. A method for providing a power control response, the method comprising:

emulating a gateway including receiving a first set of frames on a first link of a channel and grouping the first set of frames for batched processing, each of the first set of frames including a power control instruction, and outputting the power control instruction included in each of the first set of frames;

batch processing the batched first set of frames and receiving power control instructions for the first set of frames output by the gateway emulator, and generating a second set of frames for a second link of the channel, the second set of frames also batched prior to batch processing by the gateway emulator, and further:

maintaining a continuous history of predetermined lengths for power control instructions included within the first set of frames, an

Generating power control commands for the second set of frames based at least in part on the maintained continuity history, the generating in a manner that slows down a response to incoming power control instructions,

the generating step further comprises: if the two-bit continuation history is equal to a selected one of "01" and "10", generating m "zero" value power control bits and n "one" value power control bits for each batch formed with the subset of the second set of frames, where m and n differ by at most 1, m and n being integers;

wherein the power control instructions and commands are in the form of power control bits, and the predetermined length is equal to two bits.