HK1078180A - Sigma-delta modulator controlled phase locked loop with a noise shaped dither - Google Patents

Description

Sigma-delta modulator controlled phase locked loop with noise shaped dithering

FIELD

The present disclosure relates to frequency synthesizers that can be implemented in wireless communication system devices, and more particularly, to Phase Locked Loop (PLL) circuits of frequency synthesizers.

Background

Frequency synthesizers are typically implemented within wireless communication devices that transmit and receive coded Radio Frequency (RF) signals. Several different wireless communication techniques have been developed including Frequency Division Multiple Access (FDMA), Time Division Multiple Access (TDMA), and various spread spectrum techniques. One common spread spectrum technique used in wireless communications is Code Division Multiple Access (CDMA) signal modulation, in which multiple communications are simultaneously transmitted over a spread spectrum Radio Frequency (RF) signal. Some example wireless communication devices that have incorporated one or more wireless communication technologies include cellular radiotelephones, PCMCIA cards incorporated within portable computers, Personal Digital Assistants (PDAs) equipped with wireless communication capabilities, and the like.

The frequency synthesizer of the wireless communication device may be used during RF signal reception and RF signal transmission. For example, during RF signal reception of CDMA modulated signals, the received RF signal is typically downmixed to a baseband signal, which can be converted to a digital value. In the downmixing process, a reference waveform is generated by a frequency synthesizer and used to remove the RF carrier component from the received signal. The reference waveform is sometimes referred to as a Local Oscillator (LO) signal. After the RF signal is down-mixed to baseband, the baseband signal is typically passed through an analog-to-digital (a/D) converter to generate a digital value that can be tracked and demodulated. For example, a rake receiver can be used to track and demodulate the multipath signals of a CDMA system. Several different CDMA architectures have been developed, such as a heterodyne architecture that includes an Intermediate Frequency (IF) section and an RF section, and a zero IF architecture that does not convert an RF signal first to an IF signal but directly converts an incoming RF signal to a baseband signal. According to this configuration, any number of frequency synthesizers may be implemented to provide the reference waveforms to the mixers.

Frequency synthesizers are used during transmission of RF signals. Thus, the baseband signal is mixed up to RF. During the up-mixing process, the frequency synthesizer generates a carrier RF waveform. The carrier waveform is then mixed with the baseband signal before being transmitted. The frequency synthesizer may include a Voltage Controlled Oscillator (VCO), the frequency of which is controlled and adjusted by a Phase Locked Loop (PLL). The time reference of the PLL is typically a high precision low frequency crystal oscillator, such as a voltage controlled temperature compensated crystal oscillator (VCTCXO).

Phase Locked Loops (PLLs) generally operate by measuring the output frequency of the VCO and providing closed loop feedback to the input signal of the VCO. For example, a frequency divider can be used to divide the output signal of the VCO by an integer value. The divided value is then compared to a lower frequency timing reference of higher accuracy. The input voltage applied to the VCO is adjusted so that the output converges to a desired value.

To increase the amount of resolution in a PLL, circuits are developed to generate an averaged fractional division factor. For example, the division factor used by the divider can be generated by a sigma delta modulator. Such a PLL is sometimes referred to as a sigma delta controlled PLL. The sigma delta modulator generates a division factor for each iteration of the loop so that, on average, a fractional division factor can be represented in the PLL.

To avoid that the sigma delta controls the repetition period in the PLL, a pseudo random signal is introduced to the sigma delta modulator. The pseudo-random signal is sometimes referred to as a dither or dithering signal. The introduction of a dithering signal is advantageous to ensure that the sigma delta modulator does not fall into a limit cycle, where the division factor generated by the sigma delta modulator begins to repeat in a cyclic pattern.

Abstract

In one embodiment, a frequency synthesizer for use in a wireless communication device is described. For example, the frequency synthesizer may include an oscillator and a Σ Δ controlled phase-locked loop (PLL) that determines and controls the output frequency of the frequency synthesizer.

The Σ Δ controlled PLL may implement a dithering signal generation technique that can reduce or eliminate the introduction of an average frequency offset (also referred to as a dithering offset). In particular, the dithering signal generator may generate a dithering signal from two or more dithering components. The at least one dithering component may include a component used in generating a previous dithering signal.

For example, generating the dithering signal may include generating a new dithering component and subtracting the component used in generating the previous dithering signal from the new dithering signal. In this way, the introduction of an average frequency offset can be substantially avoided, since each time a new dithering component is introduced, it is removed in a later clock cycle.

The various embodiments and techniques described in detail below may be implemented in hardware, software, firmware, or any combination thereof. Additional details of other embodiments are described below and in conjunction with the following figures. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.

Brief description of the drawings

Fig. 1 is a block diagram of a wireless communication device implementing a frequency synthesizer for RF signal reception.

Fig. 2 is a block diagram of a wireless communication device implementing a frequency synthesizer for RF signal transmission.

Fig. 3 is an exemplary frequency synthesizer, such as shown in fig. 1 or 2.

Fig. 4 is a block diagram of an exemplary Σ Δ modulator coupled to a dithering signal generator.

Fig. 5 is a block diagram of an exemplary M-N accumulator that can form part of a sigma delta modulator.

Fig. 6 and 7 are flow diagrams illustrating techniques consistent with the principles of the present disclosure.

Description of The Preferred Embodiment

In general, the present disclosure is directed to a frequency synthesizer for use in a wireless communication device. The frequency synthesizer includes an oscillator, such as a Voltage Controlled Oscillator (VCO) and a Phase Locked Loop (PLL) that determines and controls the output frequency of the frequency synthesizer. The PLL includes a variable divider that divides the output of the VCO by integer values that vary over time such that the average division factor of the divider is a fractional value. The divided output of the VCO is then compared to a higher accuracy reference frequency, thereby enabling detection of errors in the VCO and adjustment of the VCO frequency.

The PLL implements a sigma delta modulator to produce a time varying division factor. Such a PLL is sometimes referred to as a sigma delta controlled PLL. The sigma delta modulator generates a different division factor for each iteration of the PLL so that, on average, a fractional division factor can be represented in the PLL. The Σ Δ modulator receives a numerator and denominator that represent the fractional portion of the division factor and a pseudorandom signal, sometimes referred to as a dithering or dithering signal. The sigma delta modulator may accumulate these values to quantize the fractional portion of the division factor for each clock cycle. The introduction of the dithering signal helps to ensure that the sigma delta modulator does not fall into a limit cycle, where the division factor produced by the sigma delta modulator begins to repeat in a cyclic pattern.

On average, however, the introduction of a dithering signal may result in the introduction of an average frequency offset (also referred to herein as a dithering offset or average dithering value) that undermines the effectiveness of ∑ Δ -controlled PLLs, particularly when used in wireless communication devices that operate in accordance with code division multiple access CDMA standards or other standards that require high frequency accuracy. For this reason, a dithering signal generator that provides a dithering signal to a ∑ Δ modulator is configured to generate a dithering signal having an average value of approximately zero, in accordance with the principles disclosed herein.

A dithering signal generator, shown in greater detail below, creates an output signal from a difference between a newly generated dithering signal component and a previously generated dithering signal component used in a previous clock cycle. In other words, the dither signal introduced into the sigma delta modulator comprises at least two components: a new dithering component and a subtracted dithering component used to offset an offset introduced by the new dithering component of a previous clock cycle. In this way, the sigma delta modulator can be provided with a dithering signal to avoid limit cycles in which the division factor generated by the sigma delta modulator begins to repeat in a cyclic pattern. On average, however, the frequency offset caused by the introduction of dithering may be substantially zero, as each new dithering signal component is introduced and then removed in a subsequent clock cycle. In this manner, the performance of the Σ Δ controlled PLL can be realized in a system operating in accordance with one or more CDMA standards or other standards requiring high frequency accuracy, such as GSM (global system for mobile communications).

Fig. 1 and 2 are block diagrams of a wireless communication device 10 including frequency synthesizers 20A and 20B, respectively. Frequency synthesizer 20A is used for RF signal reception and frequency synthesizer 20B is used for RF signal transmission. Frequency synthesizers 20A, 20B are substantially similar in structure and operation, and in some cases may be the same frequency synthesizer used for RF signal transmission and reception. Frequency synthesizers 20A and 20B are referred to herein as frequency synthesizers 20. Whether it is used for reception or transmission, the frequency synthesizer 20 may apply one or more of the techniques shown below to improve the operation of the wireless communication device 10.

The block diagram of fig. 1 illustrates an exemplary Wireless Communication Device (WCD)10 implementing a zero IF architecture, although the disclosure is not limited in this respect. In a zero-IF architecture, WCD10 converts incoming RF signals directly to baseband signals, and in particular, does not first convert the RF signals to Intermediate Frequency (IF) signals. It will be appreciated, however, that the techniques described herein may be readily applied to any architecture that implements one or more frequency synthesizers.

WCD10 includes antenna 12 that receives the resulting incoming RF signal. For example, the incoming RF signal may comprise a code division multiple access modulated signal transmitted from a CDMA base station, although not limited in this respect. The RF signal received by the antenna 12 can be processed by the RF receiver 14, for example, by passing the signal through a Low Noise Amplifier (LNA) and one or more filters. The RF signal is then downmixed by a downmixer 15 to the base station. In particular, down-mixer 15 receives the correlation waveform generated by frequency synthesizer 20A. Frequency synthesizer 20A may implement a sigma delta controlled PLL, as described herein, to control the frequency of the output signal with improved resolution. In particular, the Σ Δ controlled PLL can substantially eliminate the introduction of dithering offsets that would otherwise affect the performance of frequency synthesizer 20A.

The down-mixer 15 produces a baseband signal that is filtered and sampled by an analog-to-digital (a/D) converter 17 to produce corresponding digital values of the signal. The rake receiver 19 may receive the digital values to separate and track signals received from different sources, such as different base stations of a wireless communication system. WCD10 may also include additional components such as filters, amplifiers, and various other digital or analog signal processing components (not shown), as desired.

Fig. 2 is another block diagram of WCD10 illustrating components implemented during transmission of RF signals. In the example of fig. 2, the base station transmitter 24 may generate a baseband signal and forward it to the up-mixer 25. Frequency synthesizer 20B provides a carrier RF waveform to up-mixer 25. Likewise, frequency synthesizer 20B implements a Σ Δ controlled PLL to control the frequency of the output signal with improved resolution and improved accuracy. Frequency synthesizer 20B may be substantially similar to frequency synthesizer 20A (fig. 1) or may have a slightly different structure or operation than that used for signal reception.

The up-mixer 25 mixes the baseband signal onto an RF carrier and passes the mixed RF signal to the amplifier 26 for scaling. Amplifier 26 may include one or more of a Voltage Gain Amplifier (VGA), a Driver Amplifier (DA), and a Power Amplifier (PA). Once the mixed RF signal has been sufficiently amplified or attenuated, RF transmitter 28 may transmit the RF signal from wireless communication device 10 through antenna 12.

Fig. 3 is a more detailed block diagram of frequency synthesizer 20 according to an exemplary embodiment. Frequency synthesizer 20 corresponds to either of synthesizers 20A or 20B shown in fig. 1 and 2, respectively. As shown in fig. 3, the frequency synthesizer 20 may include an oscillator, such as a Voltage Controlled Oscillator (VCO)30 that interacts with a sigma delta controlled PLL 31. For example, the PLL31 may provide analog closed loop control of the output frequency of the VCO30 by controlling the input control voltage applied to the VCO 30. PLL31 may include several components including, for example, variable divider 32, phase detector 34, loop filter 36, and charge pump 38. In addition, PLL31 may include a dithering signal generator 37 that provides a dithering signal to sigma delta modulator 35. Sigma delta modulator 35 is capable of generating the integer value used by variable divider 32 for each clock cycle. The sequence of integer division factors provided from the sigma delta modulator to the variable divider 32 can be used to represent an average division factor that includes a fractional portion.

Variable divider 32 can scale the output frequency of VCO30 by the integer value provided by sigma delta modulator 35 so that phase detector 34 can determine the frequency difference between reference frequency 41 and the scaled VCO output. By way of example, the reference frequency 41 may be provided by a temperature compensated crystal oscillator (TCXO) which is a high precision low frequency oscillator compared to the VCO 30. Once the phase detector 34 has determined the frequency difference between the scaled VCO frequency and the reference frequency, the frequency difference can be filtered by the filter 36. Filter 36 may comprise a low pass filter and may account for fractional spikes in frequency that are introduced when available divider 32 switches between division factors.

The loop filter 36 should be selected to have an order equal to or greater than the order of the sigma delta modulator 35. In particular, if the ∑ Δ modulator 35 is a second-order ∑ Δ modulator as shown in detail below, the second-order loop filter 36 is selected. Likewise, if the sigma-delta modulator 35 is a third order sigma-delta modulator, a third order loop filter 36 is selected. The charge pump 38 receives a signal indicative of the frequency error detected in the output of the VCO30 and adjusts the input voltage to the VCO30 or increases or decreases the oscillation frequency of the VCO30 as needed.

The variable divider 32 divides the output of the VCO30 by different integer values that vary over time so that the average division factor of the divider is a fractional value. In other words, the variable divider periodically switches between two or more division factors to achieve improved resolution. For example, if the desired division factor is 10.2(10 and 1/5), variable divider 32 may switch between division factor 11 and division factor 10 so that the average division factor over time is approximately equal to 10.2.

In particular, to achieve the desired division factor of 10.2, variable divider 32 may divide by four cycles by a division factor of 10 and then divide by one cycle using a division factor of 11. That way, after five cycles, the average division factor will be (10 × 4+11)/5 — 10.2. The Σ Δ modulator 35 can receive an integer value of 10 and a numerator of the fraction of 1 and a denominator of the fraction of 5 and can generate a sequence of integers to be supplied to the variable divider to produce, on average, a division factor of 10 and 1/5. In addition, dithering signal generator 37 can provide dithering signals to Σ Δ modulator 35 to improve the randomness of the sequence of integers that averages the desired division factor. Also, dithering signal generator 37 may noise shape the dithering signal such that a transfer function associated with the dithering signal after being introduced into Σ Δ modulator 35 is 1. In other words, the transfer function of dithering signal generator 37 can be the inverse of the transfer function of the accumulator within ∑ Δ modulator 35, such that the overall transfer function associated with the dithering signal is 1.

Variable divider 32 may be implemented using a variety of different hardware configurations including multiplier circuits, divider circuits, shift registers, counters, and so forth. In one configuration, divider 32 includes counting the leading and trailing edges of the oscillator pulses and provides a signal each time an integer number of pulses are detected, and may be switched over time according to the input provided to sigma delta modulator 35.

In some cases, another frequency divider (not shown) may also be implemented to divide the reference frequency 41. In that way, the additional divider may be similar to variable divider 32, possibly receiving a signal from another sigma delta modulator coupled to another dithering signal generator. In other words, the principles described herein may be extended for use with other frequency dividers, which may be other circuits useful for introducing dithering signals.

Fig. 4 is a block diagram of an exemplary sigma delta modulator 35 coupled to dithering signal generator 37. Such an implementation is exemplary, and the functions shown in this disclosure are also implemented using look-up tables (LUTs) or alternative accumulator configurations. Additionally, although sigma delta modulator 35 is illustrated as a second order sigma delta modulator, the principles of the present disclosure can be extended to higher order sigma delta modulators.

Generally, Σ Δ modulator 35 receives values L, M and N that quantify the desired fractional division factor to be generated on average, as applied by variable divider 32. L denotes the integer part of the desired division factor, M denotes the numerator of the fractional part of the desired division factor, and N denotes the denominator of the fractional part of the desired division factor. For example, if the desired division factor is 10 and 5/6(10.833333), then L is 10, M is 5, and N is 6. L, M and the value of N may be constant or adjustable, and may be programmed into the sigma delta modulator 35 or provided as an input during operation.

The sigma delta modulator 35 receives L, M and the value of N, processes the value over several clock cycles, and outputs a control signal 44 to the variable divider 43 each clock cycle. The control signal 44 may be an integer division factor that varies with each clock cycle such that the average division factor is substantially equal to the desired division factor. For example, if L is 10, M is 5, and N is 6, then the Σ Δ modulator 35 may output control signals over six clock cycles, where five of the clock cycles represent a division factor of 11 and one of the six clock cycles represents a division factor of 10. Thus, over six clock cycles, the average division factor provided to variable divider 32 will be (11 x 5+ 10)/6-10.833333, i.e., 10 and 5/6. In addition, the introduction of the dithering signal can substantially randomize the sequence of division factors that averages the desired division factor. Randomization of the sequence is desirable to ensure that the ∑ Δ modulator does not produce the division factor in a cyclic manner.

In the configuration shown in fig. 4, sigma delta modulator 35 includes a first order M-N accumulator 46 and a second order M-N accumulator 47. M-N accumulators 46 and 47 run in parallel. In particular, M-N accumulator 46 performs an accumulation to quantize the fractional portion of division factor M/N, and M-N accumulator 47 performs another accumulation to quantize the error associated with the result produced by M-N accumulator 46. For each clock cycle, the combiner 48 adds the value L to the value generated by the M-N accumulator and the value generated by the M-N accumulator 47 for that clock cycle, and subtracts the value generated by the M-N accumulator 47 for the previous clock cycle from the control signal. In this manner, the synthesizer 48 generates the control signal 44 every clock cycle. A clock register 49 (sometimes referred to as a flip-flop) can be used to store the output of the M-N accumulator 47 for each clock cycle so that it can be subtracted by the combiner 48 at a subsequent clock cycle.

To randomize each different sequence of control signals generated by the sigma delta modulator 35, a dithering signal can be introduced into the M-N accumulators 46, 47. For example, if it is desired that a sequence of six clock cycles of control signals include five signals corresponding to a division factor of 11 and one control signal corresponding to a division factor of 10, it is not desired to generate this sequence in a repetitive manner. In contrast, the operation of frequency synthesizer 20 can be achieved by randomizing the sequence of six clock cycles so that the division factor applied by variable divider 32 does not fall into a cycle limit cycle.

For this reason, dithering signal generator 37 can be used to generate the dithering signal applied in Σ Δ modulator 35.Σ Δ modulator 35 may include and gates 51A and 51B that receive an enable signal when it is desired to use the dithering signal generated by dithering signal generator 37(s) ((s))EN₁And EN₂)。

Dithering signal generator 37 is specifically designed to generate dithering signals in a manner that substantially improves the operation of frequency synthesizer 20. In particular, the dithering signal generator generates dithering signals that, on average, add up to approximately a zero value. Thus, dithering signal generator 37 substantially avoids introducing a frequency offset (dithering offset) into frequency synthesizer 20.

For example, dithering signal generator 37 may create each dithering signal by combining two dithering components. The first dithering corresponds to a dithering component of a previous dithering signal that was applied in a previous clock cycle, and the second dithering component includes a newly generated dithering component. For example, each clock cycle, a linear feedback shift register (LSFR)53 can generate a new dithering component. Subtractor 54 subtracts the dithering component generated by LSFR53 in the previous clock cycle from the new dithering component. Clock register 55 can be used to store the output of LSFR53 for each clock cycle so that it is subtracted during generation of the dithering signal for the subsequent clock cycle. The amount of delay may also be adjusted as desired. In other words, the previous dithering component subtracted from the new dithering component corresponds to a component generated X clock cycles before the new dithering component is generated, where X is an integer.

Each new dithering component is added to produce a dithering signal, and the same component is subtracted in subsequent clock cycles to negate the effect of the component on the average dithering value, i.e., the dithering offset introduced into frequency synthesizer 20. In other words, dithering signal generator 37 generates a first dithering signal by subtracting the first dithering component from a second dithering component, and dithering signal generator 37 generates a second dithering signal by subtracting the second dithering component from a third dithering component on a subsequent clock cycle. Thus, the effect of the second dithering component of the first dithering signal on the average dithering value is negated by the effect of the second dithering component of the second dithering signal on the average dithering value.

Similarly, dithering signal generator 37 generates a third dithering signal by subtracting the third dithering component from the fourth dithering component. The effect of the third dithering component of the second dithering signal on the average dithering value is negated by the effect of the third dithering component of the third dithering signal on the average dithering value. In addition, dithering signal generator 37 generates a fourth dithering signal by subtracting the fourth dithering component from the fifth dithering component. In this manner, the effect of the fourth dithering component of the third dithering signal on the average dithering value is negated by the effect of the fourth dithering component of the fourth dithering signal on the average dithering value. Thus, the overall effect of introducing dithering signals may be negated by the subsequent introduction of other dithering signals. When a one clock cycle delay is used, only the newly added new dithering component contributes to the offset with each elapsed cycle. A larger delay may result in two or more dithering components contributing to the offset at any given instance. In any case, however, the average offset can be considered to be substantially zero, since the introduction of the dithering signal is a cancellation of the subsequent introduction of other dithering signals.

Another advantage of the configuration illustrated in fig. 4 is that the transfer function associated with the generation of the dithering signal is the inverse of the transfer function associated with the generation of the division factor. More specifically, the transfer function associated with dithering signal generator 37 is the inverse of the transfer function associated with M-N accumulators 46, 47. In the illustrated example of FIG. 4, the transfer function of dithering signal generator 37 is (1-Z)^-1) While the transfer function of the M-N accumulators 46, 47 is 1/(1-Z)^-1). By configuring the transfer function to be the inverse of the other, the collective transfer function of dithering generator 37 and sigma delta modulator 35 is approximately equal to one, i.e., a single transfer function. Thus, the overall transfer function associated with the introduction of the dithering signal is one.

Alternatively, in other configurations, the transfer function of dithering signal generator 37 may be (1-Z)^-1)²For example, if the transfer function of the MN accumulator is 1/(1-Z)^-1)². In general, the transfer function of dithering signal generator 37 may be 1/(1-Z)^-k)ⁿWherein k and n are integers. In any case, transfer function dithering signal generator 37 can be selected as the inverse of the transfer function of M-N accumulators 46, 47, such that the overall transfer function associated with introducing the dithering signal is one, i.e., a unity transfer function.

Fig. 5 is a block diagram illustrating an exemplary configuration of M-N accumulators 46 and 47. As shown, accumulator 46 accumulates (dithering up) in steps of M until the accumulated value is greater than N. Similarly, the introduction of a high frequency pulse can randomize the sequence of division factors generated by the ∑ Δ modulator 35.

With each clock cycle, another value of M is accumulated. If the accumulated value does not exceed N (as defined by the value of overflow signal 63), a zero value is quantized to output 65. More specifically, subtractor 64 subtracts the input value N (corresponding to the denominator of the fractional portion of the desired division factor) from the result of adder 66 (corresponding to the current accumulation in increments of M). If N is greater than the current accumulation, subtractor 64 generates overflow signal 1, which is cancelled to generate output 65. In addition, overflow signal 63 is used by multiplier 67 to select the current accumulation to update register 68. The contents of register 68 are then added to the value M in the subsequent clock cycle. By way of example, subtractor 64 may generate overflow signal 63 very quickly by examining the most significant bits of both components of the subtractor result.

The overflow signal 63 is used to quantize the fractional part of the division factor. As long as N is greater than the accumulated value (accumulated in steps M), signal 63 is 1, and then signal 63 is cancelled by canceller 69 to produce a zero quantized value for the fractional portion of the division factor. However, as soon as the accumulated value exceeds N, the signal 63 becomes 0, and the signal 63 is cancelled by the canceller 69 to produce a quantization of 1 of the fractional part of the division factor. Referring again to fig. 4, the output of the M-N accumulator 46 is added to the integer portion of the division factor (L) to produce the control signal 44.

The M-N accumulator 47 operates in a similar manner to the operation of the M-N accumulator 47 described above. In particular, combiner 76 operates similar to combiner 66, subtractor 74 operates similar to subtractor 64, multiplier 77 operates similar to multiplier 67, register 78 operates similar to register 68, overflow signal 73 is generated in a similar manner as overflow signal 63, and canceller 79 operates similar to canceller 69.

However, unlike M-N accumulator 46, which receives input M, second order M-N accumulator 47 receives as input the output of multiplier 67 of accumulator 46, the output of multiplier 67 of accumulator 46 also represents the error associated with output signal 65 of quantization accumulator 46 per clock cycle. Thus, the M-N accumulator 47 is used to correct the second order quantization effect. As illustrated in fig. 4, the output 75 of the second order M-N accumulator 47 is added to the control signal 44 by the combiner 48 and is also stored in the register 49 for subtraction by the combiner 48 in the next clock cycle. Even higher order M-N accumulators can be added to provide greater accuracy of the division factor produced by the sigma delta modulator 35, as desired. Alternatively, outputs similar to M-N accumulators 46 and 47 may be generated using one or more look-up tables that quantize input variables over a sequence of clock cycles to define an average desired fractional division factor.

Fig. 6 is a flow diagram illustrating a technique consistent with principles of the present disclosure. As shown, dithering signal generator 37 of phase-locked loop 31 generates dithering signals (81) such that the dithering offset is substantially equal to zero over several iterations of phase-locked loop 31. The Σ Δ modulator 35 receives the noise-shaped dithering signal and a value representing the division factor to be generated, and generates a noise-shaped (82) output. In particular, the output of the Σ Δ modulator 35 may be noise shaped such that the transfer function associated with the M-N accumulators 46, 47 is the inverse of the transfer function associated with the dithering signal generator 37. The variable divider 32 applies the output of the Σ Δ modulator 35 to select a division ratio (83), and divides the output of the oscillator 30 by the division ratio (84). Phase detector 34 compares the divided value received from variable divider 32 to reference frequency 41 to detect a frequency error and/or a phase error associated with oscillator 30 (85). Loop filter 36 filters the error signal generated by phase detector 34 (86) and applies the error signal to the voltage to adjust the output of voltage controlled oscillator 30 (87). Also, charge pump 38 may be used to create a desired input voltage to voltage controlled oscillator 30 based on the error signal.

This process may continue in a closed loop manner during operation of frequency synthesizer 20 to improve the frequency synthesis of synthesizer 20. In particular, the frequency synthesis process can be improved by using dithering signals generated from two or more dithering components such that the average dithering offset introduced by dithering signal generator 37 is approximately zero.

Fig. 7 is a flow diagram illustrating a technique consistent with principles of the present disclosure. As shown, dithering signal generator 37 of phase-locked loop 31 generates a dithering signal by subtracting a new dithering component X from a previously generated dithering component X-n (91). The integer n may correspond to a clock cycle delay and may be selected to be 1 or greater. If n is 1, each new dithering signal includes a subtracted component that corresponds to a component of the dithering signal at the previous moment, i.e., the dithering signal generated in the previous clock cycle. If n is 2, each new dithering signal includes a subtracted component that corresponds to a component of the dithering signal that was generated two clock cycles before the new dithering signal, and so on.

After dithering signal generator 37 generates a dithering signal (91), Σ Δ modulator 35 uses the dithering signal to generate a division factor for the PLL (92). The sigma delta modulator 35 may receive the dithering signal and a value representing a division factor to be generated and generate the division factor based on these inputs. This process may continue in a loop fashion to generate the division factor for subsequent iterations of the PLL (as shown by the yes branch of 93). The value X is illustrated as being incremented (94) with each iteration to illustrate that a new dithering component is generated with each elapsed clock cycle.

Several embodiments have been described, for example a sigma delta controlled PLL has been described, which is a dithering signal generation technique that enables the introduction of dithering offsets to be reduced or eliminated. Nevertheless, various modifications may be made without departing from the scope of the disclosure. For example, the Σ Δ modulator may be implemented using a lookup table stored in memory, rather than using an M-N accumulator as shown in fig. 4 and 5. In addition, a higher order sigma delta modulator may be used instead of a second order sigma delta modulator as illustrated in fig. 4. For example, a third order M-N accumulator can be added, or a set of look-up tables that add third order precision to the sigma delta modulator can be used. Even higher orders can be represented, although the degree of accuracy increase introduced by accumulators of, for example, four or more orders is relatively small.

Also, one of more of the above techniques may be implemented in devices other than wireless communication devices. Also, the same or similar techniques may be used in conjunction with oscillators other than voltage controlled oscillators. For example, similar techniques may be used to adjust current voltage controlled oscillators, and so on. Furthermore, although various detailed aspects of the various embodiments are described as being implemented using hardware, the same or similar techniques may be implemented using software, firmware, or various combinations of hardware, software, and firmware. Accordingly, these and other embodiments are within the scope of the following claims.

Claims (45)

1. The method comprises the following steps:

generating a dithering signal from two or more dithering components, at least one dithering component comprising a component used in generating a previous dithering signal; and

a division factor is generated for use in a phase locked loop of a frequency synthesizer based at least in part on the generated dithering signal.

2. The method of claim 1, wherein generating the dithering signal includes subtracting the dithering components used in generating a previous dithering signal from new dithering components.

3. The method of claim 1, wherein generating the dithering signal is separated from generating a previous dithering signal by an integer number of clock cycles.

4. The method of claim 1, further comprising generating a division factor by accumulating the generated dithering signal with an input signal to quantize a fractional portion of the generated division factor, the input signal representing a fractional portion of an average division factor.

5. The method of claim 4, wherein generating the division factor further comprises adding the quantized fractional portion of the division factor to a non-fractional portion of the division factor.

6. The method of claim 4, wherein the transfer function associated with generating the dithering signal is an inverse of a transfer function associated with accumulating the generated dithering signal with the input signal.

7. The method of claim 1, further comprising dividing an oscillating signal of a voltage controlled oscillator associated with the frequency synthesizer by a division factor.

8. The method of claim 7, further comprising comparing the divided oscillating signal to a reference frequency and adjusting an input voltage to the voltage controlled oscillator based on the comparison.

9. The method comprises the following steps:

generating a first dithering signal by subtracting the first dithering component from the second dithering component;

and

a second dithering signal is generated by subtracting the second dithering component from the third dithering component, such that an effect of the second dithering component of the first dithering signal on the average dithering value is negated by an effect of the second dithering component of the second dithering signal on the average dithering value.

10. The method of claim 9, further comprising generating a third dithering signal by subtracting the third dithering component from a fourth dithering component, such that an effect of the third dithering component of the second dithering signal on the average dithering value is negated by an effect of the third dithering component of the third dithering signal on the average dithering value.

11. The method of claim 10, further comprising generating a fourth dithering signal by subtracting the fourth dithering component from a fifth dithering component, such that an effect of the fourth dithering component of the third dithering signal on the average dithering value is negated by an effect of the fourth dithering component of the fourth dithering signal on the average dithering value.

12. The method of claim 11, further comprising:

generating a division factor for use in a phase locked loop of a frequency synchronizer, wherein generating the division factor comprises applying the generated dithering signal; and

a division factor in the phase locked loop of the frequency synchronizer is applied.

13. The method of claim 9, wherein generating the second dithering signal occurs an integer number of clock cycles after generating the first dithering signal.

14. A frequency synthesizer comprising:

an oscillator; and

a phase locked loop that controls a frequency of an oscillation signal of an oscillator, the phase locked loop comprising:

a dithering signal generator that generates a dithering signal from two or more dithering components, at least one dithering component including a component used in generating a previous dithering component;

a modulator for generating a frequency division factor based on at least the generated dithering signal; and

a frequency divider applying a division factor.

15. The frequency synthesizer of claim 14, wherein the dithering signal generator generates the dithering signal by subtracting a component used in generating a previous dithering signal from a new dithering component.

16. The frequency synthesizer of claim 14, wherein the modulator generates the division factor by accumulating the generated dithering signal with an input signal to quantize a fractional portion of the generated division factor, the input signal representing a fractional portion of an average division factor.

17. The frequency synthesizer of claim 16, wherein the modulator further generates the division factor by adding the quantized fractional portion of the division factor to a non-fractional portion of the division factor.

18. The frequency synthesizer of claim 16, wherein the transfer function associated with generating the dithering signal is an inverse of a transfer function associated with accumulating the generated dithering signal with the input signal.

19. The frequency synthesizer of claim 14, wherein the frequency divider applies the division factor in the phase locked loop by dividing the oscillator signal of the oscillator by the division factor.

20. The frequency synthesizer of claim 19, wherein the phase locked loop further comprises:

a phase detector that compares the divided oscillation signal with a reference frequency;

a loop filter for filtering the result of the comparison; and

and a charge pump applying the input voltage to the voltage controlled oscillator based on a result of the comparison.

21. The frequency synthesizer includes:

an oscillator; and

a phase locked loop controlling a frequency of an oscillation signal of the oscillator, the phase locked loop including a dithering signal generator generating a first dithering signal by subtracting the first dithering component from a second dithering component, and generating a second dithering signal by subtracting the second dithering component from a third dithering component, such that an effect of the second dithering component of the first dithering signal on an average dithering value is negated by an effect of the second dithering component of the second dithering signal on the average dithering value.

22. The frequency synthesizer of claim 21, wherein the dithering signal generator generates a third dithering signal by subtracting the third dithering component from a fourth dithering component, such that an effect of the third dithering component of the second dithering signal on the average dithering value is negated by an effect of the third dithering component of the third dithering signal on the average dithering value.

23. The frequency synthesizer of claim 22, wherein the dithering signal generator generates the fourth dithering signal by subtracting the fourth dithering component from a fifth dithering component, such that an effect of the fourth dithering component of the third dithering signal on the average dithering value is negated by an effect of the fourth dithering component of the fourth dithering signal on the average dithering value.

24. The frequency synthesizer of claim 23, wherein the phase locked loop further comprises:

a modulator that generates a division factor, wherein the modulator applies the generated dithering signal during the generation of the division factor; and

a frequency divider applying the division factor.

25. The wireless communication device includes:

a frequency synthesizer comprising an oscillator and a phase locked loop, the phase locked loop controlling a frequency of an oscillation signal of the oscillator, wherein the phase locked loop comprises:

a dithering signal generator that generates a dithering signal from two or more dithering components, at least one dithering component including a component used in generating a previous dithering component;

a modulator that generates a division factor based at least in part on the generated dithering signal; and

a frequency divider applying a division factor in a frequency phase locked loop of the frequency synthesizer; and

and a mixer for mixing the waveforms using an oscillation signal of the oscillator.

26. The wireless communication device of claim 25, wherein the dithering signal generator generates the dithering signal by subtracting a component used in generating a previous dithering signal from a new dithering component, and the modulator generates the division factor by accumulating the generated dithering signal with an input signal to quantize a fractional portion of the generated division factor, the input signal representing a fractional portion of an average division factor.

27. The wireless communication device of claim 25, further comprising a receiver that receives an RF waveform, wherein the mixer down-mixes the received RF waveform to a base station signal using an oscillating signal generated by the frequency synthesizer.

28. The wireless communication device of claim 25, further comprising a transmitter that transmits the waveform, wherein the mixer mixes the waveform by modulating a baseband signal onto an oscillator signal generated by the frequency synthesizer to create the pre-transmission waveform.

29. The wireless communication device of claim 25, wherein the device is selected from the group consisting of: personal digital assistants, laptop computers, desktop computers, cellular radiotelephones, and satellite radiotelephones.

30. The wireless communication system includes:

a frequency synthesizer including an oscillator and a phase locked loop which controls a frequency of an oscillation signal of the oscillator, wherein the phase locked loop includes a dithering signal generator which generates a first dithering signal by subtracting a first dithering component from a second dithering component, and generates a second dithering signal by subtracting a second dithering component from a third dithering component, such that an effect of the second dithering component of the first dithering signal on an average dithering value is canceled by an effect of the second dithering component of the second dithering signal on the average dithering value; and

and a mixer for mixing the waveforms using an oscillation signal of the oscillator.

31. The wireless communication device of claim 30, further comprising a receiver that receives an RF waveform, wherein the mixer down-mixes the received RF waveform to a base station signal using an oscillating signal generated by the frequency synthesizer.

32. The wireless communication device of claim 30, further comprising a transmitter that transmits the waveform, wherein the mixer mixes the waveform by modulating a baseband signal onto an oscillator signal generated by the frequency synthesizer to create the pre-transmission waveform.

33. An apparatus comprising:

a first set of digital circuits for generating a dithering signal from two or more dithering components, at least one dithering component including a component used in generating a previous dithering component;

a second set of digital circuits that generate a division factor based at least in part on the generated dithering signal; and

and a third set of digital circuits for applying the division factor to a frequency phase locked loop of the frequency synthesizer.

34. The apparatus of claim 33, wherein the first set of digital circuits generates the dithering signal by subtracting a component used in generating a previous dithering signal from a new dithering component.

35. The apparatus of claim 33, wherein the second set of circuits generates the division factor by accumulating the generated dithering signal with an input signal to quantize a fractional portion of the generated division factor, the input signal representing a fractional portion of an average division factor.

36. The apparatus of claim 35, wherein the second set of circuits is further to generate the division factor by adding the quantized fractional portion of the division factor to a non-fractional portion of the division factor.

37. The apparatus of claim 35, wherein the transfer function associated with generating the dithering signal is an inverse of a transfer function associated with accumulating the generated dithering signal with the input signal.

38. An apparatus comprising digital circuitry configured to:

generating a first dithering signal by subtracting the first dithering component from the second dithering component;

and

the second dithering signal is generated by subtracting the second dithering component from the third dithering component such that an effect of the second dithering component of the first dithering signal on the average dithering value is negated by an effect of the second dithering component of the second dithering signal on the average dithering value.

39. The apparatus of claim 38, wherein the digital circuit is further configured to generate a third dithering signal by subtracting the third dithering component from a fourth dithering component, such that an effect of the third dithering component of the second dithering signal on the average dithering value is negated by an effect of the third dithering component of the third dithering signal on the average dithering value.

40. The apparatus of claim 39, wherein the digital circuit is further configured to generate a fourth dithering signal by subtracting the fourth dithering component from a fifth dithering component, such that an effect of the fourth dithering component of the third dithering signal on the average dithering value is negated by an effect of the fourth dithering component of the fourth dithering signal on the average dithering value.

41. A frequency synthesizer, comprising:

an oscillator; and

apparatus for controlling a frequency of an oscillation signal of an oscillator, wherein the apparatus for controlling comprises:

means for generating a dithering signal from two or more dithering components, at least one dithering component including a component used in generating a previous dithering component;

means for generating a division factor based at least in part on the generated dithering signal; and

means for applying a division factor.

42. The frequency synthesizer of claim 41, wherein the means for generating the dithering signal comprises: means for generating a new dithering component, and means for subtracting the new dithering component from a component used in generating a previous dithering signal.

43. A frequency synthesizer, comprising:

an oscillator; and

apparatus for controlling a frequency of an oscillation signal of an oscillator, wherein the apparatus for controlling comprises:

means for generating a first dithering signal by subtracting the first dithering component from the second dithering component; and

means for generating a second dithering signal by subtracting the second dithering component from the third dithering component, such that an effect of the second dithering component of the first dithering signal on the average dithering value is negated by an effect of the second dithering component of the second dithering signal on the average dithering value.

44. The frequency synthesizer of claim 43, wherein the means for controlling further comprises:

means for generating a division factor based at least in part on the generated dithering signal;

means for applying a division factor to divide an oscillation signal of an oscillator;

means for detecting a frequency error in the oscillation signal based on a comparison of the divided oscillation signal and a reference frequency; and

means for adjusting an input to the oscillator based on the comparison.

45. The method comprises the following steps:

generating a series of dithering signals applied in a phase locked loop; and

the dithering signal is selected such that the average dithering value introduced in the phase-locked loop is substantially zero.