HK1077944A - Method and system for all digital gain control - Google Patents

Description

Method and system for full digital gain control

Technical Field

The present invention relates to the field of wireless communications. More particularly, the present invention relates to an all-digital gain control architecture.

Background

In most wireless communication systems, the baseband signal at the receiver is converted from analog to digital format to recover useful information through a series of digital processes. A common device for achieving this conversion function is an analog-to-digital converter (ADC). In an analog-to-digital converter (ADC), the most important specification is the number of output bits. Generally, as the number of output bits of the analog-to-digital converter (ADC) increases, the dynamic range of the input signal that the ADC can support also increases. However, the more output bits, the higher the cost of the analog-to-digital converter (ADC), and the remaining receiver components. Given the number of output bits, the output of the analog-to-digital converter (ADC) may also saturate if the input signal has too much power. On the other hand, if the power of the input signal is too small, the input signal may be heavily quantized (quantized). In either case, the information to be recovered at the receiver may be lost. To solve the above problem, it is common to add a dynamically adjustable gain amplifier in front of the analog-to-digital converter (ADC) to maintain the input signal of the ADC at a desired level. Typically, the adjustable gain is controlled using a closed loop mechanism, as shown in fig. 1, which may also be referred to as Automatic Gain Control (AGC).

In practice, several requirements must be considered using Automatic Gain Control (AGC). First, the Automatic Gain Control (AGC) should be fast enough to compensate for channel loss variations, but slow enough so that the signal envelope (envelope) does not deform. Second, the Automatic Gain Control (AGC) should not change the insertion phase of the radio, and thus not overload the de-rotation loop. In addition, the Automatic Gain Control (AGC) should also have a linear response (dB/Volt). Also, Automatic Gain Control (AGC) should be a closed loop control system to have sufficient stability (stability), settling time (settling time), overshoot (overshoot), and other design issues that should be considered. Furthermore, the Automatic Gain Control (AGC) should have control lines from the modem (modem) and usually from an additional digital-to-analog converter (DAC). In Time Division Duplex (TDD) and Time Division Multiple Access (TDMA) modes, Automatic Gain Control (AGC) must readjust the radio gain very quickly when an unknown large step (step) occurs in the input power. In addition, Automatic Gain Control (AGC) also requires a specific radio architecture with gain control, both of which increase cost and power consumption. Furthermore, Automatic Gain Control (AGC) also requires a trade-off between NF and IP3, especially when there is a large jammer (jammer). IP3 is a third order intercept point. NF is the noise figure. It is known that the higher the gain in front of the down-converter (demodulator), the better (lower) the noise figure, but the lower (worse) the third-order intercept point. In fact, some of the above requirements are very difficult to achieve. Therefore, currently available technologies must make trade-offs between the requirements, which results in a certain loss of system level performance.

Disclosure of Invention

To solve the problems faced by the currently used techniques, the present invention provides a method of compressing an input analog signal at baseband, converting the compressed signal to digital format, and expanding the digital signal to its original linear scale using anti-log techniques. The word length of the spread digital signal can be reduced by normalization.

Drawings

FIG. 1 is a block diagram illustrating a prior art closed loop Automatic Gain Control (AGC);

FIG. 2 is a block diagram showing All Digital Gain Control (ADGC) using a true logarithmic amplifier as the compressor and an inverse logarithmic look-up table (LUT) as the expander;

FIG. 3 is a graph showing the results of analog compression and digital expansion; and

fig. 4 is a graph comparing the digital gain control (ADGC) of the present invention and the conventional Automatic Gain Control (AGC) to show the performance improvement of a communication system.

Detailed Description

Fig. 1 shows a prior art closed loop Automatic Gain Control (AGC) circuit 10 in which analog inputs, including I and Q signals, are applied to amplifiers 12 and 14, respectively. The outputs of amplifiers 12 and 14 are analog-to-digital converted by analog-to-digital converters (ADCs) 16 and 18, shown as six-bit ADCs, providing I and Q outputs at outputs 16a and 18a, respectively.

The outputs of these analog-to-digital converters (ADCs) 16 and 18 are applied to a circuit 20 to obtain the sum of the squares of the I and Q signals, I²+Q²Which is then compared to a reference level in a comparison circuit 22. The output of the comparison circuit 22 is passed through an accumulator 24 are applied to a digital-to-analog converter (DAC)26 and to the gain control inputs 12b and 14b of these gain control amplifiers 12 and 14, respectively.

The all-digital gain control (ADGC) device 30 of the present invention avoids some of the requirements associated with conventional closed-loop Automatic Gain Control (AGC) circuits and readily satisfies the remaining requirements of such Automatic Gain Control (AGC) circuits. The present invention utilizes an analog-to-digital conversion method that increases the number of effective analog-to-digital conversion (ADC) bits by compressing a baseband input analog signal with an analog compressor (e.g., logarithmic circuit). The analog compressor is a nonlinear device in which the gain of the analog compressor is proportional to the analog input signal. Thus, the dynamic range of the analog input signal can be increased.

After the compressed analog signal is converted into a digital signal, a digital expander (e.g., an inverse log program or a look-up table (LUT)) is used to expand the digital signal back to the original linear scale. The digital spreader is a nonlinear device in which the gain of the digital spreader is proportional to the digital signal. The input character length of this number expander may be greater than the input character length due to the functional characteristics of most expanders. To reduce the word length of the digital signal for the remaining receivers, the present invention may utilize a normalization mechanism, which may be an open-loop or closed-loop automatic level control block.

Fig. 2 is a block diagram illustrating an All Digital Gain Control (ADGC) device 30 of the present invention. The all-digital gain control (ADGC) device 30 logarithmically amplifies the I and Q signals using logarithmic amplifiers 32 and 34, which are then passed to six-bit analog-to-digital converters 36 and 38, then to inverse-log look-up tables (LUTs) 40 and 42 to spread the digital signals, and then to a low pass filters 44 and 46 (e.g., square root raised cosine infinite impulse response (RRC + IIR) filters, each acting as an interpolation device).

The outputs of these filters 44 and 46 are applied to a circuit 48 which determines thisSum of squares I²+Q²The square root of (a). The output of circuit 48 is applied to circuit 50 to determine an average combined power measurement for the I and Q channels at the time the digital signal is reduced in number. This circuit 50 determines the average combined power block by block using equation (1), which can be expressed as:

equation (1)

Wherein n is the size of a square; s_iThe ith output of this circuit 50 within this block is sampled. The outputs of the filters 44 and 46 are delayed by n samples by delay circuits 52 and 54 to synchronize the timing of the outputs of the filters 44 and 46, thereby performing the functions of the circuits 48, 50, and 56. Thus, the outputs of circuits 58 and 60 can be represented as:

equation (2)

Wherein, I_kAnd Q_k(k-1, …, n) is the output of these filters 44 and 46, respectively, delayed by n samples.

According to the present invention, a dynamic range of 70dB can be easily achieved. An additional 20 to 30dB can be achieved by switching of a Low Noise Amplifier (LNA). The All Digital Gain Control (ADGC) device 30 does not require radio gain control and therefore has the advantages of low cost and easy implementation. The All Digital Gain Control (ADGC) device 30 can also support large real-time power variations. The All Digital Gain Control (ADGC) also supports high speed downlink and packet transmission. Furthermore, since the All Digital Gain Control (ADGC) device 30 of the present invention is an open loop, the present invention has no stability (stability) problem, no settling time (settling time), and no overshoot (overshoot). In addition, the All Digital Gain Control (ADGC) device 30 does not require knowledge of signal timing, which is also an important consideration in performing cell search, code acquisition, and frequency correction modes in systems utilizing Time Division Duplex (TDD) technology.

The all-digital gain control (ADGC) device 30 also provides fast fading compensation without distorting the signal envelope (envelope), which avoids high speed and/or high data rate problems and does not change the insertion phase of the system.

Fig. 3 shows the results of analog compression and digital expansion. In fig. 3, the step curve represents the relationship between the analog compressor input and the digital expander output. Obviously, with analog compression and digital expansion techniques, signals with small amplitudes can be quantized with very small quantization step (step). Thus, the quantization noise generated can be significantly reduced, thereby improving the overall performance of the receiver.

To facilitate observation of performance enhancements in a communication system, a Time Division Duplex (TDD) downlink simulation test, which is coupled with an ideal multiuser detector and with the addition of a Gaussian noise (Gaussian noise) channel, is used to perform a comparison between the all-digital gain control (ADGC) device 30 of the present invention and conventional Automatic Gain Control (AGC) circuitry. Fig. 4 shows the results of this simulation test. In the simulation test, each time slot of the input signal was subject to 20dB of power variation. As can be seen from fig. 4, the All Digital Gain Control (ADGC) device 30 of the present invention can improve the overall system performance by approximately 2dB at a block error rate (BLER) of 0.01.

Claims (21)

1. An apparatus for obtaining a wide range and high resolution analog to digital conversion of an input signal, comprising:

an analog compressor for compressing the input signal; and

an expander for digitally expanding the compressed signal and expanding the signal back to an original linear scale.

2. The apparatus of claim 1 wherein the analog compressor is a logarithmic compressor.

3. The apparatus of claim 1 wherein the spreader is an anti-log device.

4. The apparatus of claim 3 wherein the expander has a look-up table for determining an antilog of a compressed signal.

5. The apparatus of claim 3, further comprising: an analog-to-digital converter (ADC) is provided between the analog compressor and the digital expander.

6. The apparatus of claim 1, further comprising: a normalization circuit coupled to the number expander for reducing the word length of the digital output.

7. The apparatus of claim 1 wherein the input signal is obtained via a receiver that receives a wireless communication.

8. The apparatus of claim 1, further comprising: a receiver receives a wireless communication to provide the input signal to the analog compressor.

9. The apparatus of claim 1, further comprising: a receiver receives a wired communication to provide the input signal to the analog compressor.

10. The apparatus of claim 1 wherein the input signal is a baseband signal.

11. The apparatus of claim 1, further comprising: a filter for filtering an output of the spreader.

12. The apparatus of claim 11 wherein the filter is a root-raised cosine (RRC) filter.

13. The apparatus of claim 11 wherein the filter is an Infinite Impulse Response (IIR) filter.

14. A method for use in a communication system for performing analog-to-digital conversion of an input signal, comprising the steps of:

(A) logarithmically compressing the input signal at the fundamental frequency; and

(B) the compressed signal is logarithmically expanded to an original linear scale.

15. The method of claim 14, further comprising: converting the compressed signal to a digital format prior to the log-expansion step.

16. The method of claim 14, further comprising: normalizing the expanded digital signal.

17. The method of claim 14 wherein the input signal including I and Q components is independently compressed in step (a) and independently expanded in step (B).

18. The method of claim 17 wherein the I and Q components are independently converted from an analog format to a digital form after step (a) in preparation for step (B).

19. The method of claim 17 wherein the I and Q signals are filtered and normalized after step (B).

20. The method of claim 19, wherein the filtering step comprises: filtering is performed using an Infinite Impulse Response (IIR) filter.

21. The method of claim 19, wherein the filtering step comprises: filtering is performed using a root-raised cosine (RRC) filter.