HK1077881B - Liquid crystal display system with lamp feedback - Google Patents

Description

Lamp feedback liquid crystal display system

Technical Field

The present invention relates to dc-to-ac power converter circuits. More particularly, the present invention provides an efficient controller circuit that uses a zero voltage switching technique to regulate power to a load. The present invention is generally applicable to circuits driving one or more Cold Cathode Fluorescent Lamps (CCFLs), however, one skilled in the art will recognize that the present invention may be applied to any load requiring efficient and accurate power control.

Background

Fig. 1 illustrates a conventional CCFL power supply system 10. The system generally includes a power supply 12, a CCFL drive circuit 16, a controller 14, a feedback loop 18, and one or more CCFLs associated with an LCD panel 20. The power supply 12 provides a dc voltage to the circuit 16 and is controlled by the controller 14 through transistor Q3. The circuit 16 is a self-resonant circuit known as a Royer circuit. Essentially, circuit 16 is a self-oscillating dc-to-ac converter with a resonant frequency determined by L1 and C1, with N1 through N4 specifying the transformer windings and the number of turns in the windings. In operation, transistors Q1 and Q2 alternately conduct and switch the input voltage across windings N1 and N2, respectively. If Q1 is on, the input voltage is applied to winding N1. A voltage with opposite polarity will be placed on the other winding. The induced voltage of N4 makes the base of Q2 positive and Q1 turns on with a slight voltage drop between the collector and emitter. The induced voltage of N4 also keeps Q2 in the off state. Q1 conducts until the magnetic flux in the TX1 core reaches saturation.

In saturation, the voltage at the collector of Q1 rises rapidly (to a value determined by the base circuit) and the induced voltage in the transformer drops rapidly. Q1 is pulled far from saturation, and V_CERising, causing the voltage on N1 to drop further. Losses in the base drive cause Q1 to turn off, which in turn causes the magnetic flux in the core to drop slightly and a current to be generated in N4 to turn on Q2. The induced voltage of N4 keeps Q1 in a saturated conducting state until the core saturates in the reverse direction and a similar reverse process occurs to complete the switching cycle.

Although the inverter circuit 16 is made up of a relatively small number of components, its proper operation depends on the nonlinear complex interaction of transistors and transformers. In addition, variations in C1, Q1, and Q2 (typically 35% tolerance) do not allow circuit 16 to be suitable for use in a shunt transformer arrangement, as any duplication of circuit 16 would create additional undesirable operating frequencies that may resonate at certain harmonics. When applied to a CCFL load, this circuit produces a significant undesirable "flapping" effect in the CCFL. Even if the tolerances are nearly met, because the circuit 16 operates in a self-resonant mode, the "flapping" effect cannot be removed because any replica of the circuit will have its own characteristic operating frequency.

In U.S. patent No. 5,430,641; 5,619,402, respectively; 5,615,093, respectively; 5,818,172 some other drive systems may be found. These references all suffer from inefficiencies, two-stage power conversion, variable frequency operation, and/or load dependent disadvantages. In addition, when the load contains the CCFL and components, parasitic capacitance is introduced, thereby affecting the impedance of the CCFL itself. In order to effectively design a properly functioning circuit, the circuit design must take into account the parasitic impedance used to drive the CCFL load. Such efforts are not only time consuming, expensive, but also difficult to produce an optimal converter design when dealing with different loads. Therefore, there is a need to overcome these disadvantages and to provide a solution for a circuit that has the features of high efficiency, reliable lighting of CCFLs, load independent power regulation and single frequency power conversion.

Disclosure of Invention

The invention provides a liquid crystal display system, which comprises: a liquid crystal display panel; a cold cathode fluorescent lamp for illuminating the liquid crystal display panel; a secondary transformer winding coupled to the cold cathode fluorescent lamp, the winding providing current to the cold cathode fluorescent lamp; a primary transformer winding coupled to the secondary transformer winding, the winding providing magnetic flux to the secondary transformer winding; a switch coupled to the primary transformer winding, the switch allowing current to flow through the primary transformer winding; a feedback control loop circuit coupled to the cold cathode fluorescent lamp, the circuit receiving a feedback signal indicative of power provided to the cold cathode fluorescent lamp and controlling power delivered to the cold cathode fluorescent lamp if and only if the feedback signal is greater than a predetermined threshold, the feedback control loop maintaining a predetermined minimum power to the cold cathode fluorescent lamp when the feedback signal is not greater than a predetermined threshold.

In an alternative embodiment, a liquid crystal display system comprises: a liquid crystal display panel; a cold cathode fluorescent lamp for illuminating the liquid crystal display panel; a secondary transformer winding coupled to the cold cathode fluorescent lamp, the winding providing current to the cold cathode fluorescent lamp; a primary transformer winding coupled to the secondary transformer winding, the winding providing magnetic flux to the secondary transformer winding; a switch coupled to the primary transformer winding, the switch allowing current to flow through the primary transformer winding; a feedback control loop circuit coupled to the cold cathode fluorescent lamp, the circuit receiving a feedback signal from the cold cathode fluorescent lamp to maintain a predetermined minimum power to the cold cathode fluorescent lamp when the feedback signal indicates an open circuit condition.

The present invention also provides a method of controlling power supplied to a cold cathode fluorescent lamp in a liquid crystal display system, the method comprising the steps of: providing a pulse signal to the transistor as a conduction path of a primary transformer winding; generating a feedback signal from the CCFL coupled to the secondary transformer winding, the feedback signal being indicative of an electrical condition of the CCFL; receiving a feedback signal from the cold cathode fluorescent lamp; adjusting power supplied to the cold cathode fluorescent lamp if and only if the feedback signal indicates that the cold cathode fluorescent lamp is lit; and maintaining a predetermined minimum amount of power to said cold cathode fluorescent lamp when said feedback signal indicates no normal lighting.

It will be appreciated by those skilled in the art that although the following detailed description will proceed with reference being made to preferred embodiments and methods of use, the present invention is not intended to be limited to these preferred embodiments and methods of use. Rather, the invention is of broad scope and is intended to be defined and set forth only in the scope of the appended claims.

Other features and advantages of the present invention will be set forth in the following detailed description, which refers to the accompanying drawings, in which like parts are described with like numerals.

Drawings

FIG. 1 illustrates a conventional DC/AC converter circuit;

FIG. 2 is a diagram of a DC/AC converter circuit according to a preferred embodiment of the present invention;

FIGS. 2a-2f illustrate exemplary timing diagrams for the circuit of FIG. 2;

FIG. 3 is a schematic diagram of a DC/AC converter circuit according to another embodiment of the present invention;

FIGS. 3a-3f illustrate exemplary timing diagrams for the circuit of FIG. 3;

FIGS. 4a-4f show simulated views of the circuits of FIGS. 2 and 3;

FIG. 5 is a schematic diagram of an embodiment of a liquid crystal display system according to the present invention;

FIG. 6 is a schematic diagram of an embodiment of a liquid crystal display system according to the present invention;

FIG. 7 is a schematic diagram of an embodiment of a liquid crystal display system according to the present invention;

FIG. 8 is a schematic diagram of an embodiment of a display illumination system for an LCD system according to the present invention; and

FIG. 9 is a waveform of an embodiment of an LCD system according to the present invention;

Detailed Description

Although not intended to be limiting by way of example, the following detailed description will proceed with reference being made to a display panel having a CCFL as the load for the circuit of the present invention. It should be apparent, however, that the present invention is not limited to driving only one or more CCFLs, and should be more broadly construed as a power converter circuit and method that is independent of the particular load for a particular application.

In summary, the present invention provides a circuit for regulating the on-time of two pairs of switches using a feedback signal and a pulse signal to control the delivery of power to a load. When a pair of switches are controllably conductive such that their conduction times overlap, power is delivered to the load through a transformer along a conduction path defined by the pair of switches. Similarly, when the other pair of switches is controllably conductive such that their conduction times overlap, power is delivered to the load through the transformer along a conduction path defined by the other pair of switches. Thus, by selectively turning on the overlap between the switches and the control switch, the present invention can accurately control the power delivered to a given load. In addition, the present invention includes an overcurrent and overvoltage protection circuit that suspends power to a load in the event of a short circuit or an open circuit. Also, the controllable switching topology described herein enables the circuit to operate independently of the load and using a single operating frequency independent of the resonant effects of the transformer configuration. These characteristics will be discussed below with reference to the figures.

The circuit diagram shown in fig. 2 illustrates a preferred embodiment of the phase-shifted, full-bridge, zero-voltage-switching power converter of the present invention. In essence, the circuit shown in fig. 2 comprises: a power source 12; a plurality of switches 80 defining diagonally arranged pairs of switches of alternating conduction paths; a drive circuit 50 that drives each switch; a frequency sweep 22 for generating square wave pulses to the driving circuit 50; a transformer TX1 (with an associated resonant tank circuit defined by the primary side of TX1 and C1) and a load. Advantageously, the present invention further comprises an overlapping feedback control loop 40 that controls the on-time of at least one of each pair of switches, thereby allowing controllable power delivery to the load.

Power 12 is applied to the system. Initially, a bias/reference signal 30 is generated from the power supply for the control circuit (in control loop 40). Preferably, a frequency scanner 22 generates a pulse signal with a 50% duty cycle, starting at a higher frequency and sweeping down at a predetermined rate and in predetermined steps (i.e., a variable pulse width square wave signal). The frequency scanner 22 is preferably a programmable frequency generator as is known in the art. The pulse signal 90 (from the frequency scanner 22) is sent to the B _ Drive circuit (B _ Drive) (which drives switch _ B, i.e., the gate of control switch _ B) and to the a _ Drive circuit (a _ Drive), which generates a complementary pulse signal 92 and a ramp signal 26. The complementary pulse signal 92 is approximately 180 degrees different from the pulse signal 90 and the ramp signal 26 is approximately 90 degrees different from the pulse signal, as will be described below. The ramp signal 26 is preferably a sawtooth signal as shown. Ramp signal 26 will be compared to the output signal 24 of error amplifier 32 (referred to herein as CMP) by comparator 28, thereby producing signal 94. The output signal 94 of comparator 28 is also a 50% duty cycle pulse sent to the C _ Drive circuit (C _ Drive) to trigger the conduction of Switch _ C (Switch _ C), which in turn determines the amount of overlap between switches B and C and between switches a and D. The complementary signals (with a phase difference of about 180 degrees) are applied to the switch _ D through the D _ Drive circuit (D _ Drive). Those skilled in the art will recognize that the circuitry of driver circuits _ a through _ D are coupled to control lines (e.g., gates) of switches _ a and switches _ D, respectively, as described herein, to allow each switch to be controllably conductive. Lamp current regulation is accomplished by adjusting the amount of overlap between switches B, C and A, D. In other words, it is the amount of overlap in the on state of the switch pair that determines the amount of power handled in the converter. Thus, switches B and C, and switches a and D are referred to herein as overlay switches.

Although not intended to be limited by the example of this embodiment, the B driver circuit is preferably formed of a totem pole circuit, a normal low impedance operational amplifier circuit, or an emitter follower circuit. The D _ drive circuit has a similar configuration. Since neither the a _ driver circuit nor the C _ driver circuit is directly grounded (i.e., floating), these driver circuits are preferably formed by boot _ strap circuit or other high-side driver circuits known in the art. In addition, as described above, the a _ drive circuit and the C _ drive circuit include an inverter for inverting the signals (i.e., phases) from the B _ drive circuit and the D _ drive circuit, respectively.

Efficient operation is achieved through a zero voltage switching technique. The four MOSFETs (switch _ a to switch _ D)80 conduct after their intrinsic diodes (D1 to D4) conduct, which provides a current flow path for energy in the transformer/capacitor (TX1/C1) configuration, thereby ensuring that when these switches conduct, the voltage across them is zero. Due to this controllable operation, switching losses are minimized and high efficiency is maintained.

The preferred switching operation of the overlay switch 80 is illustrated with reference to the timing diagrams of fig. 2a to 2 f. Switch _ C is turned off during a certain period of time when switches B and C are simultaneously on (fig. 2 f). When switch _ C is turned off, the current in the tank (see fig. 2) now flows through diode D4 (fig. 2e) in switch _ D, the primary side of the transformer, C1 and switch _ B, thereby resonating the voltage and current in the capacitor C1 and the transformer as a result of the energy transfer when switch B and switch C are turned on (fig. 2 f). Note that this situation must occur because a sudden change in the direction of the primary current in the transformer will violate faraday's law. Therefore, current must flow through D4 when switch _ C is open. D4 is conductive, switch _ D is closed conductive. Likewise, switch _ B is open (fig. 2a), and current is delivered to diode D1 (fig. 2e) associated with switch _ a before switch _ a closes. Likewise, switch _ D is opened (fig. 2D), and current now flows from switch _ a through C1, the transformer primary and diode D3. Switch _ C closes after D3 turns on (fig. 2 e). Switch _ B closes after switch _ a opens, which allows diode D2 to be turned on first before switch _ B closes. Note that the overlap of the closing times of the diagonally opposite switches B, C and A, D determines the energy delivered to the transformer, as shown in fig. 2 f.

In this embodiment, fig. 2b shows that the ramp signal 26 is generated only when switch _ a is closed. Therefore, the driving circuit _ a for generating the ramp signal 26 preferably includes a constant current generator circuit (not shown) including a capacitor having a suitable time constant for generating the ramp signal. For this purpose, the capacitor is charged with a reference current (not shown) and grounded (via, for example, a transistor switch) so that the discharge rate exceeds the charge rate, thereby generating a sawtooth ramp signal 26. Of course, as described above, this may be accomplished by integrating the pulse signal 90, and thus an integrator circuit (e.g., an operational amplifier and a capacitor) may be used to form the ramp signal 26.

During the lighting process, a predetermined minimum overlap is created between the two diagonal switches (i.e., between switches A, D and B, C). This results in a minimum energy input to the tank circuit including the C1, transformer, C2, C3 and CCFL loads. Note that the load may be resistive and/or capacitive. The driving frequency starts at a predetermined higher frequency until it approaches the resonant frequency of the tank circuit and the equivalent circuit reflected by the secondary side of the transformer, and a large amount of energy is transferred to the load to which the CCFL is connected. Because of its high impedance characteristic before ignition, CCFLs are subject to high voltages from the energy supplied to the primary side. This voltage is sufficient to ignite the CCFL. The CCFL impedance drops to its normal operating value (e.g., 100K ohms to 130K ohms) and the energy provided to the primary side based on minimum overlap operation is no longer sufficient to maintain steady state operation of the CCFL. The output of error amplifier 26 begins its regulation function to increase the overlap. It is the magnitude of the error amplifier 26 output that determines the amount of overlap. For example:

referring to fig. 2b, 2C and the feedback loop 40 of fig. 2, it is important to note that switch _ C is closed when the comparator 28 determines that the values of the ramp signal 26 (produced by the drive circuit _ a) and the signal CMP24 (produced by the error amplifier 32) are equal. As shown by the intersection 36 in fig. 2 b. To prevent a short circuit, switches A, B and C, D must not be closed at the same time. By controlling the size of the CMP, the overlap time between switches A, D and B, C regulates the energy delivered to the transformer. Switches C and D are time shifted with respect to switches a and B by controlling the error amplifier output CMP24 in order to adjust the energy delivered to the transformer (and thus the energy delivered to the CCFL load). It can be seen from the timing diagram that if the drive pulses from the output of comparator 28 into switches C and D are shifted to the right by increasing the magnitude of CMP, then an increase in the overlap between switches a and D, B and C is achieved, thus increasing the energy delivered to the transformer. In practice, this corresponds to a higher lamp current operation. Conversely, shifting the drive pulses of switches C and D to the left (decreasing the CMP signal) will cause the energy transferred to decrease.

For this purpose, the error amplifier 32 compares the feedback signal FB with a reference voltage REF. FB measures the value of the current through the sense resistor Rs, which represents the total current through the load 20. REF is a signal indicative of an ideal load condition, such as a desired current through the load. In normal operation, REF ═ FB. However, if the load condition is deliberately compensated, for example by a dimmer switch connected to an LCD flat panel display, the value of REF will increase/decrease accordingly. The comparison value correspondingly yields CMP. The value of CMP reflects the load condition and/or an intentional bias and is realized by the difference between REF and FB (i.e., REG-FB).

To protect the load and circuitry from an open circuit condition at the load end (e.g., an open CCFL condition during normal operation), the FB signal is preferably compared to a reference value (not shown and different from the REF signal described above) in a current sense comparator 42, the output of which defines the state of switch 38 as described below. This reference value may be programmable and/or user definable and preferably reflects the minimum or maximum current allowed by the system (e.g., which may be rated for individual components, particularly for CCFL loads). If the values of the feedback FB signal and the reference signal are within the allowable range (normal operation), the output of the current detection comparator is 1 (or high). This allows CMP to flow through switch 38 and the circuit operates as described herein to deliver power to the load. However, if the values of the FB signal and the reference signal are outside a predetermined range (open or short state), the output of the current detection comparator is 0 (or low), prohibiting the CMP signal from flowing through the switch 38. (of course, the reverse process can be implemented where the switch is triggered in the 0 state). The minimum voltage Vmin is not provided by the switch 38 (not shown) and delivered to the comparator 28 until the current sensing comparator indicates that current is allowed to flow Rs. Accordingly, the switch 38 includes a circuit for appropriately selecting the programmable voltage Vmin when the detection current is 0. Referring again to fig. 2b, the effect of this operation is that the CMP dc value drops to the nominal or minimum value (i.e., CM ═ Vmin), so that the transformer TX1 does not experience a high voltage condition. Thus, the crossover point 36 is shifted to the left, thereby reducing the amount of overlap between the complementary switches (switch _ C closed at crossover point 36). Similarly, when the detection value is 0 (or other preset value indicating an open circuit state), the current detection comparator 42 is connected to the frequency generator 22 to turn off the frequency generator 22. The CMP is fed back to the protection circuit 62. If the CCFL is removed during operation (open circuit condition), this is to turn off the frequency scanner 22.

In order to protect the circuit from an overvoltage condition, the present embodiment preferably includes a protection circuit 60, the operation of which will be given below (the description of the overcurrent protection by the current sensing comparator 42 is as described above). Circuit 60 includes a protection comparator 62 that compares signal CMP with a voltage signal 66 derived from load 20. Preferably, the voltage signal is derived from voltage divider capacitors C2 and C3 (in parallel with load 20) as shown in fig. 2. In the open-lamp condition, the frequency sweep continues until the OVP signal 66 reaches a threshold. The OVP signal 66 is obtained from the output voltage dividing capacitors C2 and C3 to detect the voltage output by the transformer TX 1. To simplify the analysis, these capacitances also represent the total capacitance of the equivalent load capacitance. The threshold is a reference value and the circuit is designed so that the voltage on the secondary side of the transformer is greater than a minimum lamp voltage (e.g., the voltage required by an LCD display) and less than the rated voltage of the transformer. When the OVP exceeds the threshold, the frequency sweep is stopped by the frequency sweep. At the same time, the current sense 42 does not sense a signal at the sense resistor Rs. Thus, setting the signal at the output 24 of switch block 38 at a minimum value, the overlap between switches a and D, B and C is minimal. Preferably, timer 64 is started once the OVP exceeds the threshold, thereby initiating a timed-out sequence. The period of the timing sequence is preferably designed according to the load requirements (e.g., CCFL of LCD display), but may be set to some programmable value. Once the timed time is over, the drive pulse is deactivated, thereby providing a safe operating output of the converter circuit. That is, circuit 60 provides a sufficient voltage to cause the lamp to ignite, and if the lamp is not connected to the converter, it is turned off after a certain period of time, thus avoiding an erroneously high voltage at the output. Such a period of time is necessary because the unlit process is similar to the open state.

Fig. 3 and 3a-3f depict another preferred embodiment of the dc/ac circuit of the present invention. In this embodiment the circuit operates in a similar manner to that provided in figures 2 and 2a-2f, however the embodiment also includes a phase locked loop circuit (PLL)70 for controlling the frequency sweep 22 and a flip-flop circuit 72 for timing the signal input to the C _ drive circuit. As can be appreciated from the timing diagram, if the drive pulses for switches C and D are shifted to the right by 50% by increasing the size of CMP, an increase in the overlap between switches a and D, B and C can be achieved, thereby increasing the energy delivered to the transformer. In practice this corresponds to higher lamp current operation (possibly requiring a manual increase in REF voltage as described above). Conversely, left shifting of the drive pulses of switches C and D (by lowering the CMP signal) reduces the energy delivered. The phase-locked loop circuit 70 maintains the phase relationship between the feedback current (via Rs) and the slot current (via TX1/C1) under normal operation, as shown in fig. 3. The PLL circuit 70 preferably contains the input signals from the tank circuits (C1 and TX1 primary side), signals 98 and Rs (FB signal described above). Once the CCFL is lit and the current in the CCFL is detected by Rs, the PLL70 circuit is activated, which locks the phase between the lamp current and the primary resonant tank (C1 and transformer primary side) current. That is, the PLL adjusts the frequency of the frequency scanner 22 due to parasitic variations like temperature effects, mechanical arrangements like wiring between the transducers that affect the capacitance and inductance values and the LCD panel, and the distance between the lamp and the metal chassis of the LCD panel. The system preferably maintains a phase difference of 180 degrees between the resonant tank circuit and the current flowing through Rs (load current). Thus, the system can find an optimum operating point regardless of the particular load condition and/or operating frequency of the resonant tank circuit.

The operation of the feedback loop of fig. 3 is similar to that described above for fig. 2. However, as shown in fig. 3b, this embodiment clocks the enable signal output by the C _ driver circuit through the flip-flop 72. For example, in normal operation, the output of error amplifier 32 will be fed back by controlling switch block 38 (as described above), resulting in signal 24. A certain amount of overlap between switches a and D, B and C is obtained by comparator 28 and flip-flop 72, which flip-flop 72 drives switches C and D (the D drive circuit generates the complementary signal of the C drive circuit). This provides steady state operation for CCFL (display panel) loads. Considering that the CCFL (display panel) is removed in normal operation, the CMP increases to a boundary value (rail output) of the error amplifier output and immediately triggers the protection circuit. This function is disabled at the time of lighting.

Referring briefly to fig. 3a-3f, in this embodiment, switches C and D are alternately triggered by a C _ driver circuit and a D _ driver circuit as a result of the operation of trigger circuit 72. As in fig. 3b, the flip-flop toggles every other time, thereby initializing the C _ drive circuit (and, correspondingly, the D _ drive circuit). Otherwise the timing would work in the same manner as described above with reference to figures 2a-2 f.

Referring now to fig. 4a-4f, the output current of fig. 2 or 3 is simulated. For example, FIG. 4a shows that at 21V input, the output reaches 1.67KVp-p as the frequency scanner approaches 75.7KHz (0.5us overlap). If the CCFL needs 3300Vp-p to light, this voltage is not sufficient to light the CCFL. When the frequency is reduced to, for example, 68KHz, the minimum overlap produces about 3.9KVp-p at the output, which is sufficient to light the CCFL. As shown in fig. 4 b. At this frequency, the overlap was increased to 1.5u s, resulting in an output of approximately 1.9KVp-p for operating a lamp impedance of 130K ohms. This is already shown in fig. 4 c. As another example, fig. 4d shows operation at an input voltage of 7V. At 71.4KHz, the output is 750Vp-p before the lamp is ignited. As the frequency decreases, the output voltage increases until the lamp ignites. FIG. 4e shows that at 68.5KHz, the output reaches 3500 Vp-p. The adjustment of the CCFL current is done by adjusting the overlap and supports an impedance of 130K ohms after ignition. The voltage of the CCFL is 1.9KVp-p for a 660Vrms lamp. This is also shown in fig. 4 f. Although not shown, the circuit simulation of fig. 3 is performed in a similar manner.

It should be noted that the difference between the first and second embodiments (i.e. the addition of the flip-flop and PLL in fig. 3) will not affect the overall operating parameters set forth in fig. 4a-4 f. However, the decision to add a PLL is to take into account non-ideal impedance in the circuit and may be added as an alternative to the circuit shown in fig. 2. At the same time, the addition of a flip-flop allows the removal of the constant current circuit described above.

It is therefore apparent that there has been provided a highly efficient adaptable dc/ac converter circuit that meets the objectives set forth herein. It will be apparent to those skilled in the art that certain modifications may be made. For example, although the present invention has been described using MOSFETs as switches, one skilled in the art will recognize that the entire circuit may be constructed using BJT transistors, or any combination of types of transistors, including MOSFETs and BJTs. Other modifications are also possible. For example, the driver circuits associated with driver circuit _ B and driver circuit _ D may be composed of a common collector circuit, since the associated transistors are grounded, and thus no floating state occurs. The PLL circuit described herein is preferably a conventional PLL circuit 70 known in the art, suitably modified to receive an input signal and generate a control signal, as described above. The pulse generator 22 is preferably a Pulse Width Modulation (PWM) or bandwidth modulation (FWM) circuit, both of which are well known in the art. Likewise, the protection circuit 62 and the timer are constituted by known circuits and are appropriately modified to operate as described herein.

FIG. 5 illustrates an embodiment of a liquid crystal display system of the present invention. The liquid crystal display system 500 includes a thin film transistor display panel 501. Thin film transistor display 501 is coupled to column driver circuit 502. The column driver circuit 502 controls columns on the thin film transistor display panel 501. Thin film transistor display screen 501 is also coupled to row driver circuit 503. The row driver circuit 503 controls the rows on the thin film transistor display panel 501. The column driving circuit 502 and the row driving circuit 503 are coupled to a timing controller 504. The timing controller 504 controls the timing of the column driving circuit 502 and the row driving circuit 503. The timing controller 504 is coupled to the video signal processor 505. The video signal processor 505 processes a video signal. In another embodiment, the video signal processor 505 may be a scaler device.

Thin film transistor display screen 501 is illuminated by display illumination system 599. The display illumination system 599 includes a cold cathode fluorescent lamp 562. A cold cathode fluorescent lamp 562 is coupled to the secondary transformer winding 560. Secondary transformer winding 560 provides current to cold cathode fluorescent lamp 562. Secondary transformer winding 560 is coupled to primary transformer winding 518. The primary transformer winding 518 provides magnetic flux to the secondary transformer winding 560. The primary transformer winding 518 is coupled to a switch 532. Switch 532 allows current to flow through primary transformer winding 518. The primary transformer winding 518 is also coupled to the switch 512. The switch 512 allows current to pass through the primary transformer winding 518. Switch 532 and switch 512 are coupled to controller 550. The controller 550 provides a pulse signal for controlling the switching between the switch 532 and the switch 512. It is noted that any controller described herein may be used as the controller 550. It is also worth noting that any of the display illumination systems described herein may be substituted for the display illumination system 599.

FIG. 6 depicts another embodiment of a liquid crystal display system of the present invention. The liquid crystal display system 600 includes a thin film transistor display 601. Thin film transistor display 601 is coupled to column driver circuit 602. The column driver circuit 602 controls columns on the thin film transistor display screen 601. Thin film transistor display 601 is also coupled to row driver circuit 603. The row driver circuit 603 controls the rows on the thin film transistor display 601. The column driving circuit 602 and the row driving circuit 603 are coupled to a timing controller 604. The timing controller 604 controls the timing of the column driving circuit 602 and the row driving circuit 603. The timing controller 604 is coupled to the video signal processor 605. The video signal processor 605 processes a video signal. The video signal processor 605 is coupled to a video demodulator 606. The video demodulator 606 demodulates the video signal. The video demodulator 606 is coupled to a tuner 607. Tuner 607 provides a video signal to video demodulator 606. Tuner 607 tunes lcd system 600 to a particular frequency. The video demodulator 606 is also coupled to a microcontroller 608. The tuner 607 is also coupled to an audio demodulator 611. The audio demodulator 611 demodulates the audio signal from the tuner 607. An audio demodulator 611 is also coupled to the audio signal processor 610. The audio signal processor 610 processes the audio signal from the audio demodulator 611. The audio signal processor 610 is coupled to an audio amplifier 609. The audio amplifier 609 amplifies the audio signal from the audio signal processor 610.

Thin film transistor display 601 is illuminated by display illumination system 699. The display illumination system 699 includes cold cathode fluorescent lamps 662. A cold cathode fluorescent lamp 662 is coupled to the secondary transformer winding 660. Secondary transformer winding 660 provides current to cold cathode fluorescent lamp 662. Secondary transformer winding 660 is coupled to primary transformer winding 618. Primary transformer winding 618 provides magnetic flux to secondary transformer winding 660. The primary transformer winding 618 is coupled to a switch 632. Switch 632 allows current to flow through primary transformer winding 618. The primary transformer winding 618 is also coupled to the switch 612. Switch 612 allows current to pass through primary transformer winding 618. Switch 632 and switch 612 are coupled to controller 650. The controller 650 provides a pulse signal for controlling the switching between the switch 632 and the switch 612. It is noted that any controller described herein may be used as controller 650. It is also worth noting that any of the display illumination systems described herein may be substituted for display illumination system 699.

FIG. 7 depicts another embodiment of a liquid crystal display system of the present invention. The lcd system 700 includes a graphics adapter 790. The liquid crystal display system 700 may also include the components of the liquid crystal display system 500 described above and shown in fig. 5, or the components of the liquid crystal display system 600 described above and shown in fig. 6. The graphics adapter 790 is coupled to a video signal processor, which video signal processor 505 may be the video signal processor 505 described above and shown in fig. 5 or the video signal processor 605 described above and shown in fig. 6.

Graphics adapter 790 is coupled to chipset core logic 791. The chipset core logic 791 transfers data between devices connected to it. Chipset core logic 791 is also coupled to the microprocessor 792. The microprocessor 792 processes data, including video data. Chipset core logic 791 is also coupled to storage 793. The storage 793 randomly accesses storage and provides short-term storage of data. Chipset core logic 791 is also coupled to hard disk drive 794. Hard disk drive 794 provides long-term storage of data. The chipset core logic 791 is also coupled to an optical disk drive 795. The optical disk drive 795 retrieves data from a CD-ROM or DVD-ROM.

Referring to FIG. 8, one embodiment of a switched mode CCFL power supply circuit 100 in accordance with the present invention is described. The present invention is a switch mode power supply that provides power to a Cold Cathode Fluorescent Lamp (CCFL). The power supply converts a Direct Current (DC) low voltage into an Alternating Current (AC) high voltage and supplies it to the CCFL.

The switch mode power supply circuit includes a first switch having a source, a drain, and a gate. The drain of the first switch is connected to the primary winding of the step-up transformer. The number of turns of the secondary winding of the step-up transformer is at least 20 times, preferably 50 to 150 times, the number of turns of the primary winding. The source of the first switch is connected to a power source.

The second switch also has a source, a drain, and a gate. The drain of the second switch is connected to both the drain of the first switch and one end of the primary winding of the transformer. The source of the second switch is connected to a ground reference of a power supply. The primary winding has a second terminal connected to the midpoint of a two-capacitor voltage divider. Thus, the two switches are connected in series, approximately sharing the input voltage of the power supply. The two capacitors are connected in series and then connected to two ends of a power supply.

A control circuit transmits control signals to the first and second switches to alternately close the switches with a phase shift of 180 degrees. When the first switch is closed, a current flows through the first switch and the primary winding of the transformer in a reference forward direction. When the second switch is closed, the current flows in a reverse direction through the primary winding of the transformer and through the second switch.

The transformer is driven from two directions so that the magnetic flux of the core sweeps for two quadrants in the hysteresis curve associated with the transformer. This reduces the size of the transformer core and thus saves the cost of the transformer.

The two capacitors form a capacitive voltage divider connected to one end of the primary winding of the transformer. When each switch is closed, both capacitors are charged or discharged by the current flowing through the primary winding of the transformer. When the first switch is closed, the current discharges the first capacitor and charges the second capacitor at the same time, and when the first switch is turned off and the body diode connected to the second switch is turned on, the current is reset. When the second switch is closed, the current flowing through the primary winding of the transformer reverses. With this current flow direction, the first capacitor is charged and the second capacitor is discharged. After the second switch is turned off, the current is restored via the body diode of the first switch. If the switches are closed when their body diodes are conducting, the switches are closed at substantially zero voltage. This zero voltage switching technique minimizes the switching losses of the switch. Therefore, the efficiency of the power converter is improved.

The power supply circuit 100 includes a controller 150, a first switch 112, a second switch 132, and a transformer 120, and is connected to a power source 274 for providing power to a load (e.g., CCFL162 in a flat panel display, such as a liquid crystal display).

The first switch 112 may be an N-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) gated switch and includes a drain 114 connected to one end of a primary winding 118 of a step-up transformer 120. A second terminal 125 of primary winding 118 is connected to a junction of first capacitor 124 and second capacitor 126. The source 128 of the first switch 112 is connected to the ground reference of the power supply 274. The second switch 132 may be a P-channel MOSFET gate controlled switch. The drain of P-channel switch 132 is also connected to drain 114 of switch 112. Both switch 112 and switch 132 include intrinsic diodes 134 and 136, respectively. Gates 138 and 152 of switches 132 are connected to an output of controller 150.

The secondary winding 160 of the step-up transformer 120 is connected to the CCFL 162. In contrast to the non-linear permeability of the saturable core used in transformers of the prior art roy circuits, step-up transformer 120 is formed with a core having a linear permeability that is not saturated when power supply circuit 100 is operating. The turn ratio of the step-up transformer 120 is at least 20: 1 and is typically in the range of 50: 1 to 150: 1.

The secondary winding 160 of the step-up transformer 120 is connected in parallel with two capacitors 163, 164 connected in series. Capacitors 163 and 164 form a voltage divider for detecting the voltage of the secondary winding 160 of the step-up transformer 120 and converting the rectangular wave of the primary winding 118 into an approximate sine wave to be supplied to the CCFL load 162. Under normal operation, the detection voltage 186 is often reset by the switch 170, which is controlled by the current flowing through the CCFL 162. The function of the switch 170 will be described in detail below.

The controller 150 may be a pwm controller that provides a first gate driving signal 152 to the gate 152 of the switch 112 and a second gate driving signal 138 to the gate 138 of the switch 132. In addition to providing drive signals to the switches 112, 132, the controller 150 provides other functions, such as two distinct frequencies for CCFL lighting and normal operation. The lamp-on identifying circuit 250 in the controller 150 is used to determine whether the CCFL162 is lit and to determine which of the two frequencies is output. When the CCFL162 is lit, the lamp-on signal 252 is not set (de-asserted), and indicates that the CCFL162 is not lit, and indicates that its circuit is open. Based on the signal 252, a first frequency is obtained at the oscillator 254. After lighting, a current flowing through the CCFL162 is detected. Thus, signal 252 is set (asserted), representing the CCFL being lit. A second frequency is obtained at the output of oscillator 254. It should be noted that the light-on signal 252 also determines the output 256 of a low frequency Pulse Width Modulation (PWM) circuit 258. During lighting, the signal 256 does not interfere with the waveform supplied to the CCFL162 to obtain a smooth lighting voltage. In other words, the signal 256 does not affect the output control logic 286 until the signal 252 is set.

The controller 150 also contains lamp current and voltage sensing and control functions. The lamp current is sensed through resistor 182. The sensed value 184 is compared to the reference 212 by a comparator, such as an error amplifier 230 that controls the timing of the closing of the switches 112 and 132. The lamp voltage is detected by the capacitive voltage divider 163 and 164. The detection value 186 is compared to the reference 214 by a comparator 232. The output 234 of the comparator 232 determines the start of a digital clock timer 236. After a period of time (e.g., one to two seconds) has elapsed after the clock timer 236 is started, the output signal 238 of the clock timer 236 causes the protection circuit 240 to be set to stop operation of the switches 112 and 132 if the output 234 is still not set. This time period is used to provide a small amount of time (e.g., one to two seconds) for the CCFL 162. The oscillator 254 provides two frequencies for operation of the power supply circuit 100, a higher frequency for lighting and a lower frequency for normal operation. The higher frequencies may be 20% to 30% higher than the lower frequencies. The lower frequency may be 68KHz as shown in fig. 4b, or 65.8KHz as shown in fig. 4e, or a value lower than either of these two frequencies.

The low frequency pulse width modulation circuit 258 is used to generate a signal 256 to adjust the energy delivered to the lamp, thereby achieving brightness control. The frequency of signal 256 is preferably in the range of 150Hz to 400 Hz. The lamp turn-on identification circuit 250 receives a lamp current detection signal 184, the output signal 252 of which is set to identify the presence of the CCFL load 162 or completion of lighting. The protection circuit 240 receives a signal 252 indicative of the presence of the CCFL162, a signal 260 indicative of the presence of a current sensed at the CCFL162, and a signal 238 indicative of the timing of the open circuit condition. Thus, when an open circuit, overcurrent, overvoltage condition occurs at lamp 162, or an undervoltage occurs at voltage input 130, output signal 262 of protection circuit 240 is set to stop operation of switches 112 and 132.

The controller 150 includes a ground pin 272 connected to circuit ground (circuit ground) and a voltage input pin 130 connected to a dc voltage source. In the controller 150, the voltage input pin 130 is connected to a reference/bias circuit 210 that generates various reference voltages 212, 214, etc. for internal use. The voltage input pin 130 is also connected to an under-voltage lock-out circuit 220 and an output driver circuit 222. When the voltage provided to the voltage input pin 130 exceeds a threshold, the output signal 224 of the circuit 220 causes the rest of the controller 150 to begin operation. On the other hand, if the voltage at the voltage input pin 130 is less than the threshold, the signal 224 will stop the operation of other parts of the controller 150.

The dimming function and the open circuit function of the CCFL are substantially complementary when the CCFL is operating. Advantageously, the two signals 168 and 186 may be multiplexed, with the signals 168 and 186 being received at a pin 284 of the controller 150. This operation reduces the cost of the controller 150.

The clock pin 276 of the controller 150 is connected to the oscillator 254, which is connected to circuit ground via a capacitor 278 or to the voltage input pin 130 via a resistor 280 to provide a clock signal (preferably a ramp signal) at 276.

Advantageously, in the present invention, the power supply circuit 100 performs the most functions to drive the CCFL load with the least number of connections to the controller 150. The operation of this power supply is as follows.

A Direct Current (DC) voltage VIN is applied to the power supply circuit 100. Once the voltage input at 130 exceeds the threshold set by the under-voltage-lockout circuit 220, the controller 150 begins operation. reference/I-bias circuit 210 generates a reference voltage for other circuits in controller 150.

Since the CCFL162 is not lit and there is no current feedback signal 184 from the CCFL load 162, the oscillator 254 generates a higher frequency pulse signal. The driver circuit 222 outputs a pulse width modulated drive signal 152 and 138 to the switches 112 and 132, respectively. The capacitor 216 is gradually charged so that the voltage 260 gradually increases over time. Because the voltage at 260 gradually increases over time, the pulse width of the drive signals 138 and 152 gradually increases. Accordingly, the power delivered to the step-up transformer 120 and the load 162 also gradually increases. Capacitors 124 and 126 are designed such that the voltage across each capacitor is approximately one-half of the input voltage. During the first half-cycle, switch 132 is closed and a current flows from the power source, through switch 132, and to primary winding 118. This current then flows into the capacitor 126 and includes a magnetizing current and a reflected load current. When capacitor 126 charges, capacitor 124 discharges. When switch 132 is open, the current in primary winding 118 continues to flow in the same direction. Diode 134 causes the current to continue to flow in the same direction. After about 180 degrees out of phase after switch 132 is closed, switch 112 is closed. The power supply causes current to flow through capacitor 124 to primary winding 118 and in the opposite direction through switch 112 to reference circuit ground 272. The current (including the magnetizing current and the reflected load current) may flow in the reverse direction. At the same time, capacitor 124 charges when capacitor 126 discharges. Diode 136 supports the continued flow of current in primary winding 118 when switch 112 is open. After approximately 180 degrees out of phase after switch 112 is closed, switch 132 is closed. The switch continues to operate periodically. Therefore, the voltage of the primary winding 118 is substantially a rectangular wave.

Fig. 9 depicts waveforms at different ports. Fig. 9(a) shows the drive waveform at 152. Fig. 9(b) shows the corresponding drive waveform at 138. Note that the switch closure times for switches 112 and 132 are 180 degrees apart. Of course, the switch 132 could be an N-channel device instead. In this case, the logic of the drive signal 138 is inverted to represent an ON/OFF (ON/OFF) drive signal. Fig. 9(c) shows the waveform at 125. The small ripple superimposed on the dc voltage (half of the input voltage VIN) represents the charging and discharging of the capacitor 126. The voltage at 125 is subtracted from the input voltage VIN to obtain a similar waveform representing the voltage at 124, which also has a small ripple superimposed on one-half of the input voltage. Fig. 9(d) shows the voltage at 114, while fig. 9(f) shows the current flowing through the primary winding 118. Note that when the switch is closed at t1, the voltage at 114 is near VIN. Current from primary winding 118 flows in a forward direction on a reference basis to charge capacitor 126 while discharging capacitor 124. Thus, the voltage at the capacitor 126 increases (positive slope). At time t2, switch 132 is open. The current at primary winding 118 continues to flow in the same direction and tends to decrease. Diode 134 continues to circulate this current until the current decreases to zero at t 3. During the period from t2 to t3, it is apparent that the voltage at 114 is close to zero. The voltage at the capacitor 126 still increases because current flows in the same direction. At the instant after t3, a small current flows in the reverse direction due to the reverse magnetomotive force of the primary winding 118, and the diode 136 conducts, 114 with a voltage equal to VIN plus the forward voltage drop of the diode 136. At time t4, switch 112 is closed. Voltage 114 drops to near zero while the current in primary winding 118 increases in the opposite direction. When capacitor 124 is charged, capacitor 126 discharges. Therefore, the voltage of the capacitor 126 decreases (negative slope). Switch 112 is open at time t5, diode 136 is conductive, and current continues to flow. Diode 136 stops conducting when the current of primary winding 118 reaches zero. At the same time, a small current flows in the reference forward direction. In other words, since diode 134 is conducting, the voltage at 114 is close to zero. Operation continues until the next cycle begins at time t7 and switch 132 is closed again. Step-up transformer 120 is driven from both directions, thus maximizing the use of magnetic flux sweeping to provide power to the CCFL load. The step-up transformer 120, the output capacitors 163 and 164 and all parasitic reactive components associated with the secondary side circuitry of the transformer 120 form a tank circuit. The slot circuit selects the higher harmonic components associated with the rectangular wave appearing at the primary winding 118 and produces a shaped, approximately sinusoidal waveform at the CCFL 162. As shown in fig. 9 (e). Note that waveform 172 may possess different phase shifts with respect to the waveforms shown in fig. 9(a) -9(d) and 9(f) based on the parasitic elements of secondary winding 160 and load 162. The voltage at 172 is divided by capacitors 163 and 164. Thus, capacitors 163 and 164 serve two purposes. One for voltage detection 186 and another for wave shaping.

When the CCFL162 is turned on, the current through the CCFL162 is detected by the resistor 182. The detected signal 184 is passed to a current amplifier 230 which is connected at its output 260 to the compensation capacitor 216. Signal 260 is compared to a signal from oscillator 254 and generates an output that is sent to control logic 286 to determine the closing time of switches 112 and 132. One way to regulate the power delivered to the load is to provide a command signal 168 to an input 284 of the controller 150. The signal at 284 is converted to a low frequency pulse signal by the low frequency pulse width modulation circuit 258 and sent to the output control logic 286, which modulates the outputs 138 and 152 of the driver circuit 222 with the low frequency pulse signal to effectively control the power delivered to the CCFL 162.

During lighting, the CCFL162 is connected to the power supply circuit 100 as an infinite impedance element. Also, during this time, the CCFL162 typically requires a predetermined turn-on voltage. The power supply circuit 100 including the capacitors 163 and 164 detects the voltage of the CCFL 162. Thus, the predetermined turn-on voltage is scaled at signal 186 and communicated to input 284 of controller 150 for voltage regulation. The lamp identification circuit 250 generates a signal 252 indicating that the CCFL162 is not on. Signal 234 is set to start digital clock timing circuit 236. Similarly, the signal 252 commands the oscillator 254 to generate a higher frequency suitable for lighting the CCFL 162. During this time, the voltage at the CCFL162 is regulated to a predetermined value. About one or two seconds after signal 234 is set, digital clock timer 236 generates a signal 238. If the CCFL162 is lit before the signal 238 is set, the CCFL162 continues to operate as described in the preceding paragraph. If the CCFL162 is not lit (damaged, unconnected, or loose connected), the set signal 238 activates the protection circuit 240. The output of the protection circuit 240 generates a signal 262 to stop the operation of the driving circuit 222 so that the switches 112 and 132 are opened. Since the CCFL162 is not lit, no power is delivered to the CCFL162 during this period, the power control command signal 168 naturally does not contribute to the operation of the power supply. In other words, when the power supply circuit 100 implements the lighting function of the CCFL162, the luminance control of the power adjusted to the CCFL162 is stopped. Also, in normal operation, switch 170 resets voltage detect signal 186 so that this signal does not affect the brightness control of the CCFL. Thus, the multiplexing function reduces the number of pins, thus saving the cost of the controller 150 and the power supply circuit.

The oscillator 254 is coupled to a reference circuit ground via a capacitor 278 or to an input voltage via a resistor 280 and generates a pulse signal when the oscillator circuit 254 is coupled to circuit ground via the capacitor 278, the oscillator circuit 254 generates a current to the capacitor 278 and also sinks a current from the capacitor 278. When the oscillator circuit 254 is connected to the input voltage via the resistor 280, the oscillator circuit 254 sinks current from the voltage input and the resistor 280. The characteristics of sink-and-source or sink-only current enable the distinction between different control modes for regulating the power delivered to the CCFL 162. For the linear mode, to distinguish between the low frequency pulse width modulation modes as previously described, the power control command signal 168 commands and adjusts the power delivered to the CCFL162 such that it is not delivered through the low frequency pulse width modulation circuit 258. When the oscillator circuit 254 is connected to the voltage input via the resistor 280, the signal 168, 284 then flows through the low frequency pulse width modulation circuit 258 to generate/overwrite a reference signal 212 for transmission to the amplifier 230. The command signal 168 thus directly controls the magnitude of the current feedback signal 184, regulating the current through the CCFL 162. In this mode of operation, the signal at 282 shuts off the low frequency pulse width modulation circuit 258 and allows the signal 284 to pass directly. Thus, connecting either the resistor 280 or the capacitor 278 to the oscillator circuit 254 not only generates a pulse signal, but also determines the control mode (either in a linear control mode or in a low frequency pulse width modulation mode) for the CCFL load 162 power regulation. Such a design reduces the number of components used around the controller 150, but greatly increases the flexibility of the designer.

As described above, the first switch 112 and the second switch 132 of the power supply circuit 100 according to the present invention are controlled by the controller 150 and are alternately closed, so that current alternately flows through the CCFL162 in the first direction and the second direction, and the power supply circuit 100 converts the dc power into the ac power to supply the CCFL162 with power.

Accordingly, those skilled in the art who review this disclosure will recognize modifications and/or alternative applications of this invention without departing from the spirit and scope of the invention. Therefore, it is intended that the following claims be interpreted to embrace all such modifications and alternative applications as fall within the spirit and scope of the invention.

Other circuits, and all such modifications, which would occur to one skilled in the art, are intended to be within the spirit and scope of the present invention and limited only by the appended claims.

Claims (18)

1. A liquid crystal display system comprising:

a liquid crystal display panel;

a cold cathode fluorescent lamp for illuminating the liquid crystal display panel;

a secondary transformer winding coupled to the cold cathode fluorescent lamp to provide current to the cold cathode fluorescent lamp;

a primary transformer winding coupled to the secondary transformer winding for providing magnetic flux to the secondary transformer winding;

a first switch coupled to the primary transformer winding allowing current to flow through the primary transformer winding;

a second switch coupled to the primary transformer winding allowing current to flow in a reverse direction through the primary transformer winding;

a third switch coupled to the primary transformer winding and the first switch to provide current to the primary transformer winding when an overlap condition exists between the third switch and the first switch;

a feedback control loop coupled to the cold cathode fluorescent lamp, the feedback control loop receiving a feedback signal indicative of power delivered to the cold cathode fluorescent lamp and controlling power provided to the cold cathode fluorescent lamp if and only if the feedback signal is above a predetermined threshold,

wherein the feedback control loop maintains a predetermined minimum power for the cold cathode fluorescent lamp by maintaining a minimum overlap between the third switch and the first switch when the feedback signal is not above a predetermined threshold.

2. The liquid crystal display system of claim 1, further comprising:

an input voltage source coupled to the first switch to provide current to the first switch.

3. The liquid crystal display system of claim 2, wherein the input voltage source is a power source.

4. The liquid crystal display system of claim 2, further comprising:

a first capacitor coupled to the primary transformer winding and ground potential; and

a second capacitor coupled to the primary transformer winding and the input voltage source.

5. The liquid crystal display system of claim 1, further comprising:

a voltage detector coupled to the cold cathode fluorescent lamp to detect a voltage of the cold cathode fluorescent lamp.

6. The liquid crystal display system of claim 5, further comprising:

a voltage protection circuit coupled to the voltage detector to reduce power delivered to the cold cathode fluorescent lamp when the voltage of the cold cathode fluorescent lamp exceeds a predetermined threshold.

7. The liquid crystal display system of claim 6, further comprising:

a timer coupled to the voltage protection circuit to generate a timed period.

8. A liquid crystal display system, comprising:

a liquid crystal display panel;

a cold cathode fluorescent lamp for illuminating the liquid crystal display panel;

a secondary transformer winding coupled to the cold cathode fluorescent lamp to provide current to the cold cathode fluorescent lamp;

a primary transformer winding coupled to the secondary transformer winding for providing magnetic flux to the secondary transformer winding;

a first switch coupled to the primary transformer winding allowing current to flow through the primary transformer winding;

a second switch coupled to the primary transformer winding allowing current to flow in a reverse direction through the primary transformer winding;

a third switch coupled to the primary transformer winding and the first switch to provide current to the primary transformer winding when an overlap condition exists between the third switch and the first switch;

a feedback control loop coupled to said cold cathode fluorescent lamp, said feedback control loop receiving a feedback signal from said cold cathode fluorescent lamp, said feedback control loop maintaining a predetermined minimum power to said cold cathode fluorescent lamp by maintaining a minimum overlap between said third switch and said first switch when said feedback signal indicates an open circuit condition.

9. The liquid crystal display system of claim 8, wherein the feedback signal is representative of a voltage of the cold cathode fluorescent lamp and is representative of the open circuit condition when the voltage exceeds a predetermined threshold.

10. The liquid crystal display system of claim 8, wherein the feedback signal is representative of a voltage of the cold cathode fluorescent lamp and is representative of the open circuit condition when the voltage exceeds a predetermined threshold for a predetermined period of time.

11. The liquid crystal display system of claim 8, further comprising:

a first capacitor coupled to the primary transformer winding and ground potential; and

a second capacitor coupled to the primary transformer winding and a voltage input.

12. The liquid crystal display system of claim 8, further comprising:

an input voltage source coupled to the first switch for providing current to the first switch.

13. The system of claim 12, wherein the input voltage source is a power source.

14. The liquid crystal display system of claim 8, wherein the feedback signal is indicative of a current flowing through the cold cathode fluorescent lamp and is indicative of the open circuit condition when the current is below a predetermined threshold.

15. A method of controlling power delivered to a cold cathode fluorescent lamp in a liquid crystal display system, comprising the steps of:

providing a first pulse signal to the first transistor as a first conduction path of a primary transformer winding;

providing a second pulse signal to a second transistor as a second conduction path of the primary transformer winding;

providing a third pulse signal to a third transistor as the first conduction path of the primary transformer winding;

generating a feedback signal from a CCFL, the feedback signal being indicative of an electrical state at the CCFL, the CCFL being coupled to a secondary transformer winding;

receiving the feedback signal from the cold cathode fluorescent lamp;

adjusting power delivered to the cold cathode fluorescent lamp if and only if the feedback signal indicates that the cold cathode fluorescent lamp is lit;

when the feedback signal indicates no normal lighting, a minimum overlap between the first transistor and the third transistor is maintained to maintain a predetermined minimum amount of power to the CCFL.

16. The method of claim 15, wherein the feedback signal is representative of a voltage of the cold cathode fluorescent lamp and is representative of the cold cathode fluorescent lamp lighting when the voltage is below a predetermined threshold.

17. The method of claim 15, wherein the feedback signal is representative of a current flowing through the cold cathode fluorescent lamp and is representative of the cold cathode fluorescent lamp lighting when the current exceeds a predetermined threshold.

18. The method of claim 15, further comprising the step of:

and cutting off the power transmitted to the cold cathode fluorescent lamp when the feedback signal indicates that the lamp is not normally lighted for a preset time.