HK1077362A

HK1077362A - Improved integrated circuit burn-in methods and apparatus

Info

Publication number: HK1077362A
Application number: HK05109139.8A
Authority: HK
Inventors: David Pullen; Richard Kacprowicz
Original assignee: Intel Corporation
Priority date: 2001-07-02
Filing date: 2002-06-27
Publication date: 2006-02-10

Description

Integrated circuit burn-in method and apparatus

Technical Field

The present invention relates generally to the field of electronic devices, and more particularly to an improved method and apparatus for performing burn-in testing of electronic components, such as integrated circuits.

Background

In the field of electronic systems, there is a continuing competitive pressure among manufacturers to drive them to improve their device performance while reducing production costs. Particularly significant in the testing of integrated circuits (hereinafter "ICs"). In order to verify that each element in an IC functions properly, the IC must typically be tested before it is integrated into an electronic device.

It is well known to subject ICs to accelerated life testing to ensure that they do not prematurely fail when they have been integrated into higher level electronic packages, such as computer systems (e.g., desktops, laptops, handheld computers, servers, etc.), wireless communication devices (e.g., cellular phones, wireless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (moving picture experts group, audio layer 3) players, etc.), and the like.

The purpose of aging is to provide a screen for early failure rates for reliability defects. By operating at elevated voltage and/or temperature levels while activating as many transistors in the IC as possible, potentially early failing ICs are identified and rejected earlier before the device is provided to the user. It is desirable to keep the aging time (BITM) to a minimum in order to reduce manufacturing costs.

When packaging high performance ICs with millions of increased transistors, the transistor channel length L is continually shortened_eIn order to improve performance. In general, the channel length L_eThe shorter the leakage current I_SBThe larger. Following leakage current I_SBIncreases in (b) increase the corresponding power requirements, with a concomitant increase in heat losses. Thus, testing a large number of ICs may require the consumption of significant power resources, even if such resources become increasingly scarce and expensive.

It is desirable to go through burn-in testing while minimizing the cost, time, and complexity of such testing to fully test.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a great need in the art for improved IC burn-in methods and apparatus.

Drawings

Fig. 1 illustrates a block diagram of a system for performing component burn-in testing and binning in accordance with one embodiment of the present invention.

FIG. 2 illustrates an IC including devices to perform burn-in testing and binning in accordance with one embodiment of the present invention;

FIG. 3 is a simplified diagram of several electronic components mounted on a burn-in test fixture in accordance with one embodiment of the present invention;

FIG. 4 is a simplified diagram of a burn-in test fixture in a burn-in oven according to one embodiment of the present invention;

FIGS. 5A and 5B together illustrate a flow chart of a method for improved testing of an IC including a plurality of electronic devices according to one embodiment of the present invention;

FIGS. 6A and 6B together illustrate a flow chart of a method for improved testing of a plurality of electronic components, such as ICs, in accordance with one embodiment of the present invention;

fig. 7A and 7B together illustrate a flow diagram of a method to instruct a processor to perform a method of binning (bin) a plurality of ICs, each having a thermal detection circuit and a unique identifier, in accordance with one embodiment of the present invention.

Detailed Description

In the following detailed description of the embodiments of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, procedural, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.

The present invention provides an improved method for performing burn-in testing of electronic components, such as ICs. By comparing the temperature indication provided by the on-board thermal detection circuitry located on each IC with progressively lower temperature values, all ICs can be characterized or binned according to a desired thermal parameter, such as junction temperature. The split-bin separation (bin split) can be improved by adjusting the aging conditions to limit the yield loss due to thermal runaway. In addition, a real-time estimate of the burn-in time for each IC is obtained so that the burn-in time can be adjusted in real-time to maximize the burn-in yield. Various embodiments are illustrated and described herein, including methods of testing and binning, as well as ICs having interface circuitry to an aging system, an IC aging system, and a computer readable medium comprising computer instructions for instructing a processor to perform a method of binning a plurality of ICs each having a thermal detection circuit.

Fig. 1 illustrates a block diagram of a burn-in system 1 for performing component burn-in testing and binning in accordance with one embodiment of the present invention. The aging system 1 is only one example of an aging system in which the present invention is employed. In the present example, the burn-in system 1 is implemented with a data processing system.

The aging system 1 comprises equipment such as a burn-in recovery tank or a fixture 4 (shown in more detail in fig. 3). In one embodiment, the fixture 4 comprises a plurality of Printed Circuit Boards (PCBs), each of which in turn comprises a plurality of ICs undergoing burn-in testing; however, in other embodiments, the fixture 4 may contain other types of electronic components, examples of which are also described herein.

The aging system 1 comprises at least one processor 6. As used herein, "processor" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, an Application Specific Integrated Circuit (ASIC), an artificial intelligence circuit, a neural network, or any other type of circuit for performing a processing function, or a combination of such computing circuits.

The aging system 1 includes a system bus 2 to provide communication links between the various components of the aging system 1. The system bus 2 may be implemented as a single bus, a combination of buses, or in any other suitable manner.

The burn-in system 1 also includes an external memory 10 which, in turn, includes one or more memories or storage elements, a main memory 12, e.g., in the form of Random Access Memory (RAM), one or more hard drives 14, and/or one or more drives that process removable media 16, e.g., floppy disks, Compact Disks (CDs), tape drives, etc.

The aging system 1 also includes a display device 8 and a keyboard and/or controller 20, which may include a mouse, trackball, voice recognition device, or any other device that allows a system user to input information to the aging system 1 and receive information from the aging system 1.

In operation, the processor 6 of the aging system 1 controls aging and/or binning functions under the direction of computer instructions. The computer instructions are stored on one or more computer readable media within the aging system 1, including any or all of the storage elements within the external memory 10 and/or within a storage element such as a cache (not shown) of the processor 6.

FIG. 2 illustrates an IC 100 according to one embodiment of the invention, the IC 100 including means for performing burn-in testing and binning. The IC 100 is but one example of an IC that may be tested and/or binned using the present invention.

In the embodiment illustrated in fig. 2, IC 100 includes a processor 102, which may be any type of computational circuitry, such as, but not limited to, those listed above. The processor 102 is connected to a bi-directional internal bus 120.

However, the present invention should not be construed as limited to the aging and binning of processor ICs, as it also applies to any other type of IC, such as memory chips, chipset components, Peripheral Component Interconnect (PCI) devices, bus controllers, mass data interchange devices, amplifiers, silicon controlled rectifiers, and the like. Any type of IC having an on-board thermal detection circuit may be tested and/or binned using the present invention.

In this embodiment, the IC 100 also includes a memory circuit or memory 104 connected to the internal bus 120. The memory 104 may be of any type or size as long as it has sufficient memory space to store temperature values. In an alternative embodiment, the memory 104 may be eliminated from the IC 100 and the temperature values may be stored in a memory circuit or memory segment of the burn-in system 1 (FIG. 1).

In this embodiment, the IC 100 also includes a logic circuit 106 connected to the internal bus 120. The logic 106 may be of any type so long as it can perform a comparison function or a match determination function between the temperature indications generated by the thermal detection circuit 108 and the temperature values stored in the memory, or in the memory 104 or in the aging system 1 (e.g., the external memory 10 of FIG. 1). In an alternative embodiment, the logic 106 may be eliminated from the IC 100 and the match determination function performed by the processor 6 (FIG. 1) of the burn-in system 1.

The IC 100 additionally includes a thermal detection circuit 108 connected to the internal bus 120. The thermal detection circuit 108 may be implemented by any circuit capable of producing a temperature parameter or indication. In one embodiment, the thermal detection circuit 108 provides an indication or representation of temperature proportional to the substrate temperature or junction temperature on the IC 100. For example, the thermal detection circuit 108 may be implemented by a temperature detection diode, such as a forward biased diode.

The IC 100 also includes suitable interface circuitry 110 between the internal bus 120 and the test fixture bus 112 for transferring data, instructions, and/or control signals between the IC 100 and the burn-in system 1 (fig. 1).

Fig. 3 is a simplified diagram of several electronic components 100 mounted on a burn-in test fixture 150 in accordance with one embodiment of the present invention. The test board or test fixture 150 includes a plurality of sockets or connectors (not shown) to which one or more electronic components 100 are coupled. In one embodiment, electronic component 100 is an IC; however, in other embodiments, the electronic component may be virtually any other type of electronic or electrical device that generates heat during operation. Examples include cellular telephones, pagers, computers of all types, electric tools, equipment, entertainment equipment, aerospace and vehicular components, and the like.

The test fixture 150 includes a bus 112 (fig. 2) that electrically connects the electronic component 100 to the aging system 1 (fig. 1).

Fig. 4 is a simplified diagram of the test fixture 150 in the burn-in oven 200 according to one embodiment of the present invention. The weathering test fixture 150 is located in an environmentally controlled chamber containing a temperature changing mechanism such as a heater and/or cooler. In one embodiment, the chamber is heated; however, in another embodiment, the chamber may be cooled. The burn-in system 1, operating under the control of an operator or computer instructions, applies thermal stress to the electronic components 100 on the test fixture 150 by, for example, increasing the temperature in the burn-in oven 200.

In embodiments where the electronic components 100 being aged are ICs, they are typically subjected to higher operating voltages in addition to being thermally stressed. The burn-in voltage varies depending on the type of IC and the process used to manufacture it. For example, an aging voltage of 2.1 volts is used in one current processor IC product. In addition to raising the operating voltage, most, if not all, of the circuit nodes within the IC are switched during the burn-in period.

Thus, in order to run the ICs on the test fixture 150 at elevated operating voltages and switch as many circuit nodes on the ICs as possible when the burn-in test fixture 150 is located in the burn-in oven 200, they are functionally connected to the burn-in system 1 (fig. 1) through a network of connectors and wires (not shown). The burn-in oven 200 may also include power and clock circuits (not shown) to provide power and clock signals to the IC undergoing burn-in.

Fig. 5A and 5B together illustrate a flow diagram of an improved method 500 of testing an IC, which includes a plurality of circuits or electronic devices, in accordance with one embodiment of the present invention. The first of the electronic devices provides an indication of temperature, and the device may be any suitable thermal detection device, such as thermal detection circuit 108 (fig. 2). An optional second one of the electronic devices stores the temperature value and the device may be implemented by any suitable memory storage device, such as memory circuit 104 (fig. 2). If the memory device of the optional second memory is not on top of the IC, the storing of the memory may be performed by aging a suitable memory means in the system 1 (FIG. 1).

In 502, a temperature value of the IC is stored in the second electronic device or in an aging system connected to the IC. A temperature above the maximum desired IC junction temperature is selected. For example, in one aging embodiment, a temperature value of approximately 110 degrees Celsius is initially stored.

At 504, thermal stress is applied to the IC by increasing or decreasing an ambient temperature of the IC. For aging the IC, the temperature is increased, for example to 60 degrees celsius.

At 506, a first electronic device (e.g., a temperature sensing diode) provides a temperature indication.

At 508, a determination is made as to whether the temperature indication matches a stored temperature value. "match" means having the same value or substantially the same value. If so, the method proceeds to 510; otherwise, the method proceeds to 512.

At 510, the temperature value is recorded and the process ends for this IC.

At 512, the temperature value is incremented to the new temperature value by decreasing the temperature value by one or two degrees (e.g., for a burn-in test), or by increasing the temperature value by one or two degrees (e.g., for a cooling test).

At 514, a determination is made as to whether the temperature indication matches the newly stored temperature value. If so, the method proceeds to 516; otherwise, the method proceeds to 512.

At 516, a temperature value is recorded.

At 518, processing for this IC ends.

Fig. 6A and 6B together illustrate a flow chart of an improved method 600 of testing a plurality of electronic components, such as ICs, in accordance with one embodiment of the present invention. The electronic component may be any type of component other than an IC, and examples of these types of components may be provided elsewhere in this specification. Each electronic component includes a thermal detection circuit. Each electronic component also includes an optional memory circuit. If the electronic component does not have optional storage circuitry, the storage function of the memory may be performed by a suitable storage device in the burn-in system 1 (FIG. 1). Each electronic component is also identified by a unique Identification (ID), which may be of any type but is typically a number.

At 602, a temperature value is stored for each component in an optional storage circuit of the component or in an aging system connected to the component.

At 604, thermal stress is applied to the component, such as by raising the ambient temperature.

At 606, each thermal detection unit provides a temperature indication for its corresponding component.

At 608, a determination is made as to whether the temperature indication for each of the plurality of electronic components matches the temperature value. For those components for which the match is true, the method proceeds to 610; otherwise, for those components for which the match is not true, the method proceeds to 612.

In 610, a temperature value and a unique ID are recorded for each electronic component in 608 whose temperature indication matches the temperature value. From 610, the method proceeds to 618.

At 612, the temperature value is changed to a new temperature value (e.g., a lower temperature value for aging operations).

At 614, a determination is made as to whether the temperature of each of the plurality of electronic components, which is still being increased at this time, indicates a match with the temperature value. If so, the method proceeds to 616 for those components for which the match is true; otherwise, for those components whose match is false, the method proceeds to 612.

At 616, the temperature value and the unique ID for each electronic component whose temperature indication matches the temperature value are recorded at 616. From 616, the method proceeds to 618.

At 618, a determination is made as to whether all of the electronic components already have temperature values recorded for them. If so, the method proceeds to 620 and ends; otherwise, the method returns to 612.

In the present invention, the stimulus pattern for the component being tested during burn-in is the same for all components under test. It is not necessary to provide each element undergoing burn-in testing with a unique test stimulus pattern.

Fig. 7A and 7B together illustrate a flow diagram of a method 700 of instructing a processor to perform a method of binning a plurality of ICs, each having a thermal detection circuit and a unique Identifier (ID), in accordance with one embodiment of the present invention. The processor is a component in a system that includes a temperature change mechanism to apply thermal stress to the IC. In the aging system, the temperature changing mechanism raises the ambient temperature; in the cooling system, the temperature change mechanism lowers the ambient temperature. The system also includes a comparison mechanism that may be implemented in any suitable manner, for example, using "compare" program instructions or hardwired comparison circuitry.

At 702, a temperature value is stored for an IC being tested. For IC burn-in operations, a temperature value is chosen that is higher than the highest expected junction temperature of any IC. For example, in one aging embodiment, a temperature value of approximately 110 degrees Celsius is initially stored.

At 704, a temperature indication is obtained from the thermal detection circuit of each IC. Each temperature indication is suitably linked to the IC that generated it. This is performed, for example, by taking the ID of the IC and storing the ID/temperature indication pair for each IC undergoing testing at this point.

At 706, for each IC, the stored temperature value is compared to an indication of the temperature of the IC itself.

At 708, for each IC, a determination is made as to whether its temperature indication substantially matches a stored temperature value. If so, the method branches to 710; otherwise, the method proceeds to 712.

At 710, for each IC for which the match of 708 is true, a temperature value and a unique ID are recorded. Also at this point, an estimate of the aging time is calculated, if necessary, using the temperature values recorded for the IC for which the match of 708 is true. This estimation may be further refined when additional ICs are binned at 712 and 714 and then operations 712 and 714 are repeated. From 710, the method proceeds to 718.

At 712, the temperature value is changed to a new temperature value (e.g., a lower temperature value for burn-in operation).

At 714, a determination is made for each IC as to whether its temperature indication substantially matches the newly stored temperature value. If so, the method passes to 716; otherwise, the method proceeds to 712.

At 716, for each IC for which the match of 714 is true, a temperature value and a unique ID are recorded.

In 718 it is checked whether all ICs already have temperature values and IDs recorded for them. If so, the method proceeds to 720; otherwise, the method proceeds to 712.

At 720, the method ends.

The operations described above with respect to the methods illustrated in fig. 5, 6A, 6B, 7A, and 7B may be performed in a different order than those described herein.

Determining junction temperature of each componentT_j

The invention can determine the junction temperature T for each IC undergoing burn-in testing_j. Using the temperature indications generated by the thermal detection devices on the board of each IC, the burn-in system initially stores a highest expected junction temperature T above the set of ICs being tested_jThe temperature value of (2). By successively comparing the temperature indications output by the thermal detection devices of each IC and reducing the temperature value by one or two degrees in a subsequent step, for each IC of the set of ICs, corresponding to the junction temperature T_jThe final match is achieved and recorded.

Junction temperature T of IC_jCan be expressed by equation (1) as follows:

equation (1) T_j＝T_a+((j_a×P_d)

Wherein T is_jJunction temperature (c);

T_aambient temperature (c);

(j_ajunction-to-ambient thermal resistance (c/watt), which may be in the range of 0.4-2.0 c/watt for some current processor products; and

P_dat T_jThe power consumption (watts) may be in the range of 10-60 watts for some current processor products.

By obtaining the junction temperature profiles of all ICs undergoing burn-in testing, the present invention provides a direct assessment of the stability of the burn-in test. The present invention also allows the IC manufacturer to substantially remove any thermal margin from the burn-in test by allowing burn-in testing of components having shorter channel lengths, and/or components operating at higher powers or frequencies. The present invention also enhances the overall binning separation as will be discussed immediately below.

Improved separation of separated boxes

The present invention provides for relatively high binning separation of electronic components being subjected to thermal stress testing. "binning" is the process of evaluating a group of electronic components, such as ICs, to classify them according to some characteristic or to assign them to a plurality of different groups. The characteristic may be, for example, a performance-related characteristic or an operation-related characteristic, such as the standby current I_SB. High performance processors are typically at a higher I than low performance processors of the same design running at the same clock speed_SBThe value (and corresponding higher junction temperature T)_j) And (4) working.

Generally, the junction temperature T_jThe higher the aging time BITM, the shorter. However, if the aging conditions are set too high, the risk of thermal runaway increases. By obtaining T for each component_jAging conditions can be set to maximize binning separation and limit yield losses due to thermal runaway.

In the present invention, the junction temperature profile between a batch of lowest performing processors and highest performing processors undergoing burn-in testing can be determined in relatively small increments, such as from 110 degrees Celsius down to 60 degrees Celsius one degree at a time. By obtaining T for each component_jThe thermal margin can be better understood and the channel length L of the transistor can be redetermined_B(e.g., shortened) to achieve a higher frequency of binning.

It will now be discussed how the present invention provides a relatively high split.

Each IC having a T providing an IC_jThe on-chip thermal detection circuit of (1). In an aging oven, ambient temperature T_aMaintained constant, for example 60 ℃. During aging, the aging voltage V_BIMaintained constant, e.g. V for a current processor product with a normal operating voltage of 1.7V_BI2.1 volts.

For all ICs, an initial temperature value (e.g., 110 ℃) is programmed, and all ICs are checked to see if any one IC has a junction temperature indication T of 110 ℃_j. Identify its T_jAny IC at 110 ℃. For each of these ICs, the ID and the value of 110 ℃ are stored.

Then, the temperature value was reduced to 109 ℃, and all ICs were checked again. Identify its T_jAny IC at 109 ℃.

This continues to decrease until a relatively low temperature, e.g., 60 ℃, and/or until T has been recorded for all ICs (except those that failed during the burn-in test)_jThe value is obtained. Thus continuously monitoring T_jAllows the aging conditions to be adjusted so as to minimize the loss of production due to thermal runaway, thereby improving the binning separation.

According to T of IC_jThe value is binned the ICs. Having the highest T_jThose ICs of value generally have the best performance.

Determination of aging time (BITM)

Burn-in tests, which screen out early failure rates by testing at elevated voltages and temperatures, are performed for a specified length of time called the burn-in time BITM. The BITM must last long enough to provide satisfactory statistical and experimental assurance that most, if not all, electronic components that are prone to failure under test are identified. However, there is a practical upper limit to the duration of the BITM, driven in part by large manufacturing costs (including labor and energy costs), product yield requirements, and possible degradation of product reliability, where the stresses applied during aging can adversely affect reliability once the components are installed in the consumer product.

By accurately determining the BITM for each component in the test fixture undergoing burn-in testing, the present invention can achieve significant savings in the burn-in testing process, as will be explained below.

BITM can be calculated by equation (2):

equation (2) BITM ═ A_V*A_T

Wherein A is_VIs the voltage acceleration factor. For an existing product, A_VApproximately 30.

A_TIs a temperature acceleration factor that can vary within an IC of the same design. A. the_TIt can be deduced from the well-known Arrhenius relationship represented by equation (3):

equation (3) A_T＝exp[(Ea/k)(1/T1-1/T2)]

Where Ea is the activation energy (eV), typically in the range of.3-2.0 eV;

k is Bolzmann (Bolzmann) constant, k is 8.617 × 10^-5eV/K；

T1 is the intended use temperature (° c) of the IC; and

t2 is the aging temperature (. degree.C.).

A_TIs the power P consumed by the IC_dAnd it may vary within an IC of the same design. P_dIs the standby current I of the IC_SBAnd it may vary within an IC of the same design. I is_SBIs the transistor channel length L_EAnd other process parameters, and it may vary within an IC of the same design.

With the binning operation performed previously, the A of each IC can be obtained_TThus, using equation (2) above, the BITM for each individual IC undergoing burn-in can be easily calculated in real time.

As a result, the BITM changes dynamically. For example, for any IC undergoing aging, the BITM may be shortened or lengthened to correspond to the calculated maximum value of BITM.

Alternatively, the BITM may remain relatively constant, but if all of its ICs have completed aging, some of the test fixtures can be removed from the aging oven earlier, and others may remain in the aging oven for longer periods of time if some of its ICs require longer than normal aging times.

Thus, the burn-in testing process can significantly save labor, energy, and manufacturing time. Significant improvements in quality can also be obtained in an aging process that uses only static BITM.

Conclusion

The present invention provides improved methods for performing burn-in testing and/or binning of electronic components, such as ICs. By comparing the temperature indication provided by the on-board thermal detection circuit of each IC to progressively lower thermal set point values, all ICs can be characterized or binned according to a desired thermal parameter, such as junction temperature. By using the burn-in test concept of the present invention, it is not necessary to provide a unique test stimulus pattern for each component undergoing testing. The excitation pattern is the same for all components undergoing burn-in testing.

Because the aging conditions can be adjustedTo minimize thermal runaway losses, a relatively high split is therefore achieved. In addition, for example by increasing the ambient temperature T_aThen the base T can be removed_jTo increase the BITM. Moreover, a real-time estimate of the burn-in time for each IC is obtained, so that the burn-in time can be adjusted to optimize the burn-in yield and reduce manufacturing costs.

In addition to the above methods, an IC having an interface circuit to connect the burn-in system, an IC burn-in system, and a computer readable medium comprising computer instructions for instructing a processor to execute a method of binning a plurality of ICs have been described.

As shown herein, the present invention is embodied in a number of different embodiments. Other embodiments will be apparent to those of ordinary skill in the art. The elements, structures, functions, and sequence of operations may be varied to suit particular product and test needs.

For example, instead of recording the temperature value at which the match occurred, a temperature indication may be recorded as it is either the same as or substantially the same as the temperature value. In addition, the components undergoing burn-in testing may be subjected to other environmental acceleration tests, such as humidity, vibration, thermal cycling, and the like.

Furthermore, instead of storing temperature values (e.g., an initial high value), the temperature indication generated by the thermal detection unit on each IC is compared to the temperature values, any matches are recorded, and then the temperature values are successively decreased until the T for all ICs have been recorded_jSlightly different processes may be employed in which a thermal set point value is loaded into each IC. The burn-in system tests each IC to determine if a set point value has been exceeded while the IC maintains a constant elevated temperature. If the set point value is exceeded, the component is characterized by the set point; if not, it decreases the set point and checks again. This process continues until all ICs have been characterized as a particular set point. As a result of this method, the junction temperature of each IC is obtained.

The various elements shown in the figures are for illustration only and are not drawn to scale. Some parts of it are enlarged and others are minimized. The drawings are intended to illustrate various embodiments of the invention so that those skilled in the art can understand and appropriately practice the invention.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

Claims

1. An Integrated Circuit (IC), comprising:

interface the IC to an interface circuit of an aging system, the interface circuit receiving at least one temperature value from the aging system and sending at least one temperature indication to the aging system;

a storage circuit connected to the interface circuit, storing the at least one temperature value; and

a thermal detection circuit coupled to the interface circuit provides the at least one temperature indication.

2. The IC of claim 1, wherein the at least one temperature value is a set point.

3. The IC of claim 1, wherein the at least one temperature indication is proportional to a junction temperature of the IC.

4. An Integrated Circuit (IC) burn-in system, comprising:

a computer system including a processor operating under control of a computer program; and

at least one IC, the IC comprising:

an interface circuit to interface the IC to the computer system; and

a thermal detection circuit, coupled to the interface circuit, provides an indication of temperature proportional to the junction temperature of the IC.

5. The IC burn-in system of claim 4, wherein the computer system compares the temperature indication to a temperature value determined by the computer program;

wherein if the temperature indication substantially matches the temperature value, the computer system binning the IC at the temperature value; and

wherein if the temperature indication is less than the temperature value, the computer system decreases the temperature value and compares the temperature indication to the decreased temperature value.

6. The IC burn-in system of claim 4, wherein the IC further comprises:

a logic circuit connected to the interface circuit; and

wherein the logic circuit is responsive to the temperature indication generated by the thermal detection circuit;

wherein the logic circuit is further responsive to a temperature value generated by the computer system as determined by the computer program;

wherein the logic circuit compares the temperature indication to a temperature value;

wherein if the temperature indication substantially matches the temperature value, the logic circuit generates a first indication to the computer system and the computer system bins the IC at the temperature value; and

wherein if the temperature indication is less than the temperature value, the logic circuit generates a second indication to the computer system and the computer system decreases the temperature value and compares the temperature indication to the decreased temperature value.

7. An burn-in system for an IC including a thermal detection circuit, the burn-in system comprising:

a fixture electrically connected to the IC;

a temperature change mechanism that changes an ambient temperature of the IC; and

a data processing system coupled to the fixture, the data processing system executing a computer program that operates the burn-in system to characterize the IC and includes the operations of:

storing a temperature value of the IC;

controlling the temperature change mechanism to apply thermal stress to the IC;

determining whether the temperature indication from the thermal detection circuit substantially matches the temperature value;

if so, recording the temperature value; and

if not, the temperature value is changed to a new temperature value and it is determined whether the temperature indication matches the new temperature value.

8. The burn-in system of claim 7, wherein the computer program to operate the burn-in system further comprises the operations of:

determining whether the temperature indication matches the new temperature value;

if so, recording a new temperature value;

otherwise, repeatedly changing the temperature value and comparing the temperature indication with the changed temperature value until the temperature indication matches the changed temperature value; and

the changed temperature value is recorded.

9. The burn-in system of claim 7, wherein the temperature value is stored in a memory circuit in the IC.

10. The burn-in system of claim 7, wherein the temperature value is stored in a storage element in the data processing system.

11. A method of testing an Integrated Circuit (IC) comprising a plurality of electronic devices, one of the electronic devices providing an indication of temperature, the method comprising:

storing a temperature value of the IC;

applying thermal stress to the IC;

the one electronic device providing an indication of temperature;

determining whether the temperature indication matches the temperature value;

if so, recording the temperature value; and

12. The method of claim 11, further comprising:

if the temperature indication matches the new temperature value, recording the temperature value;

the changed temperature value is recorded.

13. The method of claim 11, wherein the storing is performed by another electronic device of the plurality of electronic devices in the IC.

14. The method of claim 11, wherein the storing is performed by an aging system connected to the IC and comprising a digital computer storing the program.

15. The method of claim 11, wherein the plurality of electronic devices comprise logic circuitry, and wherein the determining is performed by the logic circuitry.

16. The method of claim 11 wherein the determining is performed by an aging system connected to the IC and comprising a stored program digital computer.

17. A method of testing a plurality of Integrated Circuits (ICs), each integrated circuit including a thermal detection circuit, the method comprising:

storing a temperature value for each IC;

applying thermal stress to the IC;

each thermal detection circuit providing a temperature indication for its respective IC;

determining whether the temperature indication matches the temperature value;

if so, recording the temperature value of the corresponding IC; and

18. The method of claim 17, further comprising:

if the temperature indication matches the new temperature value, recording the temperature value of the corresponding IC;

the changed temperature values are recorded for the respective ICs.

19. The method of claim 17, wherein each IC includes a memory circuit and wherein storing is performed by the memory circuit.

20. The method of claim 17, wherein the storing is performed by an aging system connected to the IC and comprising a digital computer storing the program.

21. The method of claim 17, wherein each IC includes logic circuitry, and wherein the determining is performed by the logic circuitry.

22. The method of claim 17 wherein the determining is performed by an aging system connected to the IC and comprising a stored program digital computer.

23. A method of testing a plurality of electronic components, each electronic component including a thermal detection circuit, the method comprising:

storing the temperature value of each electronic component;

applying a thermal stress to the electronic component;

each thermal detection circuit provides a temperature indication for its corresponding electronic component;

determining whether the temperature indication matches the temperature value;

if the temperature values are matched with the temperature values, the temperature values of the corresponding electronic components are recorded; and

24. The method of claim 23, further comprising:

if the temperature indication matches the new temperature value, recording the temperature value for the corresponding electronic component;

the changed temperature values are recorded for the respective electronic components.

25. A method according to claim 23, wherein each electronic component comprises a memory circuit, the storing being performed by the memory circuit.

26. The method of claim 23, wherein the storing is performed by an aging system connected to the electronics and comprising a digital computer storing the program.

27. The method of claim 23, wherein each electronic component comprises a logic circuit, and wherein the determining is performed by the logic circuit.

28. The method of claim 23, wherein the determining is performed by an aging system coupled to the electronics and comprising a stored program digital computer.

29. The method of claim 23, wherein the electronic component is an integrated circuit.

30. A computer readable medium containing computer instructions for instructing a processor to perform a method of binning a plurality of ICs, each IC having a thermal detection circuit, the processor forming an element in a system comprising a temperature change mechanism and a comparison mechanism for applying thermal stress to the ICs, wherein the instructions comprise:

storing a temperature value for each IC;

obtaining a temperature indication from the thermal detection circuit of each IC;

for each IC that has not been binned, comparing the stored temperature value to the temperature indication; and

if the temperature indication substantially matches the stored temperature value, recording the temperature value;

otherwise, the temperature value is changed to a new temperature value and the new temperature value is compared to the temperature indication.

31. The computer readable medium of claim 30, wherein the instructions further comprise:

if the temperature indication substantially matches the new temperature value, recording the new temperature value;

otherwise, the temperature value is repeatedly changed and the temperature indication is compared with the changed temperature value until the temperature indication substantially matches the changed temperature value, and the changed temperature value is recorded.

32. The computer readable medium of claim 30, wherein the instructions further comprise:

an estimate of the aging time of each IC is determined using the specific temperature values recorded for each IC.