HK1076665B - Method and apapratus for generating a pulse width modulated signal - Google Patents

Description

Method and apparatus for generating pulse width modulated signals

Technical Field

The present invention relates generally to pulse width modulation and, more particularly, to converting one of a pulse density data stream or a pulse encoded data stream into a pulse width modulated signal.

Background

Pulse Width Modulation (PWM) is a suitable method of generating a power signal with high efficiency. In particular, many high efficiency digital audio switching power amplifiers are based on PWM signaling. The digital audio input to these amplifiers is typically Pulse Code Modulated (PCM). Direct conversion from PCM to PWM to produce a uniformly sampled PWM (upwm) signal is a nonlinear operation that results in a large amount of harmonic distortion. In contrast, naturally sampled pwm (npwm) contains no harmonic distortion. Naturally sampled PWM signals are easy to generate by comparing the analog input signal with a sawtooth or triangular ramp signal in the analog domain. The pulse edge of NPWM is determined by the natural intersection between the input analog signal and the harmonic signal. However, computing the natural intersection of the NPWM in the digital domain from the PCM input data is computationally expensive.

The Super Audio Compact Disc (SACD) is a new digital audio data format. The audio has been digitized and stored in a Pulse Density Modulation (PDM) format. It consists of an oversampled (64 x Fs, where Fs is the starting sample rate) one-bit PDM data stream. Ideally, the SACD bitstream (or any PDM bitstream) is converted to a Pulse Width Modulated (PWM) signal that can be used to drive a high efficiency switching digital audio amplifier. SACD PDM bit stream, which can be used directly as a switching signal; however, such a solution cannot be immediately used to implement any required signal processing (i.e. volume control, equalization, etc.).

Pulse density modulated signals (e.g., SACD) are typically noise shaped to reject quantized noise out of the frequency band to be used. This results in a spectrum that contains a significant amount of out-of-band noise.

A very high-end switched digital audio amplifier for SACD input has been introduced commercially. However, it cannot directly amplify the SACD PDM signal in order to accommodate volume control. Instead, it must process the PDM input signal as an analog signal that can be attenuated as desired for volume control. This signal is then fed to a seven-order one-bit sigma delta ADC modulator (seven-order one-bit ADC modulator), which generates a new PDM signal for amplification by the switching amplifier. A serious drawback of this system is that the signal cannot be kept in the digital domain. The digital input signal is converted to an analog signal, signal processed in the analog domain, and then converted to a digital (PDM) signal to drive the switching amplifier. All the advantages of digital signals are lost throughout. Furthermore, there are some disadvantages to using a PDM signal to drive a switching amplifier compared to using a PWM signal. For example, PWM has a lower average switching frequency compared to PDM, resulting in higher efficiency. Also, the non-return-to-zero (NRZ) nature of the PDM signal can cause distortion compared to a non-return-to-zero PWM signal. One might consider processing a high-speed one-bit PDM signal in the digital domain, followed by the use of a digital sigma-delta modulator. However, the cost of such high bit rate processing is extremely high.

Many common methods of SACD demodulation and amplification include: decimating the high sample rate PDM into a low sample rate PCM; carrying out signal processing; performing digital-to-analog conversion; and finally amplifying in an analog domain. A significant disadvantage of this approach is that all the advantages of efficient digital switching amplification are lost.

It is therefore desirable to have a computationally efficient method of converting both the encoded PDM and PCM input signals into PWM switching waveforms entirely in the digital domain to facilitate driving a switching digital power amplifier. Such an approach is tolerant of out-of-band noise as is commonly found in PDM signals.

Drawings

The present invention will now be described, by way of example and not limitation, in the figures of the accompanying drawings in which like references indicate similar elements.

FIG. 1 illustrates an embodiment of a digital-to-analog conversion system in accordance with the present invention.

Fig. 2 illustrates another embodiment of a digital-to-analog conversion system in accordance with the present invention.

Fig. 3 shows an embodiment of a PCM to PWM converter according to the present invention.

Fig. 4 illustrates several signals used in a natural sampling circuit in accordance with the present invention.

FIG. 5 illustrates one embodiment of a timing diagram for a two-sided PWM signal.

Fig. 6 illustrates, in flow diagram form, the functions performed by the natural sampling circuit, in accordance with one embodiment of the present invention.

FIG. 7 is a block diagram illustrating a general purpose computer for implementing an embodiment of the present invention.

It will be apparent to those skilled in the art that the elements of the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.

Detailed Description

Fig. 1 illustrates one embodiment of a digital-to-analog conversion system 10. In one embodiment of the present invention, the digital-to-analog conversion system 10 receives a Pulse Density Modulation (PDM) signal 24 as an input to the PDM-to-PWM converter 20. The PDM to PWM converter 20 then provides a Pulse Width Modulated (PWM) signal 30 to the low pass filter 18. Low pass filter 18 provides an analog signal as an output to load 22 (not shown). In one embodiment, the load 22 may be an audio speaker. Other embodiments of the invention may use other types of loads. In one embodiment of the present invention, the PDM to PWM converter 20 includes: decimation filter 12, digital signal conditioning circuit 14, and PCM to PWM converter 16. In one embodiment, decimation filter 12 receives PDM signal 24 as an input and provides Pulse Code Modulated (PCM) signal 26 as an output. It should be noted that the PDM signal 24 has a one bit resolution at high sample rates. Decimation filter 12 reduces the sampling rate and increases the bit resolution in the resulting Pulse Code Modulated (PCM) signal 26. Digital signal conditioning circuit 14 receives PCM signal 26 as an input and provides a conditioned PCM signal 28 as an output. PCM to PWM converter 16 receives PCM signal 28 as an input and provides PWM signal 30 as an output to low pass filter 18. It should be noted that in other embodiments of the present invention, an amplifier may optionally be included as part of the digital-to-analog conversion system 10. For example, an amplifier (not shown) may optionally be included between the converter 16 and the low pass filter 18. Alternatively, an optional amplifier (not shown) may be included between low pass filter 18 and load 22. It should be noted that alternate embodiments of the present invention may combine the functions of decimation filter 12 and digital signal conditioning circuit 14 in any manner. Importantly, the function of circuits 12 and 14 is to receive the PDM signal 24 as an input and provide a conditioned PCM signal as an output. The digital signal conditioning performed by the digital signal conditioning circuit 14 may vary widely. For example, some embodiments of the invention may use digital signal conditioning circuitry 14 to provide volume control, graphic equalization, and other desired digital effects or processing. Alternatively, the conditioning of the digital signal may be performed prior to the decimation filter function.

Fig. 2 illustrates one embodiment of a digital-to-analog conversion system 110. In one embodiment of the present invention, digital to analog conversion system 110 receives a Pulse Code Modulation (PCM) signal 124 as an input to PCM to PWM converter 120. PCM to PWM converter 120 then provides a Pulse Width Modulation (PWM) signal 130 to low pass filter 118. The low pass filter 118 provides an analog signal as an output to a load 122 (not shown). In one embodiment, the load 122 may be an audio speaker. Other embodiments of the invention may use other types of loads. In one embodiment of the present invention, the PCM to PWM converter 120 includes: an oversampling circuit 112, a digital signal conditioning circuit 114, and a PCM to PWM converter 116. In one embodiment, the oversampling circuit 112 receives the PCM signal 124 as an input and provides an oversampled Pulse Code Modulation (PCM) signal 126 as an output. Digital signal conditioning circuit 114 receives as input an oversampled Pulse Code Modulated (PCM) signal 126 and provides as output a conditioned PCM signal 128. PCM to PWM converter 116 receives as input conditioned PCM signal 128 and provides as output PWM signal 130 to low pass filter 118. It should be noted that in further embodiments of the present invention, an amplifier may optionally be included as part of the digital-to-analog conversion system 110. For example, an amplifier (not shown) may optionally be included between the converter 116 and the low pass filter 118. Alternatively, an optional amplifier (not shown) may be included between the low pass filter 118 and the load 122. It should be noted that alternate embodiments of the present invention may combine the functionality of the oversampling circuit 112 and the digital signal conditioning circuit 114 in any manner. Importantly, the function of circuits 112 and 114 is to receive PCM signal 124 as an input and provide a conditioned PCM signal as an output. The digital signal conditioning performed by the digital signal conditioning circuit 114 may vary widely. For example, some embodiments of the invention may use digital signal conditioning circuitry 114 to provide volume control, graphic equalization, and other desired digital effects or processing. Alternatively, the conditioning of the digital signal may be performed prior to the oversampling circuit function.

Fig. 3 illustrates an embodiment of the PCM to PWM converter 16 shown in fig. 1, and the PCM to PWM converter 116 shown in fig. 2. It should be noted that although both PCM to PWM converters 16, 116 are shown in fig. 3, the interleaved embodiment of digital to analog conversion system 10 shown in fig. 1 and digital to analog conversion system 110 shown in fig. 2 may use different embodiments of PCM to PWM converters 16, 116. It should be noted that for fig. 3, optional lines and connections are drawn with dashed lines. In one embodiment of PCM to PWM converter 16, 116, natural sampling circuit 40 and PWM quantizer and noise shaper 42 are included. In one embodiment, the natural sampling circuit 40 receives as input the conditioned PCM signal (U)28, 128 and provides as output a natural sample point output (X) 57. PWM quantizer and noise shaper 42 receives as input natural sample point output (X)57 and provides as output PWM signals 30, 130. In one embodiment of the present invention, the natural sampling circuit 40 includes: a duty cycle predictor 44, a signal value interpolator 46, and a duty cycle correction circuit 48. In one embodiment of the invention, the duty cycle predictor 44 receives as input the conditioned PCM signal (U)28, 128 and provides as output a point in time guess (G) 50. The signal value interpolator 46 receives as input the time point estimate (G)50 and provides as output an interpolated signal value (V) 52. The duty cycle correction circuit 48 receives as input the interpolated signal value (V)52 and provides as output a natural sample point output (X) 57. In one embodiment of the invention, the natural sample point output (X)57 is fed back to the duty cycle predictor 44 as a previous natural sample point output (X) 58. Also, in some embodiments of the invention, the natural sample point output (X)57 is fed back as an updated time point estimate (G)56 to the input of the signal value interpolator 46. In some embodiments of the invention, the interpolated signal value (V)52 is also fed back as an updated point in time guess (G) 59. It should be noted that feedback paths 56, 58, and 59 are optional and may or may not be included in various embodiments of the present invention. It should also be noted that the duty cycle predictor 44 is optional. Some embodiments of the invention may provide the conditioned PCM signal (U)28, 128 directly to the signal value interpolator 46. It should be noted that the time point guess (G)50 signal is also provided as an input to the duty cycle correction circuit 48. It should be noted that the adjusted PCM signal (U)28, 128 is also provided as an input to the signal value interpolator 46 and the duty cycle correction circuit 48. It should be noted that if the duty cycle predictor 44 is not used, the point in time guess (G) signal 50 is simply the same conditioned PCM signal (U)28, 128 signal. The input to the PWM quantizer and noise shaper 42 is the natural sample point output (X)57 of the high resolution PWM signal. Thus, PWM quantizer and noise shaper 42 quantizes the high resolution PWM signal, producing a lower resolution quantized PWM signal 30, 130. In one embodiment, the noise shaping function of circuit 42 shapes the quantization noise outside the passband.

Still referring to fig. 3, in one embodiment of the present invention, the addition of the duty cycle correction circuit 48 can greatly increase the accuracy of the natural sample point output (X) signal 57 produced by the converter 16, 116. In fact, in some applications, the addition of the duty cycle correction circuit 48 to the converter 16, 116 may eliminate the duty cycle predictor 44 altogether. However, in other embodiments of the present invention, a combination of the duty cycle correction circuit 48 and the duty cycle predictor 44 may be used. The addition of the duty cycle correction circuit 48 reduces the number of calculations and memory required by the converter 16, 116. The addition of the duty cycle correction circuit 48 also greatly improves the distortion performance of the natural sample point output (X) signal 57 and thus also of the PWM signals 30, 130. In addition, the duty cycle correction circuit 48 produces a natural sample point output (X) signal 57 that is less sensitive to out-of-band noise. This is particularly important because the PDM signal 24 (see fig. 1) typically contains a significant amount of out-of-band noise.

Fig. 4 depicts a time domain representation of some of the signals used and/or generated in natural sampling circuit 40 (see fig. 3) in which a single-sided PWM signal is generated by using a sawtooth shaped ramp signal 81. Other embodiments of the present invention use ramp signals other than sawtooth shapes. For example, fig. 5 illustrates an embodiment of a timing diagram for a two-sided PWM signal using a symmetrical triangular ramp signal 90. The left half of the ramp signal 90 is shown as the ramp up and the right half is shown as the ramp down. The respective samples of the conditioned PCM signal (U)28, 128 are selected to be aligned with the respective centers of the ramp signal 81 or the ramp signal 90. Theoretical analog signal 81 and theoretical analog signal 91 represent ideal analog signals corresponding to conditioned PCM signals (U)28, 128. An example of the two-sided PWM signals 30, 130 is shown in fig. 5. The selective conditioning PCM signal (U)28, 128 has an even index on the left half and an odd index aligned with the PCM signal (U)30, 130 on the right half.

Referring now to fig. 3 and 4, using the conditioned pcm (u) signal 28, 128, the time-point guess (G) signal 50 is used to calculate the value of the interpolated signal value (V) 52. Unless all errors are eliminated, the interpolated signal value (V)52 is not equal to the time point guess (G) 50. The difference (V-G) is multiplied by the estimated signal slope (S) of the theoretical analog signal 80, and a correction (C)82 is calculated. The natural sample point output (X) signal 57 is a corrected signal. It should be noted that in one embodiment of the present invention, the selection ramp signal 81 rises linearly from 0 to 1.

Fig. 6 illustrates, in flow diagram form, the functions performed by one embodiment of natural sampling circuitry 40 of fig. 3. In one embodiment, the process 199 begins at the start ellipse 200 and then proceeds to step 203, where step 203 gives the guess time (G). The guessed time (G) given in step 203 is based on the adjusted PCM samples and/or the previously calculated natural sample point output (X). Flow 199 then proceeds to step 204 where the interpolated signal value (V) at time point estimate (G) is digitally calculated based on the adjusted PCM signal (U) at step 204. The flow 199 then continues at decision diamond 202 where decision diamond 202 makes a determination as to whether it is necessary to use the interpolated signal value (V) as the next point in time estimate (G), and step 204 is repeated. It should be noted that step 204 may be repeated N times with decision diamond 202, where N is an integer greater than or equal to zero. Thus, if N is equal to 0, step 204 is performed only once and no loop iteration occurs. It should be noted that step 205 merely indicates that step 204 will use the interpolated signal value (V) as the next point in time guess (G). After repeating step 204N times, the process 199 continues at step 206, where step 206 establishes a correction (C) based on the most recent interpolated signal value (V) and the most recent time point estimate (G) and estimated signal slope (S). From step 206, the process 199 continues at step 207, where step 207 combines the correction (C) with the most recent interpolated signal value (V) to produce a natural sample point output (X). From step 207, the process 199 continues at step 208, where step 208 repeats the entire process 199 for each sample of the conditioned PCM signal (U). From step 208, the flow 199 proceeds to oval 201 where the flow ends. In further embodiments of the present invention, steps 206 and 207 may move before decision diamond 202 so that steps 206 and 207 are repeated as part of an iterative loop. It should be noted that in some embodiments of the present invention, the number N used in decision diamond 202 may be a function of one of the values used in flow 199. For example, the value N in decision diamond 202 may be a function of the correction value (C). It should be noted that in alternative embodiments of the present invention, the point in time projection (G) may be given using any suitable method, as required by step 203. An example of a method of time point inference (G) is given and is described in U.S. patent application serial No. 09/478,024, filed on 5/1/2000 by Pallab Midya et al.

It can be shown that the natural sample point output (X) produced by the process performed by the converters 16, 116 illustrated in fig. 6 for a given interpolation stage is nearly optimal compared to the ideal natural sample point for that stage.

A mathematical description of one embodiment of the present invention can be given by the following variables:

sampling index n

Conditioned PCM Signal U (n)28, 128

Estimation of time G (n)50

Interpolating signal values V (n)52

Correction signal C (n)82

Natural sampling point output X (n)57

And (3) estimating the time point of natural sampling in the first iteration: g₁(n)

Interpolated signal values obtained by interpolation at the sampling points in the first iteration: v₁(n)

Outputting natural sampling points in the first iteration: x₁(n)

And (3) estimating the time point of natural sampling in the second iteration: g₂(n)

Interpolated signal values obtained by interpolation at the sampling points in the second iteration: v₂(n)

Correction of signal values in the second iteration: c₂(n)

Outputting natural sampling points in the second iteration: x₂(n)

The first step is to determine an initial point in time guess (G) 50. In its most general form, its derivation is to combine the previous, present, and future samples of the conditioned PCM signal (U)28, 128 with the samples of the past computed natural sample point output (X) 57. An example is as follows,

G(n)＝U(n)+[2{X(n-1)-U(n-1)}-{X(n-2)-U(n-2)}] [1]

or

G(n)＝U(n)+{X(n-1)-U(n-1)} [2]

Or

G(n)＝U(n) [3]

The interpolated signal value (V)52 of the theoretical analog signal 80, 91 at the estimated point in time is calculated according to the interpolation formula. It has been observed in some embodiments of the present invention that better accuracy can be obtained when aligning the uniform sampling of the conditioned PCM signal (U)28, 128 with the center of the ramps 81, 90. Using this method for two-sided PWM (see fig. 5), the interpolated signal value (V)52 for the left-sided PWM can be calculated as follows.

[4]

To the right, there is a similar equation.

[5]

Both equations are based on a three-point second order Lagrange interpolation formula. Other orders of Lagrange interpolation formulas, or other types of interpolation formulas, may be substituted depending on the accuracy and computational constraints.

The next step is the calibration step. The correction step is based on the idea that the value of the interpolated signal (V)52 is very close to the ramp if the time point guess (G) is close to the ideal natural sampling time point. Therefore, the signal value (V) is necessarily very close to the time point estimation (G). Any difference indicates that the time point guess (G) is not completely accurate and can therefore be corrected under the assumption that the signal is moving sufficiently slowly. The first order corrections for the left and right PWM are given by the following equations, respectively.

In both cases, the corrected natural sample point output is determined by simply adding the interpolated signal value to the corrected signal value.

X(m)＝V(m)+C(m) [8]

The correction term improves accuracy. Loop iterations may be introduced to further improve accuracy. Typically two iterations improve the accuracy significantly. Loop iteration may be performed as a new point-in-time guess with the corrected natural sample point output as shown below.

[9]

G₂(2n)＝X₁(2n)＝V₁(2n)+C₁(2n) [11]

The steps in equations (9-11) may be repeated to improve accuracy. The number of iterations of the loop necessary to achieve a given accuracy is related to the oversampling ratio. If the signal corresponding to a low oversampling ratio moves rapidly and the change from this sample to the next is significant, then an increased cycle is required. With the attendant increase in computational and storage requirements. The complexity of each time point estimation, interpolation of the calculated signal values, correction of the signal values, etc., varies with the required accuracy. The optimized algorithm may be designed in accordance with the accuracy requirements, as well as constraints on memory and computation. By way of example, for an embodiment of a digital audio amplifier system where the input signal is constrained to a 20kHz bandwidth and a 375kHz PWM switching frequency, the following left hand formula can be used to achieve extremely good results.

G(2n)＝U(2n) [12]

[13]

The corresponding right formula is as follows.

G(2n+1)＝U(2n+1) [15]

[16]

It should be noted that in this example, the initial point in time guess (G)50 has been selected as the input conditioned PCM signal (U)28, 128. Because the conditioned PCM signal (U)28, 128 is already available, there is no computation or memory storage related to the speculation. The calculation related to the interpolated signal value (V)52 is an 11-step multiplication or addition calculation. 4 memory cells are required for this step. The calculation of the corrected natural sample point output requires two additional additions or multiplications and uses one memory cell. Thus, for this example, a total of 13 steps of operation and 5 memory cells are required per sample. For a switching frequency of 375kHz, two samples per switching cycle, the total calculation is 9.75 megasteps per second. The low total memory requirement is particularly advantageous for reducing the overall computational overhead.

It should be noted that direct conversion from PCM to PWM, a non-linear operation, without the use of, for example, a PCM to PWM converter 16, 116, would result in unacceptable total harmonic distortion. It should be noted that the conversion process performed by the PCM to PWM converter 16, 116 produces a highly linear output, thereby not causing significant harmonic components to be added to the PWM signal 30, 130. It should also be noted that the conversion process performed by the PCM to PWM converter 16, 116 is highly tolerant to the large amount of shaped wideband noise that often accompanies pulse density modulated input signals such as SACD.

The addition of the duty cycle correction circuit 48 in fig. 3 may result in a more efficient PCM to PWM converter 16, 116. Such a PCM to PWM converter 16, 116 can be used for both single-sided and double-sided PWM signals. Referring now to fig. 6, the iteration of the loop performed by one or more of steps 204, 206, and 207 enables the PCM to PWM converter 16, 116 to produce a PWM signal 30, 130 that is more accurate, has less harmonic distortion, and is close to the theoretical limit of accuracy.

In one embodiment, the present invention processes the new SACD audio format in an all digital configuration and converts it to a digital PWM signal, driving a highly efficient digital switching amplifier. It should be noted that such an arrangement readily accommodates volume control, graphics equalization, and other processing of desired digital signal processing functions entirely in the digital domain. Thus, the illustrated architecture of the present invention maintains a full digital path all the way from the PDM input signal to the amplified digital PWM output signal. However, although the invention has been described in terms of audio signal processing, it is important to note that the invention can be used in any type of digital signal processing application in which a pulse density modulated data stream, or a pulse code modulated data stream, is converted to a pulse width modulated signal. Audio signal processing is just one such application.

The PCM to PWM converter 16, 116 illustrated in fig. 3, in conjunction with the method illustrated in fig. 6, may be used for a wide variety of frequencies, including radio frequencies. For example, the disclosed circuits and methods may be used as part of a radio frequency amplifier.

FIG. 7 is a block diagram illustrating a general purpose computer 220 for implementing one embodiment of the present invention. The general purpose computer 220 includes a computer processor 222 and memory 224, coupled by a bus 226. Memory 224 is a relatively high-speed machine-readable medium that includes volatile memory, such as DRAM and SRAM, and non-volatile memory, such as ROM, FLASH, EPROM, EEPROM, and bubble memory. Also connected to the bus are secondary memory 230, external memory 232, output devices such as monitor 234, input devices such as keyboard (with mouse) 236, printer 238, and one or more other computers 240 coupled via communication link 228. Secondary storage 230 includes machine-readable media such as hard drives, magnetic drums, and bubble memory. External storage 232 includes machine-readable media such as floppy disks, a removable hard drive, tapes, CD-ROMs, and even other computers capable of being connected via a communication line. The differences between the secondary storage 230 and the external storage 232 are drawn here primarily to facilitate the description of the invention. Therefore, there is an overlap of basic functions between these units. Computer software 233, including user programs, may be stored in computer software storage media such as memory 224, secondary storage 230, and external storage 232. Secondary storage 230 and non-volatile memory are loaded directly into volatile memory for execution, executed directly from non-volatile memory, or stored into secondary storage 230 prior to being loaded into volatile memory for execution.

Because the apparatus implementing the present invention comprises, for the most part, electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

In the foregoing specification, the invention has been described with reference to specific embodiments. It will be apparent to those skilled in the art that various modifications and changes may be made without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications and changes are intended to be included within the scope of present invention.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims.

Claims (10)

1. A method for generating a pulse width modulated signal, comprising:

receiving a modulated input signal (24) in a digital format, the modulated input signal being in the form of pulse density modulation; and

converting (16) the modulated input signal into a pulse width modulated form (30) to provide a pulse width modulated signal (30), the converting being performed entirely in digital format, wherein the converting step comprises:

providing a natural sample point output (57) based on the modulated input signal (24), an

The natural sample point output (57) is pulse width modulated quantized and noise shaped to provide the pulse width modulated signal (30).

2. The method of claim 1, wherein the converting further comprises:

decimating (12) the modulated input signal (24) to reduce the sample rate of the modulated input signal and increase the resolution of the modulated input signal.

3. The method of claim 1, wherein the converting further comprises:

the modulated input signal is conditioned (14) by modifying at least one of an amplitude response or a frequency response of the modulated input signal.

4. A method according to claim 1, wherein the step of providing a natural sample point output (57) comprises, for each of a plurality of predetermined samples:

predicting (203) natural sampling time points for sampling the modulated input signal;

interpolating (204) the modulated input signal at the predicted natural sampling time point to provide interpolated signal values;

providing a correction value (206) for correcting an error associated with the predicted natural sampling time point, the correction value provided using the interpolated signal value, the predicted natural sampling time point, and the estimated signal slope value; and

the correction values and the interpolated signal values are combined (207) to provide a corrected natural sample point output.

5. An apparatus (10) for generating a pulse width modulated signal, comprising:

an input terminal for receiving a modulated input signal (24) in digital format, the modulated input signal being in the form of pulse density modulation; and

a converter (20) coupled to the input terminal, the converter converting the modulated input signal into a pulse width modulated form to provide a pulse width modulated signal (30), the conversion being performed by the converter substantially in digital format,

wherein the converter (20) comprises:

a natural sampling circuit (40) for providing a natural sampling point output (57) based on the modulated input signal (24), an

A pulse width modulated quantizer and noise shaper (42) for quantizing and noise shaping the natural sample point output (57) to provide the pulse width modulated signal (30).

6. The apparatus of claim 5, wherein the converter (20) further comprises:

a decimation filter (12) coupled to the input terminal for decimating the modulated input signal to reduce a sample rate of the modulated input signal and to increase a resolution of the modulated input signal.

7. The apparatus of claim 5, wherein the converter further comprises:

a digital signal conditioning circuit (14) for conditioning the modulated input signal prior to converting the modulated input signal into a pulse width modulated form.

8. The apparatus of claim 7, further comprising:

a filter (18) coupled to the digital signal conditioning circuit for filtering the pulse width modulated signal to adapt the pulse width modulated signal for driving the load by suppressing predetermined frequency components.

9. A method for generating a pulse width modulated signal, comprising:

receiving a modulated input signal in the form of either pulse code modulation (124) or pulse density modulation (24);

converting the modulated input signal into a pulse width modulated form to give a pulse width modulated signal (30, 130), the conversion being performed entirely in digital format, the conversion further comprising, for each of a plurality of predetermined samples:

predicting (203) natural sampling time points for sampling the modulated input signal;

interpolating (204) the modulated input signal at the predicted natural sampling time point to provide interpolated signal values;

providing a correction value (206) for correcting an error associated with the predicted natural sampling time point, the correction value provided using the interpolated signal value, the predicted natural sampling time point, and the estimated signal slope value; and

the corrected values and interpolated signal values are combined (207) to provide a corrected natural sample point output.

10. An apparatus (10, 110) for generating a pulse width modulated signal, the apparatus comprising:

an input terminal for receiving a modulated input signal, the form of the modulated input signal being either pulse code modulation (124) or pulse density modulation (24);

a converter (16, 116) for converting a modulated input signal into a pulse width modulated form to provide a pulse width modulated signal, the conversion being substantially in digital format, the converter further comprising:

a duty ratio predictor (44) for predicting natural sampling time points for sampling the modulated input signal;

a signal value interpolator (46) coupled to the duty cycle predictor, the signal value interpolator interpolating the modulated input signal at a natural sampling time point to provide an interpolated signal value; and

a correction circuit (48) coupled to the signal value interpolator, the correction circuit providing a correction value for correcting an error associated with the predicted natural sampling time point, the correction value provided using the interpolated signal value, the predicted natural sampling time point, and the estimated signal slope value, the correction circuit combining the correction value and the interpolated signal value to provide a corrected natural sampling point output.