HK1076188A - Data modulating and demodulating apparatus - Google Patents

Description

Data modulation and demodulation equipment

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This application is a divisional application entitled "data modulation and demodulation method and apparatus, and code arrangement method" (application No. 03165025.2; application date: 9/27/2003).

Priority

This application claims priority to korean patent applications 2002-.

Technical Field

The present invention relates to the field of data modulation and demodulation, and more particularly, to a data modulation apparatus and a data demodulation apparatus that provide a modulation code having a reduced error propagation probability, a high coding efficiency, and a DC suppression capability.

Background

The multi-mode coding method provides DC suppression capability for modulation codes without DC suppression capability. In a multi-mode encoding method, additional a-bit information is inserted into an input data stream, and 2 is generated based on the additional a-bit information^aRandom data flow, even at 2^aWhen modulation without DC suppression capability is performed in the random data stream, one of the modulated data streams containing the smallest DC component is also selected, and therefore, the modulated data stream has DC suppression capability.

Us patent 6,225,921 discloses "an apparatus for encoding/decoding n-bit source words into corresponding m-bit channel words and m-bit channel words into corresponding n-bit source words", wherein the redundancy of the code (d 1, k 7, m 2, n 3) is about 2%, the coding rate R is R49/75 0.6533, and the coding efficiency R/C (d, k) is R/C0.6533/0.6793 96.2%. For convenience, the modulation code used in us patent 6,225,921 is referred to as an a-code.

U.S. Pat. No. 6,281,815 discloses a method, a modulation method, a demodulation method, and a demodulation apparatus for assigning RLL codes with enhanced DC suppression capability, in which redundancy of a current code (d 1, k 8, n 12) is about 2%, a coding rate R thereof is R32/49 0.6531, and a coding efficiency R/C (d, k) thereof is R/C0.6531/0.6853 thereof is 95.3%. For convenience, the modulation code used in U.S. Pat. No. 6,281,815 is referred to as a B-code. Here, "C" refers to the capability depending on "d" and "k".

In the controllable scrambling method described in "for mass data storage systems" by Kees a. schouhamer Immink, Shannon Foundation Publishers, chapter13, 1999, when 4 bits of redundancy are inserted into every 25 bytes of data, RLL (1, 7) of the data is modulated, the coding rate R is 200/306-0.6536, and the coding efficiency R/C (d, k) is R/C (d, k) 0.6536/0.6793-96.2%. The modulation code used in the above-mentioned document is referred to as C-code.

The coding rates in the above-described conventional modulation methods are similar, i.e., in the range of 95.3% -96.2%, and Power Spectral Density (PSD) curves representing the DC suppression capability of the a-code, B-code, and C-code are shown in fig. 1.

However, in the multi-mode encoding method disclosed in the above-mentioned document, the frequency of utilization of additional information required to change the data stream into random data should be increased to have a sufficient DC suppression capability. Furthermore, even if a modulation technique with high coding efficiency is developed, the DC suppression capability may be insufficient. For example, when the B-code disclosed in U.S. Pat. No. 6,281,815 does not include redundant bits, DC can be suppressed, but without additional bits, there cannot be sufficient DC suppression capability. Hereinafter, a code that can suppress DC without using a redundant bit, but has weak suppression capability without the redundant bit is referred to as a weak DC-free modulation code.

Fig. 2 illustrates a conventional multiplexing method for converting an input data stream into random data. A conventional multiplexing method is disclosed in korean patent No. 1999-703183, by which an input data stream is converted into 2 by successively scrambling the input data stream with additional a-bit information^aRandom data flow, filed by SANYO DENKI co, LTD, entitled "digital modulation circuit, digital modulation method, digital demodulation circuit, and digital demodulation method".

In FIG. 2, the multiplexing information s is performed by an XOR device_tAnd a code modulation unit x_i，0To x_i，u-1Performing an XOR operation to convert predetermined bit data x_i，0To x_i，u-1Composed input data stream(called code modulation unit) to random data stream

In other words, the unit x is modulated by the first code using the exclusive-or means_i，0And initial data (multiplex information) s_tPerforming XOR operation to modulate the first code by unit x_i，0Conversion into data y^t _i，0. By means of pairs of converted data y^t _i，0And a code modulation unit x_i，1Performing XOR operation to modulate the next code by unit x_i，1Conversion into data y^t _i，1. Thereafter, the xor operation is repeated for the converted data of the previous code modulation unit and the code modulation unit to be converted until the data input streamLast code modulation unit x_i，u-1So as to produce a converted signal per code modulation unitAnd (4) data.

Fig. 3 shows a flow of data through a Run Length Limited (RLL) when an input data stream is converted into random data, RLL modulated, recorded on a storage medium, and reproduced from the storage medium according to the multiplexing method shown in fig. 2Inverting demodulated streams

During inversion of the data, except for the non-inverted RLL streamAnd a demodulation code unit (original data or non-inverted demodulation code unit) immediately before the demodulation code unit requiring inversion, generates a demodulated stream by repeatedly performing an exclusive or operation on each demodulation code unit requiring inversion

In other words, by demodulating the first demodulation code unit y^t _i，0And initial data (multiplex information) s_tPerforming XOR operation to convert the first demodulation code unit y^t _i，0Inversion into data x_i，0. Next, the first non-inverted demodulation code unit y is demodulated^t _i，0And demodulation code unit y^t _i，1Performing XOR operation to demodulate the code unit y^t _i，1Inversion into data x_i，1. Thereafter, the exclusive or operation is repeated for the demodulation code unit requiring inversion and the demodulation code unit immediately preceding the demodulation code unit requiring inversion until the RLL streamTo produce the inverse data for each demodulation code unit.

As described above, during the inversion of data, the demodulation code unit isOne demodulation code unit that is not inverted is used for the inversion of (2). Thus, when an error occurs in a demodulation code unit requiring inversion, the error also affects the next demodulation code unit. For example, when the demodulation code unit y is not inverted^t* _i，u-3When there is an error, the error affects the inverse data x^* _i，u-3And the following data x^* _i，u-2。

Accordingly, in the prior art, when RLL flowsWhen there is an error, the error propagates to the descrambled data x^* _i，u-3And the following data x^* _i，u-2. Error propagation is a general feature of multi-mode coding methods that utilize scrambling.

Disclosure of Invention

The present invention provides a data modulation method and apparatus that provides a high-efficiency modulation code with higher DC suppression capability by maintaining the DC suppression capability described in the above-mentioned 3 references and applying the multi-mode coding method to a weak DC-free modulation code.

The invention also provides a data modulation method and device and a data demodulation method and device, so as to reduce the possibility of error propagation.

The present invention also provides a data modulation method and apparatus and a data demodulation method and apparatus using a multiplexing method for generating a pseudo random data stream by maintaining a DC suppression capability and intermittently scrambling input data.

The present invention also provides a method of arranging a weak DC-free modulation code by generating codewords satisfying a (d, k) constraint conditions and then arranging the codewords, thereby maintaining an initial characteristic of a code stream even when the codewords are regularly arranged according to a boundary during arranging the code stream.

According to an aspect of the present invention, a data modulation method modulates m-bit data into n-bit (n ≧ m) codewords, where a minimum run-length restriction is defined as "d" and a maximum run-length restriction is defined as "k". The input data stream is divided by a predetermined length, and multiplexed with multiplexing information according to a predetermined multiplexing method to provide a multiplexed data stream. The multiplexed data stream is weakly DC-free runlength limited (RLL) -modulated without a separate DC control code conversion table including additional bits, and then, a code stream having a minimum DC component among the multiplexed, RLL-modulated code streams is provided.

According to another aspect of the present invention, a data modulation method modulates m-bit source data into n-bit (n ≧ m) codewords, where a minimum run-length restriction is defined as "d" and a maximum run-length restriction is defined as "k". An input data stream divided by a predetermined length is multiplexed into a plurality of types of pseudo random data streams with predetermined bit multiplexing information by applying a predetermined multiplexing method to each pseudo random data stream. These multiple types of pseudo-random data streams are RLL modulated to produce a modulated code stream that performs optimal DC suppression.

According to yet another aspect of the present invention, a data modulation method modulates m-bit source data into n-bit (n ≧ m) codewords, where a minimum run-length limit is defined as "d" and a maximum run-length limit is defined as "k". An input data stream divided by a predetermined length is multiplexed into a plurality of types of pseudo random data streams with predetermined bit multiplexing information by applying a predetermined multiplexing method to each pseudo random data stream. The multiplexed data stream is weakly DC-free RLL modulated, does not utilize a DC control code conversion table including additional bits, and provides a code stream including a minimum DC component in the multiplexed, RLL modulated code stream.

According to yet another aspect of the present invention, a data demodulation method demodulates n-bit input digital data into m-bit (n ≧ m) demodulation code units to generate an undiversified data stream having a predetermined length. The non-inverted data stream is discontinuously descrambled with multiplexing information to produce an inverted data stream.

According to yet another aspect of the present invention, a method of arranging m-bit source data into n-bit (n ≧ m) codewords defines a minimum run-length limit "d" of 1 and a maximum run-length limit "k" of 7. When codeword a is connected to codeword b, codeword a being a previous codeword, codeword b is selected from codewords b1 and b2, wherein the code stream connecting codeword a to codeword b1 is X1, wherein the code stream connecting codeword a to codeword b2 is X2, and codewords b1 and b2 are arranged to have a reverse parameter INV which predicts a transition of a next code according to whether the number of bits of value "1" in a codeword is odd or even. When the codeword a is connected to the codeword b1 or b2, although the codeword a, b1 or b2 is modulated into another type of codeword according to a boundary rule, the code streams X1 and X2 are arranged to have the inverse parameter INV.

According to still another aspect of the present invention, an apparatus modulates m-bit source data into n-bit (n ≧ m) codewords by limiting a minimum run-length restriction to "d" and limiting a maximum run-length restriction to "k" in order to improve DC suppression capability. The apparatus comprises: a multiplexer for multiplexing the input data divided by a predetermined length with multiplexing information to provide a multiplexed data stream; and an encoder for performing weak DC-free RLL modulation on the multiplexed data stream without adding a DC control subcode conversion table to which additional bits are added; and a selector that selects a code stream containing the smallest DC component among the multiplexed, RLL-modulated code streams.

According to yet another aspect of the present invention, a data modulation apparatus modulates m-bit source data into n-bit (n ≧ m) code words, where a minimum run-length restriction is defined as "d" and a maximum run-length restriction is defined as "k". The data modulation apparatus includes: a multiplexer multiplexing an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams with predetermined bits of multiplexing information by applying a predetermined multiplexing method to each pseudo random data stream; and an encoder that RLL-modulates these plural types of pseudo random data streams to generate a modulated code stream in which optimum DC suppression is performed.

According to yet another aspect of the present invention, a data modulation apparatus modulates m-bit source data into n-bit (n ≧ m) code words, where a minimum run-length restriction is defined as "d" and a maximum run-length restriction is defined as "k". The data modulation apparatus includes: a multiplexer multiplexing an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams with predetermined bits of multiplexing information by applying a predetermined multiplexing method to each pseudo random data stream; and an encoder for performing weak DC-free RLL modulation on the multiplexed data stream without adding a DC control subcode conversion table to which additional bits are added; and a selector that selects a code stream containing the smallest DC component among the multiplexed, RLL-modulated code streams.

According to still another aspect of the present invention, a data demodulation apparatus includes: a decoder for demodulating each of the n-bit input digital data into a demodulation code unit of m-bits (n ≧ m) to generate an irreversible data stream having a predetermined length; and a demultiplexer for discontinuously descrambling the non-inverted data stream with the multiplexing information to generate an inverted data stream.

The operations of the method of the present invention may be implemented using computer-executable instructions of a computer-readable medium.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

These and/or other aspects and advantages of the present invention will become apparent from the following description of the embodiments, which is to be read in connection with the accompanying drawings:

FIG. 1 shows a Power Spectral Density (PSD) curve of a conventional code;

fig. 2 illustrates a conventional multiplexing method;

fig. 3 illustrates error propagation characteristics when reproducing data converted by the conventional multiplexing method shown in fig. 2;

FIG. 4 is a block diagram of a data modulation device in accordance with an aspect of an embodiment of the present invention;

fig. 5 illustrates a multiplexing method using pseudo scrambling applied to the multiplexer of fig. 4;

fig. 6 illustrates error propagation characteristics when reproducing data converted by the conventional multiplexing method shown in fig. 5;

FIG. 7 illustrates a PSD curve showing DC suppression capability in a data modulation method according to an aspect of an embodiment of the present invention;

FIG. 8 shows codeword characteristics of a primary code group;

FIG. 9 shows codeword characteristics for a secondary code group for DC control;

FIG. 10 shows the next code group ncg determined from the number of end zeros EZ;

fig. 11 shows a Run Length Limited (RLL) condition when connecting codeword a to codeword b;

FIG. 12 shows the change of the parameter INV before and after transcoding when the RLL condition of FIG. 11 is not satisfied;

fig. 13 shows an example of code-stream divergence caused by codewords b1 and b2 for DC control;

fig. 14 shows the multiplexing information converted into the multiplexing ID in the sync signal and the multiplexing ID inserter shown in fig. 4;

FIGS. 15A to 15E show the master code conversion tables generated and arranged in consideration of the above-described conditions;

fig. 16 shows a sub-code conversion table for DC control generated and arranged in consideration of the above conditions;

FIG. 17 illustrates a PSD curve for an RLL (1, 7) code in accordance with an aspect of an embodiment of the present invention;

fig. 18 shows the recording density and recording efficiency of RLL (1, 7) codes, and the recording densities and recording efficiencies of a-codes, B-codes, and C-codes according to an embodiment of the present invention;

FIG. 19 shows a PSD curve for an RLL (2, 10) code in accordance with an aspect of an embodiment of the invention; and

fig. 20 shows the recording density and recording efficiency of RLL (2, 10), and the recording density and recording efficiency of the conventional 8-14 modulation plus (EFMP) code.

Detailed Description

Reference will now be made in detail to the present embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.

Fig. 4 is a block diagram of a data modulation apparatus according to an embodiment of the present invention. Referring to fig. 4, the input data stream may be expressed as equation 1 and divided by vXu slicer 10 as in equation 2. In other words, the input data stream is split into vXu (═ k) data streams, i.e., v data streams that are each u bytes long.

x＝(x₀，x₁，...，x_k-1，...，x_l-1) ......(1)

Here, x_i，j＝x_ixu+j。

The multiplexer 20 using the pseudo scrambling multiplexes each vXu data stream divided by the vXu slicer 10 into L2 by adding a-bit information to each vXu data stream^aA data stream, and then, according to the added multiplexing information s, L is 2^aThe data stream is converted to pseudo-random data. Data stream of u byte lengthMultiplexed into 2 with different content^au bytes of data as shown in equations 3 and 4.

Where u-1 is a multiple of q, p is 0, 1.., r, r is the average (share) of (u-1)/q, and q denotes a scrambling interval index. Function(s)Multiplexing information s for finger to input data streamConverted into a result of random data.

The sync signal and multiplex ID inserter 30 may have a plurality of channels (here, L ═ 2) according to the number of bits of the added multiplex information s^a). Sync signal and multiplex ID inserter 30 inserts sync pattern into 2^aThe multiplexed pseudo random data stream, i.e., the multiplexed pseudo random data stream to which the multiplexing information s is added, is then converted into a multiplexing ID.

The weak DC-free RLL encoder 40 may have multiple channels (here, L ═ 2) according to the added multiplexing information^a) And weak DC-free RLL modulation is performed on the modulation code. Here, according to RLL modulation, m-bit source data is converted into n-bit code words (n ≧ m), which are limited by a minimum run length "d" constraint and a maximum run length "k" constraint.

The weak DC-free RLL encoder 40 encodes a code, which is capable of suppressing DC when there is no redundancy under the condition that an additional DC suppression code conversion table including additional bits does not appear, but has weak DC suppression capability, into a code word satisfying a predetermined RLL condition. That is, an RLL (1, 7, 8, 12) code in which the minimum run length d is 1 and the maximum run length k is 7 groups code words into a plurality of code words according to the above RLL condition, and these code words are RLL modulated with a main code conversion table in which the code words are arranged so that a code word stream of source words has DC control performance and a sub code conversion table for DC control that satisfies a predetermined RLL condition and is made by shifting unnecessary code words out of the main code conversion table.

The sync signal and multiplex ID inserter 30 can reduce the interference noise of the signal by converting the multiplex information into the multiplex ID by defining the minimum run length "d" as 2 and the maximum run length "k" as 7 so as to increase the size of the minimum mark or pit. As another aspect, the weak DC-free RLL encoder 40 may encode a code, for example, an RLL (2, 10, 8, 15) code, where the minimum run-length limit "d" is 2 and the maximum run-length limit "k" is 10.

Comparator and selector 50 is at 2^aThe RLL modulated stream having the least number of DC components is selected from the RLL modulated streams.

Fig. 5 shows a multiplexing method using pseudo scrambling applied to the multiplexer 20 shown in fig. 4. The present invention refers to a method of discontinuously scrambling input data using pseudo scrambling as a multiplexing method.

In the multiplexing method using the pseudo scrambling, as shown in fig. 2, if an error occurs in a data location, the error causes an error in the next data. Accordingly, if data is discontinuously scrambled without affecting the DC component of the code stream, the possibility of error propagation to the next data can be reduced.

In fig. 5, multiplexing information s is performed by using discontinuous q-th exclusive-or means_tAnd x_i，0To x_i，u-1Performs an exclusive or operation on the non-consecutive qth multiplexed information, which will include x_i，0To x_i，u-1U byte long input data streamConversion to pseudo-random data

When multiplexing information s_tWhen the number of bits a is less than or equal to the number of bits m of the input data, the multiplexing information s is used_tAll bits of (a) will be u bytes long of the input data streamAnd (4) multiplexing. However, if a < m, the conversion of the Least Significant Bit (LSB) of the input data, the a-bits of the Most Significant Bit (MSB) of the input data, or the a-bits of the m-bits of the input data into pseudo-random data shows almost the same efficiency as the conversion of all the m-bits into pseudo-random data.

In other words, by modulating the unit x for the first code_i，0And initial data (multiplex information) s_tPerforming XOR operation to modulate the first code by the unit (first data to be modulated) x_i，0Modulated into data y^t _i，0. Modulating unit x without code_i，1To x_i，q-1Performing an XOR operation such that the code modulates the unit x_i，1To x_i，q-1The output is unchanged. Then, for modulated data y^t _i，0And a code modulation unit x of a discontinuous q-th modulation unit_i，qPerforming an XOR operation to generate the next modulated data y^t _i，q. Repeating the XOR operation until the input data streamThe last discontinuous qth modulation unit.

Fig. 6 shows error propagation characteristics when pseudo random data modulated according to the multiplexing method using pseudo scrambling shown in fig. 5 is reproduced. In thatDuring data inversion, data flowIs an RLL stream demodulated with a decoder (not shown) that demodulates the data stream according to the RLL modulation method used during modulation. Also, the structure shown in FIG. 6 may be referred to as a demultiplexer, which discontinuously descrambles the non-inverted data with multiplexing information to provide an inverted data stream.

In fig. 6, for initial data (multiplexed data s)_t) And a first demodulation code unit y^t _i，0An exclusive or operation is performed, and then, the exclusive or operation is performed on each of the discontinuous q-th demodulation code units and each of the demodulation code units preceding each of the q-th demodulation code units, which are required to be inverted, so as to generate recovered data.

In other words, for the first demodulation code unit y^t _i，0And initial data (multiplexed data s)_t) Performing an XOR operation to produce the inverted data x_i，0. Unpaired demodulation code unit x_i，1To x_i，q-1Performs an exclusive OR operation and demodulates the code unit x_i，1To x_i，q-1The output is unchanged. Thereafter, for the first demodulation code unit y^t _i，0(not inverted) and a first q-th demodulation code unit y of a discontinuous q-th demodulation code unit^t _i，qPerforming an XOR operation to produce the inverted data x_i，q. Next, the XOR operation is repeated until the data stream is not invertedThe last discontinuous qth demodulation code unit.

Accordingly, pseudo random data RLL is modulated and stored on a storage medium such as an optical disc as an RLL streamReproduced from the storage medium. Then, if only RLL stream is converted into another type of data without XOR operationData x of (2)_i，q+1Where an error occurs, the error does not propagate to another data. Error propagation occurs only when an error is generated in the RLL stream after reproduction corresponding to input data, which is modulated into another type of data through an xor operation.

When data is converted into pseudo-random data according to the multiplexing method using pseudo-scrambling as shown in fig. 5, the probability of error propagation is reduced to 1/q (q is the period of the exclusive or operation) compared to the multiplexing method shown in fig. 2. Here, the value of q should be determined to accept DC capability after RLL modulation. The probability of error propagation and DC suppression capability may decrease with increasing value of q. Conversely, the probability of error propagation and DC suppression capability may increase as the value of q decreases.

Fig. 7 depicts a PSD curve showing the change in DC suppression capability with the xor operation period q. The DC suppression capability of the modulated code stream is shown depending on the xor operation period q, where the bit number a of the multiplexing information st is 2, the multiplexing length u is 50, and the bit number m of the input data to be modulated is 8. For multiplexed information s_tAnd 2 bits of the LSB of the 8-bit input data performs an xor operation. The PSD curve shows the DC suppression capability as a function of the result of the xor operation when the xor operation period q is 1 byte, 5 bytes, 10 bytes, 15 bytes, and 20 bytes. As can be seen from fig. 7, although the xor operation is performed every 5 bytes, the DC suppression capability is almost unchanged and the error propagation rate can be reduced to 1/5.

A weak DC-free RLL modulation code according to an embodiment of the present invention is now explained.

The RLL (d, k, m, n) code was evaluated based on the recording density and DC suppression ability. Here, m denotes the number of data bits (also referred to as the number of bits of source data or the number of bits of an information word), n denotes the number of bits of a modulated codeword (also referred to as the number of channel bits), d denotes the minimum number of consecutive 0's (minimum run length limit) that can be between "1" bits of the codeword, and k denotes the maximum number of consecutive 0's (maximum run length limit) between "1" bits in the codeword. The bit slots between the codewords are represented by T corresponding to the period of the clock signal used in recording or reproduction.

In the modulation method, the recording density can be increased by reducing the number n without changing the minimum run length limit d and the number m. However, the RLL code should satisfy a minimum run length limit d and a maximum run length limit k in the code words. Thus, the number of codewords satisfying the RLL (d, k) condition is 2^m(m is the number of bits of data) or 2^mThe above. However, in order to actually use the RLL code, the portion of the code word connected to the code word should also satisfy the RLL (d, k) condition, and the code word to be used should have a DC suppression capability when the DC component of the code affects the performance of the optical recording and/or reproducing apparatus.

In an embodiment of the present invention, two types of code tables, i.e., a main code conversion table and a sub code conversion table for DC control, are generated for a codeword of a source code to be modulated.

A method of generating code words in the main code conversion table and the sub code conversion table is described below, taking an RLL (1, 7) code as an example, where the minimum run length limit is 1 and the maximum run length limit is 7.

Fig. 8 illustrates a plurality of code word groups of the main conversion and code word characteristics of the code word groups.

When the minimum run length limit is d, the maximum run length limit is k, the number of bits of the source data is m, the number of bits of the modulated codeword is n, the number of consecutive 0's from LSB to MSB of the modulated codeword is End Zero (EZ), the number of consecutive 0's from MSB to LSB is Leading Zero (LZ), codewords where d is 1, k is 7, m is 8, and 0 ≦ EZ ≦ 5 are classified as follows according to the LZ condition.

(1) The number of codewords satisfying 1 LZ < 7 is 210.

(2) The number of codewords satisfying 0 LZ < 4 is 316.

(3) The number of codewords satisfying the condition that LZ is more than or equal to 0 and less than or equal to 2 is 264.

For modulating 8-bit source data, the number of codewords should be at least 256 or more than 256. However, in group (1), the number of codewords is less than 256, so that the part of the codeword that satisfies the different LZ conditions is taken to supplement the shortage of codewords. In other words, 51 "1010 xxxxxxxx" codewords are subtracted from the codeword in group (2) satisfying LZ ═ 0, and then added to the codeword in group (1). Then, the number of code words in group (1) becomes 261, the number of code words in group (2) becomes 265, and the number of code words in group (3) becomes 264. As a result, the groups (1), (2), and (3) each contain 256 or more code words, so that the minimum number "256" of code words of 8-bit source data to be modulated can be satisfied. 256 codewords are taken from each group (1), (2), and (3), resulting in 3 main code groups MCG1, MCG2, and MCG 3. In FIG. 8, the master code group MCG1 corresponds to the inclusion group (1), the group (1) includes codewords satisfying 1. ltoreq. LZ.ltoreq.7 and 51 codewords extracted from the group (2), and the master code groups MCG2 and MCG3 correspond to the groups (2) and (3), respectively. Only 256 codewords of each master code group MCG1, MCG2 and MCG3 are used as codewords of the source data to be modulated.

Fig. 9 shows a plurality of code word groups of the sub-code conversion table for DC control and code word characteristics of the code word groups.

The code words in the sub-code conversion table are code words satisfying 6 ≦ EZ ≦ 7, redundant code words of the main code group MCG1, MCG2, and MCG3, and code words satisfying 5 ≦ LZ ≦ 6 or LZ ≦ 3, and then used as the auxiliary code group. The conditions for generating codewords of the sub-code conversion table are described in detail below, and the secondary code groups are represented by ACG1, ACG2, and ACG 3.

The secondary code group ACG1 contains 15 codewords, the 15 codewords being derived from: 8 codewords satisfying 6 ≦ EZ ≦ 7 and LZ ≠ 0 + 5 redundant codewords of the master code group MCG1 + 2 "1010 xxxxxxxx" codewords satisfying 6 ≦ EZ ≦ 7 and LZ ≠ 0.

The secondary code group ACG2 contains 40 codewords, the 40 codewords being derived from: 12 codewords satisfying 6 ≦ EZ ≦ 7 and 0 ≦ LZ ≦ 6 + 21 codewords satisfying 0 ≦ EZ ≦ 5 and 5 ≦ LZ ≦ 6 + 9 redundant codewords of the main code group MCG 2-2 "1010 xxxxxxxx" codewords satisfying 6 ≦ EZ ≦ 7 and LZ ≦ 0.

The secondary code group ACG3 contains 51 codewords, the 51 codewords being derived from: 10 codewords satisfying 6 ≦ EZ ≦ 7 and 0 ≦ LZ ≦ 3 + 33 codewords satisfying 0 ≦ EZ ≦ 5 and LZ ≦ 3 + 8 redundant codewords of the main code group MCG 3.

Fig. 10 shows a parameter ncg, and a parameter ncg indicates the next code group M ═ ncgdet, i.e., the next code group of the previous codeword a, determined from the number EZ _ a of end zeros of the previous codeword a in the main code conversion table described with reference to fig. 6 and the sub code conversion table for DC control described with reference to fig. 9. And determining the code group to which the code word b belongs according to the number EZ _ a. In other words, if the number EZ _ a is "0", the code group of codeword b is "1" (═ MCG1), if 1 ≦ EZ _ a ≦ 3, the code group of codeword b is 2(═ MCG2), if 4 ≦ EZ _ a ≦ 7, the code group of codeword b is 3(═ MCG 3).

The portion connecting the code word a and the code word b must satisfy the RLL (d, k) condition.

Fig. 11 shows the RLL (d, k) condition when codeword b is concatenated with codeword a. The value obtained by adding the EZ _ a number of ending zeros of the code word a to the LZ _ b number of leading zeros of the code word b should be greater than or equal to the minimum run length d and less than or equal to the maximum run length k in order to satisfy the RLL (d, k) condition.

Fig. 12 shows the change of the parameter INV before and after code modulation when the code words a and b do not meet the RLL (d, k) condition described with reference to fig. 11. The parameter INV denotes the transition of the next codeword, where the parameter INV is "0" if the number of bits of the value "1" in the codeword is even, and "1" if the number of bits of the value "1" in the codeword is odd. In addition, the Digital Sum Value (DSV) parameter refers to the DSV in the stream of code words, a low absolute DSV indicating that the stream of code words contains a small amount of DC or low frequency components. The Codeword Sum Value (CSV) parameter represents a DC value in a codeword for measuring a DC or low frequency component during modulation of the code, and a low CSV indicates that the codeword contains a small amount of the DC or low frequency component. If the INV value accumulated to the current codeword in the codeword stream is '0', the CSV value of the next codeword is added to the DSV value of the codeword accumulated before the next codeword in order to update the DSV value. If the accumulated INV value is "1", the sign of the CSV of the next codeword is negated and then added to the accumulated DSV value to update the DSV value.

Referring to fig. 12, a code group to which a codeword b belongs is determined according to the number EZ _ a of end zeros of a previous codeword a. In the case where one code group is designated as the code group of the code word b, which takes out the code word from another code conversion table due to the absence of the code word in the main code conversion table and the sub code conversion table for DC control, the RLL (d, k) condition may not be satisfied. In FIG. 12, the code group violation d ≦ EZ _ a + LZ _ b ≦ k for codeword b, where the number of ending zeros EZ _ a for codeword a is changed. The change in code words caused by a mismatch with the RLL condition is called the "boundary rule". The parameter INV indicating that the number of bits of the value "1" in the codeword stream is even or odd may be changed from the state before the code modulation according to the boundary rule. Thus, the codewords are arranged in a predetermined order in the code conversion table for DC control.

Fig. 13 shows the divergence of the codeword stream caused by codewords b1 and b2 for DC control. A significant feature of code modulation according to embodiments of the present invention is that the codewords in the two optional code conversion tables have opposite INV characteristics (indicating whether the number of bits of value "1" in the codeword stream is odd or even) with the aim of controlling Direct Current (DC). In this way, one of the two codewords can be aligned for optimal DC control, since the codewords in the two optional code conversion tables have opposite INV characteristics. As described above, the parameter INV may be changed according to the boundary condition. However, this change is not important when the same phenomenon occurs in both code conversion tables that can be selected at the DC control point, i.e. when the parameter INV is changed in both code conversion tables. Accordingly, in the embodiment of the present invention, the code conversion table is designed in consideration of the following conditions.

First, at position a, which connects codeword a to codeword b, codewords b1 and b2 may be selected as codeword b. In this case, the ending zeros of the number EZ _ a of code words are the same as in "xxxxxxxxx 101", the leading zeros of the number LZ _ b1 of code words b1 are the same as in "101 xxxxxxxxx", and the leading zeros of the number LZ _ b2 of code words b2 are the same as in "101 xxxxxxx". In other words, codewords having a plurality of leading zeros as in "101 xxxxxxxxx" are placed at the same positions in the primary code group MCG1 and the secondary code group ACG1, and codewords having a plurality of ending zeros as in "xxxxxxxxx 101" are placed at the same positions in the primary code group MCG1 and the secondary code group ACG1, the primary code group MCG2 and the secondary code group ACG2, and the primary code group MCG3 and the secondary code group ACG 3. Accordingly, when a plurality of end zeros of codeword a are the same as in "xxxxxxx 101", parameter INV of codeword a is changed or not changed. Thus, according to the boundary rule, the code stream to which the codeword b1 belongs and the code stream to which the codeword b2 belongs have opposite INV characteristics.

Hereinafter, when the codewords B1 and B2 are respectively connected with the codeword c, at the position B where the codeword B is connected to the codeword c, although the codewords B1, B2 or c are modulated into another type of codewords according to the boundary rule, the code stream where the codeword B1 is connected to the codeword c has the opposite parameter INV to the code stream where the codeword B2 is connected to the codeword c.

The sync pattern and multiplex ID will now be explained.

In the modulation method in which the maximum number "k" of consecutive 0 s between "1" bits is limited to 7, the synchronization pattern "010000000010000000010" in violation of the limit k being 7 is used.

A synchronous mode: 010000000010000000010

As shown in fig. 14, 4-bit multiplexing information is modulated into a 6-bit multiplexing ID to multiplex data streams. In this case, one data stream is converted to L ═ 2⁴16 types of random data streams.

Fig. 15A to 15E illustrate the master code conversion tables generated and arranged in consideration of the above-described conditions.

Fig. 16 shows the sub-code conversion tables for DC control generated and arranged in consideration of the above conditions. It is checked whether the previous codeword (codeword a of fig. 13) and the following codeword (codeword c of fig. 13) violate the run length constraint. The code words in the sub-code conversion table should be used when the previous and subsequent code words do not violate the run length constraint.

Fig. 17 shows PSD curves of RLL (1, 7) modulated code streams according to the present invention.

Fig. 18 compares the coding rate and coding efficiency of the RLL (1, 7) code according to an embodiment of the present invention with those of the conventional a-code, B-code, and C-code. The RLL (1, 7) code has a DC suppression capability similar to that of conventional A-codes, B-codes and C-codes and a higher coding efficiency. As a result, the recording density can be improved by about 2%.

Fig. 19 shows PSD curves showing the DC suppression capability of RLL (2, 10, 8, 15) and the DC suppression capability of the 8-14 modulation plus (EFMP) code used on conventional DVDs according to an embodiment of the present invention. Here, the EFMP code suppresses DC using a separate code conversion table for DC control in addition to the master code conversion table. An example of the RLL (2, 10, 8, 15) code is disclosed in korean patent application 2001-21360 filed by the present applicant. Embodiments of the present invention perform weak DC-free RLL modulation using a main code conversion table and a sub code conversion table for DC control without using a separate sub code conversion table including additional bits.

Fig. 20 compares the coding rate and coding efficiency of RLL (2, 10, 8, 15) according to an embodiment of the present invention with those of EFMP codes. The RLL (2, 10, 8, 15) code has a DC suppression capability similar to that of the EFMP code and a higher coding efficiency, which increases the recording density by 5.4%.

Embodiments of the present invention can be effectively applied to various storage media storing digital data, particularly high-density storage media such as a high-density digital versatile disc (HD-DVD).

As described above, the present invention can combine a weak DC-free modulation code with a multi-mode coding method to provide a DC suppression capability with an improved high-efficiency modulation code. As a result, the recording density can be improved.

Further, when a codeword that violates the RLL condition is replaced with another type of codeword during the DC-suppressed RLL modulation, the replaced codeword may be arranged to maintain the DC-suppressed capability of the codestream. As a result, the effect of improving the DC suppression capability of the code stream can be achieved.

Further, in the multi-mode encoding method, input data is discontinuously scrambled so as to be multiplexed into pseudo random data, thereby removing a DC component. In this way, the DC suppression capability can be retained, and the possibility of error propagation can be reduced as compared with the multi-mode coding method using the general scrambling method.

The operations of the method of the present invention may be implemented using computer-executable instructions of a computer-readable medium.

Although a few embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

Claims (36)

1. An apparatus for modulating m-bit source data into n-bit codewords, where n ≧ m, n and m are positive integers, for improving DC suppression capability by defining a minimum run-length limit to "d" and a maximum run-length limit to "k", where "d" and "k" are positive integers, comprising:

a multiplexer for multiplexing the input data divided by a predetermined length with multiplexing information to provide a multiplexed data stream;

an encoder for performing weak DC-free RLL modulation on the multiplexed data stream without adding a DC control subcode conversion table to which additional bits are added; and

and a selector that selects a code stream containing a minimum DC component among the multiplexed, RLL-modulated code streams.

2. The apparatus of claim 1, further comprising:

a divider dividing an input data stream into predetermined lengths; and

and a sync signal and multiplex ID inserter for inserting a sync pattern into the multiplexed data stream to which the multiplex information is added and converting the multiplex information into a multiplex ID.

3. The apparatus of claim 1, wherein the multiplexer converts the divided input data stream into random data by a scrambling method.

4. The apparatus of claim 1, wherein the multiplexer converts the divided input data stream into random data in an interleaving method.

5. The apparatus of claim 1, wherein the encoder performs weak DC-free RLL modulation with codewords of the same data in the primary code group and the DC control secondary code group, the codewords having opposite INV values in order to control DC, and INV is a parameter that predicts a transition direction of a next codeword according to whether a number of bits of a value "1" in a stream of codewords is odd or even.

6. The apparatus of claim 1, wherein the encoder performs the weak DC-free RLL modulation by defining a minimum run-length limit "d" as 1 and a maximum run-length limit "k" as 7.

7. The apparatus of claim 6, wherein when the bit length of the source data is 8, the modulated codeword has a bit length of 12.

8. The apparatus of claim 2, wherein the sync signal and multiplex ID inserter performs the inserting and multiplexing by limiting a minimum run length limit "d" to 1 and a maximum run length limit "k" to 7.

9. The apparatus of claim 2, wherein the encoder defines a minimum run length limit "d" as 1 and a maximum run length limit "k" as 7, and the sync signal and the multiplex ID inserter defines the minimum run length limit "d" as 2 and the maximum run length limit "k" as 7, so as to increase the minimum run length limit "d" and thus increase the minimum mark length, resulting in reduction of interference noise of the signal.

10. The apparatus of claim 2, wherein the encoder performs the weak DC-free RLL modulation by defining a minimum run-length limit "d" as 2 and a maximum run-length limit "k" as 10.

11. The apparatus of claim 10, wherein the bit length of the source data is 8, and the modulated codeword has a bit length of 15.

12. The apparatus of claim 10, wherein the sync signal and multiplex ID inserter performs the inserting and multiplexing by limiting a minimum run length limit "d" to 2 and a maximum run length limit "k" to 10.

13. A data modulation apparatus for modulating m-bit source data into n-bit codewords, wherein n ≧ m, n and m are positive integers, where a minimum run-length restriction is defined as "d" and a maximum run-length restriction is defined as "k", wherein "d" and "k" are positive integers, comprising:

a multiplexer multiplexing an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams with predetermined bits of multiplexing information by applying a predetermined multiplexing method to each pseudo random data stream; and

an encoder RLL-modulates these plural types of pseudo random data streams to generate a modulated code stream in which optimum DC suppression is performed.

14. The apparatus of claim 13, wherein the multiplexer generates the random data stream by discontinuously scrambling the input data stream with the multiplexing information.

15. The apparatus of claim 14, wherein when s_tIs multiplexing information s for multiplexing input data streams divided into v data streams each having a u byte length_tIs less than or equal to the number m of bits of the input source data, where u and v are positive integers.

16. The apparatus of claim 15, wherein the multiplexer includes an exclusive or device, each exclusive or device being provided for every qth code modulation unit of the plurality of types of random data streams, and the multiplexing information s is multiplexed by the first exclusive or device_tAnd performing an exclusive-OR operation on the first m-bit data of the first code modulation unit of the plurality of types of random data streams to generate modulated data, outputting the data from the second code modulation unit to the q-1 th code modulation unit without change without performing the exclusive-OR operation, performing the exclusive-OR operation on the first code modulation unit and the q-th code modulation unit to generate next modulated data, and repeating the exclusive-OR operation of the input data stream from the q-th code modulation unit to the last code modulation unit.

17. The apparatus of claim 16, wherein when the xor operation period is q, where q is a positive integer, the probability of error propagation is reduced to 1/q.

18. The apparatus of claim 13, further comprising:

a divider dividing an input data stream into predetermined lengths;

a sync signal and multiplex ID inserter for inserting a sync pattern into the multiplexed pseudo random data stream to which the multiplex information is added and converting the multiplex information into a multiplex ID; and

and a comparator and a selector that compare the plurality of types of RLL modulated code streams to select a code stream containing the smallest DC component.

19. A data modulation apparatus for modulating m-bit source data into n-bit codewords, wherein n ≧ m, n and m are positive integers, where a minimum run-length restriction is defined as "d" and a maximum run-length restriction is defined as "k", wherein "d" and "k" are positive integers, comprising:

a multiplexer multiplexing an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams with predetermined bits of multiplexing information by applying a predetermined multiplexing method to each pseudo random data stream;

an encoder for performing weak DC-free RLL modulation on the multiplexed data stream without adding a DC control subcode conversion table to which additional bits are added; and

and a selector that selects a code stream containing a minimum DC component among the multiplexed, RLL-modulated code streams.

20. The apparatus of claim 19, wherein the multiplexer generates the random data stream by discontinuously scrambling the input data stream with the multiplexing information.

21. The apparatus of claim 20, wherein when s_tIs multiplexing information s for multiplexing input data streams divided into v data streams each having a u byte length_tIs less than or equal to the input source dataWhere u and v are positive integers.

22. The apparatus as claimed in claim 21, wherein the multiplexer includes an exclusive or device, each exclusive or device being provided for every qth code modulation unit of the plurality of types of random data streams, the multiplexing information s being multiplexed by the first exclusive or device_tAnd performing an exclusive-OR operation on the first m-bit data of the first code modulation unit of the plurality of types of random data streams to generate modulated data, outputting without the exclusive-OR operation from the second code modulation unit to the q-1 th code modulation unit, performing the exclusive-OR operation on the first code modulation unit and the q-th code modulation unit to generate next modulated data, and repeating the exclusive-OR operation from the q-th code modulation unit to the last code modulation unit of the input data stream.

23. The apparatus of claim 22, wherein when the xor operation period is q, where q is a positive integer, the probability of error propagation is reduced to 1/q.

24. The apparatus of claim 19, further comprising:

a divider dividing an input data stream into predetermined lengths; and

and a sync signal and multiplex ID inserter for inserting a sync pattern into the multiplexed data to which the multiplex information is added and converting the multiplex information into a multiplex ID.

25. The apparatus of claim 19, wherein the encoder performs weak DC-free RLL modulation when codewords of the same data in the main code group and the DC-controlled auxiliary code group have opposite INV values for controlling DC, INV being a parameter for predicting a transition direction of a next codeword according to whether a number of bits of a value "1" in the stream of codewords is odd or even.

26. The apparatus of claim 19, wherein the encoder performs the weak DC-free RLL modulation by defining a minimum run-length limit "d" as 1 and a maximum run-length limit "k" as 7.

27. The apparatus of claim 26, wherein the bits of the source data are 8 and the modulated codeword has a length of 12 bits.

28. The apparatus of claim 24, wherein the sync signal and multiplex ID inserter performs the inserting and multiplexing by limiting a minimum run length limit "d" to 1 and a maximum run length limit "k" to 7.

29. The apparatus of claim 24, wherein the encoder defines a minimum run length limit "d" as 1 and a maximum run length limit "k" as 7, and the sync signal and multiplex ID inserter defines the minimum run length limit "d" as 2 and the maximum run length limit "k" as 7 so as to increase the minimum run length limit "d" to increase the minimum mark length such that interference noise of the signal is reduced.

30. The apparatus of claim 24, wherein the encoder performs the weak DC-free RLL modulation by defining a minimum run-length limit "d" as 2 and a maximum run-length limit "k" as 10.

31. The apparatus of claim 30, wherein when the bit length of the source data is 8, the modulated codeword has a bit length of 15.

32. The apparatus of claim 30, wherein the sync signal and multiplex ID inserter performs the inserting and multiplexing by limiting a minimum run length limit "d" to 2 and a maximum run length limit "k" to 10.

33. A data demodulation apparatus comprising:

a decoder for demodulating each of the n-bit input digital data into m-bit demodulation code units, wherein n ≧ m, n and m being positive integers, so as to generate an irreversible data stream having a predetermined length; and

a demultiplexer for discontinuously descrambling the non-inverted data stream with the multiplexing information to generate an inverted data stream.

34. The apparatus of claim 33, wherein the demultiplexer comprises an xor device, each of which is provided for every qth demodulation unit, performs an xor operation on the first demodulation code unit and initial data, which is multiplexing information, to generate first inversion data, outputs from the second demodulation code unit to the qth-1 demodulation code unit without performing the xor operation, performs an xor operation on the first demodulation code unit and a head qth demodulation code unit of the discontinuous qth demodulation code unit to generate next inversion data, and repeats the xor operation until a last one of remaining qth demodulation code units of the non-inverted data stream to provide the inverted data stream.

35. A digital modulation apparatus, comprising:

an encoder for modulating the source data into code words, wherein a minimum run length limit is defined as "d" and a maximum run length limit is defined as "k", "d" and "k" are positive integers,

wherein the encoder changes the codeword a to other codewords such that in case a combination of an ending zero of the codeword a and a leading zero of the codeword b is smaller than the minimum run length limit or larger than the maximum run length limit, the combination of the ending zero of the codeword a and the leading zero of the codeword b is larger than or equal to the minimum run length limit and smaller than or equal to the maximum run length limit, wherein the codeword b is connected to the codeword a, the codeword a is a preceding codeword, the ending zero is the number of consecutive 0's from the least significant bit to the most significant bit of the codeword a, and the leading zero is the number of consecutive 0's from the most significant bit to the least significant bit of the codeword b.

36. The apparatus of claim 35, wherein the minimum run length restriction "d" is 1, the maximum run length restriction "k" is 7, and the encoder changes the codeword a to the codeword having the least significant bit of "0" in case that the ending zero of the codeword a is "0" and the leading zero of the codeword b is "0".