HK1075960B - Driving device and driving method therefor, display apparatus using the same - Google Patents

Description

Driving device, driving method thereof, and display apparatus using the same

Technical Field

The present invention relates to a driving device, a display apparatus using the driving device, and a driving method for the display apparatus, and more particularly, to a driving device for driving a current-driven optical element, a display apparatus using the driving device for driving a simple matrix type display panel having a display element formed of a current-driven optical element, and a driving method for the display apparatus.

Background

In recent years, it has been noted that display devices and devices such as Liquid Crystal Displays (LCDs) have rapidly developed as monitors and displays for personal computers and video devices, instead of Cathode Ray Tubes (CRTs). In particular, liquid crystal displays have rapidly come into widespread use because they can achieve thin and light weight, space saving, reduction in power consumption, and the like, as compared with conventional display devices (CRTs). Further, a relatively small liquid crystal display device has been widely used as a display of a mobile phone, a digital camera, a Personal Digital Assistant (PDA), or the like, which has been commonly used in recent years.

The following are display devices (displays) and display elements that are expected as next generation display devices (displays) conforming to such liquid crystal displays: an organic electroluminescent element (hereinafter, simply referred to as "organic EL element"), an inorganic electroluminescent element (hereinafter, simply referred to as "inorganic EL element"), and a display device having a spontaneous emission type optical element such as a Light Emitting Diode (LED).

Among the above-described display devices having various spontaneous emission type display elements, display devices having display elements formed of organic EL elements composed of organic compounds as light emitting materials have undergone vigorous research and development in recent years toward practical application and commercialization, because technical achievements superior to those obtained in other display elements have been obtained in view of color display, low-voltage driving technology, and the like.

Fig. 13A, 13B, and 13C show a schematic arrangement of an organic EL element, its voltage-current characteristic, and an equivalent circuit of the organic EL element, respectively. The structure, emission principle and emission characteristics of the organic EL element are briefly described below.

As shown in fig. 13A, for example, the organic EL element OEL has the following arrangement: in which an anode (positive electrode) 112 composed of a transparent electrode material such as ITO (indium tin oxide), an organic EL layer 113 composed of a light emitting material such as an organic compound, and a cathode (negative electrode) 114 composed of a metal material and having a reflective characteristic are stacked in this order on one surface of a transparent insulating substrate 11 such as a glass substrate. The organic EL layer 113 is formed, for example, by stacking a hole transport layer 113a composed of a polymer-based hole transport material and an electron transport emission layer 113b composed of a polymer-based electron transport emission material.

In the organic EL element OEL, as shown in fig. 13A, when positive and negative voltages are applied to the anode 112 and the cathode 114, respectively, from the DC voltage source VDC, energy is generated when holes injected into the hole transport layer 113A in the organic EL layer 113 recombine with electrons injected into the electron transport emission layer 113b, and light is emitted on the basis of the energy h ν. For example, the light hv is transmitted through the anode 112 and emitted from the other surface side (upper side in fig. 13A) of the insulating substrate 111. In this case, the emission intensity of the light h ν (i.e., the emission luminance of the organic EL element) is controlled in accordance with the amount of current flowing between the anode 112 and the cathode 114.

In this case, the voltage-current characteristics of the equivalent circuit of the organic EL element OEL exhibit a tendency similar to that of a diode, as shown in fig. 13B, the electrode layers (the anode 112 and the cathode 114) are opposed to each other through the relatively thin dielectric layer (the organic EL layer 113). Therefore, as shown in fig. 13C, the optical element can be expressed as a parallel connection of the diode type light emitting element Ep and the junction capacitance Cp. It should be noted that the voltage-current characteristics of the organic EL element will be described in detail in the following embodiments of the present invention (to be described later).

As a display driving method for a display device having a display panel in which display elements (display pixels) having spontaneous emission type optical elements such as the above-described organic EL elements are arranged in a matrix form, both an active matrix driving scheme and a simple matrix (passive) driving scheme are known. As is well known, in the active matrix driving scheme, a selection switch and a storage capacitor are provided for each display pixel so as to control a driving state (emission state) of each display element according to a charging voltage of a corresponding one of the storage capacitors in the simple matrix driving scheme, the emission state of each display pixel being controlled time-divisionally by directly applying a predetermined pulse to the display element.

Although the active matrix driving scheme is superior to the passive matrix driving scheme in view of the luminance and multi-gray levels of the image display, it is necessary to provide a pixel driving function such as a selection switch (thin film transistor) for each display pixel. This complicates the device arrangement and requires more advanced micro-patterning technology, resulting in increased manufacturing costs. In contrast, in the simple matrix driving scheme, it is not necessary to prepare a pixel driving function such as a selection switch for each display pixel, and thus the device arrangement can be simplified. This can improve manufacturing yield and reduce manufacturing cost.

A schematic arrangement of a display device based on a simple matrix drive scheme will be described below.

Fig. 14 shows an example of a display device based on a simple matrix driving scheme.

As shown in fig. 14, the display device based on the simple matrix driving scheme roughly includes a display panel 110P having a plurality of scanning lines SL extending in a row direction, a plurality of signal lines DL extending in a column direction and intersecting the scanning lines SL perpendicularly, and display elements (organic EL elements) OEL formed in the vicinity of intersections of the scanning lines SL and the signal lines DL, respectively. The device also includes: a scan driver 120P which applies a scan signal to each scan line SL at a predetermined timing to sequentially scan the organic EL elements OEL on each row in a selection state; a data driver 130P which generates a driving current corresponding to display data in synchronization with scanning by the scan driver 120P and supplies the current to each of the organic EL elements OEL through a corresponding one of the signal lines DL; and a controller 140P which generates scan control signals, data control signals, and display data for displaying desired image information on the display panel 110P and supplies them to the scan driver 120P and the data driver 130P.

As driving methods for the display device having the above arrangement, the following two methods are known. One method is a current designation type driving method in which the scan driver 120P sequentially applies a scanning signal for selecting one of the scanning lines SL to the scanning lines SL on each row in every predetermined scanning period on the basis of a scanning control signal supplied from the controller 140P, and the data driver 130P generates a driving current having a predetermined current value corresponding to display data while supplying the driving current through the respective signal lines DL in synchronization with this scanning signal on the basis of a data control signal and display data supplied from the controller 140P. Accordingly, the respective organic EL elements OEL on the selected row emit light at a predetermined luminance level. Another method is a pulse width modulation type driving method in which the data driver 130P generates a driving current formed of a constant current value and having a signal time width (pulse signal width) corresponding to display data, and supplies the current to each signal line DL. Accordingly, the respective organic EL elements OEL on the selected row emit light at a predetermined luminance level. This operation is repeated for each line corresponding to one frame on the display panel, thereby displaying desired image information on the display panel 110P.

In the simple matrix driving scheme, in addition to the above-described current driving scheme, a voltage driving scheme of driving each display element by applying a predetermined voltage from a data driver to the display element is also known. It is assumed that an organic EL element is used as a display element. In this case, since each element has the following arrangement: in which the diode type light emitting element Ep and the junction capacitance Cp are connected in parallel as shown in fig. 14, and each organic EL element OEL is connected in parallel with the signal line DL, the sum of the junction capacitances becomes large, and the interconnection capacitance of each signal line increases. As a result, in the voltage driving scheme, a delay is generated in a driving state of each display element or a voltage drop is generated according to a distance from a data driver, for example, resulting in a change in emission state (brightness) of upper and lower regions of a display panel. This results in a degradation of the display image quality. Therefore, in a display device using an organic EL element as a display element, a current driving scheme is considered to be superior to a voltage driving scheme.

However, the display device based on the above-described simple matrix driving scheme has the following problems.

In the current drive scheme, operating the display elements at a predetermined luminance level by supplying a predetermined drive current to the display elements is equivalent to charging the junction capacitance or the like of a given display element with the drive current and charging the junction capacitances of the remaining unselected display elements on the signal line connected to the given display element. In this case, it is possible to suppress a decrease in response characteristics or a change in emission luminance by supplying a driving current having a large current value as compared with the voltage driving scheme. However, for the sake of explaining the power saving or the power saving, it is assumed that the driving current supplied from the data driver is set to a relatively small current value, or the sum total of the junction capacitances of the display elements increases as the number of scanning lines increases, and the number of display pixels increases as the size and the resolution of the display panel increases. In this case, when a drive current is supplied to the display element at the drive timing, response characteristics with respect to current and voltage values are degraded, and a time required for a voltage applied to the display element to reach a predetermined value is prolonged, resulting in a non-negligible emission luminance shortage and generation of variations.

Fig. 15A shows a change in a supply current with time when a drive current is supplied to a display element. Fig. 15B shows a change in voltage applied to the display element with time. Referring to fig. 15A, the abscissa represents time; and the ordinate indicates the supply current to the display element. Reference Tspy denotes a period of delivery of the drive current; and Tdly denotes a delay time from the start of supplying the driving current to the start of operating the display element. Referring to fig. 15B, the abscissa represents time; the ordinate represents the voltage applied to the display pixel in the forward direction. Reference symbol Vth denotes a threshold voltage for operating the display element. As shown in fig. 15A and 15B, the rising characteristics of the current value and the voltage value supplied to the display element are degraded due to the junction capacitance of the display element and the interconnection capacitance of the signal line. Further, the degree of degradation varies due to variations in junction capacitance between individual display elements, differences in interconnection capacitance between signal lines, and the like. As a result, the amount of charge supplied to the display elements during the drive current supply period drops below the amount required for display at a desired luminance level, which results in insufficient emission luminance or variation in emission luminance between display elements. This causes degradation of the display state.

Disclosure of Invention

According to the present invention, in the driving device that drives a plurality of current-driven optical elements, the response speed of each optical element can be improved, and therefore, even if the driving current to be supplied to each optical element is set to a relatively small current value, each optical element can be driven appropriately.

Further, in a display device to which a driving means is applied and which drives a display panel having a plurality of current-driven display elements, the response speed of each display element is increased in the entire region of the display panel, so that a good display image is obtained in accordance with the display gray scale, and the power consumption associated with the driving current supplied to each display element can be reduced.

In order to achieve the above-described effect, according to the present invention, there is provided a driving device which supplies a current to a plurality of current-driven optical elements to drive the optical elements, the driving device including at least: a drive current supply circuit for supplying a drive current to each of the optical elements for a predetermined period; and a control voltage application circuit that applies at least a charging voltage having a voltage value corresponding to a voltage to be applied to each optical element using the drive current before the drive current is supplied.

The drive current supplied to each optical element has the same current value with respect to each optical element.

The drive current supply circuit includes a single constant current generation circuit that outputs a constant current having the same current value as the drive current, and a plurality of current storage circuits that sequentially receive and hold the constant current and output the drive current on the basis of the constant current. Alternatively, the drive current supply circuit further includes a single input current storage circuit provided between the constant current generation circuit and the plurality of current storage circuits, the single input current storage circuit receiving the constant current output from the constant current generation circuit, holding a voltage component corresponding to a current value of the constant current, and supplying the current to the plurality of current storage circuits on the basis of the voltage component.

The input current storage circuit and each current storage circuit include a capacitance element that receives the constant current output from the constant current generation circuit and in which charges of a current value corresponding to the constant current are written as voltage components.

The control voltage applying circuit further includes means for applying a discharge voltage having a voltage value for causing each optical element to perform a discharge operation after the drive current is supplied to each optical element.

The driving apparatus further includes a pulse width control circuit that controls a pulse width of the driving current applied to each optical element according to a luminance level fraction of the display signal.

In order to obtain the above-described effects, according to the present invention, there is provided a display device which displays an image by supplying a drive current corresponding to a display signal to each of a plurality of current-driven display elements of a display panel, the display device comprising: a display panel including a plurality of signal lines and a plurality of scan lines that intersect perpendicularly and a plurality of display elements disposed near intersections of the signal lines and the scan lines; a scan control circuit which sequentially scans the scan lines to sequentially set the display elements connected to the scan lines in a selected state; and a signal control circuit including at least a drive current supply circuit supplying a drive current to each signal line for a predetermined period and a control voltage application circuit applying a charging voltage having a voltage value to each signal line on the basis of a voltage applied to each display element by application of the drive current before the drive current is supplied. The display element includes an optical element such as an organic electroluminescence element having an anode connected to a signal line and an anode connected to a scan line.

The charging voltage has at least a voltage value higher than a threshold voltage of each display element of the display panel and lower than a maximum value of voltage values applied to each display element when the driving current is applied to each display element through each signal line. Alternatively, the voltage value of the charging voltage is equal to an average value of voltage values applied to the respective display elements when the driving current is supplied to the respective display elements through the respective signal lines.

The driving current applied to each signal line of the display panel has the same current value for each signal line.

The signal control circuit includes at least a control unit that supplies a drive current through the drive current supply circuit and applies a charging voltage through the control voltage application circuit in accordance with a timing at which the scan control circuit sets the display element in a selected state.

The drive current supply circuit in the signal control circuit includes a single constant current generation circuit that supplies a constant current having a predetermined current value and a plurality of current storage circuits that are provided in accordance with a plurality of signal lines, sequentially receive and hold the constant current, and simultaneously output the drive current to the plurality of signal lines on the basis of the constant current. Alternatively, the drive current supply circuit further includes a single input current storage circuit that is provided between the constant current generation circuit and the plurality of current storage circuits, receives the constant current output from the constant current generation circuit, holds a voltage component corresponding to a current value of the constant current, and supplies the current to the plurality of current storage circuits on the basis of the voltage component.

The current storage circuit and the input current storage circuit each include a capacitance element that receives the constant current output from the constant current generation circuit and writes therein electric charges corresponding to the constant current as a voltage component.

The control voltage applying circuit in the signal control circuit further comprises means for applying a discharge voltage to each signal line after the drive current is applied to each signal line, the discharge voltage causing each display line to display

The display element performs a discharge operation and does not exceed a threshold voltage of the display element.

The signal control circuit includes a pulse width control circuit that controls a pulse width of the drive current to each signal line in accordance with a luminance level fraction of the display signal.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.

Fig. 1 is a block diagram showing an example of the entire arrangement of a driving device and a display apparatus using the driving device;

fig. 2 is a schematic circuit diagram showing the arrangement of a part of a display device suitable for the present invention;

fig. 3 is a circuit diagram showing the arrangement of a part of a data driver applicable to the driving apparatus according to the present invention;

FIG. 4 is a timing diagram showing control operations in a scan driver and a data driver applicable to the present invention;

fig. 5 illustrates a graph of voltage-current characteristics representing a relationship between voltages applied by a scan driver and a data driver applicable to the present invention;

fig. 6 is a timing chart showing a display driving operation of a display device applicable to the present invention;

fig. 7 is a schematic block diagram showing a first embodiment of a constant current feeding circuit applicable to the driving device according to the present invention;

fig. 8 is a circuit diagram showing a specific example of a current generation circuit applicable to the constant current feeding circuit according to the present invention;

fig. 9 is a circuit diagram showing a specific example of an arrangement constituted by a current storage circuit and a switching device applicable to the constant current feeding circuit according to the present invention;

fig. 10A and 10B are current diagrams showing basic operations in a current storage circuit applicable to the constant current feeding circuit according to the present invention;

fig. 11 is a schematic block diagram showing a second embodiment of a constant current supply circuit applicable to the driving device according to the present invention;

fig. 12 is a schematic block diagram showing a third embodiment of a constant current supply circuit applicable to the drive device according to the present invention;

fig. 13A is a sectional view showing a schematic arrangement of an organic EL element;

fig. 13B is a graph showing approximate voltage-current characteristics of the organic EL element;

fig. 13C is an equivalent circuit diagram showing an organic EL element;

fig. 14 is a schematic diagram showing an example of a display device based on a simple matrix driving scheme;

fig. 15A is a graph showing a change with time of a supply current when a drive current is supplied to an organic EL element; and

fig. 15B is a graph showing a change with time of a voltage applied to the display element when a driving current is applied to the organic EL element.

Detailed Description

Embodiments of a driving device, a display apparatus using the driving device, and a driving method for a display apparatus according to the present invention will be described in detail below.

< arrangement of display apparatus >

A driving device and a display apparatus using the same according to the present invention will be described first with reference to the accompanying drawings.

Fig. 1 is a block diagram showing an example of the overall arrangement of a driving device according to the present invention and a display apparatus which can use the driving device. Fig. 2 is a schematic circuit diagram showing the arrangement of the main part of a display device applicable to the present invention.

In the following description, the organic EL element OEL is used as a display element of the display panel. However, the display apparatus according to the present invention is not limited thereto. The present invention is also applicable to a case where an optical element such as a Light Emitting Diode (LED) is used as a display element instead of the organic EL element.

As shown in fig. 1 and 2, a display device 100 applicable to the present invention is constituted by a display panel (display array) 110, a scan driver (scan control circuit) 120, a data driver (signal control circuit) 130, a system controller 140, and a display signal generation circuit 150. In the display panel 110, display elements including, for example, organic EL elements OEL are formed in the vicinity of intersections of a plurality of scanning lines SL and a plurality of signal lines DL provided in the vertical direction. The scan driver 120 is connected to the scan lines SL of the display panel 110 and controls the display elements of each row in a selected state by applying a scan signal Vs to each scan line SL at a predetermined timing. The data driver 130 is connected to the signal lines DL of the display panel 110, supplies a constant current (drive current) Ic having a signal time width (pulse width) corresponding to display data in synchronization with the application timing of the scan signal Vs, and applies a set voltage Vset (charging voltage) or a reset voltage Vreset (discharging voltage) at a predetermined timing. The system controller 140 generates and outputs at least a scan control signal and a data control signal for controlling the operation states of the scan driver 120 and the data driver 130 on the basis of the timing signal supplied from the display signal generation circuit 150. The display signal generation circuit 150 supplies the above-described display data to the data driver 130 on the basis of a video signal supplied from the outside of the display device 100, generates a timing signal (system clock or the like) for operating each organic EL element in a predetermined driving state on the basis of the display data, and supplies the timing signal to the system controller 140.

The arrangement of each unit described above will be described below.

(display panel)

As shown in fig. 2, the display panel 110 applicable to the present invention has n scan lines SL and m signal lines DL perpendicularly intersecting each other. The display panel 110 has a simple matrix arrangement in which organic EL elements OEL each having a cross-sectional structure shown in fig. 13A are formed at intersections of respective signal lines DL and respective scanning lines SL, and anodes (positive electrodes) and cathodes (negative electrodes) of the elements are connected to the signal lines DL and the scanning lines SL, respectively. In this case, each organic EL element OEL has the following arrangement: in which the diode type display element Ep and the junction capacitance Ca are connected in parallel as shown in fig. 14.

(Scan driver)

The scan driver 120 sets the display elements of each row in a selected state by sequentially applying a scan signal Vs (═ Vs1) to each scan line SL on the basis of a scan control signal supplied from the system controller 140, thereby performing control so that the constant drive current Ic supplied from the data driver 130 is written through the signal line DL and a predetermined reset voltage Vreset is applied.

As shown in fig. 2, the scan driver 120 is composed of a shift register 121, switches SWL1, SWL 2.., SWLn (which may also be referred to as "switch SWL" herein for convenience), a high voltage power supply, and a low voltage power supply. The shift register 121 sequentially outputs shift output signals RS1, RS2,. RSn (which may also be referred to as "shift output signals RS" hereinafter for convenience) on the basis of scan control signals (shift start signals, shift clocks, etc.) supplied from the system controller 140. Switches SWL1, SWL2,. cndot.swln are provided for the respective scan lines SL, and the contacts of the switches are switched on the basis of the shift output signals RS1, RS2,. cndot.rsn. The high-voltage power supply supplies a signal voltage Vsh (charge control voltage) of a predetermined high voltage (high level) to one of the switch contacts of each of the switches SWL1, SWL 2. The low-voltage power supply commonly applies a signal voltage Vs1 (drive control voltage) of a predetermined low voltage (low level) to the other switch contact of each of the switches SWL1, SWL 2. When shift output signals R21, RS2,. cnsn, which are simultaneously shifted from the upper side to the lower side of the display panel 110 in sequence, are generated by the shift register 121 and input to the switches SWL1, SWL2,. cnln, the switch contacts are sequentially switched to the low-voltage power supply side. As a result, the scan signal Vs having the low-level signal voltage Vs1 is applied to the anodes of the organic EL elements OEL on the selected row only for a predetermined period (a period of the supply of the drive current Ic and a period of time of the reset voltage Vreset in one scan period). It should be noted that when the shift output signals R21, RS2,. · RSn (unselected rows) are not input from the shift register 121 to the switches SWL1, SWL2,. and.. SWLn, the switch contacts of the switches SWL1, SWL2,. SWLn are switched to the power supply side, and the scan signal Vs having the high-level signal voltage Vsh is applied. Each switch SWL is a switching element formed of, for example, a field effect transistor.

Fig. 3 is a circuit diagram showing the arrangement of the main part of a data driver applicable to the driving apparatus according to the present invention.

The transfer driver 130 receives and holds the display data transferred from the display signal generation circuit 150 in sequence, line by line, within a predetermined timing on the basis of various data control signals (output excitation signal, output control signal, shift start signal shift clock, etc.) transferred from the system controller 140. The data driver 130 converts each display data into a current component of a constant value having a signal time width (pulse width) corresponding to a luminance level of the display data, and supplies the data to each signal line DL at a predetermined timing within a scanning period set for each of the above-mentioned scanning lines.

As shown in fig. 2, the data driver 130 is constituted by a control unit 131, switches SWC1, SWC2,. SWCm (hereinafter may also be referred to as "switch SWC" for convenience), a control voltage applying circuit 132, and a constant current supplying circuit 133 (driving current supplying circuit). The control unit 131 outputs the control signals CS1, CS2,. CSm according to a timing in which the scan driver 120 sets the display elements of each row in the selected state by applying the scan signal Vs to each scan line SL on the basis of the data control signal (output control signal or the like) supplied from the system controller 140. The switches SWC1, SWC2,. cndot.swcm are provided for the respective signal lines DL, and the contacts of the switches are switched on the basis of control signals CS1, CS2,. cndot.csm supplied from the control unit 131. The control voltage applying circuit 132 commonly applies a set voltage Vset (charging voltage) of a predetermined high voltage (high level) to the first switch contacts of the switches SWC1, SWC2,. SWCm, and commonly applies a reset voltage Vreset (discharging voltage) of a predetermined low voltage (low level) to the third switch contacts of the switches SWC1, SWC2,. SWCm. The set voltage Vset is set to a value corresponding to a potential to be applied to the display elements by supplying the constant driving current Ic, wherein the value is at least equal to or greater than a threshold voltage of the display elements and does not exceed a maximum voltage applied to each display element when the driving current Ic is supplied. More preferably, the set voltage Vset is set to an average voltage of the maximum voltage and the minimum voltage on the signal line DL when the driving current Ic is supplied. The reset voltage Vreset is set to a value capable of temporarily discharging and resetting the charges of the signal line DL, for example, to a ground potential (0V). More preferably, the reset voltage Vreset is set to be slightly lower than the threshold voltage of the display element. Each of the constant current supply circuits 133 supplies the drive current Ic having a constant current value and a signal time width (pulse width) to the second switch contact of a corresponding one of the switches SWC1, SWC 2. A constant current supplying circuit applicable to the data driver according to the present invention will be described in detail later.

Fig. 3 is a circuit diagram of an example of the arrangement of the switch SWC applicable to the data driver 130. For example, as shown in fig. 3, each of the switches SWC1, SWC2,. SWCm provided for the respective signal lines DL of the data driver 130 may have an arrangement including the following units: the switching element (hereinafter referred to as "NMOS transistor") Trl1, the NMOS transistor Trl2, and the switching element (hereinafter referred to as "PMOS transistor") NMOS transistor Trl1 are formed of an n-channel field effect transistor and have a source terminal connected to the high-voltage power application circuit 132 for applying the constant setting voltage Vset, a drain terminal connected to the signal line D1, and a gate terminal to which the control signal Vgs is applied at the first timing. The NMOS transistor Trl2 has a source terminal connected to the constant current supplying circuit 133 for applying the constant driving current Ic, a drain terminal connected to the signal line D1, and a gate terminal to which the control signal Vgc is applied at the second timing. The PMOS transistor Trl3 is formed of a p-channel field effect transistor and has a source terminal connected to the low-voltage power application circuit 134 for applying the constant reset voltage Vreset, a drain terminal connected to the signal line D1, and a gate terminal to which the control signal Vgr is applied at the third timing.

That is, the switches SWC1, SWC 2. In which NMOS transistors Trl1 and Trl2 and a PMOS transistor Trl3 are connected in parallel with the single signal line DL. The switches SWC1, SWC 2.. SWCm are selectively turned on at different timings so as to supply a predetermined voltage or current to the signal line DL.

The control signals Vgs, Vgc, and Vgr applied to the gate terminals of the NMOS transistors Trl1 and Trl2 and the PMOS transistor Trl3 are generated on the basis of the data control signal supplied from the system controller 140 and the display data supplied from the display signal generation circuit 150, and are selectively applied to the respective transistors at predetermined timings within a scan period set for each row (scan line). The operation of these switches SWC1, SWC 2.. SWCm and the voltage and current components supplied to the signal line DL will be described in detail later.

Referring to fig. 3, the resistance elements Rpa, Rp, and Rpb formed in series with the signal line D1 equivalently represent the interconnection resistance of the signal line DL, and the capacitance components Cpa and Cpb formed at both ends of the signal line DL are interconnection capacitances (parasitic capacitances) parasitic on the signal line DL.

(System controller)

The system controller 140 generates and outputs a scan control signal and a data control signal to the scan driver 120 and the data driver 130 for controlling their operation states to cause the respective drivers to operate at predetermined timings so as to generate and output the scan signal Vs, the driving current Ic, the set voltage Vset, and the reset voltage Vreset. The system controller 140 then supplies the scan signal Vs to the cathode of each organic EL element, and supplies the drive current Ic, the set voltage Vset, and the reset voltage Vreset to the anode of each organic EL element, thereby causing each organic EL element to operate at a predetermined luminance level to display image information on the display panel 110 on the basis of a predetermined video signal.

(display Signal generating Circuit)

The display signal generation circuit 150 extracts a luminance level signal component from a video signal supplied from, for example, the outside of the display device, and supplies the signal component as display data to the data driver 130 for each row of the display panel 110. If the above-mentioned video signal contains a timing signal component for determining the display timing of the image information, such as a TV broadcast signal (composite video signal), the display signal generation circuit 150 (fig. 1) may have a function of extracting the timing signal component and supplying it to the system controller 140 and a function of extracting the above-mentioned luminance level signal component. In this case, the system controller 140 described above generates the scan control signal and the data control signal to be supplied to the scan driver 120 and the data driver 130, respectively, on the basis of the timing signal supplied from the display signal generation circuit 150.

< Driving method for Driving device >

The operations of the scan driver and the data driver and the voltages and currents supplied to the scan lines and the signal lines will be described in detail later with reference to the accompanying drawings.

Fig. 4 is a timing chart showing a control operation (driving method) of a scan driver and a data driver applicable to the present invention. Fig. 5 is a graph showing a voltage-current characteristic showing a relationship between voltages applied from a scan driver and a data driver applicable to the present invention. Fig. 6 is a timing chart showing a display driving operation of a display device applicable to the present invention.

In the control operation of the scan driver and the data driver according to the present invention, as shown in fig. 4, a set period Tset in which the above-described set voltage Vset (charging voltage) is applied to each signal line D1, a constant current supply period Tc in which the drive current Ic is supplied to each signal line D1, and a reset period Treset in which the reset voltage Vreset (discharging voltage) is applied to each signal line DL are sequentially set in a scan period Tsel (selection period) set at different timings for each scan line. It should be noted that fig. 4 shows a case where display elements on a specific row (scanning line) are driven.

(setting period)

In the reset period Tset, as shown in fig. 4, in the start timing of the scanning period set for a specific row, the high-level set control signal Vgs is applied to the gate terminal of the NMOS transistor Trl1 provided in the data driver 130 to turn on the transistor, and the reset high-level control signal Vgr is applied to the gate terminal of the PMOS transistor to turn on the transistor. At this time, the low-level current transfer control signal Vgc is applied to the gate terminal of the NMOS transistor Tr12, and is turned off. As a result, the set voltage Vset having a predetermined high voltage (for example, 12V) is applied to the signal line DL via the NMOS transistor Trl1, and is applied to the anode of the organic EL element via the signal line DL (signal line voltage Vd1 ═ Vset).

The set voltage Vset is set to a value corresponding to the potential (Vc) to be applied to the display element by supplying the constant drive current Ic to the signal line DL during a constant current supply period TC (to be described later). That is, as shown in fig. 5, when the driving current Ic is applied to the signal line DL, a voltage drop Vdrop is generated according to the interconnection length from the data driver 130 serving as a power supply to the organic EL element OEL. Accordingly, the maximum voltage Vmax is applied to the side closest to the data driver 130, and the minimum voltage Vmin is applied to the side farthest from the data driver 130. As described later, in order to set the organic EL elements OEL connected to all the scanning lines SL in a non-emission state, it is sufficient if the set voltage Vset is set to be at least equal to or greater than the threshold voltage (on voltage) of the organic EL elements OEL and not more than the maximum voltage Vmax applied to each display element when the drive current Ic is supplied. More preferably, in order to improve the uniformity of the effect obtained in the entire display panel by applying the set voltage Vset, the set voltage Vset is set to a voltage capable of supplying the driving current Ic having a constant current value, that is, an average voltage of the maximum voltage Vmax and the minimum voltage Vmin on the signal line DL, to the organic EL elements OEL in the central region of the display panel 110.

Further, in the set period Tset, the switch SWL provided in the scan driver 120 is connected to the switch contact on the high voltage power supply side, whereby the high-level scan signal Vs (═ Vsh) is applied to the scan signal line S1 (the cathode of the organic EL element). In this case, the high-level scan line Vs (═ Vsh) is applied from the scan driver 120 to the scan lines SL of the remaining rows in the unselected state and the above-described specific row.

In the set period Tset, the high-level scan signal Vs (═ Vsh) applied to the scan lines SL of all the rows is set to a voltage (for example, 9V) such that the organic EL elements OEL connected to all the scan lines SL do not emit light even if the above-described maximum voltage (Vmax) is applied to the signal line D1 as the set voltage Vset. More preferably, as shown in FIG. 5 and the following given inequality (1), the scanning signal Vs is set to a voltage higher than a voltage (Vmax-Vturn-on) obtained by subtracting the turn-on voltage Vturn-on of the organic EL element OEL from the maximum voltage value (≈ Vmax) applied to the signal line DL.

Vs(＝Vsh)>Vmax-Vtrun-on ...(1)

In this case, the set voltage Vset and the scan signal Vs (═ Vsh) having a relationship expressed by inequality (1) are respectively applied to the anode and cathode of each organic EL element OEL connected to each row of the scan line, thereby generating a potential difference between the anode and the cathode. In the present invention, this potential difference does not generate a current flowing in any organic EL element.

Therefore, since each voltage is applied in the set period Tset, the junction capacitance added to the signal line and the junction capacitance of each organic EL element are quickly charged to a predetermined voltage (═ Vset) before the drive current Ic (to be described later) is supplied (constant current supply period TC), and each organic EL element is kept in a non-emission state.

(constant Current supply period)

In the constant current transmission period TC, as shown in fig. 4, after the low-level set control signal Vgs is applied to the gate terminal of the NMOS transistor Trl1 provided in the data driver 130 to turn off the transistor, the high-level current transmission control signal Vgc is applied to the gate terminal of the NMOS transistor Trl2 to turn on the transistor. At this time, the high-level reset control signal Vgr is applied to the gate terminal of the PMOS transistor Trl3 to keep it turned off. As a result, the drive current Ic having a constant current value is generated by the constant current supply circuit 133 and supplied to the signal line DL (anode of the organic EL element) via the NMOS transistor Trl2 (organic EL element supply current Iel ═ Ic).

In this case, the driving current Ic supplied from the data driver 130 to the organic EL element OEL via the signal line DL is set to be supplied with a predetermined signal time width (pulse width) corresponding to the luminance level on the basis of the display data supplied from the display signal generating circuit. The voltage Vc (for example, 12V) applied to the signal line DL by supplying the drive current in the constant current supply period Tc is set equal to the set voltage Vset applied to the signal line DL in the set period Tset (the signal line voltage Vd1 ═ Vc ═ Vset).

In the constant current supply period Tc, the switch SWL provided in the scan driver 120 is connected to a switch contact on the low voltage power supply side, and a low-level scan signal Vs (═ Vs1) is applied to the scan line SL (cathode of the organic EL element). In this case, the high-level scan signal Vs (═ Vsh) remains applied to the scan lines SL of the remaining rows in the non-rotated state. The low-level scanning signal Vs (═ Vs1) is set to, for example, the ground potential (0V).

Since the respective currents and voltages are applied in the constant current supply period Tc, the predetermined drive current Ic required for light emission is supplied to each organic EL element connected to the selected scanning line with a predetermined signal time width (for a short time period when the gray scale is low, or vice versa) corresponding to display data on the basis of a known pulse width modulation (PWM drive) control method. As a result, each organic EL element emits light at a predetermined luminance level. In this case, since the interconnection capacitance added to the signal line DL and the junction capacitance of each organic EL element have been charged to the set voltage Vset (═ Vc) by the constant voltage source (power supply for applying the set voltage Vsetde) during the set period Tset, the drive current increases to a current value required for light emission in a short time after the drive current Ic is supplied, and each organic EL element rapidly emits light.

(reset period)

In the reset period Treset, as shown in fig. 4, after the low-level current-supply control signal Vgc is applied to the gate terminal of the NMOS transistor Trl2 provided in the data driver 130 to turn off the transistor, the low-level reset control signal Vgr is applied to the gate terminal of the PMOS transistor Trl3 to turn on the transistor. At this time, the low-level set control signal Vgs is applied to the gate terminal of the NMOS transistor Trl1 to keep it off. As a result, a reset voltage Vreset having a predetermined low voltage (e.g., 6V) is applied to the signal line DL (the anode of the organic EL element) via the PMOS transistor Trl3, and charges stored in the interconnection capacitance added to the signal line DL and the element capacitance of the organic EL element are discharged (the signal line voltage Vd1 — Vreset).

The reset voltage Vreset is set to a potential at which a potential of a high voltage (Vset ═ Vc) applied to the signal line DL can be temporarily discharged and reset during the set period Tset and the constant current transmission period Tc described above, and is set to a ground potential (0V), for example. More preferably, as shown in fig. 5, the reset voltage Vreset is set to be slightly lower than the on voltage Vturn-on of the organic EL element (Vreset < Vturn-on). With this arrangement, when one row is repeatedly scanned and then selected, the time required for the charging operation in the setting period Tset is shortened, and the power consumption of the charging/discharging operation is reduced as compared with the case where the reset voltage Vreset is set to the ground potential (0V).

In this way, the above-described series of operation periods are set within the scanning period for each scanning line constituting the display panel, as shown in fig. 6, thereby performing gray scale display of predetermined image information on the display panel on the basis of the display data.

As described above, in the display device according to the present embodiment, in the scanning period before the drive current Ic is supplied, the set voltage Vset is applied from the constant voltage source to the signal line DL to charge the interconnection capacitance added to the signal line DL and the junction capacitance of the organic EL element in advance. This makes it possible to perform the charge/discharge operation quickly in a short time, as compared with the case where only the constant current source is used to charge the capacitor. In this case, the device can resist the influence of a voltage drop due to the interconnection length of the signal lines DL, etc., and can be charged to the substantially uniform set voltage Vset regardless of the arrangement position of the scan lines SLDE in the display panel 110.

In this case, the set voltage Vset is close to the voltage Vc set to supply the drive current Ic to the organic EL element. Therefore, even if the set period Tset is shifted to the constant current supply period Tc to supply the constant drive current Ic, the adjustment amount of the signal line voltage Vd1 can be reduced. This makes it possible to shorten the time required for this adjustment and improve the response display characteristics.

Further, due to the rapid charging operation in the set period Tset, a relatively long operation time (constant current supply period Tc) can be ensured within the scanning period. Therefore, even if the operation time (signal time width) of each organic EL element is controlled using the pulse width modulation control scheme, good gray scale display can be achieved.

In the set period Tset, the potentials of all the scanning lines SL are set to the voltage Vsh having the predetermined high level. Therefore, even if the set voltage Vset is applied to the signal line DL, no current flows in any of the organic EL elements. This shortens the time required for the precharge (charge) operation to the set voltage Vset, thereby improving the response characteristic.

Further, in the constant current source supply period Tc, supplying the drive current Ic having a constant current value from the constant current source can compensate for the voltage drop at the signal line DL so as to secure the predetermined voltage Vc. This makes it possible to appropriately accommodate the change in the voltage applied to the organic EL element OEL with time variation and supply the constant current (drive current) Ic to the organic EL element OEL on the basis of the substantially uniform voltage Vc, thereby achieving high display image quality without changing the luminance level.

In this case, since the pulse width modulation control scheme of supplying the drive current Ic having a constant current value in a time signal width (pulse width) corresponding to the luminance level component contained in the display data is used for each organic EL element OEL, it is sufficient if the drive current Ic to be supplied to each organic EL element during the constant current supply period Tc has a constant current value. Further, since it is not necessary to change/control the voltage value of the set voltage Vset, a simple circuit arrangement can be used as the constant current source and the constant voltage source for supplying the above-described current and voltage.

In the reset period after the constant current supplying period Tc, the voltage value of the reset voltage Vreset applied to the signal line DL is not necessarily set to the ground potential (0V), but may be set to an arbitrary voltage equal to or smaller than the on voltage Vturn-on of the organic EL element OEL. Therefore, the amount of charge to be charged/discharged to/from the interconnection capacitance or the junction capacitance of the organic EL element OEL can be reduced by the potential difference (Vreset < Vturn-on). This can reduce power consumption.

In the reset period Treset, instead of resetting all the scan lines SL including the unselected scan lines, the reset voltage Vreset is applied to the signal lines DL every time the constant-current transfer period Tc (reset period) ends. This eliminates the need for the charge/discharge operation of the junction capacitance of the organic EL element OEL, thereby reducing power consumption.

(first embodiment of constant Current feeding Circuit)

A first embodiment of a constant current supply circuit for outputting a driving current having a constant current value in a data driver is described in detail below with reference to the accompanying drawings.

FIG. 7 is a diagram showing constant current supply applicable to the data driver according to the above embodiment

A schematic block diagram of a first embodiment of a circuit.

As shown in fig. 7, the constant current supply circuit 133 includes a single constant current generation circuit 10A, a shift register 20A, a plurality of switching devices 40A, a plurality of current storage circuits 30A, and a PWM control circuit 80. The constant current generating circuit 10A generates the driving current Ic for operating the plurality of loads (organic EL elements OEL). The shift register 20A sets the timing at which the constant current Ip supplied from the constant current generating circuit 10A is sequentially supplied to the current storage circuit 30A. The plurality of switching devices 40A control the transfer state of the constant current Ip to each current storage circuit 30A in accordance with the switching signal (shift output) SR output from the shift register 20A at a predetermined timing. The plurality of current storage circuits 30A sequentially receive and hold (store) the constant current Ip supplied from the constant current generating circuit 10A via the switching device 40A within a predetermined timing on the basis of the shift register 20A. The PWM control circuit 80 is connected to the output terminal Tout, receives display data, and sets the time width (pulse width) of a signal to be supplied by PWM control on the basis of a luminance level component contained in the display data.

Further, "SWC" in fig. 7 corresponds to the switch SWC in fig. 2, and is a three-contact switch provided among the output terminal of the PWM control circuit 80, the set voltage Vset, the reset voltage Vreset, and the signal line DL connected to the plurality of organic EL elements OEL.

The arrangement of each of the above units is described in detail below.

(Current generating Circuit)

Fig. 8 is a circuit diagram showing the arrangement of a specific example of a current generation circuit applicable to the above-described constant current feeding circuit or circuit 10A.

Briefly, the constant current generating circuit 10A is designed to generate a constant current Ip having a current value required to operate each organic EL element in a predetermined emission state and output the current to each current storage circuit 30A provided in correspondence with a corresponding one of the organic EL elements.

In this case, the constant current generating circuit 10A may have a circuit arrangement including the control current generating circuit 11 on the front stage and the output current generating circuit 12 on the rear stage, for example, as shown in fig. 8. It should be noted that the current generation circuit described in the present embodiment is only one example applicable to the driving device according to the present invention, and is not limited to such a circuit arrangement. As the constant current generating circuit 10A, the present embodiment is represented by an arrangement having a control current generating circuit 11 and an output current generating circuit 12. However, the present invention is not limited thereto. For example, a circuit having a circuit arrangement formed only by the control current generating circuit 11 may also be used.

For example, as shown in fig. 8, the control current generation circuit 11 has a circuit arrangement including a pnp bipolar transistor (which will be hereinafter simply referred to as "pnp transistor") Q11 and an NMOS transistor M11. The pnp transistor has an emitter connected to the other end of the resistor R11 and a collector connected to the subsequent-stage current mirror circuit unit 12 (output node N11), wherein one end of the resistor R11 is connected to a high potential power supply Vdd. The NMOS transistor M11 has a source connected to the base of the pnp transistor Q11, a drain connected to the SET terminal Tset to which the SET signal SET is to be input, and a gate connected to the input terminal Tin to which a predetermined control signal IN is to be input.

For example, as shown in fig. 8, the output current generation circuit 12 has a circuit arrangement including an npn bipolar transistor (hereinafter simply referred to as an "npn transistor") Q12, a resistor R12, an npn transistor Q13, and a resistor R13. The npn transistor Q12 is formed of a current mirror circuit and has a collector and a base connected to the output node N11 of the control current generation circuit 11. The resistor R12 is connected between the emitter of the npn transistor Q12 and the low potential power supply Vss. The npn transistor Q13 has a collector connected to an output terminal Tcs that outputs an output current (constant current Ip) having a predetermined current component, and a base connected to an output node N1 of the control current generating circuit 11. The resistor R13 is connected between the emitter of the npn transistor Q13 and the low potential power supply Vss.

In this case, the output current (constant current Ip) has a current value corresponding to a predetermined current ratio defined by the current mirror circuit arrangement with respect to the current value of the control current generated by the control current generating circuit 11 and input via the output node N11. In the present embodiment, when the output current of the negative electrode is supplied to the current storage circuit 30A, a current component flows from the current storage circuit 30A to the constant current generating circuit 10A.

(Shift register/switching device)

The shift register 20A sequentially applies shift outputs as sequential outputs of the switching signals SR to the respective switching devices 40A provided corresponding to the respective signal lines DL on the basis of, for example, control signals supplied from a control unit such as the system controller 140 shown in fig. 1. The switching devices 40A are turned on at different timings on the basis of the switching signal SR output from the shift register 20A, thereby supplying the constant current Ic from the constant current generating circuit 10A to the current storage circuit 30A to control them to receive and hold the current.

(Current storage Circuit)

Fig. 9 is a circuit diagram showing an example of an arrangement including a current storage circuit and a switching device applicable to the above-described constant current feeding circuit. Fig. 10A and 10B are conceptual diagrams showing the basic operation of a current storage circuit applicable to the above-described constant current delivery circuit.

The current storage circuit 30A is designed to sequentially receive and hold the constant current 10A output from the constant current generating circuit 10A on the basis of the shift output from the shift register 20A, and simultaneously output the held current component or a predetermined current generated on the basis of the current component directly to each signal line DL via the output terminal Tout as the drive current Ic.

In this case, the current storage circuit 30A may have a voltage component holding unit 31 (including the switching device 40A) included on the front stage and a driving current generating unit 32 on the rear stage, for example, as shown in fig. 9. It should be noted that the current storage circuit described in the present embodiment is only an example of a driving device applicable to the present invention, and is not limited to such a circuit arrangement. As the current storage circuit 30A, the present embodiment is represented by an arrangement having a voltage component holding unit 31 and a drive current generating unit 32. However, the present invention is not limited thereto. For example, a circuit having a circuit arrangement formed only by the voltage component holding unit 31 may also be used.

For example, as shown in fig. 9, the voltage component holding unit 31 has an arrangement including PMOS transistors M31, M32, and M33, a storage capacitor C31, and a PMOS transistor M34. The PMOS transistor M31 has a source and a drain connected to the node N31 and the output terminal Tcs of the constant current generating circuit 10A, respectively, and a gate connected to the shift output terminal Tsr of the shift register. The PMOS transistor M32 has a source and a drain connected to the high potential power supply Vdd and the node N32, respectively, and a gate connected to the node N31. The PMOS transistor M33 has a source and a drain connected to the node N32 and the output terminal Tcs of the constant current generating circuit 10A, respectively, and a gate connected to the shift output terminal Tsr of the shift register 20A. The storage capacitor C31 is connected between the high potential power supply Vdd and the node N31. The PMOS transistor M34 has a source and a drain connected to the node N32 and the output node N33 of the rear stage driving current generating unit 32, respectively, and a gate connected to an output control terminal Ten to which an output enable signal EN, which is an output state of a control current supplied from a control unit such as the system controller 140 shown in fig. 1 and controlling the rear stage driving current generating unit 32, is input. In this case, the PMOS transistors M31 and M33 that are turned on/off on the basis of the switching signal (shift output) SR from the shift register 20A constitute the above-described switching device 40A. The storage capacitor C31 provided between the high potential power supply Vdd and the node N31 may be a parasitic capacitor formed between the gate and the source of the PMOS transistor M32.

For example, as shown in fig. 9, the drive current generation unit 32 includes a current mirror circuit and has an arrangement including npn transistors Q31, Q32, and Q33, and resistors R31 and R32. npn transistors Q31 and Q32 have collectors and bases connected to the output node N33 of the above-described voltage component holding unit 31, and emitters connected to a node N34.

The resistor R31 is connected between the node N34 and the low potential power source Vss. npn transistor Q33 has a collector connected to high potential power supply Vdd and a base connected to output node N33 of voltage component holding unit 31 described above. The resistor R32 is connected between the emitter of the npn transistor Q33 and the output terminal Tout that outputs an output current (drive current Ic).

In this case, the output current (drive current Ic) has a current value corresponding to a predetermined current ratio defined by the current mirror circuit arrangement with respect to the current value of the control current output from the voltage holding unit 31 and input via the output node N33.

It should be noted that, instead of using the resistors R31 and R32 that define the current ratio in the circuit arrangement of the current mirror circuit 32, the above current ratio can be defined by changing the area ratio between npn transistors Q31-Q33. In this case, it is possible to suppress a change in the output current by suppressing a change in the current component inside the circuit due to a change in the resistance values of the resistors R31 and R32.

In the basic operation of the current storage circuit (including the switching device) having the above-described arrangement, the current holding operation and the current feeding operation are performed at predetermined timings in the operation cycle (scanning period) of the organic EL element so as not to overlap temporarily. The current holding operation and the current feeding operation will be described in detail below.

(Current conservation operation)

In the current holding operation, first, by applying a high-level output enable signal EN from the control unit (system controller 140) via the output control terminal Ten, the PMOS transistor M34 serving as an output control means is turned off. In this state, by supplying a current Ip having a current component of negative polarity from the constant current generating circuit 10A through the input terminal Tcs (the output terminal Tcs of the constant current generating circuit 10A) at a predetermined timing and applying a low-level switching signal SR to the transistors from the shift register 20A through the shift output terminal Tsr, the PMOS transistors M31 and M33 serving as the input control means (the switching device 40A) are turned on.

By this operation, a low-level voltage corresponding to the negative polarity current Ip is applied to the node N31 (i.e., the gate terminal of the PMOS transistor M32 or one end of the storage capacitor C31), thereby generating a potential difference between the high potential power supply Vdd and the node N31 (between the gate and the source of the PMOS transistor M32). Thus, the PMOS transistor M32 is turned on. Then, as shown in fig. 10A, a write current Iw equivalent to the current Ip flows from the high potential power supply Vdd to the input terminal Ics through the PMOS transistors M32 and M33.

At this time, the electric charge corresponding to the potential difference generated between the high potential power supply Vdd and the node N31 (between the gate and the source of the PMOS transistor M32) is stored in the storage capacitor C31 and held as a voltage component. At the end of the current holding operation, the PMOS transistors M31 and M33 are applied with the high-level switching signal SR from the shift register 20A via the shift output Tsr, thereby turning off these transistors. Thus, the electric charge (voltage component) stored in the storage capacitor C31 can be saved even after the supply of the write current Iw is stopped.

(Current feeding operation)

In the driving operation after the current holding operation, the low-level output enable signal EN is applied from the control unit (system controller 140) to the PMOS transistor M34 via the output control terminal Ten, turning the transistor on. At this time, since a potential difference equivalent to that in the current holding operation is generated between the gate and the source of the PMOS transistor M32 due to the voltage component held in the storage capacitor C31, a drive control current Iac (i.e., a current Ip) having a current equal to the write current Iw flows from the high potential power supply to the output node N33 via the PMOS transistors M32 and M34, as shown in fig. 10B.

The drive control current Iac flowing to the current mirror circuit unit 32 by this operation is converted into the drive current Ic having a current value corresponding to a predetermined current ratio defined by the current mirror circuit arrangement. This current is supplied to each signal line DL via a corresponding one of the output terminals Tout. At the end of the current supply operation, the high-level output enable signal EN is applied from the control unit to the PMOS transistor M34 via the output control terminal Ten, turning off the transistor, thereby stopping the supply of the drive current Ic from the current storage circuit 30A to the signal line DL.

In the current drive device having the above-described arrangement and drive method, during the current holding operation period, the single constant current generation circuit 10A generates and outputs the constant current Ip having a predetermined current value, and the switching signals SR sequentially output from the shift register 20A are sequentially applied to the respective switching devices 40A. By this operation, the respective switching devices 40A are turned on in sequence at different timings, and the write currents Iw each corresponding to the constant current Ip output from the constant current generating circuit 10A flow in sequence to the respective current storage circuits 30A to be written and are held as voltage components (the above-described current holding operation).

After the constant current Ip output from the single constant current generating circuit 10A is held in all the current storage circuits 30A in the current feeding operation period, the output enable signal EN is applied in common from the control unit to the respective current storage circuits 30A at the same timing. By this operation, currents corresponding to the voltage components stored in the respective current storage circuits 30A, each having a predetermined signal time width set by a PWM control unit (not shown), are supplied to the respective signal lines simultaneously via the output terminals Tout as the drive currents Ic.

(the above-mentioned current feeding operation)

The current holding operation period and the current supply operation period as described above are repeatedly set for each scanning period in which the respective scanning lines SL are sequentially selected by the scan driver 120 shown in fig. 1. This makes it possible to operate each row of organic EL elements in turn at a predetermined luminance level.

The data driver with the constant current supply circuit according to the present embodiment repeats the following operations for each row in turn:

the organic EL elements connected to each of the scanning lines SL provided in the display device 100 shown in fig. 2 are simultaneously supplied with a drive current Ic, each formed of a constant current supplied from a signal current source (current generating circuit) and having a uniform current characteristic, for each of the scanning lines SL via the respective signal lines DL during a scanning period, and have a signal time width corresponding to display data, thereby causing each of the organic EL elements to emit light at a predetermined luminance level. This allows each organic EL element to operate with uniform operating characteristics while suppressing variations in current values between the respective signal lines (between the respective semiconductor chips constituting the constant current feeding circuit and between the output terminals of the semiconductor chips). Therefore, desired image information can be displayed with excellent luminance levels while the occurrence of display unevenness can be suppressed.

< second embodiment of constant Current feeding Circuit >

A second embodiment of the above-described constant current feeding circuit will be described with reference to the drawings.

Fig. 11 is a schematic block diagram showing a second embodiment of a constant current feeding circuit applicable to the above-described embodiments. The same reference numerals as those of the above-described embodiment denote the same or similar elements in the embodiment, and the description thereof is simplified or omitted.

As shown in fig. 11, the constant current feeding circuit according to the present embodiment has a circuit arrangement including: a single constant current generating circuit 10B that commonly supplies a constant current Ip, a plurality of current storage circuits 30B (current storage units 31a and 31B) provided in accordance with a predetermined number of output terminals Tout, a shift register 20B (shift register units 21a and 21B), a plurality of input side switching devices 40B (switches 41a and 41B), and a plurality of output side switching devices 50B. This constant current delivery circuit has a pair of current storage cells for each output terminal and is designed to simultaneously perform the following operations: an operation of sequentially holding the constant current supplied from the signal current generating circuit in one current storage unit of each current storage circuit, and simultaneously outputting the current already held in the other current storage unit of each current storage circuit through a corresponding one of the output terminals.

In the constant current feeding circuit having the above-described arrangement, during the first operation period (the period in which the current storage unit 31a is set in the current holding state and the current storage unit 31B is set in the current feeding state), the switching signal SR1 from the shift register unit 21a is sequentially output to the switches 41a provided corresponding to the current storage units 31a of the respective current storage circuits 30B. By this operation, the respective switches 41a are sequentially set in the on state only for a predetermined period, and the current Ip supplied from the constant current generating circuit 10B is sequentially written in the respective current storage units 31 a. At this time, the switch signal SR2 is not output from the shift register unit 21b, and all the switches 41b are in the off state. At this time, the control unit commonly outputs the selection signal SEL for switching the output side switching device 50B to the current storage unit 31B side to the output side switching device 50B provided corresponding to each output terminal Tout, and also outputs the output enable signal EN2 to all the current storage units 31B at a predetermined timing, thereby simultaneously outputting the currents which have been stored in the respective current storage units 31B via the respective output terminals Tout.

In a second operation period (a period in which the current storage unit 31a is set in the current-feeding state and the current storage unit 31B is set in the current-holding state) set after the end of the first operation period, the switching signal SR2 from the shift register 21B is sequentially output to the switches 41B provided corresponding to the current storage units 31a of the respective current storage circuits 30B. By this operation, the respective switches 41B are sequentially set in the on state only for a predetermined period, and the current Ip supplied from the constant current generating circuit 10B is sequentially written in the respective current storage units 31B. At this time, the switch signal SR1 is not output from the shift register unit 21a, and all the switches 41a are in the off state. At this time, the control unit commonly outputs to the output side switching device 50B the selection signal SEL for switching the output side switching device 50B to the current storage unit 31a side, thereby simultaneously outputting the currents already stored in the respective current storage units 31a via the respective output terminals Tout.

Such first and second operation periods are repeatedly set in each predetermined operation cycle so as to alternately and successively perform an operation of holding the current Ip successively output from the constant current generating circuit 10B in one of each pair of current storage units 31a and 31B and an operation of outputting the current Ip from the other of each pair.

As in the first embodiment described above, the data driver having the constant current supply circuit according to the present embodiment sequentially receives and holds the currents output from the single constant current generation circuit in the respective current storage circuits, and simultaneously outputs the currents at predetermined timings. This allows having a uniform current characteristic and the current supplied from the signal current source to be held for each output terminal, thereby suppressing variations in the drive current between the respective output terminals. Further, a pair of current storage units is provided for each output terminal, so that when the current output from the current generation circuit is sequentially written in the current storage unit on one side, the current held in the current storage unit on the other side is simultaneously output. This may reduce or eliminate the latency of the current write operation. Compared with the first embodiment, the delivery time for delivering the drive current to each load (each organic EL element) can be extended, and therefore the drive state of each load can be controlled more accurately. Further, the time for the current holding operation in each current storage circuit can be extended, and therefore the current holding operation can be stably performed in each current storage circuit.

< third embodiment of constant Current feeding Circuit >

A third embodiment of the above-described constant current feeding circuit will be described with reference to the drawings.

Fig. 12 is a schematic block diagram showing a third embodiment of a constant current feeding circuit applicable to the above-described embodiments. The same reference numerals as those of the above-described embodiment denote the same or similar elements in the embodiment, and the description thereof is simplified or omitted.

As shown in fig. 12, the constant current supply circuit according to the present embodiment includes a plurality of semiconductor chips CP1, CP2,. cnn and a single constant current generating circuit 10C, which circuit 10C supplies a constant current Ip in common to the respective semiconductor chips CP1, CP2,. cnn. Each semiconductor chip has the following two circuit arrangements formed on the same semiconductor substrate: one circuit arrangement includes a plurality of current storage circuits 30C (current storage units 31a and 31b), shift registers 20C (shift register units 22a and 22b), a plurality of input side switching devices 40C (switches 42a and 42b), and a plurality of output side switching devices 50C, which are provided corresponding to a predetermined number of output terminals Tout; and another circuit arrangement is provided in an input unit to which the constant current Ip output from the constant current generating circuit 10C is supplied, and which is located at a preceding stage of the above circuit arrangement, the circuit arrangement being constituted by an input unit switching device 60C that is turned on/off on the basis of a shift output from a shift register (not shown), and an input current storage circuit 70C that receives and holds the constant current Ip output from the constant current generating circuit 10C.

It should be noted that the constant current generating circuit 10C, the shift register 20C (shift register units 22a and 22b), the current storage circuit 30C (current storage units 31a and 31b), and the input side switching device 40C have substantially the same arrangement as the above-described embodiment, and therefore detailed description thereof is omitted.

In this case, the output side switching device 50C selectively switches and controls the current output state held in the current storage units 31a and 31b to the respective output terminals Tout (signal lines DL) by selecting one of the current storage units 31a and 31b on the basis of a predetermined output selection signal SEL. The input unit switching devices 60C provided for the respective semiconductor chips CP1, CP2,. CPn are turned on at different timings on the basis of shift outputs sequentially output from a shift register (or a control unit) (not shown), thereby supplying the constant current Ic output from the constant current generating circuit 10C to the respective semiconductor chips CP1, CP2,. CPn and causing the input current storage circuit 70C to hold the current.

Each input current storage circuit 70C has the same arrangement as the current storage circuit in the above-described embodiment (see fig. 9). The input current storage circuit 70C sequentially receives and stores the current Ip output from the constant current generating circuit 10C at different timings at which the above-described input cell switching device 60C is turned on, and outputs the stored current Ip to the current storage circuit 30C (the current storage unit 31a or the current storage unit 31b) via the input side switching device 40C (the switch 42a or the switch 42b) in each semiconductor chip on the basis of the output enable signal output from the control unit (the system controller 140).

In the current drive device having the above arrangement, first, the constant current Ip having a predetermined current value and output from the constant current generating circuit 10C is commonly supplied to the semiconductor chips CP1, CP2,. cnn, and sequentially received and held in the input current storage circuit 70C via the respective semiconductor chips CP1, CP2,. cndot. (the input cell switch device 60C provided for Pn).

In the first operation period (period in which the current storage unit 31a is set in the current holding state and the current storage unit 31b is set in the current delivery state), the switching signal SR1 from the shift register unit 22a is sequentially output to the switches 42a provided corresponding to the current storage units 31a of the respective current storage circuits 30C. By this operation, the respective switches 42a are sequentially set in the on state only for a predetermined period, and the current held in the input current storage circuit 70C is transferred to the current storage unit 31a to be held therein. At this time, the control unit commonly outputs the output selection signal SEL for switching the output side switching device 50C to the current storage unit 31b side to the output side switching device 50C provided corresponding to each output terminal Tout, and also outputs the output enable signal EN2 to all the current storage units 31b at a predetermined timing, thereby simultaneously outputting the currents that have been held in the respective current storage units 31b via the respective output terminals Tout. These operations are simultaneously performed in the respective semiconductor chips CP1, CP 2.

After the first operation period ends, the constant current Ip outputted again from the constant current generating circuit 10C at a predetermined timing is sequentially received and held in the input current storage circuit 70C at a predetermined timing via the input cell switching devices 60C provided for the respective semiconductor chips CP1, CP 2.

In the second operation period (the current storage section 31a is set in the current-supplied state and the current storage section 31b is set in the current-held state) after the end of the first operation period, which is set after the constant current Ip is completely received and held in each of the input current storage circuits 70C, the switching signal SR2 from the shift register unit 22a is sequentially output to the switches 42b provided to the current storage sections 31b corresponding to the respective current storage circuits 30C. By this operation, the respective switches 42b are sequentially set to the on state only for a predetermined period, and the current held in the input current storage circuit 70C is transferred to the current storage unit 31b to be held therein, as in the above-described first operation period.

At this time, no switching signal SR1 is output from the shift register 22a, and all the switches 42a are in the off state. At this time, the control unit commonly outputs the output selection signal SEL for switching the output side switching device 50C to the current storage unit 31a side to the output side switching device 50C, and also outputs the output enable signal EN1 to all the current storage units 31a at a predetermined timing, thereby simultaneously outputting the currents held in the respective current storage units 31a during the first operation period via the respective output terminals Tout. These operations are simultaneously performed in the respective semiconductor chips CP1, CP 2.

Such a series of operation cycles are repeatedly set in each predetermined operation cycle so as to sequentially hold the constant currents Ip output from the constant current generating circuit 10C in the input current storage circuits 70C of the input units of the respective semiconductor chips CP1, CP 2. Further, the above arrangement makes it possible to alternately and continuously perform the operation of holding the constant current Ip in one current storage section of each current storage circuit 30C and the operation of simultaneously outputting the current held in the other current storage section of each current storage circuit as the drive current Ic to each output terminal Tout.

In the arrangement of the constant current supply circuit according to the present embodiment, even in the case where the number of signal lines provided in the display panel as shown in fig. 2 is increased, and the signal lines are formed into a plurality of groups each of which is constituted by a predetermined number of lines so as to be driven by a plurality of semiconductor chips (driver chips), since the current output from the single current generation circuit can be commonly supplied to each of the semiconductor chips, it is possible to suppress variations in the drive current between all the signal lines on the plurality of semiconductor chips. Further, since the operations of sequentially supplying a current to the input current storage circuit provided for each semiconductor chip and then supplying the current to each current storage circuit in each semiconductor chip can be performed simultaneously in the respective semiconductor chips, a predetermined drive current can be held in the current storage circuits corresponding to all the signal lines substantially only for the time required to write the current in each semiconductor chip (input current storage circuit). This can greatly shorten the time required to hold the drive current. Therefore, the delivery time of the drive current can be extended, and thus the drive state can be accurately controlled. Further, this arrangement can appropriately cope with an increase in the screen area or an increase in the resolution of the display panel.

As described above, the driving apparatus according to the present invention, which drives a plurality of current-driven optical elements, can improve the response speed of each optical element by applying a predetermined charge voltage to the interconnection capacitance and the element capacitance of the optical element to charge them before supplying a driving current to the optical element. Even if the drive current supplied to the optical element has a relatively small value, the element can be driven appropriately. In a display device that drives a display panel having a plurality of current-driven display elements using such a driving means, a charging voltage to be applied to each display element connected to a data line of the display panel is set using a driving current to a voltage determined with reference to an average value of voltages to be applied to the respective display elements. This improves the response speed of all display elements in the entire display panel area, thereby obtaining good display quality according to the display gray scale. Further, the voltage to be applied to the data line after the driving current is supplied is set to a voltage higher than the ground potential and equal to or less than the threshold voltage of each display element. This arrangement can reduce the potential difference and the amount of charge stored in the interconnection capacitance or element capacitance, thereby reducing power consumption associated with supplying a drive current to the display element.

Additional advantages and modifications will readily appear to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made of the invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims (48)

1. A driving apparatus for supplying a current to a plurality of current-driven type optical elements to drive the optical elements, comprising at least:

a drive current supply circuit (133) for supplying a drive current to each of the optical elements in a predetermined period; and

a control voltage application circuit (132) that applies at least one charging voltage to each of the optical elements before the drive current is supplied, the charging voltage having a voltage value corresponding to a voltage value applied using the drive current,

the drive current delivery circuit (133) includes:

a single constant current generation circuit (10A, 10B, 10C) that outputs a constant current having a predetermined current value; and

a plurality of current storage circuits (30A, 30B, 30C) for sequentially receiving and holding the constant current and outputting the drive current based on the constant current.

2. The driving device according to claim 1, wherein the driving currents supplied to said respective optical elements have the same current value with respect to said respective optical elements.

3. The driving device according to claim 1, wherein the constant current has a current value equal to the driving current.

4. The drive device according to claim 1, wherein the constant current generating circuit (10A, 10B, 10C) includes:

a control current generation circuit (11) that generates a control current having a predetermined current value; and

an output current generation circuit (12) that generates an output current having a predetermined current ratio with respect to the control current and outputs the output current as a constant current.

5. The drive device according to claim 4, wherein the output current generating circuit (12) includes a current mirror circuit (12) having a predetermined current ratio.

6. The drive apparatus according to claim 1, wherein

Each of the current storage circuits (30B, 30C) includes a pair of current storage units (31a, 31B) arranged in parallel,

the drive device comprises a control unit (20), the control unit (20) alternately performing the following operations:

causing one current storage unit to receive the constant current output from the constant current generation circuit (10) and hold a voltage component corresponding to a current value of the constant current, and outputting the drive current by another current storage unit on the basis of the voltage component held in the another current storage unit; and

another current storage unit is caused to receive the constant current output from the constant current generation circuit (10) and hold a voltage component corresponding to a current value of the constant current, and the one current storage unit outputs the drive current on the basis of the voltage component held in the one current storage unit.

7. The drive device according to claim 1, wherein the current storage circuit (30A, 30B, 30C) includes a voltage component holding unit (31), the voltage component holding unit (31) receiving the constant current output from the constant current generating circuit and holding a voltage component corresponding to a current value of the constant current.

8. The drive device according to claim 7, wherein the voltage component holding unit (31) includes a capacitance element (C31) in which a charge corresponding to the constant current is written.

9. The drive of claim 8, wherein

The voltage component holding unit (31) includes a field effect transistor (M32) that causes a constant current to flow between the source and the drain, and

the capacitive element (C31) includes at least a parasitic capacitance between the source and the gate of the field effect transistor (M32), and writes therein a voltage applied between the source and the gate of the field effect transistor and corresponding to a constant current.

10. The drive device according to claim 1, wherein the drive current supply circuit (133) further includes a single input current storage circuit (70C) provided between the constant current generation circuit (10C) and the plurality of current storage circuits (30C), the input current storage circuit (70C) receiving the constant current output from the constant current generation circuit and holding a voltage component corresponding to a current value of the constant current, and supplying a current based on the voltage component to the plurality of current storage circuits (30C).

11. The drive device according to claim 10, wherein the input current storage circuit (70C) includes a capacitance element in which a charge corresponding to a constant current is written as a voltage component.

12. The drive of claim 11, wherein

The input current storage circuit (70C) includes a field effect transistor for causing a constant current to flow between a source and a drain, and

the capacitive element includes at least a parasitic capacitance between a source and a gate of the field effect transistor, and writes therein a voltage applied between the source and the gate of the field effect transistor and corresponding to a constant current.

13. The driving device according to claim 1, wherein the control voltage applying circuit (132) further comprises means for applying a discharge voltage after being applied to said optical elements at the time of driving the current, wherein said discharge voltage has a voltage value for causing said optical elements to perform a discharge operation.

14. The driving device according to claim 1, further comprising a pulse width control circuit (80) controlling a pulse width of a driving current to be applied to said each optical element.

15. The driving apparatus according to claim 14, wherein the pulse width control circuit (80) controls the pulse width of the driving current according to the luminance level fraction of the display signal.

16. A display apparatus which displays image information by supplying a drive current corresponding to a display signal to each display element of a display panel having a plurality of current-driven type display elements, comprising:

a display panel (110) including a plurality of signal lines (DL) and a plurality of Scanning Lines (SL) which are orthogonal to each other, and the plurality of display elements (OEL) disposed in the vicinity of intersections of the respective signal lines and the respective scanning lines;

a scan control circuit (120) that sequentially scans the Scan Lines (SL) to sequentially set the display elements (OEL) connected to the Scan Lines (SL) to a selection state; and

a signal control circuit (130) including at least a drive current supply circuit (133) for supplying a drive current to each of the signal lines for a predetermined period and a control voltage application circuit (132) for applying a charging voltage to each of the signal lines before the drive current is supplied, the charging voltage having a voltage value based on a voltage applied to each of the display elements by the application of the drive current,

the drive current delivery circuit (133) in the signal control circuit (130) includes:

a single constant current generation circuit (10A, 10B, 10C) that outputs a constant current having a predetermined current value; and

and a plurality of current storage circuits (30A, 30B, 30C) provided in correspondence with the plurality of signal lines, receiving and holding the constant current in sequence, and outputting the drive current to the plurality of signal lines simultaneously on the basis of the constant current.

17. The display device according to claim 16, wherein the drive current supplied to the respective signal lines of the display panel has the same current value for the respective signal lines.

18. The display device according to claim 16, wherein the signal control circuit (130) comprises at least a control unit (131), the control unit (131) performing a supply operation of the drive current by the drive current supply circuit (133) and an application operation of the charging voltage by the control voltage application circuit (132) in accordance with a timing at which the scan control circuit (120) sets the display element to the selected state.

19. The display device according to claim 16, wherein the charging voltage has a voltage value at least higher than a threshold voltage of the respective display elements of the display panel and smaller than a maximum value of voltage values applied to the respective display elements when the driving current is applied to the respective display elements through the respective signal lines.

20. The display device according to claim 19, wherein the charging voltage has a voltage value equal to an average value of voltage values applied to the respective display elements when the driving current is supplied to the respective display elements through the respective signal lines.

21. The display device according to claim 16, wherein the display element (OEL) comprises an optical element (Ep).

22. A display device according to claim 21, wherein each optical element (Ep) comprises an organic electroluminescent element having an anode connected to the signal line and a cathode connected to the scan line.

23. The display device according to claim 16, wherein the constant current has a current value equal to the drive current.

24. The display device according to claim 16, wherein the constant current generating circuit (10A, 10B, 10C) comprises:

a control current generation circuit (11) that generates a control current having a predetermined current value; and

an output current generation circuit (12) that generates an output current having a predetermined current ratio with respect to the control current and outputs the output current as a constant current.

25. A display device according to claim 24, wherein the output current generating circuit (12) comprises a current mirror circuit having a predetermined current ratio.

26. A display device according to claim 16, wherein

Each of the current storage circuits (30B, 30C) includes a pair of current storage units (31a, 31B) arranged in parallel,

the signal control circuit comprises a control unit (20), the control unit (20) alternately performing the following operations:

causing one current storage unit to receive the constant current output from the constant current generation circuit (10) and hold a voltage component corresponding to a current value of the constant current, and causing another current storage unit to output the drive current on the basis of the voltage component held in the another current storage unit; and

another current storage unit is caused to receive the constant current output from the constant current generation circuit (10) and hold a voltage component corresponding to a current value of the constant current, and the one current storage unit outputs the drive current on the basis of the voltage component held in the one current storage unit.

27. The display device according to claim 16, wherein the current storage circuit (30A, 30B, 30C) includes a voltage component holding unit (31) which receives the constant current output from the constant current generating circuit and holds a voltage component corresponding to a current value of the constant current.

28. The display device according to claim 27, wherein the voltage component holding unit (31) includes a capacitive element (C31) in which a charge corresponding to a constant current is written.

29. A display device according to claim 28, wherein

The voltage component holding unit (31) includes a field effect transistor (M32) that causes a constant current to flow between the source and the drain, and

the capacitive element (C31) includes at least a parasitic capacitance between the source and the gate of the field effect transistor (M32), and writes therein a voltage applied between the source and the gate of the field effect transistor and corresponding to a constant current.

30. The display device according to claim 16, wherein the drive current supply circuit (133) further comprises a single input current storage circuit (70C) provided between the constant current generating circuit (10C) and the plurality of current storage circuits (30C), the input current storage circuit (70C) receiving the constant current output from the constant current generating circuit and holding a voltage component corresponding to a current value of the constant current, and supplying a current based on the voltage component to the plurality of current storage circuits.

31. The display device according to claim 30, wherein the input current storage circuit (70C) includes a capacitance element in which a charge corresponding to a constant current is written as a voltage component.

32. A display device according to claim 31, wherein

The input current storage circuit (70C) includes a field effect transistor for causing a constant current to flow between a source and a drain, and

the capacitive element includes at least a parasitic capacitance between a source and a gate of a field effect transistor (M32), and writes therein a voltage applied between the source and the gate of the field effect transistor and corresponding to a constant current.

33. The display device according to claim 16, wherein at least the plurality of current storage circuits in the signal control circuit are formed on at least one semiconductor Chip (CP).

34. The display device according to claim 33, wherein the constant current generating circuit is formed on a semiconductor chip different from the semiconductor chip.

35. The display device according to claim 33, wherein a constant current generating circuit is formed on said semiconductor Chip (CP).

36. The display device according to claim 16, wherein the control voltage applying circuit (132) in the signal control circuit (130) further comprises means for applying a discharge voltage to said respective signal lines after supplying a drive current to said respective signal lines, wherein said discharge voltage has a voltage value for causing said respective display elements to perform a discharge operation.

37. A display device according to claim 36, wherein the discharge voltage has a voltage value not exceeding a threshold voltage of the display element.

38. The display device according to claim 16, wherein the signal control circuit (130) further comprises a pulse width control circuit (80) controlling a pulse width of the drive current applied to said each signal line.

39. The display device according to claim 38, wherein the pulse width control circuit (80) controls the pulse width of the drive current according to a luminance level fraction of the display signal.

40. The display device of claim 16, further comprising means for preventing current flow in the display element (OEL) when a charging voltage is applied to the display element (OEL) from a control voltage applying circuit (132) in the signal control circuit (130).

41. A display device according to claim 16, wherein the scanning control circuit (120) comprises means for applying a charging control voltage to all the scanning lines during a period in which a charging voltage is applied to said respective signal lines from a control voltage applying circuit (132) in the signal control circuit (130), said charging control voltage having a voltage value that prevents a current from flowing in the display element.

42. A display device according to claim 41, wherein the charge control voltage has a voltage value higher than a voltage obtained by subtracting a threshold voltage of the display element from the charge voltage.

43. A display device according to claim 16, wherein the scanning control circuit (120) comprises means for applying a driving control voltage to the scanning lines connected to the display element during a period in which the driving current is supplied from the driving current supply circuit (133) in the signal control circuit (130) to said respective signal lines, said driving control voltage having a voltage value at which the driving current flows in the display element.

44. A display device according to claim 43, wherein the drive control voltage is set to ground potential.

45. A driving method of a driving apparatus that supplies a current to a plurality of current-driven type optical elements to drive the optical elements, the driving method comprising at least:

a step of supplying a drive current to each of the Optical Elements (OEL) for a predetermined period; and

applying a charging voltage having a voltage value based on a voltage applied to the optical element by applying the driving current to the optical element, to the optical elements before the driving current is supplied,

the step of delivering a drive current comprises:

a step of generating a constant current having a predetermined current value by using a single constant current generation circuit (10A, 10B, 10C) and supplying the constant current to a plurality of current storage circuits (30A, 30B, 30C);

a step of sequentially receiving and holding a constant current in each of the current storage circuits; and

a step of applying the driving current from each of the current storage circuits to each of the Optical Elements (OEL) on the basis of a constant current stored in each of the current storage circuits.

46. The driving method of claim 45, further comprising applying a discharge voltage to the Optical Elements (OEL) after supplying the driving current to the optical elements, wherein the discharge voltage has a voltage value that causes the optical elements to perform a discharge operation.

47. The driving method according to claim 45, wherein the step of holding said driving current in said respective current storage circuits (30A, 30B, 30C) and the step of applying said driving current to said respective Optical Elements (OEL) are performed simultaneously.

48. The driving method according to claim 45, wherein the step of outputting the constant current to the respective current storage circuits (30C) includes:

a step of receiving and holding a voltage component corresponding to a current value of the constant current output from the constant current generation circuit (10C) in a single input current storage circuit (70C); and

a step of supplying a current based on the voltage component held in the input current storage circuit to the plurality of current storage circuits.