HK1074918A - Multiple analog and digital downconversion - Google Patents

Description

Multiple analog and digital down conversion

Correlation reference

This application claims priority from U.S. provisional application No. 60/337,469, filed 9.9.2001, entitled "Method and Apparatus for Matching Receiver Carrier Frequency".

FIELD

The disclosed embodiments relate generally to wireless communications and, more particularly, to frequency matching of received carrier signals in a mobile wireless communication system.

Background

As modern wireless communication systems become ubiquitous, the demand for wireless system capacity is increasing. To support a greater number of subscribers, wireless service providers may either increase the spectrum used for their systems or seek ways to support more users in the spectrum to which they have been allocated. Because additional spectrum is generally not available, wireless service providers must seek ways to increase capacity without using more spectrum. In other words, wireless service providers must seek more efficient ways to use their existing spectrum.

In response to the demand for more efficient use of spectrum, manufacturers of wireless devices have developed various techniques for increasing the capacity of wireless systems. One way to provide efficient wireless voice and data communications is to use Code Division Multiple Access (CDMA) techniques. Several standards using CDMA technology have been developed for terrestrial wireless voice and data systems. Examples of such standards include "TIA/EIA/IS-95 Mobile Station-Base Station compatibility Standard for Dual-Mode Wireless Spread Spectrum cellular System", hereinafter referred to as "IS-95", and "TIA/EIA/IS-2000", hereinafter referred to as "cdma 2000". Other standards have been proposed for wireless communication systems that are optimized to provide high-speed wireless data communication. Examples of such standards for high-speed wireless data communication include "TIA/EIA/IS-856", hereinafter referred to as "HDR".

In an HDR system, the rate at which a ue receives data is limited by the quality of the signal received by the ue. In such systems, the data rate of a signal transmitted to a user terminal is determined based on a received signal quality metric made at the user terminal. One type of quality metric used to determine the data rate is the carrier-to-interference ratio (C/I) of the received signal. When the power of the received carrier signal is strong compared to the power of the interfering signal, the C/I value is considered high. The C/I value is considered low when the power of the received carrier signal is weak compared to the interference. When the C/I value is high, the user terminal may receive more data for a given period of time. When the C/I value is low, the data rate transmitted to the user terminal is reduced in order to maintain an acceptable frame error rate.

Carrier frequency recovery is an aspect of the user terminal design that greatly affects the C/I perceived by the user terminal. Carrier frequency recovery refers to the generation of a reference carrier signal within the user terminal, the reference carrier signal having the same frequency as the carrier signal received from the base station. The user terminal demodulates the data signal received from the base station using the base station carrier signal. The mismatch between the reference carrier signal and the received carrier signal, referred to as carrier frequency mismatch, reduces the efficiency of the demodulation process. The user terminal reflects this reduced efficiency of demodulation as a reduction in C/I. Thus, carrier frequency mismatch reduces the rate at which data can be transmitted to the user terminal.

Along with the need for accurate carrier frequency recovery comes the desire to minimize the hardware cost of the user terminal. The market for subscriber terminal equipment such as wireless telephones and modems is very competitive, often presenting a low profit, or even subsidized by the service provider. There is therefore a need in the art for techniques that can improve the accuracy of carrier frequency recovery in a user terminal device without substantially increasing the hardware cost of the user terminal.

SUMMARY

Embodiments disclosed herein address the above stated needs by dividing the task of carrier frequency recovery into multiple levels of different resolutions. In an exemplary aspect, a user terminal tracks the frequency of a signal received from a base station. The base station typically uses a very accurate frequency source like a GPS receiver, so that a simpler and cheaper frequency source can be used in the user terminal. An exemplary user terminal comprises means for generating an error signal indicative of a difference between a frequency of a received carrier and a frequency of a locally generated reference carrier. The error signal is used to adjust the frequency of the reference carrier until it matches the frequency of the received carrier.

In an exemplary aspect, two stages are used to generate the reference carrier, a first stage generating a carrier with a wide frequency range but coarse frequency resolution, and a second stage generating a carrier with a narrower range but finer frequency resolution. In such an aspect, the first stage is an analog device such as a voltage controlled oscillator and the second stage is a digital device such as a digital oscillator. The frequency of the signal generated by the first stage may be adjusted so that the frequency of the signal generated by the second stage may be maintained within a predetermined frequency range.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment described as an "exemplary embodiment" is not necessarily to be construed as preferred or advantageous over other embodiments.

Brief Description of Drawings

Fig. 1 shows a multistage carrier frequency recovery apparatus;

FIG. 2 illustrates a frequency tracking module apparatus; and

fig. 3 is a flow diagram illustrating a method for adjusting the frequency of a down-converter in a multi-stage carrier frequency recovery system.

Detailed Description

A user terminal, as referred to herein, may be mobile or stationary and may communicate with one or more base stations. A user terminal transmits and receives data packets through one or more base stations. The base station is called a modem pool transceiver. Each modem pool transceiver may be connected to an HDR base station controller, referred to as a Modem Pool Controller (MPC). The modem pool transceivers and modem pool controllers are part of a network known as an access network. The interconnected nodes of the access network typically communicate with each other using a fixed, land-based connection, such as a T1 connection. An access network transports data packets between a plurality of user terminals. The access network may also be connected to other networks outside the access network, such as a corporate intranet or the internet, and may transport data packets between individual user terminals and such outside networks. A user terminal that has established an active traffic channel connection with one or more modem pool transceivers is referred to as an active user terminal and is said to be in a traffic state. A user terminal that is in the process of establishing an active traffic channel connection with one or more modem pool transceivers is said to be in a connection setup state. A user terminal may be any data device that communicates through a wireless channel or through a wired channel, for example using fiber optic or coaxial cables. The user terminal may also be any kind of device including, but not limited to: PC card, micro flash, external or internal modem, or wireless or wired telephone. The communication link through which the user terminal sends signals to the modem pool transceiver is called a reverse link. The communication link through which the modem pool transceiver sends signals to the user terminal is called a forward link.

Fig. 1 is a block diagram of an exemplary multi-stage carrier frequency recovery apparatus. In the illustrated embodiment, carrier frequency recovery is divided into two stages, one using analog carrier signal source 114 and the other using digital carrier signal source 110. An embodiment may have more than two stages, or use different combinations of analog and digital stages.

The signal is received by an antenna 100 and mixed with an analog carrier signal in an analog mixer 102. The analog carrier signal is generated by a variable frequency signal source such as a Voltage Controlled Oscillator (VCO) 114. The frequency of the carrier signal generated by the VCO114 varies according to the input voltage. The input voltage is based on a digital control signal provided by the control processor 112. In the exemplary embodiment shown, a Pulse Density Modulator (PDM)118 and a Low Pass Filter (LPF)116 are used to convert the digital control signal to an input voltage to the VCO 114. The PDM 118 receives a digital value from the control processor 112 and outputs a sequence of pulses having a duty cycle based on the digital value. The LPF 116 may be a simple RC circuit or an integrator or any equivalent circuit. The LPF 116 converts the pulse sequence output by the PDM 118 into a DC voltage that determines the frequency of the carrier signal output from the VCO 114. In an alternative embodiment, the PDM 118 and LPF 116 are replaced with a simple digital-to-analog converter (DAC).

The resolution of the voltage adjustments that can be made at the input to the VCO114 is relatively coarse. In other words, a change in the least significant bit of the digital value provided to the PDM 118 from the control processor 112 may result in a relatively large change in the frequency of the carrier signal output by the VCO 114. As such, the control processor 112 is generally unable to match the frequency of the carrier signal output by the VCO114 to the carrier frequency of the signal received through the antenna 100. Even with the use of a high resolution DAC instead of the LPF 116 and PDM 118, analog noise at the input to the VCO114 can make the fine tuning of the VCO output frequency very inaccurate.

The output of the analog mixer 102 is typically not a full baseband signal due to an expected mismatch in frequency between the output of the VCO114 and the carrier frequency of the signal received through the antenna 100. In other words, the signal output by the analog mixer 102 will generally retain the low frequency carrier component.

In the exemplary embodiment shown, the remaining low frequency carrier is separated from the desired baseband signal in the digital domain. Thus, the output of analog mixer 102 is digitally sampled in sampler 104 and mixed with a low frequency digital carrier in digital mixer 106. The output of the digital mixer 106 is a downconverted baseband signal that is provided to decoding circuitry known in the art, such as filters, PN and/or Walsh despreaders, deinterleavers, and decoders. The low frequency digital carrier is generated by a digital oscillator 110. The frequency of the carrier generated by the digital oscillator 110 may be adjusted with a higher resolution than the carrier generated by the VCO114, however the VCO114 may be adjusted over a wider range of frequencies. For example, the VCO114 can produce signals in a frequency range of +/-45 megahertz in steps of 30 hertz, while the digital oscillator 110 can produce signals with any fine resolution and frequency range limited only by the sampling frequency of the analog-to-digital converter. Those skilled in the art will recognize that obvious variations using different combinations of digital and analog frequency generators and mixers are alternative embodiments to the above described embodiments.

In an exemplary embodiment, the digital oscillator 110 is a digital rotator capable of generating fine resolution frequency and phase correction signals. By increasing the number of bits used to represent the frequency and phase inputs, the digital rotator can be easily designed to have a higher frequency and phase resolution. In an alternative embodiment, the digital oscillator 110 is a Direct Digital Synthesizer (DDS). The digital oscillator 110 may also be any of a variety of other types of digital frequency reference generators. VCO114 may be any of a variety of voltage controlled oscillators, including a temperature controlled crystal oscillator (TCXO) and an oven controlled crystal oscillator (OCXO).

The frequency tracking module 108 measures the residual frequency error in the signal output by the digital mixer 106 and generates at least one error signal that is provided to the control processor 112. Control processor 112 uses at least one error signal from frequency tracking module 108 to adjust the control signals to digital oscillator 110 and PDM 118. By varying the control signal provided to the PDM 118, the control processor 112 produces a change in the frequency of the signal output by the VCO 114.

In an exemplary embodiment, the control processor 112 controls the output frequency of the VCO114 such that the remaining frequency correction required is from within a predetermined optimum or operational range of the digital oscillator 110. For example, even if the digital oscillator 110 is capable of generating a frequency within a frequency band having a bandwidth of several megahertz, the VCO114 is adjusted so that the frequency of the digital oscillator 110 can be maintained within a range having a bandwidth of 128 hertz. Furthermore, it may be desirable to keep the VCO frequency reference relatively close to the carrier frequency of the received signal. Adjusting the frequency of the VCO114 as close as possible to the received carrier frequency minimizes the frequency of the signal output by the digital oscillator 110.

Likewise, to keep the digital oscillator 110 operating within its optimum or operational frequency range, the control processor 112 raises the frequency of the VCO114 and lowers the frequency of the digital oscillator 110. Instead, the control processor 112 lowers the frequency of the VCO114 and raises the frequency of the digital oscillator 110, as appropriate.

In an exemplary embodiment, the control processor 112 adjusts the coarse frequency in fixed frequency steps by changing the digital control signal provided to the PDM 118. For example, if the resolution of the PDM is 30 Hz per bit, the control processor 112 may increase the PDM control signal by 30, 60, or 90 Hz by changing the digital input value of the PDM by 1, 2, or 3. At the same time, control processor 112 adjusts the control signal to digital oscillator 110 so that the output frequency of digital oscillator 110 is reduced by 30, 60, or 90 hertz. Due to the coarse resolution of the output of the VCO114, only the frequency step of the VCO114 can be estimated. In contrast, the frequency step of the digital oscillator 110 is very accurate. Thus, even after adjusting the frequency of the digital oscillator 110 by a step change in the frequency of the VCO114, the digital oscillator 110 typically must be further adjusted before the output of the digital mixer 106 will have a frequency and phase that best matches the frequency and phase of the received carrier signal.

Fig. 2 is a more detailed diagram of an embodiment of the frequency tracking module 108, the frequency tracking module 108 being suitable for use in an HDR system. In an exemplary embodiment, the receiver uses exclusively the signals received in the two pilot bursts received in each time slot. In HDR, for example, each slot is 1.667 milliseconds in length, with one pilot burst center in each half of the slot. In other words, each slot has a first pilot burst centered 417 milliseconds from the start of the slot and a second pilot burst centered 1.25 milliseconds from the start of the frame. In HDR, each pilot burst is 96 chips in duration and has a chip rate of 1.2288 mhz. The pilot burst signal is multiplied by a Pseudo Noise (PN) sequence prior to transmission. The frequency tracking module 108 shown in fig. 2 is used to remove the PN component of the down-converted baseband signal received from the digital mixer 106 and to accumulate the portion of the signal received in the pilot burst.

The pilot burst chip clock 210 generates a clock signal during the pilot burst of each received time slot. The clock signal is provided to a PN generator 208 that generates a PN signal having the same clock rate as the pilot burst chip clock 210. The PN signal is then mixed with the downconverted baseband signal in digital mixer 202 to produce a PN despread pilot signal. The PN despread pilot signal is then accumulated over a pilot burst period in accumulator 204. The output of accumulator 204 will be a phase error signal corresponding to the phase error of the now fully demodulated pilot signal. The phase error is then provided to a Frequency Tracking Loop (FTL)108, and the frequency tracking loop 108 converts the phase error signal into a digital signal that can be used by a control processor 112. Those skilled in the art will recognize that FTL 108 can be a first order loop, a second order loop, or other configuration of FTL.

In an exemplary embodiment, the frequency tracking module 108 uses two pilot burst periods within a slot to generate one phase error estimate per slot. In an alternative embodiment, the frequency tracking module 108 generates more than one phase error estimate per slot. For example, frequency tracking module 108 may generate one phase error estimate and four phase error estimates for each half of the frequency burst period. These phase error estimates may then be used to estimate the rate of change of phase and hence the residual frequency error remaining in the baseband signal. Since smaller sampling periods are used to generate the individual phase error estimates, a phase error metric based on half of the pilot burst is more noisy than a single estimate generated over two pilot burst periods. In another alternative embodiment, one phase error estimate is generated for each pilot burst period in the slot, and two phase error estimates are generated. In another alternative embodiment, pilot burst periods of more than one slot are used to generate a single phase error estimate. Due to aliasing problems, selecting the number of phase error estimates over multiple time slots represents a compromise between signal noise and the magnitude of the frequency error that can be detected. In an alternative embodiment, the frequency tracking module 108 may be configured in real time by the control processor 113 to operate in any of several modes, where each mode uses a different phase error estimate to slot ratio.

In HDR, the pilot is spread using an all-one code, so there is no need for an explicit Walsh despreader between the digital mixer 202 and the integrator 204. In an exemplary embodiment, the PN generator 208 generates a complex PN code and the digital mixer 202 is a complex multiplier. The complex output of the digital mixer 202 is accumulated in an accumulator 204 by storing the phase information as the real and imaginary parts of the accumulated value.

Fig. 3 is a flow diagram of an exemplary method for adjusting the frequency of a downconverter in a multi-stage carrier frequency recovery system, such as that shown in fig. 1. During operation of the carrier frequency recovery system, the fine frequency value F is monitored 302_fTo determine when it is operating within the optimum or operable frequency range of a precision frequency generating source, such as digital oscillator 110 shown in fig. 1. In step 304, the precision is testedFrequency value F_fTo determine whether adjustments should be made in the coarse frequency output of the coarse frequency generating source, such as the VCO114 shown in fig. 2. If an adjustment is necessary, F is adjusted in step 306_fAnd F_C. If no adjustment is necessary, the adjustment step of 306 is skipped. In step 306, if F_fIncrease, then F_CBy about the same amount. If F_fDecrease, then F_CIncreasing by about the same amount.

Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Those of skill would further appreciate that the various illustrative logical blocks, modules, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. The skilled person will recognize the interactivity of the hardware and software in these cases and how best to implement the described functionality for each particular application. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The implementation or execution of the various illustrative logical blocks, modules, and algorithm steps described in connection with the embodiments described herein may be implemented or performed with: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a subscriber unit. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

The previous description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (36)

1. A method for down-converting a received signal, the method comprising:

generating an analog carrier signal having a first frequency from a first generation source having a first frequency range and a first frequency resolution;

generating a digital carrier signal having a second frequency from a second generation source having a second frequency range and a second frequency resolution, wherein the first frequency range is greater than the second frequency range and the first frequency resolution is lower than the second frequency resolution; and

the received signal is multiplied by the analog carrier signal and the digital carrier signal to produce a down-converted signal.

2. The method of claim 1, further comprising:

measuring a residual frequency error in the down-converted signal; and

adjusting the second frequency according to the metric.

3. The method of claim 1, further comprising:

increasing said first frequency by a coarse frequency step; and

decreasing the second frequency by the coarse frequency step.

4. The method of claim 1, further comprising:

decreasing said first frequency by a coarse frequency step; and

increasing the second frequency by the coarse frequency step.

5. A method for down-converting a received signal, the method comprising:

generating an analog carrier signal having a first frequency from a first generation source having a first frequency range and a first frequency resolution;

multiplying said received signal with said analog carrier signal to produce a conditioned analog signal;

sampling the conditioned analog signal to produce a stream of digital samples;

generating a digital carrier signal having a second frequency from a second generation source having a second frequency range and a second frequency resolution, wherein the first frequency range is greater than the second frequency range and the first frequency resolution is lower than the second frequency resolution; and

the conditioned analog signal is multiplied by the digital carrier signal to produce a down-converted signal.

6. The method of claim 5, further comprising:

measuring a residual frequency error in the down-converted signal; and

adjusting the second frequency according to the metric.

7. The method of claim 5, further comprising:

increasing said first frequency by a coarse frequency step; and

decreasing the second frequency by the coarse frequency step.

8. The method of claim 5, further comprising:

decreasing said first frequency by a coarse frequency step; and

increasing the second frequency by the coarse frequency step.

9. An apparatus for downconverting a received signal, the apparatus comprising:

means for generating an analog carrier signal having a first frequency from a first generation source having a first frequency range and a first frequency resolution;

means for generating a digital carrier signal having a second frequency from a second generation source having a second frequency range and a second frequency resolution, wherein said first frequency range is greater than said second frequency range and said first frequency resolution is lower than said second frequency resolution; and

means for multiplying the received signal with said analog carrier signal and said digital carrier signal to produce a down-converted signal.

10. The method of claim 9, further comprising:

means for measuring a residual frequency error in the down-converted signal; and

means for adjusting the second frequency in accordance with the metric.

11. The method of claim 9, further comprising:

means for increasing said first frequency by a coarse frequency step; and

means for decreasing said second frequency by said coarse frequency step.

12. The method of claim 9, further comprising:

means for reducing said first frequency by a coarse frequency step; and

means for increasing said second frequency by said coarse frequency step.

13. An apparatus for downconverting a received signal, the apparatus comprising:

means for generating an analog carrier signal having a first frequency from a first generation source having a first frequency range and a first frequency resolution;

means for multiplying said received signal with said analog carrier signal to produce a conditioned analog signal;

means for sampling said conditioned analog signal to produce a stream of digital samples;

means for generating a digital carrier signal having a second frequency from a second generation source having a second frequency range and a second frequency resolution, wherein said first frequency range is greater than said second frequency range and said first frequency resolution is lower than said second frequency resolution; and

means for multiplying said conditioned analog signal with said digital carrier signal to produce a down-converted signal.

14. The method of claim 13, further comprising:

means for measuring a residual frequency error in the down-converted signal; and

means for adjusting the second frequency in accordance with the metric.

15. The method of claim 13, further comprising:

means for increasing said first frequency by a coarse frequency step; and

means for decreasing said second frequency by said coarse frequency step.

16. The method of claim 13, further comprising:

means for reducing said first frequency by a coarse frequency step; and

means for increasing said second frequency by said coarse frequency step.

17. A receiver apparatus, comprising:

an analog oscillator having a first frequency range and a first frequency resolution for generating an analog carrier signal having a first frequency;

an analog mixer for multiplying a received signal with the analog carrier signal to produce a first down-converted signal;

a digital oscillator having a second frequency range and a second frequency resolution for generating a digital carrier signal having a second frequency, wherein the first frequency range is greater than the second frequency range, and the first frequency resolution is lower than the second frequency resolution; and

a digital mixer for multiplying the first down-converted signal with the digital carrier signal to produce a second down-converted signal.

18. The apparatus of claim 17, further comprising:

a frequency tracking module to measure a residual frequency error in the second down-converted signal; and

a control processor to adjust a first frequency of the first carrier signal and a second frequency of the second carrier signal according to the metric.

19. The apparatus of claim 18, wherein the frequency tracking module is a frequency tracking loop.

20. The apparatus of claim 18, wherein the frequency tracking module is a first order frequency tracking loop.

21. The apparatus of claim 18, wherein the frequency tracking module is a second order frequency tracking loop.

22. The apparatus of claim 17, wherein the digital oscillator is a digital rotator.

23. The apparatus of claim 17, wherein the digital oscillator is a direct digital synthesizer.

24. The apparatus of claim 17, wherein the analog oscillator is a voltage controlled oscillator.

25. The apparatus of claim 17, wherein the analog oscillator is a temperature controlled crystal oscillator.

26. The apparatus of claim 17, further comprising:

a Pulse Density Modulator (PDM) for boosting a sequence of pulses, said pulses having a duty cycle that varies in accordance with a digital input signal; and

a Low Pass Filter (LPF) for converting the pulse sequence into a time-invariant voltage, wherein an amplitude of the time-invariant voltage varies according to a duty cycle of the pulse sequence, and wherein the first frequency varies according to the time-invariant voltage.

27. The apparatus of claim 17 further comprising a control processor for adjusting said first frequency and said second frequency.

28. The apparatus of claim 27, further comprising a computer-readable medium embodying a method for down-converting a received signal, the method comprising:

measuring a residual frequency error in the down-converted signal; and

adjusting the second frequency according to the metric.

29. The apparatus of claim 27, further comprising a computer-readable medium embodying a method for down-converting a received signal, the method comprising:

increasing said first frequency by a coarse frequency step; and

decreasing the second frequency by the coarse frequency step.

30. The apparatus of claim 27, further comprising a computer-readable medium embodying a method for down-converting a received signal, the method comprising:

decreasing said first frequency by a coarse frequency step; and

increasing the second frequency by the coarse frequency step.

31. A computer-readable medium embodying a method for downconverting a received signal, the method comprising:

generating a first frequency control signal for controlling a first frequency of an analog carrier signal output by an analog oscillator, the analog oscillator having a first frequency range and a first frequency resolution;

generating a second frequency control signal for controlling a second frequency of a digital carrier signal output by a digital oscillator, the digital oscillator having a second frequency range and a second frequency resolution, wherein the first frequency range is greater than the second frequency range and the first frequency resolution is lower than the second frequency resolution;

measuring a residual frequency error in the down-converted signal; and

adjusting the second frequency according to the metric.

32. The computer-readable medium of claim 31, wherein the method further comprises:

adjusting said first frequency control signal to increase said first frequency by a coarse frequency step; and

adjusting the second frequency control signal to decrease the second frequency by the coarse frequency step.

33. The computer-readable medium of claim 31, wherein the method further comprises:

adjusting said first frequency control signal to decrease said first frequency by a coarse frequency step; and

adjusting the second frequency control signal to increase the second frequency by the coarse frequency step.

34. The computer-readable medium of claim 31, wherein the first frequency control signal is a digital signal provided to a pulse density modulator.

35. The computer-readable medium of claim 31, wherein the second frequency control signal is a digital signal provided to a digital rotator.

36. The computer-readable medium of claim 31, wherein the second frequency control signal is a digital signal provided to a direct digital synthesizer.