HK1074531B

HK1074531B - Semiconductor device using low dielectric constant material film and method of fabricating the same

Info

Publication number: HK1074531B
Application number: HK05108528.9A
Authority: HK
Inventors: Koyanagi Mitsumasa
Original assignee: Rambus Inc.
Priority date: 2001-11-05
Filing date: 2002-11-05
Publication date: 2007-11-02

Description

Semiconductor device using low dielectric constant material film and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device in which a substrate including a low dielectric constant material film having a dielectric constant lower than that of silicon (Si) is used to increase an operating speed, and a method for manufacturing the semiconductor device.

Background

Conventionally, as one of techniques to cope with miniaturization and high integration of semiconductor elements mounted On semiconductor devices, an SOI (Silicon On Insulator) technique (Silicon On Insulator technique) is known. This technique is a technique for forming a single crystal silicon film on an insulating substrate, and has the following advantages because insulation separation between semiconductor elements can be performed almost completely: (i) the method is easy to adapt to the miniaturization and high integration of semiconductor elements; (ii) the parasitic capacitance between the semiconductor element and the substrate can be reduced, and the operation speed can be easily increased.

In recent semiconductor devices, with the miniaturization and high integration of semiconductor elements, the operating speed has been further increased, and the operating frequency of semiconductor elements has come to the order of GHz. In addition, not only high integration is proceeding, but also the size of a chip of a semiconductor device (i.e., a semiconductor chip) itself is further expanded, and therefore, the characteristics of a wiring (chip wiring) for interconnecting a semiconductor element on a semiconductor chip and a substrate (for example, wiring resistance, parasitic capacitance of the wiring and the substrate, and the like) are becoming more and more decisive for the performance of the semiconductor device.

Therefore, in recent semiconductor devices, in order to reduce the resistance of the wiring itself, a transition from aluminum (Al) wiring to copper (Cu) wiring has been made. In addition, in order to reduce parasitic capacitance and suppress propagation delay of a signal, an insulating material film having a low dielectric constant (for example, a specific dielectric constant of 3 or less) is used as an interlayer insulating film, and a wiring structure is also shifted from a single-layer wiring to a multilayer wiring.

The above-described conventional techniques can be adapted to increase the operating speed to some extent. However, once the operating frequency is in the order of GHz, it becomes difficult to implement even with the above-mentioned prior art techniques. The reason for this is that a signal transmission delay due to a parasitic resistance and a parasitic capacitance of the single crystal silicon substrate itself becomes significant.

To accommodate operating frequencies in the order of GHz, it is possible to use semiconductor substrates other than single crystal silicon substrates (e.g., GaAs substrates). However, there are other problems such as increase in manufacturing cost and failure to improve integration.

Disclosure of the invention

It is therefore an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can accommodate operating frequencies in the order of GHz at reasonable cost and which does not impose restrictions on the degree of integration.

Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which uses a substrate having a low-dielectric-constant material film having a lower dielectric constant than silicon, and which can be adapted to an operating frequency of the order of GHz.

It is still another object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can cope with a wavelength of a signal to be processed approaching a wiring length even when the size of the semiconductor device (chip) is increased and an operation speed is increased.

Other objects of the present invention, not specifically mentioned herein, will become apparent from the description to follow.

The semiconductor device of the present invention includes:

(a) a substrate having a first surface and a second surface located on the opposite side of the first surface and containing a low dielectric constant material film having a lower dielectric constant than silicon;

(b) a first semiconductor element layer containing a semiconductor element formed directly on or through another layer on the first surface of the base;

(c) a first wiring layer formed directly on or through another layer above the first semiconductor element layer; and

(d) an electrode formed on the second surface of the base,

the semiconductor element of the first semiconductor element layer is formed of a semiconductor film formed in an island shape, and is embedded in an insulating film formed in the first semiconductor element layer.

In the semiconductor device of the present invention, a first semiconductor element layer is formed directly or with another layer interposed therebetween on a first surface of a base including a low dielectric material film having a dielectric constant lower than that of silicon, and a first wiring layer is formed directly or with another layer interposed therebetween on the first semiconductor element layer. And the electrode is formed on the second surface of the substrate. The semiconductor element of the first semiconductor element layer is formed using a semiconductor film formed in an island shape, and is embedded in an insulating film formed in the first semiconductor element layer.

Therefore, a silicon film which is conventionally used and has a lower cost than a compound semiconductor film such as GaAs can be used as a semiconductor film for forming a semiconductor element, and the amount (area) of the silicon film used can be suppressed to the minimum necessary for forming the semiconductor element. In other words, the signal propagation delay due to the silicon film can be suppressed to the minimum.

On the other hand, the base may be formed of any low-dielectric-constant material film having a lower dielectric constant than silicon, as long as the base supports the first semiconductor element layer including the semiconductor element, the first wiring layer, and the electrode, that is, the base is not directly used for formation of the semiconductor element.

Thus, operating frequencies in the order of GHz can be accommodated at reasonable cost without imposing restrictions on the degree of integration.

Further, an electrode is formed on the second surface of the base body, and thus the electrode forms a so-called "return path" for a signal transmitted through the first wiring layer. Therefore, even if the wavelength of the signal to be processed approaches the wiring length with the increase in the size of the semiconductor device or the increase in the operating speed, the wavelength can be handled.

In the semiconductor device of the present invention, the low dielectric constant material film of the base may be formed of any material having a lower specific dielectric constant than silicon, for example, an organic material such as alumina (Al2O3), silicon carbide (SiC), diamond, sapphire, aluminum nitride (AlN), glass, or plastic, or may be formed of a porous inorganic material such as porous SOG or a plastic material, or a porous organic material. The low dielectric constant material film is preferably made of any material known as a "low-k material" (e.g., HSQ, SiOF, organic SOG, BCB, SILK, porous material, polyimide, teflon (japanese: テフロン, registered trademark), or the like).

In a preferred embodiment of the semiconductor device of the present invention, the base body includes a substrate made of an insulator, a semiconductor, or a metal, on which the low-permittivity material film is formed. In this case, the low-dielectric-constant material film itself does not need to be rigid, and therefore, there is an advantage in that the low-dielectric-constant material film can be selected in a wide range and an optimum material can be easily selected depending on the application. As the substrate, a metal sheet of Cu, Al or the like can be preferably used, but an organic material film (an insulator or a semiconductor) of plastic or the like, a mounting film, a mounting substrate (an insulator) such as a glass fiber epoxy substrate or the like can also be used.

Also, the number of both the low-dielectric-constant material film and the substrate may be more than 1. That is, a laminate structure of 3 or more layers using a plurality of the low-k material films or a plurality of the substrates is also possible.

The substrate may be formed of only the low dielectric constant material film if it has such rigidity as to support at least the first semiconductor element layer and the first wiring layer. This has the advantage that the base body is simple to construct.

In another preferred embodiment of the semiconductor device according to the present invention, the insulating film in the first semiconductor element layer in which the semiconductor element is embedded is disposed to face the first surface of the base. Alternatively, a surface of the first semiconductor element layer opposite to the insulating film in which the semiconductor element is embedded is disposed to face the first surface of the base.

In another preferred embodiment of the semiconductor device according to the present invention, the semiconductor device further includes a second semiconductor element layer or a second wiring layer disposed between the first surface of the base and the first semiconductor element layer, and the first semiconductor element layer is formed on the first surface of the base with the second semiconductor element layer or the second wiring layer interposed therebetween. Alternatively, the semiconductor device further includes a second semiconductor element layer or a second wiring layer arranged between the first semiconductor element layer and the first wiring layer, and the first wiring layer is formed on the first semiconductor element layer with the second semiconductor element layer or the second wiring layer interposed therebetween.

In another preferred embodiment of the semiconductor device of the present invention, the semiconductor element of the first semiconductor element layer is a field effect transistor formed on the island-type semiconductor film, and the field effect transistor has a first gate electrode formed on one side of the semiconductor film and a second gate electrode formed on the opposite side of the first gate electrode. This example has advantages in that the operation speed can be increased compared to the case of 1 gate electrode, and leakage current caused by short tunnel effect can be prevented.

In another preferred embodiment of the semiconductor device of the present invention, the semiconductor element in the first semiconductor element layer is a field effect transistor formed on the island-shaped semiconductor film, and the field effect transistor has a first gate electrode formed on one side of the semiconductor film. This example has an advantage that the configuration of the semiconductor element and the manufacturing method thereof are simple as compared with the case of 2 gate electrodes.

The first gate electrode of the field effect transistor is disposed on the base side with respect to the island-shaped semiconductor film.

In another preferred embodiment of the semiconductor device of the present invention, the embedded wiring penetrating the substrate is provided, and the electrode is formed so as to be in contact with the embedded wiring, thereby realizing a function as an interposing selection finger (Interposer).

The method for manufacturing a semiconductor device of the present invention comprises the following steps:

(a) a step of forming a substrate which has a first surface and a second surface located on the opposite side of the first surface, and which contains a low dielectric constant material film having a lower dielectric constant than silicon;

(b) forming a semiconductor element on a sacrificial substrate by using a semiconductor film formed in an island shape;

(c) forming an insulating film on the sacrificial substrate so as to cover the semiconductor element, and forming a first semiconductor element layer by burying the semiconductor element in the insulating film;

(d) bonding the first semiconductor element to the first surface of the base directly or with another layer interposed therebetween;

(e) removing the sacrificial substrate;

(f) forming a first wiring layer on a side of the first semiconductor element layer opposite to the base directly or with another layer interposed therebetween; and

(g) and forming an electrode on the second surface of the base.

In the method for manufacturing a semiconductor device of the present invention, a base body including a low dielectric constant material film having a lower dielectric constant than silicon is formed in the step (a), and a semiconductor element is formed on a sacrificial substrate using a semiconductor film formed in an island shape in the step (b). Next, in step (c), an insulating film is formed on the sacrificial substrate so as to cover the semiconductor element, and the semiconductor element is buried in the insulating film, thereby forming a first semiconductor element layer. In the step (d), the first semiconductor element and the first surface of the substrate are bonded directly or with another layer interposed therebetween. The sacrificial substrate is removed in the process (e). In the step (f), a first wiring layer is formed on the first semiconductor element layer on the side opposite to the base directly or with another layer interposed therebetween. In the step (g), an electrode is formed on the second surface of the substrate. Thus, it is apparent that the above-described semiconductor device of the present invention can be obtained.

In a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention, the base used in the step (a) includes a substrate made of an insulator, a semiconductor, or a metal, on which the low-permittivity material film is formed. In this example, the low dielectric constant material film itself does not need to be rigid, and therefore, there is an advantage in that the low dielectric constant material film can be selected in a wide range and an optimum material can be easily selected depending on the application.

However, the substrate used in the step (a) may be formed of only the low dielectric constant material film. In this case, the low-dielectric-constant material film has at least such rigidity as to support the first semiconductor element layer and the first wiring layer, and the structure of the substrate is advantageous in that it is simple.

The matters discussed above for the semiconductor device of the present invention apply equally well with respect to the substrate and the low-k material film.

In another preferred example of the method for manufacturing a semiconductor device according to the present invention, in the step (d), the insulating film in which the semiconductor element is embedded in the first semiconductor element layer and the first surface of the base are bonded to each other so as to face each other. Alternatively, in the step (d), a surface of the first semiconductor element layer opposite to the insulating film in which the semiconductor element is embedded and the first surface of the base body are bonded to each other so as to face each other.

In still another preferred embodiment of the method for manufacturing a semiconductor device according to the present invention, in the step (d), the first semiconductor element layer and the first surface of the base are bonded to each other with a second semiconductor element layer or a second wiring layer interposed therebetween. Alternatively, in the step (f), the first wiring layer is formed on a side of the first semiconductor element layer opposite to the base with a second semiconductor element layer or a second wiring layer interposed therebetween.

In still another preferred embodiment of the method for manufacturing a semiconductor device according to the present invention, the semiconductor element formed by using the island-type semiconductor film in the step (b) is a field effect transistor having a first gate electrode formed on one side of the semiconductor film and a second gate electrode formed on the opposite side of the first gate electrode. This example has advantages in that the operation speed can be increased compared to the case of 1 gate electrode, and leakage current caused by short tunnel effect can be prevented.

In still another preferred embodiment of the method for manufacturing a semiconductor device according to the present invention, the semiconductor element formed by using the island-type semiconductor film in the step (b) is a field effect transistor having a first gate electrode formed on one side of the semiconductor film. This example has an advantage that the configuration of the semiconductor element and the manufacturing method thereof are simple as compared with the case of 2 gate electrodes.

In the step (d), when the first semiconductor element layer is bonded to the first surface of the base, the first gate electrode of the field effect transistor is preferably disposed on the base side with respect to the island-shaped semiconductor film. However, the first gate electrode of the field effect transistor may be arranged on the first wiring layer side with respect to the island-type semiconductor film.

In still another preferred embodiment of the method for manufacturing a semiconductor device according to the present invention, a step of forming a buried wiring penetrating through the substrate is included between the step (d) and the step (e), and the step (g) is performed by forming the electrode in contact with the buried wiring to function as an interposing option finger.

Brief description of the drawings

Fig. 1 is a schematic sectional view of an essential part showing a configuration of a semiconductor device according to a first embodiment of the present invention.

Fig. 2 is a process diagram showing a method of manufacturing the semiconductor device of the first embodiment in fig. 1.

Fig. 3 is a process diagram showing a method of manufacturing the semiconductor device of the first embodiment in fig. 1.

Fig. 4 is a process diagram, continuing from fig. 2 and 3, illustrating a method of manufacturing the semiconductor device of the first embodiment in fig. 1.

Fig. 5 is a process diagram continuing from fig. 4 showing the method of manufacturing the semiconductor device of the first embodiment in fig. 1.

Fig. 6 is a process diagram continuing from fig. 5 showing the method of manufacturing the semiconductor device of the first embodiment in fig. 1.

Fig. 7 is a process diagram continuing from fig. 6 showing a method of manufacturing the semiconductor device of the first embodiment in fig. 1.

Fig. 8 is a process diagram continuing from fig. 7 showing a method of manufacturing the semiconductor device of the first embodiment in fig. 1.

Fig. 9 is a schematic sectional view of an essential part showing the configuration of a semiconductor device according to a second embodiment of the present invention.

Fig. 10 is a process diagram showing a method of manufacturing the semiconductor device of the second embodiment in fig. 9.

Fig. 11 is a process diagram continuing from fig. 10 showing a method of manufacturing the semiconductor device of the second embodiment in fig. 9.

Fig. 12 is a schematic sectional view of a main part showing the configuration of a semiconductor device according to a third embodiment of the present invention.

Fig. 13 is a schematic sectional view of an essential part showing the configuration of a semiconductor device according to a fourth embodiment of the present invention.

Fig. 14 is a schematic sectional view of an essential part showing a configuration of a semiconductor device according to a fifth embodiment of the present invention.

Fig. 15 is a process diagram showing a method of manufacturing the semiconductor device of the fifth embodiment in fig. 14.

Fig. 16 is a process diagram continuing from fig. 15 showing a method of manufacturing the semiconductor device of the fifth embodiment in fig. 14.

Fig. 17 is a schematic sectional view of an essential part showing a configuration of a semiconductor device according to a sixth embodiment of the present invention.

Fig. 18 is a process diagram showing a method of manufacturing the semiconductor device of the sixth embodiment in fig. 17.

Best mode for carrying out the invention

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First embodiment

Fig. 1 is a principal part sectional view showing the configuration of a semiconductor device according to a first embodiment of the present invention.

As shown in fig. 1, the semiconductor device of the first embodiment includes a substrate 11 and a low-dielectric-constant material film 12 formed on the substrate 11. The substrate 11 and the low-dielectric-constant material film 12 constitute a base 10. The substrate 10 has rigidity capable of supporting the multilayer structure formed thereon. The surface of the low-dielectric-constant material film 12 forms a first surface of the substrate 10. The second surface of the base body 10 is formed by the inner surface of the substrate 11.

A semiconductor element layer including a MOS transistor 30 is fixed to a first surface of the base 10, that is, a surface of the low dielectric material film 12, by an adhesive film 13. The semiconductor element layer is composed of a MOS transistor 30, interlayer insulating films 14 and 15, and insulating films 16 and 17. A multilayer wiring structure 18 is further formed on the upper surface of the semiconductor element layer (on the insulating film 17).

A lower electrode 20 is formed on a second surface of the base 10, i.e., the inner surface of the substrate 11. The lower electrode 20 covers all or a portion of the inner surface of the substrate 11.

The low-dielectric-constant material film 12 of the substrate 10 is preferably formed of an insulating material having a low specific dielectric constant as much as possible in order to suppress parasitic capacitance. May be an organic insulating material, may be an inorganic insulating material, or may be a porous insulating material. Specifically, it is preferably made of a material having a specific dielectric constant (11.8) lower than that of silicon, high thermal conductivity, and low cost. The reason why the high thermal conductivity is desirable is to direct the heat generated from the MOS transistor 30 in the semiconductor element layer towardThe substrate 11 is highly conductive. Thus, the heat can be efficiently dissipated to the outside. As a material satisfying these 3 conditions (low specific permittivity, high thermal conductivity, and low cost), alumina (Al), for example, is preferable₂O₃) Or silicon carbide (SiC). Further, the diamond may have a low dielectric constant and a high thermal conductivity, although the cost is slightly higher than that of alumina and silicon carbide.

However, other materials may be used to form the low dielectric constant material film 12. For example, sapphire, aluminum nitride (AlN), various glasses, porous low dielectric constant plastics, etc. may also be used.

The substrate 11 of the base 10 is formed of a material that does not hinder the low-permittivity material film 12 from having such a characteristic of low permittivity as to support the low-permittivity material film 12 and the multilayer structure thereabove. Therefore, the substrate 11 may be formed of any insulator, semiconductor, or metal as long as it is a material having such characteristics.

In the present embodiment, the base 10 has a two-layer structure composed of the substrate 11 and the low dielectric constant material film 12, but the present invention is not limited to this configuration. The entire substrate 10 may be formed of a material used for the low-dielectric-constant material film 12 as long as a certain degree of rigidity is obtained. That is, the base 10 may also be formed only from the low-dielectric-constant material film 12. For example, as long as Al is used₂O₃SiC or diamond, the low dielectric constant material film 12 can be easily realized.

The thickness of the substrate 11 is arbitrarily set in a range of, for example, 1 μm to 300 μm as required. The thickness of the low-dielectric-constant material film 12 is arbitrarily set, for example, in the range of 0.1 μm to 50 μm as required. Therefore, flexibility (flexibility) can be imparted to the base 10 by setting the thicknesses of the substrate 11 and the low-dielectric-constant material film 12 to be small.

The MOS transistor 30 provided in the semiconductor element layer is formed of an island-type p-type single crystal silicon (Si) film 31. A pair of n electrodes formed at intervals in the silicon film 31⁺Type source electrodeIn the drain regions 32a and 32b, a gate insulating film 33 is formed on the surface (lower surface in fig. 1) of the silicon film 31. The gate insulating film 33 is located between the source and drain regions 32a, 32 b. A gate electrode 34 made of polycrystal is formed on the surface (lower surface in fig. 1) of the gate insulating film 33. The gate electrode 34 may be made of metal.

The back surface (upper surface in fig. 1) of the silicon film 31 is covered with an insulating film 16, and a second gate electrode 35 made of metal is formed on the insulating film 16. The second gate electrodes 35 have almost the same shape as the gate electrodes 34, and are arranged to coincide with each other. Therefore, the second gate electrode 35 is also located between the source-drain regions 32a, 32 b. The portion of the insulating film 16 located directly below the second gate electrode 35 functions as a gate insulating film.

A signal voltage is typically applied to the gate electrode 34. On the other hand, a signal voltage may be applied to the second gate electrode 35, or a predetermined fixed potential may be applied, similarly to the gate electrode 34.

The thickness of the island-type single crystal silicon film 31 is arbitrarily set in a range of, for example, 10nm to 100nm as required. The shape of the single crystalline silicon film 31 is generally rectangular, and the size thereof can be set appropriately so that the desired characteristics of the MOS transistor 30 can be obtained. The thickness of the gate insulating film 33 is arbitrarily set in a range of, for example, 1nm to 10 nm. The thickness of the gate insulating film 34 is arbitrarily set in a range of, for example, 50nm to 500 nm. The thickness of the second gate electrode is set almost the same as the thickness of the gate electrode 34, for example. As will be described later, the MOS transistor 30 is preferably formed using an SOI substrate.

The MOS transistor 30 having the above configuration is embedded in the stacked structure of the interlayer insulating film 15 and the insulating films 16 and 17. Therefore, the area (amount of use) of the single crystal silicon film 31 is extremely small compared to the case where the single crystal silicon substrate 41 is left.

The source/drain regions 32a and 32b of the MOS transistor 30 are electrically connected to the multilayer wiring structure 18 through connection holes 17a and 17b that vertically penetrate the insulating films 16 and 17. That is, via holes 17a and 17b are formed through the laminated insulating films 16 and 17, and conductive via cores 19a and 19b are filled therein, respectively. The connection cores 19a and 19b are made of a conductive material such as tungsten (W), aluminum (Al), or copper (Cu). One ends (lower ends in fig. 1) of the connection cores 19a, 19b are in contact with the source-drain regions 32a, 32b directly therebelow, respectively. The other ends (upper ends in fig. 1) of the connection cores 19a, 19b are in contact with the wiring electrodes 18a, 18b of the multilayer wiring structure 18 located near the surface of the insulating film 17, respectively. Then, the source/drain regions 32a and 32b of the MOS transistor 30 are electrically connected to the metal wiring 18c inside the multilayer wiring structure 18.

The gate electrode 34 and the second gate electrode 35 of the MOS transistor 30 are electrically connected to a wiring or a conductive film, not shown. The specific structure of the electrical connection is well known, and therefore, the description thereof will be omitted.

The adhesive film 13 for bonding the substrate 10 and the semiconductor circuit layer may be formed of any insulating adhesive and has a thickness of 0.1 μm to several μm. For example, an epoxy resin or a polyimide resin may be suitably used. The adhesive film 13 also preferably has a dielectric constant as low as possible.

The interlayer insulating film 14 may be formed of, for example, TEOS. The surface (lower surface in fig. 1) of the interlayer insulating film 14 is planarized.

The interlayer insulating film 15 is formed of, for example, BPSG, and embeds the entirety of the MOS transistor 30 except for the second gate electrode 35. The thickness of the interlayer insulating film 15 is, for example, 0.1 to 3 μm.

The insulating film 16 is included in an SOI substrate used when forming the MOS transistor 30, and is usually silicon dioxide (SiO)₂). However, the insulating film 16 may be formed later. The thickness of the insulating film 16 is arbitrary.

The insulating film 17 serves as an electrical insulation between the MOS transistor 30 and the multilayer wiring structure 18, and may be formed of any insulating material (e.g., BPSG, etc.). The thickness of the insulating film 17 is arbitrary.

The multilayer wiring structure 18 is a structure in which a plurality of metal wirings 18c are stacked via an insulating layer. This structure is well known, and a detailed description thereof will be omitted.

In the above configuration, the MOS transistor 30, and the interlayer insulating films 14 and 15 and the insulating films 16 and 17 in which the MOS transistor 30 is embedded constitute a "semiconductor element layer". And the multilayer wiring structure 18 constitutes a "wiring layer".

A method for manufacturing the semiconductor device of the first embodiment having the above-described configuration is described below with reference to fig. 2 to 8.

The structure shown in fig. 2 is first formed by known methods. Here, any SOI substrate is used, but the present invention is not limited thereto.

For example, a "bonded substrate" is prepared which is composed of the single crystal silicon substrate 41 and the single crystal silicon film 31 bonded to each other with the insulating film 16 interposed therebetween. Next, the single crystal silicon film 31 is selectively etched until reaching the insulating film 16, thereby defining an island-shaped element formation region having a substantially rectangular shape. Next, a gate insulating film 33 is selectively formed on a predetermined portion of the surface of the single crystal silicon film by a thermal oxidation method and an etching method. A polysilicon film is formed on the gate insulating film 33 and then etched to form a gate electrode 34. Thereafter, n-type impurities are selectively introduced into the single crystalline silicon film 31 by ion implantation using the gate electrode 34 as a mask, thereby forming a pair of source/drain regions 32a and 32 b. In this way, the MOS transistor 30 having the configuration shown in fig. 2 is formed on the insulating film 16.

It goes without saying that instead of the above-mentioned "bonding substrate", a so-called "SIMOX (Separation by IMplantation of Oxygen) substrate" or other similar substrates may be used.

Thereafter, an interlayer insulating film 15 is formed on the insulating film 16 so as to cover the entire MOS transistor 30, and an interlayer insulating film 14 is formed thereon.

Finally, the surface of the interlayer insulating film 14 is planarized by CMP (Chemical Mechanical Polishing) or etching. This results in the structure shown in fig. 2.

The method for obtaining the structure shown in fig. 2 described here is merely an example, and it is needless to say that a method other than the method described here may be used.

On the other hand, as shown in fig. 3, a low dielectric constant material film 12 having the above-described characteristics is formed as a base 10 on a substrate 11 formed of an insulator, a semiconductor, or a metal. After the low-dielectric-constant material film 12 is formed separately from the substrate 11, the low-dielectric-constant material film 12 may be adhered to the surface of the substrate 11 with an appropriate adhesive, or the low-dielectric-constant material film 12 may be directly formed and fixed on the surface of the substrate 11 by a CVD (Chemical Vapor Deposition) method or the like. The surface of the low-dielectric-constant material film 12 thus formed is planarized by an arbitrary method.

Next, an appropriate adhesive is applied to the surface of the low dielectric constant material film 12 to form an adhesive film 13. The state at this time is shown in fig. 3. In addition, the adhesive may be applied to the surface of the insulating film 14 in the state of fig. 2. Further, an adhesive may be applied to both surfaces of the low-dielectric-constant material film 12 and the insulating film 14.

When the low-dielectric-constant material film 12 itself has the adhesive ability, it is needless to say that the application of the adhesive film 13 can be omitted.

Next, the structure of fig. 2 is turned upside down, and the structure of fig. 3 is joined while aligning the positions, and the two are integrated as shown in fig. 4. That is, the interlayer insulating films 14 are bonded to each other through the adhesive film 13 via the planarized surface facing the planarized surface of the low-dielectric-constant material film 12 of the substrate 10. In this state, when the adhesive 13 is subjected to a predetermined curing treatment, the adhesive film 13 is cured, and the semiconductor element layer is bonded to the upper surface of the base 10. At this time, the substrate 11 is at the lowermost position and the silicon substrate 41 is at the uppermost position. Also, the MOS transistor 30 is upside down.

Next, the entire uppermost silicon substrate 41 is removed by grinding or etching, and the insulating film 16 is exposed as shown in fig. 5. Then, an appropriate metal film (e.g., W) is formed on the insulating film 16, and then patterned by etching, thereby forming the second gate electrode 35. The state at this time is shown in fig. 5.

The silicon substrate 41 is thus completely removed in the middle of the manufacturing process and may be referred to as a "sacrificial substrate".

Next, as shown in fig. 6, an insulating film 17 is formed on the insulating film 16 so as to cover the second gate electrode 35. The surface of the insulating film 17 is planarized by CMP or the like as necessary.

Then, as shown in fig. 7, connection holes 17a and 17b penetrating the insulating films 17 and 16 are formed by etching to expose the source and drain regions 32a and 32b (i.e., the back surface of the single crystal silicon film 31).

Next, a conductive film (not shown) having a thickness sufficient to fill the connection holes 17a and 17b is formed on the upper surface of the insulating film 17, and then the conductive film is selectively removed from portions other than the connection holes 17a and 17b by etching or CMP. Thus, as shown in fig. 8, connection cores 19a and 19b made of a conductive film are formed inside the connection holes 17a and 17b, respectively. As the conductive film, for example, a film of W, Al, Cu, or the like can be used.

Next, a multilayer wiring structure 18 including wiring electrodes 18a and 18b and metal wiring 18c is formed on the insulating film 17 by a known method.

Finally, a metal film of copper, aluminum, or the like is formed on the entire or a part of the bottom surface of the substrate 11 as the bottom electrode 20 by vapor deposition or plating. Thus, the semiconductor device of the first embodiment shown in fig. 1 can be obtained.

Alternatively, as shown in fig. 3, the bottom electrode 20 may be formed on the back surface of the substrate 11 in advance when the base 10 is formed of the substrate 11 and the low-dielectric-constant material film 12.

As described above, in the semiconductor device according to the first embodiment of the present invention, the semiconductor element layer including the MOS transistor 30 is formed on the surface of the base 10 including the low dielectric material film 12 having a dielectric constant lower than that of silicon, and the multilayer wiring structure 18 (wiring layer) is formed on the semiconductor element layer. The bottom surface of the substrate 10 forms a bottom electrode 20. Further, the MOS transistor 30 is formed with a very small single crystal silicon film 31 formed in an island shape, while being embedded in the inside of the interlayer insulating films 14 and 15 and the insulating films 16 and 17 formed in the semiconductor element layer.

Thus, the single crystal silicon film 31 which is conventionally used is used, and therefore, the cost is low, and the amount (area) of the single crystal silicon film 31 to be used is suppressed to the minimum necessary for forming the MOS transistor 30.

And the substrate 10 includes: a substrate 11 having a certain degree of rigidity, and a low-dielectric-constant material film 12 formed of a material having a lower specific dielectric constant than silicon.

Therefore, the method can adapt to the GHz-order working frequency at reasonable cost, and the integration level is not limited.

Further, since the bottom electrode 20 is formed on the bottom surface of the base body 10, the bottom electrode 20 forms a so-called "return path" for a signal transmitted through the metal wiring 18c of the multilayer wiring structure 18. Therefore, even if the wavelength of the signal to be processed becomes close to the wiring length with the increase in size of the semiconductor chip (i.e., the semiconductor device) or the increase in operating speed, the wavelength can be adapted to the wiring length.

In addition, in the semiconductor device of the first embodiment described above, the MOS transistor 30 has not only the (first) gate electrode 34 but also the second gate electrode 35, and therefore, as compared with the case where the second gate electrode 35 is not present, the change in the drain current, that is, the drive current can be increased. Thus, there is an advantage in that the operation speed can be increased as compared with the case without the second gate electrode 35.

Further, the second gate electrode 35 can cut off the spread of the drain electric field, and thus there is an advantage in that a leakage current caused by a short tunnel effect can be prevented from flowing therethrough when the MOS transistor 30 is in an off state.

Second embodiment

Fig. 9 is a principal part sectional view showing the constitution of a semiconductor device according to a second embodiment of the present invention.

The semiconductor device of fig. 9 corresponds to the case where the multilayer wiring structure 51 is added to the semiconductor device of the first embodiment. Therefore, in fig. 9, the same or corresponding elements are denoted by the same reference numerals as in the case of the semiconductor device of the first embodiment, and detailed description thereof will be omitted.

As shown in fig. 9, the multilayer wiring structure 51 is provided between the low-dielectric-constant material film 12 forming the base 10 and the interlayer insulating film 14, in other words, between the base 10 and the semiconductor element layer. The source/drain region 32a of one of the semiconductor element layer MOS transistors 30 is electrically connected to a predetermined wiring in the multilayer wiring structure 51. The multilayer wiring structure 51 is bonded to the low dielectric constant material film 12 with the adhesive film 13 on the surface thereof.

In the semiconductor device of the second embodiment, the MOS transistor 30, the interlayer insulating films 14, 15 in which the MOS transistor 30 is embedded, and the insulating films 16, 17 form a "semiconductor element layer". The multilayer wiring structure 18 forms a "first wiring layer". The multilayer wiring structure 51 forms a "second wiring layer".

The semiconductor device of the second embodiment having the above-described configuration can be manufactured in the same manner as in the case of the first embodiment.

That is, as shown in fig. 10 (this figure corresponds to fig. 2), the MOS transistor 30 is formed on the insulating film 16 formed on the silicon substrate 41 in the same manner as described in the first embodiment. Then, an interlayer insulating film 15 is formed on the insulating film 16 so as to cover the entire MOS transistor 30, and an interlayer insulating film 14 is formed thereon.

Next, a multilayer wiring structure 51 is formed on the interlayer insulating film 14 having the planarized surface by a known method. At this time, the source/drain region 32a of the MOS transistor 30 is electrically connected to a predetermined wiring in the multilayer wiring structure 51 through a connection core filled in a connection hole penetrating the interlayer insulating films 14 and 15. This method is the same as the case of the multilayer wiring structure 18, and therefore, the description thereof is omitted. Finally, the surface of the multilayer wiring structure 51 is planarized by a CMP method or an etching method.

On the other hand, as shown in fig. 3, after a base 10 composed of a substrate 11 and a low-dielectric-constant material film 12 is formed, the surface of the low-dielectric-constant material film 12 is planarized. Next, an appropriate adhesive is applied to the upper surface of the low dielectric constant material film 12 to form an adhesive film 13.

Next, the structure of fig. 10 is turned upside down, and joined to the structure of fig. 3 while aligning the positions, and the two are integrated as shown in fig. 11. That is, the multilayer wiring structure 51 is opposed to the flat surface of the low dielectric constant material film 12 through the flat surface, and is bonded to each other through the adhesive film 13. In this state, when the adhesive film 13 is subjected to a predetermined curing treatment, the adhesive film 13 is cured, and the semiconductor element layer is bonded to the upper surface of the base 10. At this time, the substrate 11 is at the lowermost position and the silicon substrate 41 is at the uppermost position. Also, the MOS transistor 30 is upside down.

Next, the entire silicon substrate 41 at the uppermost position is removed by etching to expose the insulating film 16. Further, as in the case of the first embodiment, after the second gate electrode 35 is formed on the insulating film 16, the insulating film 17 is formed on the insulating film 16. Then, the coupling holes 17a, 17b are formed and the cores 19a, 19b are coupled, respectively, by the same method as in the case of the first embodiment. Further, a bottom electrode 20 is formed on the entire or a part of the bottom surface of the substrate 11. Thus, a semiconductor device having the structure shown in fig. 9 can be obtained.

As described above, the semiconductor device according to the second embodiment of the present invention has substantially the same configuration as the semiconductor device according to the first embodiment, and therefore, the same effects as those of the semiconductor device according to the first embodiment can be obtained.

Third embodiment

Fig. 12 is a principal part sectional view showing the constitution of a semiconductor device according to a third embodiment of the present invention. The semiconductor device of fig. 12 corresponds to a case where the second gate electrode 35 of the MOS transistor 30 is omitted from the semiconductor device of the first embodiment. Therefore, in fig. 12, the same or corresponding elements are denoted by the same reference numerals as in the case of the semiconductor device of the first embodiment, and detailed description thereof will be omitted.

The semiconductor device according to the third embodiment of the present invention has substantially the same configuration as the semiconductor device according to the first embodiment, and thus it is apparent that the same effects as those of the semiconductor device according to the first embodiment can be obtained.

Further, in the semiconductor device of the third embodiment, the MOS transistor 30 does not have the second gate electrode 35, and therefore, there is an advantage in that the structure and the manufacturing process are simplified as compared with the first embodiment having the second gate electrode 35.

Fourth embodiment

Fig. 13 is a principal part sectional view showing the constitution of a semiconductor device according to a fourth embodiment of the present invention. The semiconductor device of fig. 13 is a semiconductor device of the third embodiment (see fig. 12) having no second gate electrode, in which the semiconductor element layer and the multilayer wiring structure are arranged in two stages, i.e., upper and lower. That is, it corresponds to a case where a "lower semiconductor element layer" composed of the MOS transistor 30, the interlayer insulating films 14, 15 and the insulating films 16, 17, and a "lower wiring layer" composed of the multilayer wiring structure 18 are formed on the base 10 in a stacked manner, and then an "upper semiconductor element layer" composed of the MOS transistor 30, the interlayer insulating films 14 ', 15 ' and the insulating films 16 ', 17 ', and an "upper wiring layer" composed of the multilayer wiring structure 18 ' are formed thereon in a stacked manner. Therefore, in fig. 13, the same or corresponding elements are denoted by the same reference numerals as in the case of the semiconductor device according to the third embodiment, and detailed description thereof will be omitted.

The semiconductor device according to the fourth embodiment of the present invention has substantially the same configuration as the semiconductor device according to the third embodiment, and it is therefore apparent that the same effects as those of the semiconductor device according to the third embodiment can be obtained.

The structure of the semiconductor device according to the fourth embodiment is equivalent to the case where the "upper semiconductor element layer" and the "upper wiring layer" are added and formed to the basic structure of the present invention composed of the base 10, the "lower semiconductor element layer" and the "lower wiring layer". However, the structure may be such that an "upper semiconductor element layer" is formed on the base 10 via a "lower semiconductor element layer" and a "lower wiring layer" and then an "upper wiring layer" is formed thereon, or such that a "lower semiconductor element layer" is directly formed on the base 10 and an "upper wiring layer" is formed thereon via a "lower wiring layer" and an "upper semiconductor element layer". In addition, it goes without saying that the "upper semiconductor element layer" and the "lower semiconductor element layer" can be electrically connected to each other as needed.

In fig. 13, the "upper semiconductor element layer" and the "lower semiconductor element layer" are directly bonded through the adhesive film 13', but the present invention is not limited thereto. For example, a low-dielectric-constant material film may be formed on the side of the "upper semiconductor element layer" or the side of the "lower semiconductor element layer", and the "upper semiconductor element layer" and the "lower semiconductor element layer" may be bonded together through the low-dielectric-constant material film and the adhesive film 13'. In this case, the adhesive film 13' may be omitted as long as the dielectric constant material film has adhesiveness.

In this way, the semiconductor device of the present invention is sufficient if a "semiconductor element layer" is formed directly on the base 10 or through another layer and a "wiring layer" is formed directly on the "semiconductor element layer" or through another layer.

Fifth embodiment

In the first to fourth embodiments described above, the semiconductor element layer in which the MOS transistor is formed is bonded to the base 10 upside down (i.e., with the gate electrode of the MOS transistor facing down), but the present invention is not limited thereto. The semiconductor element layers in which the MOS transistors are formed may be bonded without being turned upside down (i.e., with the gate electrodes of the MOS transistors facing upward). Fig. 14 shows an example of such a case.

Fig. 14 is a sectional view of an essential part showing a configuration of a semiconductor device according to a fifth embodiment of the present invention, in which a semiconductor element layer is disposed on an upper surface of a base 10 so that a gate electrode 34 of a MOS transistor 30 faces upward in the semiconductor device according to the third embodiment (see fig. 12) having no second gate electrode. Therefore, in fig. 14, the same or corresponding elements are denoted by the same reference numerals as in the case of the semiconductor device according to the third embodiment, and detailed description thereof will be omitted.

The semiconductor device according to the fifth embodiment can be manufactured through substantially the same steps as the semiconductor device according to the third embodiment, except for the step of forming the semiconductor element layer and the step of attaching the semiconductor element layer to the base 10. Therefore, referring to fig. 15 and 16, differences in manufacturing steps will be mainly described below.

After the structure shown in fig. 2 is first formed by a known method, a support substrate 24 is pasted to the planarized surface of the interlayer insulating film 14. As the support substrate 42, a plate of any material (for example, silicon, quartz, or the like) can be used as long as the structure of fig. 2 can be maintained. The state at this time is shown in fig. 15.

Then, the entire silicon substrate 41 is removed by a known polishing method or etching method while being held by the support substrate 42, thereby exposing the insulating film 16. Therefore, in the manufacturing method of the semiconductor device of the fifth embodiment, the silicon substrate 41 is also a "sacrificial substrate".

On the other hand, as described in the first embodiment, the base 10 including the substrate 11 and the low-dielectric-constant material film 12 is formed, and the adhesive film 13 is applied and formed on the surface of the low-dielectric-constant material film 12 (see fig. 3).

Next, a portion of the silicon substrate 41 removed from the structure of fig. 15 is aligned and bonded to the structure of fig. 3, and the two are integrated as shown in fig. 16. That is, the exposed surface of the insulating film 16 is opposed to the flat surface of the low dielectric material film 12 of the substrate 10, and is bonded to each other through the adhesive film 13. In this state, when the adhesive film 13 is subjected to a predetermined curing treatment, the adhesive film 13 is cured, and the semiconductor element layer is bonded to the upper surface of the base 10. At this time, the substrate 11 is in the lowermost position, and the support substrate 42 is in the uppermost position. While the orientation of MOS transistor 30 is not inverted, i.e., gate electrode 34 is located at the top. The state at this time is shown in fig. 16.

Next, the support substrate 42 at the uppermost position is entirely removed by grinding or etching, so that the interlayer insulating film 14 is exposed. Then, after forming the insulating film 17 on the upper surface of the interlayer insulating film 14, a connection hole 17c penetrating the insulating film 17 and the interlayer insulating films 14 and 15 is formed by etching, thereby exposing the gate electrode 34.

Next, after a conductive film (not shown) having a thickness enough to fill the connection hole 17c is formed on the insulating film 17, the conductive film is selectively removed at a portion other than the connection hole 17c by applying a reverse etching method or a CMP method. Thus, as shown in fig. 14, a connection core 19c made of a conductive film is formed inside the connection hole 17 c. As the conductive film, for example, a film of W, Al, Cu, or the like is used.

Next, on the upper surface of the insulating film 17, a multilayer wiring structure 18 including a metal wiring 18c and a wiring electrode 18d connected to the connection core 19c is formed by a known method.

Finally, a metal film of copper, aluminum, or the like is formed on the entire bottom surface of the substrate 11 by vapor deposition or plating, thereby forming the bottom electrode 20. Thus, the semiconductor device of the fifth embodiment shown in fig. 14 can be obtained.

In addition, as in the case of the third embodiment, the bottom electrode 20 may be formed on the back surface of the substrate 11 in advance when the base 10 is formed of the substrate 11 and the dielectric constant material film 12 as shown in fig. 3.

As described above, the semiconductor device according to the fifth embodiment of the present invention has substantially the same configuration as the semiconductor device according to the third embodiment, and it is apparent that the same effects as those of the semiconductor device according to the third embodiment can be obtained.

In the fifth embodiment, it goes without saying that the second gate electrode may be provided as needed. For example, the manufacturing method described with reference to fig. 15 and 16 can be easily implemented by adding a step of forming the second gate electrode 35 on the insulating film 16 after removing the silicon substrate 41 from the structure of fig. 15.

Sixth embodiment

Fig. 17 is a principal part sectional view showing the constitution of a semiconductor device according to a sixth embodiment of the present invention.

The semiconductor device of fig. 17 is a case where a body 10A having a function of an insertion-type selection finger is provided instead of the body 10 in the semiconductor device of the second embodiment. Therefore, in fig. 17, the same or corresponding elements are denoted by the same reference numerals as in the case of the semiconductor device according to the second embodiment, and detailed description thereof will be omitted.

The semiconductor device of the sixth embodiment has a plurality of buried wirings 61 penetrating through the substrate 11 forming the base 10A and the low-dielectric-constant material film 12 as shown in fig. 17. The upper end of each embedded wiring 61 is in contact with a corresponding wiring inside the multilayer wiring structure 51. The lower end of each embedded wiring 61 is in contact with the corresponding bottom electrode 20A. As a result, the substrate 10A and the bottom electrode 20A have a function of "insertion selection finger".

The semiconductor device of the sixth embodiment having the above-described configuration can be manufactured in the same manner as in the case of the second embodiment.

That is, as shown in fig. 10 (which corresponds to fig. 2), the MOS transistor 30 is formed on the insulating film 16 formed on the silicon substrate 41 in the same manner as described in the first embodiment. Then, an interlayer insulating film 15 is formed over the insulating film 16 so as to cover the entire MOS transistor 30, and an interlayer insulating film 14 is formed thereon.

Next, a multilayer wiring structure 51 is formed on the interlayer insulating film 14 having the planarized surface by a known method. At this time, the source/drain regions 32a and 32b of the MOS transistor 30 are electrically connected to predetermined wirings in the multilayer wiring structure 51 via connection cores filled in connection holes penetrating the interlayer insulating films 14 and 15. This method is the same as the case of the multilayer wiring structure 18, and therefore, the description thereof is omitted. Finally, the surface of the multilayer wiring structure 51 is planarized by a CMP method or an etching method.

On the other hand, as shown in fig. 3, after a base 10 composed of a substrate 11 and a low-dielectric-constant material film 12 is formed, the surface of the low-dielectric-constant material film 12 is planarized. Next, an appropriate adhesive is applied to the low dielectric constant material film 12 to form an adhesive film 13.

Next, the structure of fig. 10 is turned upside down, and joined to the structure of fig. 3 while aligning the positions, and the two are integrated as shown in fig. 18. That is, the multilayer wiring structure 51 is opposed to the flat surface of the low dielectric constant material film 12 through the flat surface, and is bonded to each other through the adhesive film 13. In this state, when the adhesive film 13 is subjected to a predetermined curing treatment, the adhesive film 13 is cured, and the semiconductor element layer is bonded to the upper surface of the base 10. At this time, the substrate 11 is at the lowermost position and the silicon substrate 41 is at the uppermost position. Also, the MOS transistor 30 is upside down.

Next, a plurality of through holes penetrating the substrate 10A are formed by etching, and then a conductive material such as tungsten (W) is embedded in the through holes to form embedded wirings 61. The upper end of each embedded wiring 61 is in contact with a corresponding wiring inside the multilayer wiring structure 51. The lower end of each embedded wiring 61 is exposed from the bottom surface of the substrate 11.

Then, a metal film of copper, aluminum, or the like is formed on the entire or partial bottom surface of the substrate 11 by vapor deposition or plating, and then patterned, thereby forming a plurality of bottom electrodes 20A. The state at this time is shown in fig. 18.

Next, the entire silicon substrate 41 at the uppermost position is removed by etching, so that the insulating film 16 is exposed. Then, as in the case of the first embodiment, after the second gate electrode 35 is formed on the insulating film 16, the insulating film 17 is further formed on the insulating film 16. Then, the connection holes 17a, 17b, the connection cores 19a, 19b are formed, respectively, by the same method as in the case of the first embodiment. Thus, a semiconductor device having the structure shown in fig. 17 can be obtained.

As described above, the semiconductor device according to the sixth embodiment of the present invention has substantially the same configuration as the semiconductor device according to the first embodiment, and therefore, the same effects as those of the semiconductor device according to the first embodiment can be obtained. Further, the body 10A and the bottom electrode 20A have a function of "insertion-type selection finger", so that there is an advantage in that an electric signal can be easily extracted from the inside of the semiconductor device.

Modification example

The first to sixth embodiments are preferable examples of the present invention, and the present invention is not limited to these embodiments, and various changes may be made.

For example, in the first to sixth embodiments, the base 10 is formed in a 2-layer structure of the substrate 11 and the low dielectric constant material film 12, but the present invention is not limited thereto. The substrate 10 may be formed only of the low-dielectric-constant material film 12. Note that, although only one MOS transistor 30 is formed in the semiconductor element layer, it goes without saying that a plurality of MOS transistors 30 may be formed as necessary, another semiconductor element may be included instead of the MOS transistor 30, or various semiconductor elements may be mixed together.

As described above, with the semiconductor device and the manufacturing method thereof of the present invention, it is possible to adapt an operating frequency in the order of GHz at a reasonable cost, while also having no limitation on the degree of integration. Furthermore, a substrate with a material having a lower specific dielectric constant than silicon can be used, accommodating operating frequencies in the order of GHz. Further, this has an effect that even if the wavelength of the signal to be processed approaches the wiring length with the enlargement of the scale of the semiconductor device (chip) or the improvement of the operation speed, it can be coped with.

Claims

1. A semiconductor device is characterized by comprising:

(b) a first semiconductor element layer formed directly or through another layer on the first surface of the base body, the first semiconductor element layer including a semiconductor element and an insulating film in which the semiconductor element is embedded;

(d) an electrode formed on the second surface of the base body and forming a return path for a signal transmitted through the first wiring layer,

the substrate, the first semiconductor element layer, and the first wiring layer constitute a three-dimensional laminated structure,

the semiconductor element of the first semiconductor element layer is formed using a semiconductor film formed in an island shape, and the size of the semiconductor film is defined to be a size capable of obtaining desired characteristics of the semiconductor element.

2. The semiconductor device according to claim 1, wherein the base body comprises a substrate made of an insulator, a semiconductor, or a metal having a low dielectric constant characteristic that does not hinder the low-dielectric-constant material film, the substrate having the low-dielectric-constant material film formed thereon.

3. The semiconductor device according to claim 1, wherein the base is formed only of the low dielectric constant material film.

4. The semiconductor device according to claim 1, wherein the insulating film in which the semiconductor element is embedded in the first semiconductor element layer is disposed to face the first surface of the base.

5. The semiconductor device according to claim 1, wherein a surface of the first semiconductor element layer opposite to the insulating film in which the semiconductor element is embedded is disposed to face the first surface of the base.

6. The semiconductor device according to claim 1, further comprising a second semiconductor element layer or a second wiring layer provided between the first surface of the base body and the first semiconductor element layer, wherein the second semiconductor element layer or the second wiring layer is formed on the first surface of the base body with the first semiconductor element layer interposed therebetween.

7. The semiconductor device according to claim 1, further comprising a second semiconductor element layer or a second wiring layer provided between the first semiconductor element layer and the first wiring layer, wherein the first wiring layer is formed over the first semiconductor element layer with the second semiconductor element layer or the second wiring layer interposed therebetween.

8. The semiconductor device according to claim 1, wherein the semiconductor element in the first semiconductor element layer is a field effect transistor formed in an island-type semiconductor film, and the field effect transistor has a first gate electrode formed on one side of the semiconductor film and a second gate electrode formed on the opposite side of the first gate electrode.

9. The semiconductor device according to claim 1, wherein the semiconductor element in the first semiconductor element layer is a field effect transistor formed in the island-type semiconductor film, and the field effect transistor has a first gate electrode formed on one side of the semiconductor film.

10. The semiconductor device according to claim 8, wherein the first gate electrode of the field-effect transistor is disposed on the base side with respect to the island-type semiconductor film.

11. The semiconductor device according to claim 9, wherein the first gate electrode of the field-effect transistor is disposed on the base side with respect to the island-type semiconductor film.

12. A method for manufacturing a semiconductor device, comprising the steps of:

(b) forming a semiconductor element over a sacrificial substrate by using a semiconductor film formed in an island shape;

(c) forming a first semiconductor element layer by covering the upper surface of the sacrificial substrate with the semiconductor element forming insulating film and burying the semiconductor element in the insulating film;

(d) bonding the first semiconductor element layer to the first surface of the base directly or with another layer interposed therebetween;

(e) removing the sacrificial substrate;

(f) forming a first wiring layer directly or with another layer interposed therebetween on a side of the first semiconductor element layer opposite to the base; and

(g) a step of forming an electrode on the second surface of the base, the electrode forming a return path for a signal transmitted through the first wiring layer,

in the step (b), the size of the semiconductor film is limited to a size that can obtain desired characteristics of the semiconductor element,

the substrate, the first semiconductor element layer, and the first wiring layer constitute a three-dimensional laminated structure.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the base used in the step (a) comprises a substrate made of an insulator, a semiconductor, or a metal having a low dielectric constant characteristic that does not hinder the low dielectric constant material film, the substrate having the low dielectric constant material film formed thereon.

14. The method for manufacturing a semiconductor device according to claim 12, wherein the base used in the step (a) is formed only of the low dielectric constant material film.

15. The method for manufacturing a semiconductor device according to claim 12, wherein in the step (d), the insulating film in which the semiconductor element is embedded in the first semiconductor element layer and the first surface of the base are bonded to each other so as to face each other.

16. The method for manufacturing a semiconductor device according to claim 12, wherein in the step (d), a surface of the first semiconductor element layer opposite to the insulating film in which the semiconductor element is embedded and the first surface of the base are bonded to each other so as to face each other.

17. The method for manufacturing a semiconductor device according to claim 12, wherein in the step (d), the first semiconductor element layer and the first surface of the base are bonded to each other with a second semiconductor element layer or a second wiring layer interposed therebetween.

18. The method for manufacturing a semiconductor device according to claim 12, wherein in the step (f), the first wiring layer is formed on a side of the first semiconductor element layer opposite to the base with a second semiconductor element layer or a second wiring layer interposed therebetween.

19. The method for manufacturing a semiconductor device according to claim 12, wherein the semiconductor element formed using the island-type semiconductor film in the step (b) is a field effect transistor having a first gate electrode formed on one side of the semiconductor film and a second gate electrode formed on the opposite side of the first gate electrode.

20. The method for manufacturing a semiconductor device according to claim 12, wherein the semiconductor element formed using the island-type semiconductor film in the step (b) is a field effect transistor having a first gate electrode formed on one side of the semiconductor film.

21. The method for manufacturing a semiconductor device according to claim 19, wherein in the step (d), when the first semiconductor element layer and the first surface of the base are bonded to each other, the first gate electrode of the field-effect transistor is disposed on the base side with respect to the island-type semiconductor film.

22. The method for manufacturing a semiconductor device according to claim 20, wherein in the step (d), when the first semiconductor element layer and the first surface of the base are bonded to each other, the first gate electrode of the field-effect transistor is disposed on the base side with respect to the island-type semiconductor film.

23. A semiconductor device is characterized by comprising:

(c) a first wiring layer formed directly on or through another layer above the first semiconductor element layer;

(d) a plurality of electrodes formed on the second surface of the base; and

(e) a plurality of embedded wirings formed through the substrate and in contact with the electrodes, respectively,

the semiconductor element of the first semiconductor element layer is formed of an island-type semiconductor film, and the size of the semiconductor film is defined to be a size capable of obtaining desired characteristics of the semiconductor element,

the substrate, the plurality of electrodes, and the plurality of embedded wirings function as an insertion-type selection finger.

24. The semiconductor device according to claim 23, wherein the base body comprises a substrate made of an insulator, a semiconductor, or a metal having a low dielectric constant characteristic that does not hinder the low-dielectric-constant material film, the substrate having the low-dielectric-constant material film formed thereon.

25. The semiconductor device according to claim 23, wherein the base is formed only of the low dielectric constant material film.

26. A method for manufacturing a semiconductor device, comprising the steps of:

(e) forming a plurality of embedded wirings penetrating the substrate;

(f) removing the sacrificial substrate;

(g) forming a first wiring layer directly or with another layer interposed therebetween on a side of the first semiconductor element layer opposite to the base; and

(h) forming a plurality of electrodes on the second surface of the base, the electrodes being in contact with the plurality of buried wirings,

the substrate, the plurality of electrodes, and the plurality of buried wirings function as an interposing option finger,

in the step (b), the size of the island-shaped semiconductor film is limited to a size that can obtain the desired characteristics of the semiconductor element, thereby suppressing propagation delay of a signal caused by the semiconductor film,

27. The method for manufacturing a semiconductor device according to claim 26, wherein the base used in the step (a) comprises a substrate made of an insulator, a semiconductor, or a metal having a low dielectric constant characteristic which does not hinder the low dielectric constant material film, the substrate having the low dielectric constant material film formed thereon.

28. The method for manufacturing a semiconductor device according to claim 26, wherein the base used in the step (a) is formed only of the low dielectric constant material film.