HK1074290B - Method and apparatus for processing paging indicator bits transmitted on a quick paging channel - Google Patents

Description

Method and apparatus for processing paging indicator bits transmitted on a quick paging channel

RELATED APPLICATIONS

The present application claims the benefit of U.S. provisional application serial No. 60/235,416 entitled "Method of Processing Quick Paging Channels (QPCH) Paging Indicators (PI) Bits", filed on 26/9/2000, which is incorporated herein by reference.

Background

FIELD

The present invention relates to data communications, and more particularly to techniques for processing data, such as paging indicator bits on a quick paging channel, sporadically transmitted at designated times on a code channel.

Background

Terminals in wireless (e.g., cellular) communication systems are typically designed to operate in one of several modes, such as active and standby, at any given moment. In the active mode, the terminal can actively exchange data (e.g., for voice or data calls) with one or more base stations. In standby mode (also called idle mode), the terminal typically monitors the paging channel for messages addressed to the terminal, including messages informing the terminal of an incoming call (i.e., paging message) and updating the terminal's system parameters (i.e., overhead messages).

During the idle mode, the terminal continues to consume power to support the circuitry needed by the circuitry to monitor the signals transmitted from the base station. Many terminals, such as cellular telephones, are portable and powered by internal batteries. The power consumption of the terminal in idle mode reduces the available battery resources and thus reduces the "standby" time between battery recharging and the "talk" time of making or receiving a call. Therefore, to extend battery life, it is highly desirable to minimize power consumption of the terminal in idle mode.

In one technique to reduce idle mode power consumption, messages on the paging channel are sent to the terminal (if any) at specified times. For IS-95 and cdma2000 systems, the paging channel IS divided into numbered "time slots" and a terminal may be assigned one or more time slots by the base station with which it has established communication. In such a slotted paging channel, the terminal periodically, rather than continuously, monitors the paging channel for messages from the base station. The terminal wakes up from the inactive state before its assigned slot, enters the active state and processes the paging channel for messages, and returns to the inactive state if no further communication is required. The terminal remains active (also referred to as "awake") if the received message requires the terminal to perform other actions. In the period between successive active states, the terminal is in the inactive state and the base station does not send messages to it.

In another technique to further reduce idle mode power consumption, a Quick Paging Channel (QPCH) is used to indicate whether or not to transmit paging messages to the terminal on the paging channel. The quick paging channel includes a plurality of paging indicator bits transmitted as binary on/off bits. For each (80 ms) QPCH slot, two page indicator bits are assigned to each terminal, and the location of the assigned page indicator bits is determined by a hash function. The paging indicator bits can be detected more quickly and if the bits indicate that no message is to be transmitted to the terminal on the paging channel, the terminal can go to sleep without having to process the paging channel.

In the inactive state, power is typically reduced to save power for as many circuits as possible, which may de-power some analog circuits (e.g., RF circuits) and turn off the clocks for some digital circuits. During sleep, only the precision oscillator, sleep timer, and some other necessary circuitry remain active.

To handle the active paging channel, the terminal acquires and synchronizes with the timing of the transmitting base station. During reacquisition of the initial portion of the active state, the terminal typically searches for strong signal instances (or multipaths) in the received signal and acquires the timing and frequency of each multipath found to be of sufficient strength. The timing is typically derived from the phase of a (complex) pseudo-random number (PN) sequence used to spread the data at the base station.

It usually takes a long time to search the entire PN code space for strong multipaths comprehensively, but if the terminal wakes up from sleep without knowing the timing of the multipaths, a comprehensive search is required. To reduce the need for a full search, the digital circuit is typically turned off for a delicate time such that when the clock is later gated to wake-up, the timing of the circuit substantially aligns with the system timing.

For IS-95 and cdma2000 systems, the data frames are interleaved within 20 milliseconds, and the duration of the PN sequence IS 26.67 milliseconds. The shortest period of (20 ms) frame timing in combination with (26.67 ms) PN timing is 80 ms, covering four frames and three PN sequences. If the sleep duration is chosen to be an integer multiple of 80 milliseconds, then the timing is approximately aligned with the system timing when the terminal wakes up from sleep, and only an integer number of frames and PN sequences have elapsed since the terminal went to sleep. By using approximately the correct wake-up timing, multipath can be detected with only limited searching, and thus the sleep duration is typically chosen to be an integer multiple of 80 milliseconds or the least common multiple of frame and PN timing.

A coarse increment of 80 milliseconds in sleep duration limits the ability of the terminal to quickly go into and out of sleep. The terminal must spend more active time processing the required channel. Since the active state typically consumes many times more power than the inactive state, reducing the amount of time spent in the active state directly and significantly improves standby time.

Accordingly, there is a need in the art for techniques to more efficiently process sporadically transmitted data (e.g., page indicator bits on a quick paging channel) to reduce power consumption.

Disclosure of Invention

Aspects of the present invention provide techniques for handling sporadic (if any) data transmissions at specified time instances, such as Paging Indicator (PI) bits on a Quick Paging Channel (QPCH) and paging messages on a Paging Channel (PCH) in cdma2000, in a wireless communication system. The techniques described herein support sleep cycles that start at any time and whose sleep duration may be selected in fine time increments (or "sleep time limits"). As an example design described below, the sleep period may be selected to be 512PN chips (416.6 microseconds in cdma 2000).

Techniques are described herein to ensure that proper timing is maintained for the finger processor and symbol combiner of a rake receiver that is typically used to demodulate a received signal in a CDMA system. In one aspect, the sleep time period may be selected to be an integer multiple of the symbol buffer size for the symbol combiner and an integer multiple of the PN phase shift that may be obtained by "masking". The sleep time period ensures that the finger processor and symbol combiner are easily moved to the correct position after waking up from sleep. Various techniques are also provided necessary to align the symbol combiner timing to the timing of a particular multipath in the received signal, if desired.

In a particular application, the techniques described herein facilitate detecting PI bits transmitted on a QPCH. Since the sleep duration can be selected in relatively fine increments (e.g., integer multiples of 512PN chips) and the start of falling asleep and waking up at any time, the terminal can fall asleep between a pair of assigned PI bits within the same QPCH slot or between an assigned PI bit and the start of a PCH slot. Because the single PI bit can be awakened and processed, the power consumption can be reduced, and the standby time can be prolonged.

The techniques described herein may be used for various CDMA and wireless communication systems such as IS-95, CDMA2000, and W-CDMA, among others.

The invention also provides methods, apparatus (e.g., terminals), and other elements that can implement various aspects, embodiments, and features of the invention, as described in detail below.

Brief description of the drawings

The features, nature, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like characters represent corresponding parts throughout the drawings, wherein:

FIG. 1 is a diagram of a wireless communication system with multiple base stations and terminals;

fig. 2 is a simplified block diagram of an embodiment of a base station and a terminal;

FIG. 3 is a block diagram of an embodiment of a rake receiver and sleep circuitry;

fig. 4 is a diagram of a Quick Paging Channel (QPCH) and a Paging Channel (PCH) as specified by cdma 2000;

FIGS. 5A-5C are PN circle diagrams showing received signals before sleep, after awakening from sleep, and after reacquisition after awakening, respectively;

FIG. 6 illustrates read and write timing of a symbol buffer within a rake receiver;

FIG. 7 is a timeline diagram of processing a QPCH and a PCH in an embodiment of the present invention;

FIG. 8 is a diagram of a sleep cycle;

FIG. 9 is a process flow diagram for sleep; and

FIG. 10 is a flowchart of a process for detecting PI bits on the QPCH, in accordance with one embodiment of the present invention.

Detailed Description

Fig. 1 is a diagram of a wireless communication system 100 in which various aspects and embodiments of the invention may be implemented. The system 100 includes a plurality of base stations 104 that may cover a plurality of regions 102. A base station is also known as a Base Transceiver System (BTS) or access point, and the base station and/or its coverage area are also commonly referred to as a cell. System 100 IS designed to implement one or more CDMA standards, such as IS-95, CDMA2000, IS-856, and W-CDMA, and/or some other standard.

As shown in fig. 1, terminals 106 are dispersed throughout the system. In an embodiment, each terminal 106 may communicate with one or more base stations 104 on the forward and reverse links at any given moment, depending on whether the terminal is active and in soft handoff. The forward link (i.e., downlink) refers to base station to terminal transmissions, and the reverse link (i.e., uplink) refers to terminal to base station transmissions.

In the example of fig. 1, on the forward link, base station 104a transmits terminal 106a, base station 104b transmits to terminals 106b, 106c, and 106i, base station 104c transmits to terminals 106d and 106f, and so on. In fig. 1, the solid line with arrows represents the transmission of user-specific data from the base station to the terminal. The dashed line with arrows indicates that the terminal is receiving pilot and other signaling (e.g., paging indicator bits, paging messages) from the base station, but no user-specific data transmission. For simplicity, fig. 1 does not show reverse link communications.

Fig. 2 is a simplified block diagram of one embodiment of a base station 104 and a terminal 106, which are capable of implementing various aspects and embodiments of the present invention. On the forward link, at base station 104, a transmit (Tx) data processor 214 receives different types of traffic, such as user-specific data from a data source 212, messages (e.g., paging messages, page indicator bits) from a controller 230, and so on, and then formats and encodes the data and messages in one or more coding schemes to provide coded data. The various coding schemes include any combination of Cyclic Redundancy Check (CRC), convolutional, Turbo, block, and other coding methods, or no coding at all. Different classes of traffic are typically encoded with different coding schemes.

A Modulator (MOD)216 then receives the pilot data and coded data from the Tx data processor 214 and further processes the received data to generate modulated data. For IS-95 and cdma2000 systems, the processing by modulator 216 includes (1) covering the coded data and pilot data with Walsh codes to channelize the user-specific data, messages, and pilot data onto their respective code channels, and (2) spreading the channelized data with a (complex) pseudo-random number (PN) sequence having a particular PN offset assigned to the base station. The modulated data is then provided to a transmitter unit (TMTR)218 that conditions (e.g., converts to one or more analog signals, amplifies, filters, and quadrature modulates) to generate a forward modulated signal, which is transmitted via an antenna 220 and over a wireless link to the terminals.

At terminal 106, the forward modulated signal is received by an antenna 250 and provided to a receiver unit (RCVR)252 that processes (e.g., filters, amplifies, frequency downconverts, and digitizes) the received signal and provides data samples. A demodulator (DEMOD)254 then receives and processes the data samples to provide recovered symbols. For IS-95 and cdma2000 systems, the processing by demodulator 254 includes (1) despreading the data samples with the same PN sequence used to spread the data at the base station, (2) decovering the despread samples to channelize the received data and message onto their respective code channels, and (3) coherent demodulation of the channelized data with pilots recovered from the received signal. Demodulator 254 may implement a rake receiver that can process multiple signal instances in the received signal, as described below.

A receive (Rx) data processor 256 then receives and decodes the symbols from demodulator 254 to recover the user-specific data and messages transmitted on the forward link. For uncoded data, such as the page indicator bits on the quick paging channel, the recovered symbols from demodulator 254 constitute recovered data. The processing by the demodulator 254 and the Rx data processor 256 is complementary to the processing by the modulator 216 and the Tx data processor 214, respectively, of the base station 104.

Fig. 3 is a block diagram of an embodiment of a rake receiver 254a that is capable of receiving and demodulating forward modulated signals transmitted from one or more base stations. Rake receiver 254a includes a plurality of finger processors 310, a searcher 312, and a symbol combiner 330. Rake receiver 254a may be used to implement demodulator 254 of fig. 2.

Due to the multipath environment, a forward modulated signal transmitted by a base station arrives at a terminal via multiple signal paths, and thus the signal received by the terminal includes multiple instances of the forward modulated signal from each of one or more transmitting base stations. Each instance (or multipath) in the received signal is typically associated with a particular amplitude, phase, and time of arrival.

Receiver unit 252 conditions (e.g., filters and amplifies) the received signal, quadrature downconverts the conditioned signal, digitizes the downconverted signal to provide data samples, and provides the data samples to a plurality of finger processors 310 and a searcher 312.

The searcher 312 is used to search for strong multipaths in the received signal indicating the strength and timing of each found multipath in accordance with a set of criteria. The searcher 312 may be designed with one or more search elements, each designed to search for multipaths over a respective code space or search window. To speed up the search operation, the search cells may be operated in parallel. Each finger processor 310 is then assigned to process the respective multipath (e.g., multipath of sufficient strength as determined by the main controller 260 based on the signal strength information provided by the searcher 312).

Within each assigned finger processor 310, the data samples are provided to a PN despreader 322 which also receives from a PN generator 326 a (complex conjugate) PN sequence corresponding to the PN sequence used at the base station with an offset ti corresponding to the time of arrival of the ith multipath being processed by the finger processor. PN despreader 322 then despreads the data samples with a locally generated PN sequence to provide despread samples.

To recover the data on a particular code channel, a decover/data demodulator 324 first decovers (i.e., multiplies) the despread samples with the Walsh code also used for that code channel and then accumulates the decovered data samples over the length of the Walsh code to provide data symbols. To recover the pilot, the despread samples are decovered using the Walsh code that was also used for pilot channelization, accumulated and filtered over a particular accumulation time interval to provide a pilot estimate. Decover/data demodulator 324 then demodulates the data symbols with the pilot estimates to produce demodulated symbols, which are provided to a symbol buffer 332 associated with the finger processor.

Finger counters 328 within each finger processor 310 are used as write address generators for associated symbol buffers 332. Finger counter 328 may be implemented as a wrap-around counter that counts PN sequencesLength (2 for IS-95 and cdma 2000)¹⁵) And then "flip" or "wrap around" each time the end of the PN sequence is reached. Finger counter 328 is reset with the same PN chip offset (corresponding to the PN chip offset of the assigned multipath) fed to PN generator 326, incrementing the counter by 1 for each PN chip. The output of finger counter 328 is used as a write index or address for associated symbol buffer 332.

Each symbol buffer 332 receives and temporarily stores demodulated symbols from the correlation finger processor 310, the size of which is selected based on various factors, such as the worst expected delay spread between the earliest and latest arriving multipaths. In one particular implementation, each buffer 332 is configured as a circular buffer capable of storing 8 symbols, although other buffer sizes may be used and are within the scope of the invention. If each data symbol is generated by accumulating the decovered data samples for 64 PN chips, the 8-symbol buffer size effectively covers a time period of 512PN chips.

Since each multipath has a different propagation delay and arrival time, symbols from the assigned finger processor 310 with the same index are written to the correlation symbol buffer 332 at different times. At each chip time, symbols with the same index from all buffers 332 of the assigned finger processor 310 are sent to an adder 334 to be combined, thus also referring to the buffers 332 as "deskew" buffers.

A combination counter 336 is used as a read address generator for symbol buffer 332 and is also implemented as a wrap around counter that counts integer multiples of both frame and PN timing (e.g., 80 milliseconds) and then wraps around. The combination counter 328 is delayed by a particular number of PN chips (e.g., 256 or 384 PN chips) from a particular finger counter 328 (e.g., the finger counter assigned to the finger processor for the earliest arriving multipath). The output of the combination counter 336 is used as a read index or address for the buffer 332.

Adder 334 receives and combines the time-aligned symbols from symbol buffer 332 with the same index for each chip time to provide a recovered symbol. The Rx data processor 256 then receives and deinterleaves and decodes the recovered symbols from the adder 334 to provide decoded data and messages. Pilot demodulation and symbol combining is described in U.S. patent No.5,764,687, the contents of which are incorporated herein by reference.

Symbol combiner 330 also typically maintains a system time for the terminal. The symbol combiner timing is found by a combination counter 336 that is slowly adjusted or abruptly "turned off" (i.e., reset) based on the timing of the assigned finger processor 310, as described below.

The main controller 260 is designed to direct the demodulation and decoding process and control hardware sleep. If no processing of any code channels is required, the master controller 260 may send a sleep command to the sleep controller 364 and correspondingly send a value to the sleep counter 362 indicating the sleep duration. Sleep controller 364 then starts sleep counter 362, and also generates various control signals that cause various hardware elements to fall asleep. For example, the sleep controller 364 may send a disable signal to the clock generator 366 commanding the clock to be turned off, and may also send a next electrical signal to some of the analog components in the receiving unit 252. By using the oscillator 368 as a precision clock source, the sleep counter 362 counts down the sleep duration and sends a wake-up signal upon reaching the count-down value. The sleep controller 364 and the clock generator 366 receive the wake-up signal, power up the analog circuits, and restart the clocks, respectively.

The inventive techniques described herein may generally be used to process data sporadically transmitted in any type of wireless communication system. For clarity, various aspects and embodiments of the present invention are described with particular reference to the quick paging channel and the paging channel in cdma 2000.

Fig. 4 is a diagram of a Quick Paging Channel (QPCH) and a Paging Channel (PCH) specified by cdma 2000. The PCH is used to transmit paging messages to terminals in standby mode, and since paging messages are relatively long and may occur at any time, continuously monitoring the PCH for paging messages can significantly consume battery power in standby mode. The QPCH and PCH are therefore designed to make the terminal active for only a portion of the time to receive paging messages.

In cdma2000, the paging channel is divided into a number of PCH slots, each slot having a duration of 80 milliseconds. Each PCH slot is further divided into four 20-millisecond frames. Each PCH slot is assigned a set of terminals based on some identification information of the terminal, such as the terminal's unique international mobile subscriber id (imsi), Mobile Identification Number (MIN), Electronic Serial Number (ESN), or temporary mobile subscriber id (tmsi). The paging channel is used to transmit encoded messages to "idle" terminals, i.e., terminals that are logged on to the system but are in standby mode.

In cdma2000, the quick paging channel is divided into QPCH slots, each of which is also 80 milliseconds in duration. Each QPCH slot is further divided into four frames labeled A, B, A 'and B', with each frame including 96 or 192 Paging Indicator (PI) bits depending on whether the QPCH is used at a rate of 9.6kbps or 19.2 kbps. Each PI bit is an on/off keying bit (i.e., a "0" or "1" bit value, 0 off, 1 on). For each assigned QPCH slot, two PI bits are assigned to each logged in terminal, the assigned QPCH slot being the slot starting 100 milliseconds before the assigned PCH slot. The position of each assigned PI bit is determined by a prescribed hash function and varies from bit to bit. In each assigned pair of PI bits of the QPCH slot, one PI bit is transmitted in frame a and a second PI bit is transmitted in frame a ', or one PI bit is transmitted in frame B and a second PI bit is transmitted in frame B'. This transmission scheme may ensure that two PI bits are separated by at least 20 milliseconds and that the second and following PI bit arrives at least 20 milliseconds before the start of the PCH associated with the QPCH slot. The PI bits sent to the terminal may be considered a type of data that is sporadically transmitted at a given time.

The QPCH is used with the PCH and functions like a control channel for the PCH. Each QPCH slot is associated with a corresponding PCH slot but is transmitted 100 milliseconds before the associated PCH slot. The PI bit on the QPCH is a quick paging signal that tells the terminal to prepare to transmit an encoded paging message on the PCH within the relevant PCH slot.

When the base station sends a page to the terminal on the PCH (or requires the terminal to wake up to receive new configuration information), the base station turns "on" the two PI bits allocated to the terminal in the QPCH slot. Since more than one terminal may hash and be assigned to any given PI bit, detecting the assigned PI bit as "on" does not guarantee that the terminal will actually receive paging messages (i.e., configuration information) in the associated PCH slot. However, the PI bit detected as an "off bit may be interpreted to indicate that the terminal does not need to process the associated PCH slot for paging or other information, which may significantly reduce power consumption since the paging message is encoded and long.

In order to correctly process QPCH, PCH or any other code channel that is spread by the PN sequence before transmission, the terminal needs to acquire the timing of the processed multipath. A common implementation is to correlate the data samples of the received signal with a locally generated PN sequence at each chip or sub-chip offset. If the locally generated PN sequences are aligned in time with the multipath PN sequences, high correlation values are obtained. A finger processor may be assigned to process the multipath and then track the timing of the multipath as it shifts over time (e.g., due to changing link conditions).

As mentioned above, the clocks of the demodulator and decoder hardware are typically turned off while the terminal is asleep. When the terminal wakes up and then re-clocks, the timing of the demodulator and decoder hardware may not be aligned with the timing of the multipath without care being taken to select the sleep duration. For example, when the decoder and demodulator hardware is turned back on, the finger processors (i.e., PN generator and finger counters), the searcher, the symbol combiner (i.e., combination counter), and the deinterleaver may be misaligned. Also, if the sleep duration is not an integer multiple of the PN sequence length, the correlation of the data samples with the locally generated PN sequence may get low values due to timing misalignment.

The sleep cycle also typically starts at a tightly defined boundary, such as the PN flip that occurs in the symbol combiner. The PN sequence used to spread the data prior to transmission has a fixed length (e.g., 32768 chips), but repeats itself to generate a continuous spreading sequence. "PN flip" refers to the PN sequence repetition (i.e., the PN sequence resumes at the first PN chip index 0 after encountering the last PN chip index 32767). For IS-95 and cdma2000, PN flips occur every 26.67 milliseconds. As commonly used in the art, "sleep cycle" refers to the entire sleep process, including the ability to wake up periodically without having to turn on the receiver, demodulator and decoder hardware in order to check for external events such as key presses, connection and disconnection to car kits, headsets, computers, etc.

The sleep duration is typically chosen to be an integer multiple of both the frame timing and the PN timing. For cdma2000, it is 80 milliseconds, and is the duration of four data frames or three PN sequences. By employing sleep durations that are integer multiples of 80 milliseconds, the demodulator and decoder hardware is not affected by turning off the clock and remains substantially aligned with the PN sequence and deinterleaver framing despite being turned off while sleeping. Specifically, for such sleep durations, the values of counters 328 and 336 and PN generator 326 approximately coincide with the timing of the signal received immediately after waking from sleep. However, such 80 ms coarse increments in sleep duration limit the ability of the terminal to effectively sleep. This sleep duration increment is also referred to as a "sleep time limit".

A recently developed "1/4 flip timeline" may assign four finger processors to multiple PN sequences that are offset from each other by 1/4PN sequence lengths (i.e., 6.67 milliseconds), resulting in one of the four finger processors flipping over its PN sequence every 6.67 milliseconds. Thus, the symbol combiner can "close" the PN flip of one of the finger processors and then align the symbol combiner timing with that of the finger processor. Also, sleep controller 364 may be set to begin sleep when the PN flip "close" to the finger processor is active. This "close-sleep" technique reduces the sleep time limit to 6.67 milliseconds. However, it is still required to initiate sleep cycles on strictly defined boundaries, such as PN flips of the symbol combiner.

Aspects of the present invention provide techniques to process any channel so that data can be transmitted sporadically (if at all) at known times. These techniques facilitate processing of the PI bit on the QPCH and paging messages on the PCH in cdma 2000. The techniques described herein support sleep cycles that can start at almost any time and the sleep duration can be selected in fine sleep time limits, as the sleep time limit can be selected as 512PN chips (416.6 microseconds in cdma 2000) for the design example described below, or even smaller values for some other designs.

As described above, the two PI bits assigned to a terminal are transmitted within an 80 ms QPCH slot but are separated by at least 20 ms, with the second PI bit being transmitted 20-60 ms before the start of the associated PCH slot. Also, depending on whether a rate of 19.2kbps or 9.6kbps is used for the QPCH, the two PI bits are only 104.2 or 208.3 microseconds each. If a sleep time limit of 80 ms is used for the sleep duration, the terminal is required to wake up for the entire QPCH slot in order to decode both PI bits. If a sleep time limit of 26.67 milliseconds or 6.67 milliseconds is used for the sleep duration, the time period is still long relative to the short duration of the PI bit. If even shorter sleep periods are used, such as a sleep period in which the terminal can wake up long enough to just detect the PI bit, a large amount of battery power can be saved.

To support small sleep time periods, various timing assumptions are proposed. First, the sleep period is chosen so that the finger processor and searcher can be quickly moved to the correct PN phase when the terminal wakes up from sleep. Second, the sleep time limit is selected so that the symbol combiner can be quickly moved to the correct position. These two aspects are detailed below.

Searcher and finger timing

Fig. 5A is a circumferential diagram showing the entire code space of the PN sequence. The PN sequence has a particular data pattern and a fixed length of 32768 chips, each of which is assigned a respective PN chip index. The beginning of the PN sequence is assigned PN chip index 0 and its last chip is assigned PN chip index 32767. The PN sequence can be considered to lie on the circle 510, which begins to align with the top of the circle (i.e., the PN index 0 is located at the position pointed by the line 512). Although not shown in fig. 5A, the circle 510 is divided into 32768 equally spaced points, each corresponding to a respective PN chip index. Moving around the PN circle in a clockwise direction along the circle 510, the length of the PN sequence may be traversed.

As shown in fig. 5A, the received signal 520 includes a plurality of multipaths, represented as peaks in the signal, each multipath being associated with a respective time of arrival at the terminal. To find a particular multipath, the data samples of the received signal are correlated with a locally generated PN sequence at each chip or sub-chip offset. Due to the pseudo-random nature of the PN sequence, the correlation of the data samples with the PN sequence is low, unless the phase of the locally generated PN sequence is aligned with the phase of the multipath, which can yield a high value. The range of tile offsets to be searched forms a search window. In the example of fig. 5A, four multipaths are found in the received signal and four finger processors are assigned to process these multipaths. The timing of the earliest arriving multipath is typically used as the system time for the terminal.

As also shown in fig. 5A, the symbol combiner position is offset from the position of the earliest arriving multipath by a certain number of PN chips, represented by arrow 514. Such an offset between the symbol combiner position and the earliest arriving multipath position may be, for example, 256 or 384 PN chips, a scale not shown in fig. 5A.

Fig. 5B is a PN circle diagram after waking up from sleep. When the sleep duration is not an integer multiple of the PN sequence length (i.e., not a multiple PN roll over), then the multipath moves around the PN circumference in proportion to the fractional PN roll over portion of the sleep duration relative to the timing of the finger processor. In the example of fig. 5B, the sleep duration is (L +1/4) PN flips, L being an integer. Thus, the multipath is offset by 1/4PN flips (i.e., fractional parts), 1/4 counterclockwise on the PN circle.

Fig. 5C is a diagram of the PN cycle after the processor has awakened from sleep, shifted to its correct PN phase to compensate for the fractional PN flip portion of the sleep duration. To compensate for the offset in multipath due to the sleep duration of the fractional PN flip, the PN generator and finger processor in the searcher may be offset by the same amount and direction as the fractional PN flip (e.g., 1/4 counterclockwise on the PN circle for the example of fig. 5B). This PN phase shift may be achieved by "rotation", "masking", or a combination of both.

When the rotation method is used, the LSSR used to generate the PN sequence can be shifted in the forward or reverse direction by manipulating a clock applied to a Linear Sequence Shift Register (LSSR). For example, if the LSSR operates at the chip rate, the LSSR may skip a clock pulse and go one PN chip back, and go one PN chip forward (i.e., clock the LSSR twice) by inserting an additional clock pulse. In one embodiment, the terminal is designed to turn the finger processor to any position on the PN circle within a specified period of time (e.g., about 2 milliseconds), turn the finger processor to the correct position within a relatively short period of time, and then properly locate the PN flip.

When masking IS used, the LSSR generated "master" PN sequence IS provided to a masking circuit that also receives an N-bit mask, N being 15 for IS-95 and cdma 2000. The masking circuit then generates a shifted PN sequence whose phase is offset from the phase of the received PN sequence by an amount determined by the value of the applied mask. In this way, the masking method can be used to effectively "jump" the phase of the main PN sequence to a new phase. The LSSR and masking circuit may be implemented as described in U.S. patent No.5,228,054, the contents of which are incorporated herein by reference.

A mask may be generated to provide any increment of PN phase shift. However, since the PN sequences assigned to the base stations in cdma2000 systems are offset in phase from each other by integer multiples of 64 PN chips, it is common to store PN sequences that produce a separation of 64 PN chips for shifting the PN sequence to a desired phase. A mask is also stored that can shift the PN sequence by increments less than 64 PN chips (e.g., 32, 16, or 8 PN chips). However, each halving of the increment size (e.g., from 64 chips to 32 PN chips) requires twice as much masking and almost twice as much storage.

To provide a PN sequence of any desired phase in less time, a combination of masking and rotation can be used, with the masking being used to adjust the phase of the PN sequence in coarse increments (e.g., 64 PN chip increments) and then rotation being used to adjust the PN phase to the desired phase in fine increments (e.g., 1/8 PN chip increments). Thus, the masking method is advantageous for compensating for large phase adjustments, which would otherwise take more time with the rotation method.

In one embodiment, to avoid the need to rotate the PN generator to the correct PN chip offset after waking from sleep, the sleep duration is chosen to be an integer multiple of the masking increment (e.g., a multiple of 64 PN chips).

In one embodiment, a rotation method may be applied to the finger processor and a masking method may be applied to the searcher to obtain the following benefits.

Symbol combiner timing

As described above, the symbol combiner may provide the terminal with the system time, the timing of which is typically derived from the earliest arriving multipath. The combination counter may provide symbol combiner timing and adjust slowly or shut down abruptly based on that timing or the particular finger processor. Here "turn off" is the resetting of the (typically 80 ms) symbol combiner timing to a known reference time (to zero or some other specified value), which is typically triggered by a PN flip event on a designated finger processor (e.g., the processor assigned to handle the earliest arriving multipath).

The master controller also selects the particular finger processor that is turned off, enabling or disabling it. In addition to timing variations due to shutdown, it is generally specified that the symbol combiner timing changes smoothly, if at all (e.g., 1/8 chips change every 160 milliseconds). Techniques are provided herein to obtain correct symbol combiner timing after non-integer PN roll-over sleep.

The sleep duration with fractional PN flips affects the symbol combiner timing. In one embodiment, the combination counter is not corrected after waking up from sleep, but rather adds the fractional PN flip portion of sleep to the "virtual symbol combiner" offset. The system time is then obtained by adding the virtual symbol combiner offset to the value from the combination counter. This technique is described in detail in U.S. patent application Ser. No. 09/540,302 entitled "Symbol combination synchronization after a Jump to a New Time Alignment", filed on 31/3/2000. Which is assigned to the assignee of the present application and is incorporated herein by reference. If it is desired to align the symbol combiner timing with the received signal timing, the finger processor may be turned off for the earliest arriving multipath to ensure that the PN flip position for the finger processor is properly set (e.g., by rotation and/or masking).

Fig. 6 shows read and write timings of the symbol buffer. As mentioned above, the symbol buffer is typically implemented as a circular buffer, with their read and write pointers proceeding in the same direction for each read and write, respectively (as shown on the right side of fig. 6). The symbol combiner depth is the distance between the write position of the earliest arriving multipath and the read position of all buffers. The read position is also referred to as a symbol combiner read position, or simply a symbol combiner position.

The duration of sleep with fractional PN flips also affects the read and write pointers of the symbol buffer. The read and write locations (i.e., addresses) of the symbol buffer are provided by a combination counter and a finger counter, respectively, as shown in fig. 3.

When the finger counter wakes up from sleep and moves to the correct PN phase (e.g., the finger processor's PN generator is turned to its correct PN phase around the PN circle), the write position in the symbol buffer is also moved accordingly, which affects the symbol combiner depth. According to various aspects, the correct symbol combiner depth may be maintained upon waking from sleep.

In a first scheme, the PN generators in the finger processor are rotated around the PN circle by an integer multiple of the size of the buffer. If each symbol buffer is implemented as a circular buffer (e.g., 8 symbols), then a rotation of an integer multiple of 512PN chips results in the same write position as before. If the read position is unchanged after sleep, the symbol combiner depth remains unchanged.

In a second scheme, the symbol combiner read position can be moved to the correct symbol combiner depth by forcing the symbol combiner to turn off the PN flip assigned to the finger processor of the earliest arriving multipath. This is accomplished by moving the PN generator of the finger processor to a position that triggers a PN flip that is then used for symbol combiner shutdown. By masking the (rotated) PN sequence, the correct PN phase required by the finger processor to process the assigned multipath can be obtained.

In a third scheme, the sleep time period is selected to be an integer multiple of the symbol buffer size, and the sleep duration is quantized accordingly to an integer multiple of the symbol buffer size. For this scheme, after waking up from sleep, the read and write locations are unchanged, and the symbol combiner depth is also maintained. The scheme does not have to turn off the symbol combiner after sleep to get the desired symbol combiner depth. For the 8 symbol size symbol buffer design example described above, the sleep time limit may be chosen to be 512PN chips, i.e., 416.7 microseconds.

Based on the small sleep period and the ability to start sleep cycles at any time, an "instant" sleep can be performed, reducing the amount of time required for the terminal to wake up the QPCH and PCH, thereby reducing power consumption and increasing standby time.

Handling PI bits on QPCH

Various methods may be used to process the PI bit on the QPCH and the paging message on the PCH, some of which are described below, and others may be used and are within the scope of the invention.

In the first scheme, the terminal processes two PI bits on a designated QPCH slot and determines whether to process the relevant PCH slot. For this scheme, if two PI bits are detected as "off" bits, indicating that no paging message is transmitted to the terminal, the PCH is not processed. Otherwise, if any PI bit is detected as a null bit or a "on" bit, indicating that a paging message is transmitted to the terminal, the PCH is processed. For a PI bit that is not reliably detected, indicating erasure, the state is represented by (1) the energy detected for that PI bit being below a first energy threshold indicating an "on" bit but greater than a second energy threshold indicating an "off" bit, and/or (2) the energy detected for the received pilot being below a third energy threshold. This scheme reduces the likelihood of missing paging messages, but consumes more power.

In a second scheme, if any detected PI bit indicates that no paging message is transmitted to the terminal, the terminal skips PCH processing. For this scheme, if the first PI bit is detected as an "off" bit, the terminal does not process the second PI bit.

In a third scheme, the terminal uses the first reliably detected PI bit to determine whether to process the PCH. For this scheme, the terminal processes the second PI bit only if the first PI bit is detected as erased.

In a fourth scheme, the terminal processes only certain PI bits that are estimated to be reliably detectable, the estimation being based on the QPCH channel, the pilot channel, or some other channel. If each of the two PI bits is neither processed nor detected as being erased, or one of the PI bits is detected as a "on" bit, the terminal processes the PCH.

In a fifth scheme, the terminal detects a single PI bit (first or second PI bit), and processes the PCH according to the detected PI bit.

In the sixth scheme, the terminal disregards the PI bit on the QPCH and wakes up to process the PCH anyway.

In summary, a terminal is designed to handle PCH if the detected/undetected PI bit is not sufficient to determine whether a paging message is to be transmitted to the terminal in the upcoming PCH slot.

Fig. 7 is a timeline diagram for processing a QPCH and a PCH, according to an embodiment of the invention. In this embodiment, the terminal can start falling asleep at almost any point in time (i.e., at discrete points in time finer than the boundaries of the 1/4PN roll-over, 26.67 msec, or 80 msec timing), and can also sleep for a duration determined by a small sleep period (e.g., 512PN chips). This enables the terminal to sleep between the pair-wise allocated PI bits in the designated QPCH slot, and also between the second PI bit and the start of the associated PCH slot, as described below.

At time T1, the terminal wakes up for the first PI bit on its QPCH and prepares toAnd then acquiring the multipath. This preparation masks the searcher's PN generator and shifts the finger processor's PN generator to the correct PN phase based on the fractional PN inversion portion of the last sleep cycle. If the mask does not meet the design goal, a rotation method can be applied to the finger processor so that it later generates the PN flip at the correct time. Since PN flipping by the finger processor (but not the searcher) can be used for symbol combiner shutdown, the rotation method is advantageously used for the finger processor, while the masking method can be used for the searcher. In any case, then at time T₂The QPCH is processed by the finger processor and the first PI bit assigned to the terminal is detected. The terminal then prepares to sleep until the next required wake-up time and at time T₃And (6) falling asleep.

For the second scheme described above, the terminal wakes up to process the second PI bit only when the first PI bit is detected as the "on" bit or is erased. Conversely, if the terminal detects the first PI bit as an "off" bit (indicating that no paging message is transmitted to the terminal in the next PCH slot), the terminal sleeps until time T before the first PI bit in the next QPCH slot assigned to the terminal₁。

If the terminal is to process the second PI bit, it is at time T₄Wake up and prepare to reacquire multipath. The preparation can still mask the searcher PN generator and depends on the time T₃And T₄The fractional PN flip portion of the last sleep cycle in between, shifts the finger processor PN generator to the correct PN phase. Then at time T₅The finger processor processes the QPCH and detects the second PI bit assigned to the terminal. The terminal then prepares to sleep before the next required wake-up time and at time T₆And (6) falling asleep.

For the second scheme, the terminal wakes up to process the PCH only when the second PI bit is detected as the "on" bit or is eliminated, otherwise it sleeps until the first PI bit in the next assigned QPCH slot.

If the terminal wants to process the PCH, it is at time T₇Wake up and prepare to reacquire multipath. This preparation also masks the searcher PN generator and depends on the time T₆And T₇The fractional PN flip portion of the last sleep cycle in between, shifts the finger processor PN generator to the correct PN phase. The finger processors are then assigned to the multipaths and at time T₈It is prepared to reset the PCH timing, frame timing, and PN timing to the timing for receiving the PCH.

At time T₉The decoder is also initialized to a normal state (e.g., the Viterbi decoder is initialized to the appropriate starting state) based on the timing of the finger processor for the earliest arriving multipath, with the (80 ms) PCH timing, the (20 ms) frame timing, and the (26.67 ms) PN timing all being reset (i.e., turned off). The PCH is then processed to recover the paging message transmitted on the channel. After decoding the first frame of the paging message, the terminal can determine whether to send the message to it and/or whether additional processing is required. If the terminal does not continue to process the PCH or perform other operations, it prepares to sleep until the next required wake-up time (i.e., the first PI bit in the next assigned QPCH slot) and at time T₁₀And (5) falling asleep.

Various schemes may be used to process sporadically transmitted data, such as data on QPCH and PCH. By way of example, the following describes at time T₂And T₅Several schemes to detect the PI bit on the QPCH. Other methods of processing sporadic transmission data may also be implemented and are included within the scope of the present invention.

In the first approach (also referred to as the "online" approach), a search is initially made for strong multipaths, and finger processors are then assigned to the found multipaths. In order to correctly detect the signal strength of the PI bit, the allocation should be much earlier than the expected PI bit. Since each PI bit is transmitted as an on/off keying bit, the transmitted PI bit value is detected by measuring the energy of the PI bit (e.g., using a Received Signal Strength Indicator (RSSI), as known in the art) and comparing the detected energy to a particular energy threshold.

In a second scheme (also referred to as an "off-line" method), data samples within a small time window around the desired PI bit are captured and stored in a sample buffer, and then multipath, assigned fingers are searched for based on the data samples stored in the sample bufferProcessor and detect PI bit. Using a sample buffer may also reduce the amount of time required to turn on analog circuitry (e.g., RF circuitry), e.g., may reduce time T₁And T₃The interval between and T₄And T₅To increase sleep duration, reduce power consumption, and increase standby time.

For short duration sleep, the amount of circuitry that can be switched off depends on the sleep duration and the circuit requirements. Such as some RF circuits, may require a relatively long normal warm-up period (e.g., in excess of 10 milliseconds). If the sleep duration is shorter than the warm-up requirement of a particular circuit, that circuit may remain on for the sleep duration. If the two PI bits are close to each other, or the second PI bit is close to the start of the associated PCH slot, there may not be enough time to sleep completely and the RF circuitry is switched off. At this point, the RF circuitry remains on, cutting off only the demodulator and decoding hardware to save power. Alternatively, the demodulator and decoder hardware remain on, at which point no rotation or masking should be required.

Sleep cycle

Fig. 8 is a sleep cycle diagram of an embodiment of the present invention. Before the sleep controller enters a sleep cycle, the sleep duration is determined according to the current time and the time (the time of the next PI bit or the start of the upcoming PCH slot) at which the terminal requires to wake up. Preparing to sleep typically requires a certain amount of time (e.g., to determine sleep duration, generate control signals to hardware, etc.). The preparation time is a variable amount of time that can be estimated. The estimated sleep onset time may then be determined as the current time plus the estimated preparation time. The sleep duration may be determined as the desired wake up time minus the estimated sleep onset time.

The demodulator and decoder hardware are disabled from being clocked for the entire sleep duration. If the demodulator and decoder hardware are still clocked after the estimated sleep onset time (e.g., because the actual preparation time is longer than the estimated sleep onset time), an error is made between the actual sleep onset time and the estimated sleep onset time, and the actual hardware timing (when clocking is actually disabled) will precede the desired hardware timing (assuming clocking is disabled at the estimated sleep onset time). The complementary phenomenon occurs upon wake-up, and the hardware is not clocked until slightly after the desired wake-up time, thereby causing an error between the actual wake-up time and the desired wake-up time. Since the "to sleep" error is equal to the "wake from sleep" error, hardware timing can be expected upon re-timing.

To avoid waking up later than desired, the preparation time is estimated as the worst preparation time for all expected operating conditions, as shown in fig. 8.

If the opposite occurs and the actual sleep start time is earlier than the estimated sleep start time (e.g., because the actual preparation time is shorter than the estimated time), the actual hardware timing (timing off) will lag behind the expected hardware timing. But the complementary phenomenon, which occurs when waking up, counteracts the "going to sleep" error. Since these two errors are the same, hardware timing can be expected upon re-timing.

Waking from instant sleep

Some tasks are typically performed when waking from sleep. An interrupt signal may be sent to the master controller indicating to wake up from sleep, and the master controller may then use the interrupt signal as an indication to initiate the reacquisition procedure. For some terminal hardware designs, the interrupt signal is generated when a PN flip occurs in the symbol combiner, possibly four or six symbols later than the earliest arriving finger.

If the terminal is made to operate to sleep on the PN roll-over as usual, the hardware will generate a PN roll-over interrupt signal when it wakes up when the clock is turned back on. The interrupt signal will inform the host controller that the reacquisition process can begin as the clock is restarted.

By using "instant" sleep, the terminal does not have to sleep on the PN flip. Therefore, for the above hardware design, if no PN roll-over occurs, no PN roll-over interrupt signal is generated when the clock is turned back on. In particular, the hardware timing is a specific period of time (e.g., 5 milliseconds) from the PN roll-over when going to sleep. When the hardware is retimed upon waking, the PN roll-over will occur after the specified period of time (e.g., 5 milliseconds), and the PN roll-over interrupt signal is not generated until the PN roll-over occurs. To not waste this period waiting for the next PN roll over, the master may be signaled to start reacquisition when it wakes up.

In the first scheme, additional hardware is provided to generate interrupt signals when re-clocked at wake-up. The interrupt signal may be generated and sent directly to the controller 260 of fig. 3, for example, by a clock generator 366. This scheme can be implemented in new hardware designs, but is not applicable to the original hardware design.

In the second scheme, the extra time before the next PN flip is taken into the warm-up time of the RF circuit. For example, if the warm-up time of the RF circuit is 30 milliseconds, and the hardware would go to sleep 20 milliseconds before the PN flip, the programmed warm-up time is reduced to 10 milliseconds (i.e., 30-20 milliseconds). Thus, 10 milliseconds after waking up, the sleep controller will start the clock and the demodulator hardware will work. After 20 milliseconds, a PN roll-over interrupt is generated by the demodulator hardware, almost coinciding with the end of the RF warm-up time. The master controller begins reacquisition at this point and the RF circuitry is ready. This scheme can be used if the RF warm-up time exceeds the "wait for next PN flip" time.

In a third scenario, the searcher is programmed to wake up from sleep and generate an interrupt immediately. Before going to sleep, the searcher is programmed to perform a small search. The sleep controller then switches off the clock, freezing the searcher state. When the sleep controller restarts the clock, the searcher continues to work, completing the small search of the last pre-sleep programming, and generating a clear interrupt. The master controller will override the search result and indicate that the clock has been restarted based on the search clear interrupt. The small search should be long enough to ensure that the sleep controller turns off the clock (and disables the searcher) before the search is complete, but short enough so that the main controller is notified of the restarted clock immediately after it wakes up.

Fig. 9 is a flow diagram of a sleep process 900 according to an embodiment of the invention. Initially in step 912, a sleep condition is identified. Sleep is triggered by various conditions and events, such as the time difference between the current time and the next processing time being equal to or longer than a certain time threshold. In one aspect, the time threshold may be less than 1/4PN flips (i.e., less than 1/4PN sequence lengths).

If a sleep condition is identified, then the sleep duration and sleep onset time are determined at step 914. The sleep duration may be a non-integer multiple of the PN roll-over, while the fractional portion of the sleep duration may be less than 1/4PN rolls-over. The sleep duration and the sleep onset time are determined as described above. In step 916, the terminal sleeps for the determined duration and begins near the determined start time.

The techniques described herein facilitate detecting PI bits transmitted on a QPCH. Since the sleep duration can be selected in relatively fine increments (e.g., an integer multiple of 512PN chips) and can be asleep and awake at any time, the terminal can sleep between a pair of assigned PI bits on the same QOCH slot or between the assigned PI bit and the start of the PCH slot. Because a single PI bit can be awakened and processed, the power consumption is reduced, and the standby time is prolonged.

FIG. 10 is a flow diagram of a process 1000 for detecting a PI bit on a QPCH in accordance with one embodiment of the invention. Process 1000 generally conforms to the timeline of FIG. 7. Initially at step 1012, the terminal wakes up and processes the first PI bit. As determined in step 1014, if the first PI bit is detected as an "off bit, the process proceeds to step 1028, otherwise the terminal performs sleep in step 1016 until the second PI bit on the same QPCH slot. Such short duration sleep may be achieved using the techniques described herein.

At step 1018, the terminal wakes up and processes the second PI bit. If the second PI bit is detected as an "off" bit, as determined in step 1020, the process proceeds to step 1028, otherwise the terminal performs sleep in step 1022 until the associated PCH slot starts. Then, in step 1024, the terminal wakes up and processes the paging message on the relevant PCH slot. If the received message indicates that additional actions are required, as determined in step 1026, the terminal remains in step 1026 to continue processing the paging channel and/or to perform the required actions, otherwise the terminal performs another sleep in step 1028 until the first PI bit in the next assigned QPCH slot. The process then terminates.

The techniques described herein may be used for sleep from one PI bit to another PI bit, from one PI bit to the start of a PCH slot, and from a PCH slot to one PI bit. These techniques may be used for QPCH operation when the terminal monitors the PCH. As mentioned above, these techniques may also be used for other types of sporadically transmitted data, such as terminals that may also monitor for broadcast messages that occur in broadcast slots that start on an 80 millisecond boundary (like PCH slots). However, the broadcast slot (currently) has no indicator bit in the QPCH that starts 100 milliseconds before the broadcast slot. Using the techniques described herein, an access terminal may sleep for a particular period of time and wake up at a broadcast slot if the PI bit is detected as zero.

For ease of explanation, the various methods and embodiments of the present invention are described specifically with respect to IS-95 and cdma 2000. The techniques described herein may also be used for other CDMA and wireless communication systems, such as may be used for a W-CDMA system that also supports a Paging Indicator Channel (PICH) that transmits paging indicators to terminals, referred to as User Equipment (UE) in W-CDMA. Various differences exist between Cdma2000 and W-Cdma, and the techniques described herein may be modified for W-Cdma, e.g., using a perturbation sequence (instead of a PN sequence) of length 38640 chips for spreading data prior to transmission.

The techniques described herein may be implemented in various ways, such as by implementing the techniques in hardware, software, or a combination thereof. For a hardware implementation, the elements used for sleeping and processing various types of sporadic transmission data may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, and combinations thereof.

For a software implementation, the components used to sleep and process various types of sporadic transmissions may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in a memory unit (e.g., memory 262 of fig. 2) and executed by a processor (e.g., main controller 260 and/or sleep controller 364). The memory unit may be implemented within the processor or external to the processor, and may be communicatively coupled to the processor via various means as is known in the art.

While the embodiments disclosed above are susceptible to embodiments of the invention, it will be apparent to those skilled in the art that various modifications can be made to the embodiments and that the general principles defined herein can be applied to other embodiments without departing from the spirit or scope of the invention. Accordingly, the present invention is not limited to the embodiments shown herein. But is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (25)

1. A method for processing quick paging channel paging indicator bits to conserve power and extend standby in a CDMA communication system, comprising:

identifying a sleep condition; and

the sleep onset is triggered at a time based on a fractional portion of the sleep duration that is less than the 1/4PN sequence length, thereby facilitating a rollover event in the symbol combiner without the use of finger rollover.

2. A method of processing data transmitted at specified time instances on a particular code channel in a wireless communication system, comprising:

identifying a sleep condition; and

performing sleep for a duration that is a non-integer multiple of a PN sequence length used to spread data prior to transmission, wherein a fractional portion of the sleep duration is less than 1/4PN sequence lengths.

3. The method of claim 2, wherein the data corresponds to paging indicator bits transmitted on a quick paging channel.

4. The method of claim 3, wherein the sleeping is performed between a pair of paging indicator bits within a particular quick paging channel slot.

5. The method of claim 2, wherein the data corresponds to a paging message transmitted on a paging channel.

6. The method of claim 2, wherein the data corresponds to a broadcast message transmitted on a broadcast channel.

7. The method of claim 2, wherein the sleep duration is selected to be an integer multiple of a time increment, the time increment being less than 1/4PN sequence lengths.

8. The method of claim 7, wherein the time increment is selected based on a mask used to mask a PN sequence.

9. The method of claim 7, wherein the time increment is selected based on a buffer size used to store the symbol.

10. The method of claim 7, wherein the time increment is selected to be an integer multiple of 64 PN chips.

11. The method of claim 10, wherein the time increment is selected to be 512PN chips.

12. The method of claim 2, wherein the step of performing sleep comprises:

the demodulator and decoder hardware are de-clocked for the duration of sleep.

13. The method of claim 2, wherein the step of performing sleep comprises:

some RF circuits are disabled for the duration of sleep.

14. The method of claim 2, further comprising:

an interrupt is generated upon waking from sleep.

15. The method of claim 14, wherein the interrupt is generated by hardware upon waking up to restart a clock.

16. The method of claim 14, wherein the interrupt is generated based on a signal search being completed after waking up.

17. The method of claim 16, wherein the signal search is programmed before falling asleep.

18. The method of claim 2, wherein a sleep condition is identified if a period of time between a current time of day and a next processing time of day exceeds a predetermined time threshold.

19. The method of claim 2, wherein the communication system is a CDMA system.

20. The method of claim 19, wherein the CDMA system implements IS-95 or CDMA2000 standards.

21. A memory communicatively coupled to a digital signal processing apparatus, wherein the digital signal processing apparatus is capable of interpreting digital information to:

identifying a sleep condition; and

sleep is initiated for a duration that is a non-integer multiple of a PN sequence length used to spread data prior to transmission, wherein a fractional portion of the sleep duration is less than 1/4PN sequence lengths.

22. A terminal in a wireless communication system, comprising:

a first controller for identifying a sleep condition; and

a sleep controller for initiating sleep for a duration that is a non-integer multiple of a PN sequence length used to spread data prior to transmission, wherein a fractional portion of the sleep duration is less than 1/4 of the PN sequence length.

23. The terminal of claim 22, further comprising:

a clock generator for disabling clocking of selected circuits within the terminal for the sleep duration.

24. The terminal of claim 22, further comprising:

a searcher element for providing interrupts after waking from sleep.

25. The terminal of claim 22, further comprising:

at least one finger processor for providing a PN roll-over event from which a system time can be reset for the terminal.