HK1069675B - Lead frame and semiconductor device using it - Google Patents

Description

Lead frame and semiconductor device using the same

Technical Field

The present invention relates to a lead frame and a semiconductor device in which a semiconductor chip mounted on the lead frame is encapsulated in a resin.

The present application claims priority based on Japanese patent application No. 2003-.

Background

Fig. 19 and 20 show an example of a semiconductor device (designated by reference numeral '20') encapsulated in a resin, the semiconductor device 20 including a lead frame 11 made of a prescribed metal such as a copper alloy and 42 alloy, a semiconductor chip 18 bonded to an upper surface of a die stage (die stage)12 of the lead frame 11 by a bonding material 17 such as Ag paste and solder paste, a plurality of bonding wires 16 electrically connecting electrodes of the semiconductor chip 18 and leads 15 of the lead frame 11 together, a mold resin 19 made of a thermosetting resin such as epoxy resin for enclosing inner leads 15a of the leads 15, and the like.

The semiconductor device 20 having the above-described configuration is temporarily mounted on a prescribed position of a circuit board mounted in an electronic device, and the semiconductor device 20 is then subjected to reflow soldering in which solder paste is melted and then solidified so that the outer leads 15b of the leads 15 are electrically connected to the circuit board, thereby enabling the semiconductor device 20 to be reliably mounted on the prescribed position of the circuit board.

Generally, Sn-Pb solder (or Sn-Pb alloy) is used for mounting the semiconductor device 20 on a circuit board, wherein the Sn-Pb solder has recently been replaced with lead-free solder such as Sn-Ag-Cu alloy because toxic substances such as lead (Pb) contained in the Sn-Pb solder may destroy the natural environment and may adversely affect the human body.

Since the lead-free solder does not contain toxic substances (or harmful materials) such as lead (Pb), it can be advantageous to protect the environment; however, its melting point (about 217 ℃ C.) is higher than that of Sb-Pn solder (about 183 ℃ C.); therefore, it is necessary to increase the heating temperature of reflow soldering, and accordingly, it is necessary to increase the heat resistance in soldering with respect to the semiconductor device 20.

When the above-described semiconductor device 20 is heated in the reflow soldering process, there are easily separable portions and difficultly separable portions due to the relationship between different materials used for its constituent elements. That is, a relatively high adhesion force is formed at the boundary between the semiconductor chip 10 made of silicon and the molding resin 19 and thus can be hardly separated from each other, and a relatively low adhesion force is formed at the boundary between the chip stage 12 made of a specified metal such as 42 alloy and the molding resin 19 and thus can be easily separated from each other. When separation occurs at the boundary between the chip stage 12 and the molding resin 19, the separated area extends toward the boundary between the semiconductor chip 18 and the molding resin 19 due to the influence caused by the separation, so that it may become a crack (or cracks) to undesirably damage the bonding wire 16. This phenomenon clearly occurs as the heating temperature in reflow soldering becomes high; therefore, appropriate measures must be taken to avoid this phenomenon.

Japanese patent application laid-open No.2000-49272 (see pages 4-5 and 7 and fig. 1, 2 and 19) discloses another example of a semiconductor device (designated by reference numeral '30') in which the chip carrier 22 of the lead frame 21 is formed in an X shape as shown in fig. 21 to 23 in order to reduce the total bonding area formed between the chip carrier 22 and the mold resin 29.

Japanese patent application laid-open No. h07-211852 (see pages 2 and 4 and fig. 5 and 11) discloses yet another example of a semiconductor device (designated by reference numeral '40') in which, as shown in fig. 24 and 25, an opening 32a is formed in a central portion of a chip stage 32 of a lead frame 31 in order to reduce the total bonding area between the chip stage 32 and a molding resin 39.

The above-described semiconductor device 30 is designed to reduce the adhesion area formed between the chip stage 22 and the mold resin 29, so that the separation region occurring in the boundary therebetween can be reduced, so that the separation region may hardly extend toward the boundary between the semiconductor chip and the mold resin regardless of the influence caused by the separation. However, when the semiconductor device 30 is bonded to the circuit board with a lead-free solder having a high melting point, separation can be easily caused due to heating.

In the semiconductor device 40, the peripheral portion of the chip carrier 32 extends beyond the peripheral portion of the semiconductor chip 38 so that separation may occur in such "extended" peripheral portion to cause an influence by which the separation region may extend further toward the boundary between the semiconductor chip 38 and the molding resin 39 so that it may gradually become a crack (or cracks) so as to undesirably break the bonding wire 36.

Disclosure of Invention

An object of the present invention is to provide a lead frame and a semiconductor device in which a bonding wire is not broken by a crack undesirably formed in a molding resin in a heating step when the semiconductor device is mounted on a circuit board.

Another object of the present invention is to provide a lead frame and a semiconductor device which can be manufactured with high yield and thus contribute to environmental protection.

The lead frame of the present invention has a chip carrier for mounting a semiconductor chip thereon and is encapsulated in a molding resin so that the semiconductor chip adheres to an upper surface of the chip carrier, thereby producing a semiconductor device in which the outer shape of the chip carrier is shaped so as to be smaller than the outer shape of the semiconductor chip and a plurality of cutouts are formed on each side of the chip carrier so as to reduce the total area of the chip carrier.

In the above-described structure, the chip carrier has a rectangular shape (or a square shape), and the cutouts are formed inward in the peripheral edge regions corresponding to the four sides of the chip carrier. Wherein each cutout has a semicircular shape, a length L2 of which is defined in a range from (L1 × 0.05) to (L1 × 0.20), wherein 'L1' indicates a length of each side of the chip carrier. Further, the total area S2 of the chip stage is defined in the range from (S1 × 0.10) to (S1 × 0.40), where 'S1' indicates the total area of the semiconductor chip.

The bonding area between the chip carrier and the semiconductor chip firmly bonded together is surrounded by the molding resin introduced into the cutout of the chip carrier; therefore, a firm bonding state can be established between the semiconductor chip and the molded resin inside the cutout of the chip carrier. Therefore, even when separation occurs at the boundary between the chip stage and the molding resin, the separation does not extend toward the boundary between the semiconductor chip and the molding resin. That is, separation can be prevented from gradually growing into cracks that can cause breakage of the weld line.

The above-described relationships defined between L1 and L2 and between S1 and S2 ensure high bonding strength between the chip carrier and the semiconductor chip, so as to prevent separation from occurring in the boundary between the semiconductor chip and the molding resin.

When the semiconductor device is mounted in an electronic device, the lead frame is bonded to a circuit board with a lead-free solder free from toxic substances, thereby contributing to environmental protection during manufacture.

Drawings

These and other objects, aspects and embodiments of the invention will be described in more detail with reference to the accompanying drawings, in which:

fig. 1 is a sectional view showing the configuration of a semiconductor device having a lead frame according to a first embodiment of the present invention;

fig. 2 schematically shows a diagram of a lead frame of a chip carrier having a prescribed shape as viewed from the back;

fig. 3 schematically shows a diagram of an application area of the bonding material on the chip carrier shown in fig. 2;

fig. 4 is a diagram of a change in the S2/S1 ratio between the back area (S2) of the chip stage and the back area (S1) of the semiconductor chip having a size of 4mm × 4 mm;

FIG. 5 is a graph of the variation in adhesion force determined between a chip carrier and a semiconductor chip having a size of 4mm by 4 mm;

fig. 6 is a diagram of a change in the S2/S1 ratio between the back area (S2) of the chip stage and the back area (S1) of the semiconductor chip having a size of 7mm × 7 mm;

FIG. 7 is a graph of the variation in adhesion force determined between a chip carrier and a semiconductor chip having dimensions of 7mm by 7 mm;

fig. 8 is a diagram of a change in the S2/S1 ratio between the back area (S2) of the chip stage and the back area (S1) of the semiconductor chip having a size of 10mm × 10 mm;

FIG. 9 is a graph of the variation in adhesion force determined between a chip carrier and a semiconductor chip having a size of 10mm by 10 mm;

fig. 10 is a diagram of a change in the S2/S1 ratio between the back area (S2) of the chip stage and the back area (S1) of the semiconductor chip having a size of 12mm × 12 mm;

fig. 11 is a diagram of the variation in adhesion force determined between a chip stage and a semiconductor chip having a size of 12mm × 12 mm;

fig. 12A schematically shows a rear view of a semiconductor chip and a chip carrier of a lead frame according to a second embodiment of the invention;

FIG. 12B is a cross-sectional view taken along line A-A of FIG. 12A;

fig. 13A schematically shows a rear view of a semiconductor chip and a chip carrier of a lead frame according to a third embodiment of the invention;

FIG. 13B is a cross-sectional view taken along line B-B of FIG. 13A;

fig. 14 schematically shows a rear view of a semiconductor chip and a chip carrier of a lead frame according to a fourth embodiment of the invention;

fig. 15A schematically shows a rear view of a semiconductor chip and a chip carrier of a lead frame according to a fifth embodiment of the invention;

FIG. 15B is a cross-sectional view taken along line C-C of FIG. 15A;

fig. 16A schematically shows a rear view of a semiconductor chip and a chip carrier of a lead frame according to a sixth embodiment of the invention;

FIG. 16B is a cross-sectional view taken along line D-D of FIG. 16A;

fig. 17 schematically shows a rear view of a semiconductor chip and a chip carrier of a lead frame according to a seventh embodiment of the invention;

fig. 18A schematically shows a rear view of a semiconductor chip and a chip carrier of a lead frame according to an eighth embodiment of the invention;

FIG. 18B is a cross-sectional view taken along line E-E of FIG. 18A;

fig. 19 is a sectional view showing the configuration of a conventionally known semiconductor device;

fig. 20 is a plan view simply showing the relationship between the semiconductor chip and the chip stage in the semiconductor device shown in fig. 19;

fig. 21 schematically shows a plan view of an example of a lead frame;

fig. 22 is a plan view schematically showing a semiconductor chip mounted on the lead frame shown in fig. 21;

fig. 23 is a sectional view showing the configuration of a conventionally known semiconductor device having the lead frame shown in fig. 21;

fig. 24 schematically shows a plan view of an example of a lead frame;

fig. 25 is a perspective view showing an external appearance of a conventionally known semiconductor device having the lead frame shown in fig. 24;

FIG. 26 shows a comparison between samples for their size and adhesion; and

fig. 27 shows a comparison between samples for their defects.

Detailed Description

The invention is described in more detail by way of example with reference to the accompanying drawings.

Fig. 1 to 3 show a lead frame 1 and a semiconductor device 10 according to a first embodiment of the invention. The lead frame 1 is made using a thin plate composed of a prescribed metal such as copper alloy and 42 alloy, which is etched and then subjected to die pressing so that it is formed into a prescribed shape. Specifically, lead frame 1 includes a chip stage 2 on the upper surface of which a semiconductor chip 8 is mounted, a plurality of support posts 4 for supporting chip stage 2, and a plurality of leads 5 which are provided outside chip stage 2 and electrically connect electrodes of semiconductor chip 8.

The chip stage 2 is formed in a prescribed shape so as to match the shape of the semiconductor chip 8. In the present embodiment, the chip carrier 2 is formed roughly in a rectangular shape as a whole to match the rectangular shape of the semiconductor chip 8 shown in fig. 2 and 3.

The total area of the chip carrier 2 is reduced so as to be smaller than the area of the semiconductor chip 8 (i.e., the area of the back of the semiconductor chip 8 mounted on the chip carrier 2), wherein the outer contour shape of the chip carrier 2 is shaped so as to be completely contained inside the outer contour shape of the semiconductor chip 8. Therefore, when the semiconductor chip 8 is mounted on the chip stage 2, the peripheral portion of the semiconductor chip 8 having a prescribed area extends to the outside of the peripheral portion of the chip stage 2.

Semicircular cutouts 3 are formed at the centers of the four sides of the chip carrier 2, respectively, which reduces the total area of the chip carrier 2. Therefore, when the semiconductor chip 8 is mounted on the upper surface of the chip stage 2, a specified portion of the back side of the semiconductor chip 8 that matches the semicircular cutout 3 of the chip stage 2 is exposed toward the back side of the semiconductor chip 8.

In the above, each semicircular notch 3 is cut out inside the chip carrier 2 at a prescribed length L2, setting L2 within a range defined by the following equation (1) (where L1 indicates the length of each side of the chip carrier 2).

L2 ═ (L1 × 0.05) to (L1 × 0.20. (1)

The back area S2 of the chip carrier 2 excluding the notch 3 is set within a range defined by the following equation (2) (where S1 indicates the back area of the semiconductor chip 8 mounted on the upper surface of the chip carrier 2).

S2 ═ S1 × 0.10 to (S1 × 0.40. (2)

The support columns 4 are formed together with the chip stage 2 and are provided so as to be radial to the four corners of the chip stage 2, so that the support columns 4 reliably support the chip stage 2.

As shown in fig. 1, lead lines 5 are provided outside the chip carrier 2 with a prescribed distance therebetween so as to surround the chip carrier 2, wherein each lead line 5 is constituted by an inner lead line 5a provided inside the semiconductor device 10 and an outer lead line 5b provided outside the semiconductor device 10.

The inner leads 5a of the leads 5 are electrically connected to electrodes of the semiconductor chip 8 by bonding wires 6, and the outer leads 5b are electrically bonded to a circuit board (not shown) mounted in an electronic device (not shown) by solder.

When the lead frame 1 having the above-described structure is used to fabricate the semiconductor device 10, a die bonding step is first performed in such a manner that an appropriate amount of a bonding material 7 such as Ag paste and lead-free solder (for example, Sn — Ag — Cu alloy) is applied onto the upper surface of the die stage 2 of the lead frame 1, wherein when the bonding material 7 is melted and then solidified, the semiconductor chip 8 is mounted on the upper surface of the die stage 2 and pressed with a prescribed load, so that the semiconductor chip 8 is integrally bonded onto the upper surface of the die stage 2.

In the above, Ag paste or the like is applied to the designated area 7A (surrounded by a dotted circle in fig. 3) of the upper surface of the chip stage 2, which is positioned so as to avoid the notch 3. Therefore, the notch 3 of the chip stage 2 does not interfere with the application of the bonding material 7.

Next, in the wire bonding step, the electrode of the semiconductor chip 8 is electrically connected to the inner lead 5a of the lead 5 by means of the bonding wire 6 such as a metal wire.

Next, in the molding step, the lead frame 1 is placed in a cavity of a metal mold constituted by an upper mold and a lower mold, and then filled with a thermosetting resin such as an epoxy resin, which is injected into the cavity and then hardened. Thus, the semiconductor chip 8, the chip stage 2, the bonding wires 6, and the inner leads 5a of the leads 5 can be encapsulated in the mold resin 9 formed of a thermosetting resin.

In the above, the mold resin 9 flows into the cutouts 3 of the chip stage 2 to bond the back portions of the semiconductor chips 8, so that the mold resin 9 is partially formed inside the cutouts 3 of the chip stage 2.

Next, in the lead surface treatment step, if necessary, lead-free solder plating is performed on a prescribed portion of the lead 5 that protrudes outside the mold resin 9, so as to prevent rusting of the lead 5 from occurring. This makes it easy to perform soldering work when the semiconductor device 10 is mounted on a circuit board.

Next, in the cutting and forming step, unnecessary portions of the leads are cut off so that the leads 5 are defined to a prescribed length, with the outer leads 5b being bent so that they form a prescribed shape.

Thus, the semiconductor device 10 can be produced by the above-described steps. Then, the semiconductor device 10 having the above-described configuration is temporarily mounted at a prescribed position on the circuit board, in which the lead-free solder is melted and solidified in the reflow soldering, and the outer leads 5b of the leads 5 are electrically joined to the circuit board. Thus, the semiconductor device 10 can be securely mounted at a prescribed position on the circuit board.

In the semiconductor device 10 having the lead frame 1 described above, even when the semiconductor device 10 is heated at the time of reflow soldering so that separation may occur between the chip stage 2 and the mold resin 9, it is possible to avoid separation occurring between the semiconductor chip 8 and the mold resin 9 and breakage of the soldering wire 6.

The present embodiment is characterized in that the outer shape of the chip carrier 2 is shaped smaller than the outer shape of the semiconductor chip 8 so that the total area of the chip carrier 2 is reduced to be smaller than the total area of the semiconductor chip 8, and then when the semiconductor chip 8 is mounted on the upper surface of the chip carrier 2, the peripheral portion of the semiconductor chip 8 partially extends outside the peripheral portion of the chip carrier 2. Thus, the separation area can be reduced to the minimum, which can be easily formed in the peripheral portion of the chip carrier 2 when the semiconductor device 10 is mounted on the circuit board by heating. Therefore, even when separation occurs between the chip carrier 2 and the mold resin 9, the separation is reliably prevented from extending toward the interface between the semiconductor chip 8 and the mold resin 9, so that it is possible to reliably prevent the bonding wire from being undesirably broken due to the formation of cracks that may be caused by the separation.

The semiconductor chip 8 is welded on the chip carrier 2; therefore, they can be firmly joined together. That is, the adhesion area formed between the semiconductor chip 8 and the mold resin 9 inside the cutout 3 of the chip stage 2 is surrounded by the firm bonding area between the chip stage 2 and the semiconductor chip 8; therefore, a firm adhesion state between the semiconductor chip 8 and the mold resin 9 inside the cutout 3 of the chip stage 2 can be established. Further, the mold resin 9 itself may be bonded inside the cutout 3 of the chip stage 2; therefore, it is difficult for both the mold resin 9 and the chip stage 2 to move relative to each other in a prescribed direction matching the four sides of the chip stage 2. Therefore, although separation occurs between the chip carrier 2 and the molding resin 9, the separation does not extend toward the interface between the semiconductor chip 8 and the molding resin 9, so that it will not gradually become a crack so as to undesirably damage the bonding wire 6.

Further, the present embodiment introduces the relational expression between the length L1 of each side of the chip carrier 2 in the rectangular shape and the length L2 of each cutout 3 formed inward with respect to each side of the chip carrier 2, as defined by the above equation (1), so that the bonding strength can be improved so that the bonding strength with respect to the chip carrier 2 is higher.

Although as an environmental countermeasure, a lead-free solder that does not contain a toxic substance such as lead (Pb) is used when the lead frame and the circuit board are joined together, cracks are generated in the molding resin 9 during heating to undesirably damage the bonding wires 6 when the semiconductor device is firmly mounted on the circuit board; therefore, the actual manufacturing yield of the electronic device can be increased.

Further, the present embodiment introduces the relational expression between the back surface area S1 of the semiconductor chip 8 and the back surface area S2 of the chip stage 2, as defined by the above equation (2), so that the bonding strength can be increased so that the bonding strength with respect to the chip stage 2 is higher.

The above range defined by equation (2) can be explained using an example of a semiconductor device designed to the following dimensions.

That is, there are provided an example of a semiconductor chip having a square shape whose side length is set to 4mm, and an example of a chip carrier having a square shape in which a semicircular cutout is formed on each side, in which the semiconductor chip and the chip carrier are bonded together and then integrally encapsulated in a mold resin. Here, the length L2 of each semicircular cutout is set to (L1 × 0.20).

FIG. 4 shows the ratio S2/S1 [% ]]I.e., the back area S2 of the chip stage and the back area S1 of the semiconductor chip (16 mm)²) Wherein the length of each side of the chip carrier is varied. The drawing of fig. 4 shows a comparison between the above-described example of the semiconductor device in which the cutouts are formed on the respective sides of the chip stage and the comparative example of the semiconductor device in which the cutouts are not formed in the chip stage, with reference to the above-described parameters S2/S1.

Further, so-called adhesion (or adhesion factor) is introduced to evaluate the adhesion characteristics of the semiconductor device, in which the adhesion established between the semiconductor chip and the molding resin is generally set to 1.00, and the adhesion established between the chip stage and the molding resin drops to 0.50 when the adhesion becomes weak. Specifically, the adhesion force can be explained as follows:

fig. 26 shows a comparison between "sample a" in which the semiconductor chip has a square shape with a side length set to 9.9mm and the chip stage has a square shape with a side length set to 9mm, and "sample B"; in "sample B", the semiconductor chip has the same size as described above and the chip carrier has a square shape with its side length set to 4.2mm, where neither sample a nor sample B is provided with a notch in its chip carrier.

These samples a and B passed through a full water content situation; specifically, in the pretreatment process, they were initially exposed to a temperature of 125 ℃ for 24 hours, then exposed to a temperature of 85 ℃ for 336 hours at a humidity of 30%, and also exposed to a temperature of 30 ℃ for 216 hours at a humidity of 70%, so that the water content sufficiently permeated into them. They were then subjected to a heat treatment at 260 ℃ for 10 seconds, i.e. in the case of a simulation of the actual reflow situation in which they were subjected to two reflows such that they were heated to 265 ℃. Thereafter, an ultrasonic inspection apparatus is used to perform an inspection involving the formation of cracks in the semiconductor device, the occurrence of separation with respect to the chip stage, and the occurrence of separation with respect to the back of the semiconductor chip. The result is shown in fig. 27, in which separation inevitably occurs in the back area of the chip carrier and the back area of the semiconductor chip due to the acceleration test.

Fig. 27 shows that since the adhesion between the chip stage and the molding resin is relatively weak, the stage back separation ratio for samples a and B is 100%, while the chip back separation ratio for sample a is 82%, where S2/S1 is 83%, and the chip back separation ratio for sample B is 15%, where S2/S1 is 18%, where the chip back separation ratio can be considered to be approximately proportional to the ratio of the back area S2 of the chip stage to the back area S1 of the semiconductor chip, i.e., S2/S1. That is, when both the back of the semiconductor chip and the back of the chip stage are exposed at the same ratio, in other words, when S2/S1 is 50%, it is assumed that the stage back separation ratio is 100% and the chip back separation ratio is 50%, where it can be considered that the stage back separation ratio is twice the chip back separation ratio under the same conditions for comparison. This is because the occurrence of separation may greatly depend on the adhesion of the molding resin; therefore, when the adhesion between the semiconductor chip and the molding resin is 1.00, the adhesion between the chip stage and the molding resin is assumed to be 0.50. For this reason, it is assumed that the area involved (S1-S2) where the back area S2 of the chip stage is subtracted from the back area S1 of the semiconductor chip bonds the semiconductor chip to the molding resin with an adhesion of 1.00, and the area involved S2 of the back of the chip stage bonds the chip stage to the molding resin with an adhesion of 0.50. Thus, the predetermined adhesion forces shown in the rightmost columns of fig. 26 may be defined for samples a and B, respectively. This definition for adhesion can be used to evaluate semiconductor devices.

In the case where the semiconductor chip 8 is bonded to the chip stage, involving the "exposed" back area of the semiconductor chip 8, i.e., the above-mentioned area (S1-S2), the semiconductor chip 8 is bonded to the mold resin 9 with an adhesion of 1.00, wherein the back area S2 of the chip stage 2 excluding the notch 3 is subtracted from the back area S1 of the semiconductor chip 8; referring to back area S2 of chip carrier 2, chip carrier 2 is bonded to mold resin 9 with an adhesion of 0.50. Fig. 5 shows a change in adhesion force with respect to the adhesion of the mold resin 9 to the semiconductor chip 8 and the chip carrier 2 bonded together when the side length of the chip carrier 2 is changed in the above-described conditions, in which two curves are drawn with respect to the formation of the notch 3 in the chip carrier 2.

Preferably, in order to secure a sufficiently high bonding strength with respect to the chip carrier 2, the adhesion is 0.80 or more. Referring to FIGS. 4 and 5, the range of securing adhesion of at least 0.80 may translate into a range of the above-described ratio S2/S1 of approximately at most 40%. In order to ensure that a relatively high adhesion is established between the semiconductor chip 8 and the chip carrier 2, it is preferable that the ratio S2/S1 be about at least 10%. That is, it is preferable that the ratio S2/S1 be in the range of 10% to 40%, as can be estimated from the above equation (2).

In short, as long as the above equation (2) is satisfied, even when the lead frame of the semiconductor device is bonded to the circuit board using a lead-free solder containing no toxic substance such as lead (Pb), it is possible to avoid the occurrence of a situation where cracks are formed in the molding resin to undesirably damage the bonding wire due to heating when the semiconductor device is bonded to the circuit board; thus, the yield in manufacturing the electronic device can be increased.

In order to satisfy the above equation (2) in which the ratio S2/S1 is about 18%, for example, a semiconductor chip having a square shape with a side length set to 4mm and a chip carrier having a square shape with a side length set to 2mm and a notch formed on each side are bonded together, wherein they are integrally encapsulated in a molding resin to fabricate a semiconductor device, which is now evaluated as follows:

in the evaluation, the semiconductor device was subjected to baking at a temperature of 125 ℃ for 24 hours, humidification at 85 ℃ for 30% for 168 hours, humidification at 30 ℃ for 70% for 120 hours, and heating in reflow soldering to a peak temperature of 265 ℃ for 10 seconds 2 times. In this case, no separation is found for the chip carrier; thus, very good results were obtained.

Fig. 6, 8, and 10 show the relationship between the variation of the above-described ratio S2/S1 and the variation of the side length of the chip stage, respectively, concerning three types of square-shaped semiconductor chips having a size of 7mm × 7mm, a size of 10mm × 10mm, and a size of 12mm × 12mm, respectively. Further, fig. 7, 9, and 11 show variations in adhesion to three types of square-shaped semiconductor chips, respectively. From these figures, an adhesion range of at least 0.80 can be converted into a ratio S2/S1 range of about at most 40%, wherein since it is preferable that the ratio S2/S1 is about at least 10%, it is generally considered that the semiconductor device should satisfy the above equation (2).

Next, a second embodiment of the present invention will be described, in which parts equivalent to those used in the first embodiment are designated by the same reference numerals; therefore, detailed description will be omitted.

Fig. 12A and 12B show a lead frame 1 and a semiconductor device 10 according to a second embodiment of the present invention, in which a second cutout 3A is formed so as to surround the cutout 3 inside a chip stage 2, except for the above-described cutout 3 formed at the center of each side of the chip stage 2, and the back of the chip stage 2 is half-etched.

Each second slit 3A is cut with respect to the slit 3 and the back of the chip carrier 2, wherein in the above-described molding step, the molding resin 9 flows into the second slit 3A except for the slit 3 of the chip carrier 2.

The second embodiment can provide the same effects as those demonstrated in the first embodiment. Further, due to the formation of the second cutout 3A, in the same plane formed between the back of the chip stage 2 and the mold resin 9, the total adhesion area is reduced, so that the stress therein is dispersed; therefore, separation can be made difficult to occur between the chip stage 2 and the mold resin 9. This effect can be obtained by roughening the back of the chip stage 2 using a machine such as a sandblasting machine.

Next, a third embodiment of the present invention will be described, in which parts equivalent to those used in the first and second embodiments are designated by the same reference numerals; therefore, detailed description will be omitted.

Fig. 13A and 13B show a lead frame 1 and a semiconductor device 10 according to a third embodiment of the present invention, in which a second cutout 3A is formed on the upper surface of a chip carrier 2 by performing half etching so as to surround a semicircular cutout 3, the semicircular cutout 3 being formed at the center of each side of the chip carrier 2.

A second cutout 3A is cut out in the cutout 3 on the upper surface of the chip carrier 2, wherein in the aforementioned molding step, the molding resin 9 is introduced into the second cutout 3A in addition to the cutout 3, so that the molding resin 9 partially formed inside the second cutout 3A is bonded to the back of the semiconductor chip 8.

The third embodiment can provide the same effect as that demonstrated in the first embodiment, in which the total contact area between the semiconductor chip 8 and the mold resin 9 can be increased due to the formation of the second cutout 3A. Further, second cutouts 3A are formed at the side edges of the upper surface of chip stage 2; therefore, in the wire bonding step described above, a stable condition in which the chip stage 2 is fixed can be maintained, the chip stage 2 serving as a base for mounting the semiconductor chip 8.

Next, a fourth embodiment of the present invention will be described, in which parts equivalent to those used in the first to third embodiments are designated by the same reference numerals; therefore, detailed description will be omitted.

Fig. 14 shows a lead frame 1 and a semiconductor device 10 according to a fourth embodiment of the present invention, in which a chip carrier 2 is provided with through holes 3B in addition to semicircular cutouts 3, the through holes 3B penetrating through corner portions of the chip carrier 2.

Each through-hole 3B is cut on both the upper surface and the back of the chip carrier 2, wherein in the above-described molding step, the molding resin 9 is introduced into the inside of the through-hole 3B in addition to the cut 3, so that the molding resin 9 partially formed inside the through-hole 3B is bonded to the back of the semiconductor chip 8.

The fourth embodiment can provide the same effect as that demonstrated in the first embodiment, in which the total contact area formed between the semiconductor chip 8 and the molding resin 9 can be further increased. Further, the through-holes 3B do not interfere with the sides of the chip stage 2 forming the peripheral portion of the chip stage 2; therefore, in the wire bonding step described above, a stable situation in which the chip stage 2 is fixed can be maintained, the chip stage 2 serving as a base for mounting the semiconductor chip 8. Incidentally, the fourth embodiment can be modified in such a manner that the upper surface or the back of the chip carrier 2 is subjected to half etching at a specified area surrounding the through-hole 3B.

Next, a fifth embodiment of the present invention will be described, in which parts equivalent to those used in the first to fourth embodiments are designated by the same reference numerals; therefore, detailed description will be omitted.

Fig. 15A and 15B show a lead frame 1 and a semiconductor device 10 according to a fifth embodiment of the present invention, in which a third cutout 3C is formed on the back of a chip carrier by performing half etching so as to provide communication between "opposing" cutouts 3 formed at the centers of the sides of the chip carrier 2.

A third slit 3C is cut between the slits 3 on the back of the chip carrier 2, wherein in the above-described molding step, the molding resin 9 is introduced into the third slit 3C in addition to the slits 3.

The fifth embodiment demonstrates the same effects as those set forth in the first embodiment, and it can also demonstrate the same effects as those set forth in the second embodiment.

Next, a sixth embodiment of the present invention will be described, in which parts equivalent to those used in the first to fifth embodiments are designated by the same reference numerals; therefore, detailed description will be omitted.

Fig. 16A and 16B show a lead frame 1 and a semiconductor device 10 according to a sixth embodiment of the present invention, in which a third cutout 3C is formed on the upper surface of a chip carrier 2 by performing half etching so as to provide communication between "opposing" cutouts 3 formed at the centers of the sides of the chip carrier 2.

Third cutouts 3C are cut between the cutouts 3 on the upper surface of the chip carrier 2, wherein in the above-described molding step, the mold resin 9 is introduced into the third cutouts 3C in addition to the cutouts 3, so that the mold resin 9 partially formed inside the third cutouts 3C engages the back portions of the semiconductor chips 8.

The sixth embodiment demonstrates the same effects as those set forth in the first embodiment, and it can also demonstrate the same effects as those set forth in the third embodiment.

Next, a seventh embodiment of the present invention will be described, in which parts equivalent to those used in the first to sixth embodiments are designated by the same reference numerals; therefore, detailed description will be omitted.

Fig. 17 shows a lead frame 1 and a semiconductor device 10 according to a seventh embodiment of the present invention, in which a plurality of semicircular cutouts 3 are formed on each of four sides of a chip carrier 2, so that the same effects as those set forth in the first embodiment can be demonstrated.

Next, an eighth embodiment of the present invention will be described, in which parts equivalent to those used in the first to seventh embodiments are designated by the same reference numerals; therefore, detailed description will be omitted.

Fig. 18A and 18B show a lead frame 1 and a semiconductor device 10 according to an eighth embodiment of the present invention, in which a plurality of semicircular cutouts 3 are formed on each of four sides of a chip carrier 2, and a fourth cutout 3D is formed on an upper surface of a peripheral portion of the chip carrier 2 including the cutouts 3 by performing half etching.

Fourth cutouts 3D are cut between the cutouts 3 in the upper surface of the chip carrier 2 at the corners thereof, wherein in the above-described molding step, the mold resin 9 is introduced into the fourth cutouts 3D in addition to the cutouts 3, so that the mold resin 9 partially formed inside the fourth cutouts 3D engages the back portions of the semiconductor chips 8.

The eighth embodiment demonstrates the same effects as those set forth in the first embodiment, and it can also demonstrate the same effects as those set forth in the third embodiment.

Incidentally, the cutout 3 of the chip carrier 2 is not necessarily limited to a semicircular shape, and may be changed to, for example, a triangular shape or a rectangular shape.

As described so far, the present invention has various effects and technical features as will be described below.

(1) The semiconductor device including the lead frame according to the present invention is designed so as to shape the outer shape of the chip carrier to be smaller than the outer shape of the semiconductor chip, thereby making it possible to minimize a separation area which may be formed in the boundary between the chip carrier and the molding resin due to heating when the semiconductor device is soldered onto a circuit board. This can prevent the separation area formed near the chip carrier from extending to the boundary between the semiconductor chip and the molding resin; therefore, it is possible to prevent the weld line from being undesirably broken due to the formation of cracks due to the growth of separation.

(2) The plurality of cutouts are sufficiently formed at the peripheral portion of the chip stage so that the mold resin formed inside the cutouts can firmly bond the back portion of the semiconductor chip. Therefore, even when separation occurs in the boundary between the chip stage and the molding resin, it does not extend toward the boundary between the semiconductor chip and the molding resin; therefore, it is possible to prevent the weld line from being undesirably broken due to the formation of cracks due to the growth of separation.

(3) As a result, although the semiconductor device is firmly bonded to the circuit board using the lead-free solder containing no toxic substance such as lead (Pb), it is possible to prevent the solder line from being undesirably broken due to the formation of cracks in the molding resin in the heating process. Thus, the yield in manufacturing the electronic device can be increased, which contributes to environmental protection.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (11)

1. A lead frame (1) comprising:

a chip carrier (2) for mounting a semiconductor chip (8) thereon, wherein an outer shape of the chip carrier is shaped smaller than an outer shape of the semiconductor chip; and

a plurality of semicircular cutouts (3) formed in a peripheral portion of the chip carrier, wherein the chip carrier and the semiconductor chip are integrally encapsulated in a molding resin (9) introduced into the cutouts of the chip carrier,

wherein a length L2 of each of the cutouts is defined in a range of L1 × 0.05 to L1 × 0.20, wherein L1 represents a length of each side of the chip carrier.

2. The lead frame according to claim 1, wherein said chip carrier has a rectangular shape such that said plurality of cutouts are formed inwardly with respect to four sides of said chip carrier.

3. The lead frame according to claim 1, wherein said cutout has a half-etched portion (3A, 3C) formed inside said chip carrier.

4. The lead frame according to claim 1, wherein a plurality of second cutouts (3B) are formed inside said chip carrier with respect to said cutouts.

5. The lead frame according to claim 1, wherein a total area S2 of said chip stage is defined in a range of S1 x 0.10 to S1 x 0.40, where S1 denotes a total area of said semiconductor chip.

6. A semiconductor device (10) comprising:

a semiconductor chip (8);

a lead frame (1) having a chip carrier (2) for mounting the semiconductor chip thereon, wherein an outer shape of the chip carrier is shaped smaller than an outer shape of the semiconductor chip;

a plurality of semicircular cutouts (3) formed in a peripheral portion of the chip carrier; and

a mold resin (9) for integrally encapsulating the chip carrier and the semiconductor chip, wherein the mold resin is introduced into the cutout of the chip carrier,

wherein a length L2 of each of the slit arrangements is defined in a range of L1 × 0.05 to L1 × 0.20, wherein L1 denotes a length of each side arrangement of the chip carrier.

7. The semiconductor device according to claim 6, wherein the chip carrier has a rectangular shape such that the plurality of cutouts are formed inward with respect to four sides of the chip carrier.

8. The semiconductor device according to claim 6, wherein said cutout has a half-etched portion (3A, 3C) formed inside said chip carrier.

9. The semiconductor device according to claim 6, wherein a plurality of second cutouts (3B) are formed inside said chip carrier with respect to said cutouts.

10. The semiconductor device according to claim 6, wherein a total area S2 of the chip stage is defined in a range of S1 x 0.10 to S1 x 0.40, where S1 denotes the total area of the semiconductor chip.

11. A semiconductor device according to any one of claims 6 to 10, wherein the lead frame is bonded to the circuit board using a lead-free solder.