HK1068982A - Smart memory - Google Patents

Description

Intelligent memory

Technical Field

The present invention relates to integrated circuit memory chips and, more particularly, to an enhanced integrated circuit memory chip that incorporates additional functionality into a standard memory package.

Background

Portable electronic devices such as laptop computers, cell phones, personal digital assistants (PDA's), handheld or portable game consoles such as those manufactured by Nintendo and Sony, and other portable electronic devices, all of which employ standard integrated circuit memory. Standard memory includes, but is not limited to, Static Random Access Memory (SRAM), pseudo-SRAM, Dynamic Random Access Memory (DRAM), flash memory, Electrically Erasable Programmable Read Only Memory (EEPROM), Electrically Programmable Read Only Memory (EPROM), Read Only Memory (ROM), and the like. The various standards of memory are commonly manufactured by many memory manufacturers such as Samsung, Sony, Mitsubishi, NEC, Micron, Infineon, Cypress, IDT, UMC, Hyundai, and so on. Since standard memory is a commodity that is heavily consumed, there are industry standards that define various physical forms and electrical functions of various memory packages, such as Small Outline Packages (SOPs), Thin Small Outline Packages (TSOPs), scaled small outline packages (stsels), and a Ball Grid Array (BGA) package. For pin-in packages such as various Small Outline Packages (SOPs), one industry standard includes pin-line configurations. For BGA packages, an industry standard includes the diameter size of the balls, pitch, and layout.

Successful memory products tend to become industry standard and thus important to memory. An Original Equipment Manufacturer (OEM) is preferably an industry standard that is a buyer of standard memory and prefers multiple suppliers of the same parts so that the OEM may have multiple sources for competitive pricing, scheduling and other considerations. Memory manufacturers also agree to standardization, particularly for those more recent manufacturers who want to acquire customers of existing suppliers. In order to compete with existing vendors, newer memory manufacturers must maintain the same basic configuration, form and functionality as a standard integrated circuit memory package or at least minimize the difference between the manufacturer's product and the standard. The configuration of the memory package is the size of a memory integrated circuit package in all three dimensions and the wiring configuration of the memory integrated circuit package. In the form of a kind of encapsulation and an encapsulating material, such as plastic or ceramic. Procurement of an industry-standard component will minimize the work required by the customer OEM manufacturer to accommodate the integrated circuits of newer memory manufacturers. Memory integrated circuits of newer memory manufacturers typically have the same memory function as existing vendor memory integrated circuits. Newer memory integrated circuits often have improvements in speed, power consumption, and performance to make newer memory integrated circuits more attractive than those offered by existing vendors.

The processing technology for memory fabrication has been improved so that every few years the density and size of the memory has doubled. For example, in the wireless communications industry, the memory required for cell phones has typically increased from 1MB SRAM with 8MB flash memory to 2/4/8MB SRAM with 16/32/64MB flash memory. The configuration and form of the memory package has evolved from an SRAM package and a separate flash memory to a flash/SRAM combination package that places the SRAM and flash memory into the same package module, such as a Ball Grid Array (BGA). All BGA flash/SRAM combinations have similar package sizes, types, ball pitches and configurations, while, as previously mentioned, the combinations are interchangeable with other manufacturers' products for customer specific applications.

As the design of handsets moves from 2G (second generation) to beyond 3G (third generation), the memory required for new handset designs is further increased. In RAM design, SRAM is evolving into pseudo-static memory having a DRAM core cell and a static RAM I/O interface. Finally, as the size and density of memories increase, SRAM will develop into pure DRAM for cost reasons.

New wireless communication devices such as cell phones, PDAs, game consoles and other portable devices require an increase in memory array size. Along with the need to increase the size of memory arrays, many additional functions are being added to wireless communication devices because cell phone designs have moved from analog to digital formats. Currently, new handset designs provide high fidelity sound quality and provide audio signal capabilities, such as MP3 music, video, and other multimedia capabilities. Other additional functions being added to wireless communication devices include bluetooth devices for short-range wireless communication between the network access data stream, the Global Positioning System (GPS) of real-time directions and locations on maps, and wireless communication devices. Other additional functions are being introduced by IC vendors and added to cell phones and other wireless communication devices.

The wireless communications industry has rapidly developed in the 1990's. In 1999, global mobile phones sold about 2 hundred million and 8 million. In 2000, global mobile phone sales exceeded 4 billion stations and estimated to approach 5 billion stations in 2001. With the explosion of the internet, the global economy driven by the internet is motivating and starting a rapidly growing market for mobile data content and applications.

Fig. 1 is a diagram illustrating the evolution of various stages of a mobile communication system. The radio industry has evolved from the initial first generation 1G to second generation 2G telephony to the 2.5G digital phase. The third generation 3G digital multimedia phase provides wireless multimedia devices such as cell phones and wireless Personal Digital Assistants (PDAs) such as Palm, palmtop and laptop computers. These 3G multimedia wireless devices are provided with high definition color image displays, which are comparable in quality to television sets or personal computer monitors. In order to minimize the amount of data transfer required for such multimedia wireless devices, data compression and decompression (CODEC) techniques such as the moving Picture Expert Group-4(MPEG-4) are widely used for streaming audiovisual information to provide applications such as digital access media, content-based access for digital audiovisual communications, and other applications. Some companies have developed CODEC DSP chips that are capable of transmitting and receiving high quality audio and video signals over the internet and next generation mobile handsets. The CODEC DSP chip employs a Quarter Common Intermediate Format (QCIF) standard screen size of 176 x 144 pixels to reproduce images in a videophone at typical speeds of 10 to 15 frames per second.

Typical handset devices employ an embedded controller/processor in conjunction with analog-to-digital (a-to-D) and digital-to-analog (D-to-a) converters to implement the CODEC DSP in the baseband IC chip of the handset.

In addition to CODECs, baseband (BB) IC vendors are also adding one or more additional functions such as Global Positioning System (GPS) and bluetooth local wireless communication functions to the vendor's baseband integrated circuit. To achieve the full functionality, manufacturers such as ARM, Intel, and MIP are required to make better processors to run at high clock frequencies and meet the processing requirements of additional functionality. The current strong processors operating at high data rates consume significant power, thus draining the battery quickly and reducing the effective operating time of the mobile handset.

In addition, to store data stored in the integrated circuit memory in the handset for use as data encoding/decoding, data compression/decompression and display, the baseband chip must communicate with the memory chip on a printed circuit data bus each clock cycle, the bus being between the single baseband integrated circuit package and the memory integrated circuit package. To efficiently drive a Printed Circuit (PCB) data bus between a single baseband integrated circuit package and a single memory integrated circuit package at a sufficiently high data rate, the integrated circuit output drivers on each integrated circuit provide sufficient current drive to the PCB data bus. This further increases power consumption and drains the battery.

Fig. 2 shows a simplified system architecture of a prior art multimedia wireless system 10, which is employed in a typical wireless communication device such as a cellular phone. The system generally includes several discrete integrated circuit packages that are interconnected by a bus on a printed circuit, represented by PCB bus 12. An RF integrated circuit 14 transmits and receives RF signals through an antenna 16. Data signals are transferred to and from the RF integrated circuit 14 on the PCB bus 12. A standard memory integrated circuit package 18, such as an SRAM or FLASH/SRAM combination memory, is connected to the system bus 12 at its terminals. Terminals of an LCD display controller integrated circuit 20 are connected to the system bus 12 and provide signals for displaying text on a suitable LCD display device 21, such as an LCD text display screen. A baseband (BB) integrated circuit 22 is equipped with a micro control core such as that provided by ARM or MIPs.

Fig. 2 shows most of the additional functionality required in a typical handset, typically provided by a baseband integrated circuit 22. Additional functions such as MPEG4 functions, which are equipped with either hardwired or hardwired functions, are embedded in the hardware and/or software of baseband integrated circuit 22.

Where the baseband integrated circuit is not capable of accommodating additional functionality, one or more integrated circuit packages of particular additional functionality are provided, as indicated at 24, for example, a GPS integrated circuit chip package providing the desired additional functionality. To provide more specific functionality, a set of baseband chips is provided, typically including a microcontroller and one or more additional DSP integrated circuits.

It is believed that handset manufacturers dislike the use of additional integrated circuits in the baseband chipset. The additional integrated circuit will increase the size of the printed circuit in the handset, increase the weight of the handset, require more inventory and control of the additional integrated circuit, and add additional cost. Thus, as the cellular industry develops more advanced models of cellular telephones, there is a trend to incorporate as many functions as possible into a single multifunction baseband integrated circuit and to eliminate specially-functioning integrated circuits or chipsets.

However, it should also be appreciated that the handset industry tends to add more functionality to a single baseband integrated circuit or a baseband chipset in order to increase the complexity of the baseband integrated circuit or chipset and require additional signal processing capability in the baseband integrated circuit. For example, the basic microcontroller employed in baseband chips has been changed from ARM 7 to 9 to ARM10 to 11, and the clock cycle rate is from megahertz to several hundred megahertz. The greatly increased performance requirements of a single baseband integrated circuit or a baseband chipset will increase the size, number, complexity, and cost of the baseband integrated circuit.

It is also seen that more energy is required for more complex baseband integrated circuits. In the future, 3G and beyond designs will be required and handsets or wireless devices will often be equipped with baseband integrated circuits that need to operate often at very high clock rates. This will greatly increase the power consumption of the baseband integrated circuit and quickly drain the battery of the handset, and the available time between charging of the handset battery is shortened.

Accordingly, there is a need for a technical approach to adding additional memory enhancement functionality to a portable electronic device, such as a wireless device or a cell phone, without increasing the number of packages and power consumption, while maintaining substantially the same configuration and form as a standard memory integrated circuit.

Disclosure of Invention

It is therefore an object of the present invention to provide a method for adding additional functionality of mobile communication and consumer electronics to a wireless device, such as a cellular phone. The method does not significantly increase power consumption and provide additional functionality while maintaining substantially the same configuration and form as a standard integrated circuit memory.

The present invention provides a smart memory that includes a memory array and additional functionality that is enhanced in conjunction with one or more memories. All of which are packaged in a standard memory package to ease the workload of a baseband chip. By combining the additional functionality of the memory enhancement with a standard memory package, such as a flash-SRAM combination package, a number of advantages are obtained. The advantages include: integrated circuit packages that do not require additional special functions; the functions performed by the baseband chip are greatly reduced and the clock rate and power consumption of the baseband chip are reduced.

One type of smart memory chip is a multimedia ram (mmram) chip having a memory array and a compressor/decompressor (CODEC) portion on a single integrated circuit chip, with the connections between the memory array and CODEC portions being on the single integrated circuit chip.

The smart memory and the multimedia RAM are provided with a single chip architecture that greatly reduces the processing rate and power required by the baseband microcontroller unit (MPU). The smart memory and multimedia RAM are equipped with minimal or no modification of a PC board, such as a PC board of a personal communication device, using the same package as a conventional memory, having a similar or identical pin or ball-and-bump design. Special functions, such as the MPEG4 function, interact internally with the flash/RAM memory without the need for external I/O buffers. The present invention allows for low voltage and low power data interaction that occurs on the same chip or between chips in the same package that stores enhanced functionality, such as is required in an MPEG4 system. Internal special functions may be achieved using an internal supply voltage level that is lower than the external supply voltage level, i.e., a level required to interface with the outside of other integrated circuit packages.

The present invention provides a smart memory integrated circuit device that includes a memory array portion and a special function portion that is packaged with the memory array portion in separate smart memory integrated circuit packages. Such a configuration provides a single smart memory integrated circuit package that incorporates all of the memory functions of a standard memory array into the single integrated circuit package, except for the special functions provided by the special function portion. The separate smart memory integrated circuit package is substantially the same type, configuration and form as a conventional memory package, but the conventional memory package has only a memory array without special functionality.

The special function portion is connected to the memory array portion through a common internal bus in the smart memory integrated circuit package. The invention is particularly useful for special functions, i.e. memory intensive functions, in other words, functions requiring a lot of interaction with a memory array. Thus, the present invention greatly reduces the need for the memory array portion to communicate with other external baseband integrated circuits via an external shared bus that has significant propagation delays, parasitic capacitances, inductances, and resistances, and needs to be driven by higher current interface driver circuits.

Smart memory is used in a wireless device to replace a standard memory product and also to add special features to a standard memory package. The smart memory therefore does not require the addition of a special function IC; no strong baseband chip is required or the design of the hardware, software, system architecture and a printed circuit of the wireless device need to be changed significantly, and its individual package design can be installed in the wireless device.

In one embodiment of the invention, the memory array portion and the special function portion are monolithically formed as a single integrated circuit chip. The memory array portion and the special function portion are formed on a single integrated circuit in the same manufacturing method. In another aspect, the memory array portion and the special function portion are provided as separate integrated circuit chips contained in the same smart memory package. To conserve power, the special function portion operates with an internal power supply voltage level that is lower than an external power supply voltage level of the smart memory integrated circuit package.

The special function portion of an intelligent memory includes a number of special functions. One particular set of functions includes functions selected from the group consisting of high fidelity audio systems, codecs, wireless local communication systems, streaming video systems, wireless LANs, global positioning systems, and a video presentation. Many memory types that are employed include a memory array portion selected from the group consisting of an SRAM, a pseudo SRAM, DRAM, EEPROM, EPROM, flash, DRAM/flash combinations, ferroelectric RAM, and magnetized RAM. In addition, many kinds of smart memory packages may be employed, such as ball grid array, BGA, packages.

One type of smart memory is a multimedia RAM (mmram) having a memory array portion on a separate integrated circuit chip formed on the separate integrated circuit chip and contained in a multimedia RAM package. A compressor/decompressor (CODEC) portion is integrally formed on the same separate integrated circuit chip and contained in the same multimedia RAM package as the conventional memory array portion. The CODEC portions are formed in the same manufacturing process as the conventional memory array portion and the connections between the memory array portion and the CODEC portions are on the same, separate integrated circuit chip.

The CODEC of the multimedia RAM is provided as hardwired logic on a separate integrated circuit chip. In another aspect, the CODEC is disposed on a separate integrated circuit chip via the digital signal processor.

A multimedia RAM according to the present invention is particularly useful for wireless devices having a baseband DSP IC and wherein the separate IC chip is adapted to have minimal I/O interfaces with the baseband DSP IC in the wireless device, thus reducing the processing data rate of the baseband DSP IC.

The packaging of the monolithic multimedia RAM according to the present invention is substantially the same as that of a conventional memory array.

In accordance with the present invention, a method is provided for enhancing the capabilities of an integrated circuit memory by packaging the memory array portion with the special function portion in a single smart integrated circuit package. The method includes adding all memory functions of a standard memory (provided by the memory array portion) to a separate smart memory integrated circuit package, as well as adding special functions (provided by the special function portion). Such a single smart memory integrated circuit package has the type, configuration and form of a conventional standard memory package with no special functional portion but with a memory array portion. The separate smart memory integrated circuit provided according to the present method is suitable for replacing the memory products standardized in wireless devices. The separate smart memory integrated circuit incorporates the special function portion into the smart memory integrated circuit package without the need for additional special function ICs, without the need for a strong baseband chip, and without significantly changing the hardware, software, system architecture of the wireless device and the design of the printed circuit on which the separate package is mounted in the wireless device.

The method ensures that the special function portion is connected to the memory array portion through a common internal bus in the smart memory integrated circuit package. This greatly reduces the need for the memory array portion to communicate with external baseband integrated circuits via an external shared bus that has significant propagation delays, parasitic capacitances, inductances, and resistances, as well as interface driver circuits that require higher currents. The method uses the same manufacturing method to form the memory array portion and the special function portion together as a single integrated circuit chip. In another aspect, the method includes forming the memory array portion and the special function portion as a single integrated circuit chip and then packaging the chips together in a single smart memory integrated circuit package.

The method ensures that the special function portion operates at an internal power supply voltage level that is lower than the external power supply voltage level of the smart memory integrated circuit package. The special function portion is selected from the group consisting of a high fidelity audio system, a multimedia digital signal codec, a wireless local communication system, a streaming video system, a wireless LAN, a global positioning system, and a video display. The memory array portion is selected from the group consisting of SRAM, a pseudo SRAM, DRAM, EEPROM, EPROM, flash, a DRAM/flash combination, ferroelectric RAM and magnetized RAM.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a diagram illustrating the evolution of various stages of a mobile communication system standard.

FIG. 2 is a block diagram illustrating the architecture of a conventional system of a prior art conventional multimedia wireless system, in which a memory enhanced MPEG4 function is embedded in the hardware and software of the baseband chip and other additional memory enhanced functions are embedded in an additional chip or chipset;

FIG. 3 is a block diagram showing the architecture of a multimedia wireless system of the present invention by which an additional memory enhancement function, such as an MPEG4 multimedia function, is embedded in hardware and software in a separate memory chip package; and

FIG. 4 is a block diagram of a chip architecture of a memory chip of a multimedia integrated circuit according to the present invention.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to the embodiments described. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims.

Fig. 3 shows a general system architecture for implementing a multimedia wireless system 30 employed in a typical wireless communication device, such as a cellular phone. In contrast to the conventional system of fig. 2, the wireless communication system 30 includes integrated circuit packages that are in much less communication with each other via a system printed circuit bus 32. A system of the present invention is very different from conventional systems. It should be appreciated that the present system requires fewer individual integrated circuit packages and much less need for the system bus 32 of fig. 3, which is most important to efficiently rearrange memory enhancement functions within the integrated circuit packages. This allows low voltage and low power data interaction to occur on the same chip or between chips in the same package that stores enhanced functionality such as that required by MPEG4 systems.

Fig. 3 shows a system 30 having a printed circuit bus 32 that provides appropriate signals between a simplified baseband (BB) integrated circuit 34 and an intelligent multimedia memory (MMRAM) integrated circuit 36 in accordance with the present invention. The intelligent multimedia memory MMRAM integrated circuit 36 configured in accordance with the present invention combines a memory array with a memory enhancement feature such as MPEG4 CODEC in a single chip or package.

Because the multimedia memory MMRAM integrated circuit 36 also includes display controller circuitry to provide signals to an appropriate display device, such as an LCD screen 40, a separate display controller integrated circuit is not required. The multimedia memory MMRAM integrated circuit 36 is also directly connected to a camera 42.

The baseband (BB) integrated circuit 34 may be simplified because additional memory enhancement functions, such as MPEG4, need not be left in the baseband (BB) integrated circuit 38. The multimedia memory MMRAM integrated circuit 36 is provided with an ARM or MIP microcontroller core as required.

The intelligent multimedia memory MMRAM integrated circuit 36 is provided with a standard memory function in a package that has substantially the same footprint, style and configuration as a standard integrated circuit memory package. In addition, the integrated circuit package of the smart memory also incorporates one or more memory enhancement functions into the same package. These memory enhancement functions are provided to a hardwired or hardwired compressor/decompressor (CODEC) function such as MPEG4 in the multimedia memory MMRAM integrated circuit 36. Placing memory enhancement functions such as CODECs in the same chip as a memory array has significant advantages over the prior art of attaching separate baseband chips that must be communicatively coupled at high signal levels over a bus between separate integrated circuits. Handsets and other wireless devices employ standard memory to process large amounts of data, including program code or other code stored in the handset.

By adding additional memory enhancement functions to a standard memory, such as a flash-SRAM combination, it is possible to eliminate the need for separate special function integrated circuits. Then, it is possible to reduce the functions performed by the baseband chip and reduce the clock frequency and power consumption of the baseband chip.

Even though the multimedia memory MMRAM integrated circuit 36 provides MPEG4 multimedia functionality, the smart memory package according to the present invention is packaged in a standard memory package with embedded logic functionality. The embedded logic function is provided by hard-wired logic or by software built in DSP macro cells, whether or not there is an on-chip microcontroller core.

The multimedia memory MMRAM integrated circuit 36 has a number of important advantageous features. An important advantageous feature of the multimedia memory MMRAM integrated circuit 36 according to the present invention is that the circuit performs all of the conventional functions of a standard memory package and takes the same package, configuration and style as a standard memory. Thus, a multimedia memory MMRAM integrated circuit 36 is a substantially compatible replacement for the pins of a standard memory package used in PCB designs for existing handset configurations. Thus, the multimedia memory MMRAM integrated circuit 36 can easily replace the special functionality of an existing standard memory package with existing baseband software with only minor modifications and with minor changes on the handset PCB if desired. Existing handset designs may employ the multimedia memory MMRAM integrated circuit 36 to almost immediately incorporate additional functionality already incorporated into the multimedia memory MMRAM integrated circuit 36.

The additional functionality incorporated into the multimedia memory MMRAM integrated circuit 36 chip or package does not require a separate additional special function integrated circuit. In addition, the fundamental frequency chip does not need to be changed if a stronger fundamental frequency chip is not needed. No additional chip or stronger baseband chip is required to obtain the special functionality provided by the multimedia memory MMRAM integrated circuit 36. It is also important that the multimedia memory MMRAM integrated circuit 36 according to the present invention greatly reduces the time required to develop new products, where such product development typically takes several months to over one or two years.

Another important advantageous feature of the multimedia memory MMRAM integrated circuit 36 according to the present invention is to tie the memory intensive functions on the multimedia memory MMRAM integrated circuit 36 so as to reduce the amount of work required from the baseband chip.

The baseband chip does not need to operate at a very high clock frequency to perform various memory intensive functions, and the invention can enable the baseband chip to operate in a plurality of monitoring modes. In the monitor mode, the baseband chip functions just specified to be performed by the multimedia memory MMRAM integrated circuit 36. The designated functions may include video signal codec functions, display drivers, a GPS location function or bluetooth data stream functions, and the like. After the designated function is performed by the multimedia memory MMRAM integrated circuit 36, the baseband chip continues to do other tasks. The multimedia memory MMRAM integrated circuit 36 then consults the baseband chip only when needed and/or when the tasks of the multimedia memory MMRAM integrated circuit 36 are completed. By distributing memory enhancement functions to the multimedia memory MMRAM integrated circuit 36, the baseband chip can operate at a relatively low clock frequency and reduce power consumption of the chip.

Monolithic addition of memory enhancement functions to the smart memory chip also provides the multimedia memory MMRAM integrated circuit 36 with its own internal hardwired logic, microcontroller and/or DSP functions. In the case where no multimedia memory MMRAM integrated circuit 36 is needed external to the memory enhancement function, no high current input/output interface driver is needed because the power required for the communication in one chip is much less than the power required to drive another separate chip on a common bus through an external interface. Since the multimedia memory MMRAM integrated circuit 36 stores, retrieves, and decodes data internally on the same chip or package without driving another external chip such as an external baseband chip, there is no need for high current I/O drivers in the multimedia memory MMRAM integrated circuit 36. This greatly reduces the power consumption required to combine the memory retrieval and decoding functions.

Many integrated circuit designs employ dual or multiple supply voltages VCC. For example, the external I/O communication between the chip and other chips uses a 3V power supply, and the internal signal communication in one chip uses a 1.5V internal power supply. A single monolithic chip according to the present invention internally places all memory enhancement functions into a single memory chip. Instead, the conventional approach is to add all new memory enhancement functions to a single baseband chip. The memory enhancement function using the baseband chip or an additional chip set requires a fixed outer surface between the memory chip and the baseband chip. Because the memory enhancement function is internal to the smart memory integrated circuit chip, the memory enhancement function is now enabled with the low voltage of the available internal supply voltage. For example, an internal voltage of 1.5V is used instead of an external voltage of 3V. The chip power is reduced by a factor of four as a result of the power scaling to the square of the voltage. It should be appreciated that internally coupling signals between a memory array and a memory enhancement function in a single smart memory integrated circuit chip greatly reduces signal propagation delays and removes additional I/O parasitic capacitance and resistive loading.

The present invention provides for storage enhancement functions, such as the data compression/decompression CODEC function of MPEG4, to be incorporated into the same memory integrated circuit chip package that is currently employed on all wireless handset devices. The memory includes SRAM, low power DRAM, pseudo static RAM, and flash/RAM combined IC, typically in a Ball Grid Array (BGA) package.

CODECs are implemented by Digital Signal Processing (DSP) techniques or employ hardwired logic gates. By using hardwired logic for calculations in the smart memory integrated circuit chip, the smart integrated circuit chip detaches or eliminates the CODEC function from the baseband (BB) IC. This will greatly reduce the processing requirements of the baseband IC 38.

CODEC functions implemented in hardwired logic may typically incorporate 10 to 30 thousand gates. This would require a smaller silicon chip than would be required for a typical memory in a typical telephone handset. The memory range of a typical cell phone is from 8 to 32MB, such as SRAM. Thus, memory intensive CODECs can be incorporated into smart memory integrated circuit chips without a significant increase in chip area. The final smart memory integrated circuit chip in the BGA package is also provided with the same pin configuration as existing conventional memories that employ the same BGA pin configuration.

The main advantage of being able to implement additional memory enhancement functions, such as multimedia functions in a cell phone, in the same package as a conventional memory pin package is portability for many applications. For example, the conventional memory in a GPRS phone can be replaced by the MMRAM package of the present invention, which has the same density and pin configuration as the typical memory package used in a cell phone. For a flash/SRAM combination chip in a BGA (ball grid array) package, the smart memory integrated circuit package employs the same package and the same ball pitch and configuration as conventional memory. Any additional pins, such as clocks or interrupt types, are added to the same ball/pin configuration map. Modifying the existing baseband chip with software can greatly enhance the handset functionality, making it multimedia capable and more attractive to service providers and end customers. A product according to the present invention serves instant video clip-on services and enables video communication to other wireless devices such as PDAs, laptops, smart cameras, cell phones and others by wireless. Video clips with download features and/or internet video will be very popular, as evidenced by the great success of IMODE offered by SMS (short message service) and NTT DoCoMo offered in europe. An MMRAM or smart memory integrated circuit package according to the present invention enables video clips in the form of SMS. In addition, strong support is available from multimedia service providers because video clips are associated with data packets and because service providers can support such services for a fee per message (as opposed to a timed) basis.

Since the multimedia CODEC function is implemented in the memory chip rather than in a separate baseband chip, an integrated CODEC function can be completely portable and can be used with a variety of different baseband chips such as TI, Analog device, Qualcomm, Infineon, etc. as long as the software of the existing baseband chip IC is modified. The present invention provides portability between designs of various equipment manufacturers for personal communication devices. The present invention provides the ability to add additional multimedia functionality to a smart storage integrated circuit package to reduce the power requirements of a personal communication device and can replace the traditional handset memory with an MMRAM or an MMRAM-flash combination plus less/no modification of the printed circuit board/module. The present invention provides a new set of special function memory packages that provide many applications for a new generation of multimedia wireless devices.

Fig. 4 shows an example of the architecture of an intelligent multimedia integrated circuit memory chip 50 according to the present invention. The memory slice 50 includes a conventional memory portion 52, an MPEG4 special function portion 54, and a video recording interface special function portion 56. The package of the chip 50 has substantially the same kind, configuration and form of package as that of a conventional memory having only a memory array without a particular function.

The memory portion 52 includes a RAM array 60 to which address signals are supplied from an address logic circuit 64 via an address bus 62. The address logic 64 receives an external address signal from an address input signal bus 66. Internal address signals are received from the internal address bus 68. Internal control signals are received from the internal address control bus 70. Memory control signals are provided from a RAM control circuit 73 via memory control bus 72, said circuit 73 receiving chip enable signal CE via signal line 74, enable write signal WE via signal line 76 and output enable signal OE via signal line 78.

The memory portion 52 also includes an I/O logic circuit 80 that transmits and receives memory data from the RAM array 60 via the internal memory data bus. The I/O logic 80 transmits and receives data signals between the MPEG4 special function section 54 via a data bus 90. Control signals for the I/O logic 80 are received from the MPEG4 special function section 54 via control lines 92.

The I/O logic circuit 80 transmits and receives memory data via a data bus 84 connected to the I/O input receiver/output buffer circuits. External input and output data is received and transmitted via a data I/O bus.

Special function portion 54 of MPEG4 includes an MPEG4 data compressor/decompressor CODEC circuit 100, a microcontroller core 102 and a system control circuit 104. The clock signal is supplied via a control line to MPEG4 data compressor/decompressor CODEC circuit 100, a microcontroller core 102 and a system control circuit 104. Microcontroller 102 supplies control signals to MPEG4 CODEC circuit 100 via control lines 108. The microcontroller 102 also supplies control signals to the system control circuitry 104 via control lines 110. MPEG4 CODEC circuit 100 supplies control signals to system control circuit 104 via control lines 112. MPEG4 CODEC circuit 100 supplies address signals to system control circuit 104 via address signal bus 114.

The video recording interface special function portion 56 includes a display driver circuit 116 that receives input signals from MPEG4 CODEC circuit 100 via signal bus 118. The output display signals from the MPEG4 CODEC circuit 100 are supplied to an external display device, such as an LCD display, via a signal bus.

The video interface special function portion 56 includes a camera interface circuit 122 that receives external camera signals via a bus 124. The camera interface circuit 122 supplies output signals to the MPEG4 CODEC circuit 100 via the bus 126.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined from the appended claims and equivalents thereof.

Claims (31)

1. An apparatus of a smart memory integrated circuit, the apparatus comprising:

a memory array portion;

a special function portion packaged with the memory array portion in a separate smart memory integrated circuit package; and wherein

The package of the single smart memory integrated circuit combines the memory function of all standard memories provided by the memory array portion with a special function provided by the special portion in a single integrated circuit package.

2. The smart memory of claim 1 wherein the special function portion is connected to the memory array portion by a common internal bus in the smart memory integrated circuit package, thereby substantially reducing the need for the memory array portion to communicate with other external baseband integrated circuits having significant propagation delays, parasitic capacitances, inductances and resistances and which need to be driven with higher current interface drive circuitry via the external common bus.

3. The smart memory of claim 1 wherein said individual smart memory integrated circuit packages are substantially homogeneous, co-configured and co-type with a package of a conventional memory package having a memory array without special functional portions.

4. The smart memory of claim 1 wherein the special function portion provides one or more memory intensive functions.

5. The smart memory of claim 1, wherein the smart integrated circuit package is adapted to replace standard memory products in wireless devices and is also adapted to incorporate special function portions into a standard memory package, thereby requiring no additional special function ICs, requiring no stronger baseband chips, or requiring no significant changes in the design of the hardware, software, system architecture and printed circuitry of the wireless device on which the separate package is mounted.

6. The smart memory of claim 1 wherein the memory array portion and the special function portion are monolithically formed together as a single integrated circuit chip.

7. The smart memory of claim 6 wherein the memory array portion and the special function portion are formed on a single integrated circuit in the same manufacturing process.

8. The smart memory of claim 1 wherein the memory array portion and the extra-function portion are each provided as separate integrated circuit chips contained in the same smart memory package.

9. The smart memory of claim 1 wherein the special function portion and the memory array portion operate at an internal power supply voltage level that is lower than an external power supply voltage level of the smart memory integrated circuit package.

10. The intelligent storage of claim 1, wherein the special features are selected from the group consisting of high fidelity audio system, a multimedia CODEC, a short range wireless communication system, a mobile video system, a wireless LAN, a global positioning system, a video system, and a video display.

11. The smart memory of claim 1 wherein said memory array is selected from the group consisting of an SRAM, a pseudo SRAM, DRAM, EEPROM, EPROM, flash, DRAM/flash combinations, a RAM/flash/ROM combination, ferroelectric RAM, and magnetized RAM.

12. The smart memory of claim 1 wherein the smart memory package is selected from the group consisting of a Ball Grid Array (BGA) package, a shoulder flat package (QFP), a pin grid array (pga) package, and a multi-chip module (MCM) package.

13. An apparatus of a smart memory integrated circuit, the apparatus comprising:

a memory array portion;

a special function portion packaged with the memory array portion in a separate smart memory integrated circuit package; wherein

The package of the separate smart memory integrated circuit combines the memory function of all standard memories provided by the memory array portion with a special function provided by the special portion in the separate integrated circuit package; wherein the special function portion is connected to the memory array portion via a common internal bus in the smart memory integrated circuit package; and wherein

The individual smart memory integrated circuit packages have substantially the same type, configuration and style as a package of a conventional memory package having only a memory array without special functional portions.

14. A multimedia ram (MMRAM) on a single integrated circuit chip, the MMRAM comprising: a memory array portion formed on a separate integrated circuit die and contained in a multimedia RAM package; a compressor/decompressor (CODEC) portion integrally formed on the same separate integrated circuit die and contained within the same multimedia RAM package as the conventional memory array portion, said CODEC portion being formed on the same separate integrated circuit die in the same manufacturing process as the memory array; and wherein the connection between the memory array portion and the CODEC portion is on a separate integrated circuit die.

15. The multimedia RAM of claim 14 wherein the COODEC section is provided as hardwired logic on a separate integrated circuit die.

16. The multimedia RAM of claim 14, wherein the data retrieval and data compression/decompression are performed in a single integrated circuit chip without high current input/output interface circuitry.

17. The multimedia RAM of claim 14, wherein the separate integrated circuit die is adapted for use with a wireless device having a baseband DSP IC and wherein the separate IC die is adapted to have minimal I/O interfacing with the baseband DSP IC in the wireless device.

18. The multimedia RAM of claim 14, wherein the CODEC is provided with a digital signal processor on a single integrated circuit die.

19. The multimedia RAM of claim 18, wherein the CODEC is implemented as a digital signal processor with a microcontroller on a separate integrated circuit chip.

20. The multimedia RAM of claim 18, wherein the package of the separate integrated circuit chip is substantially the same as the package of a conventional memory array formed on the separate integrated circuit chip.

21. The multimedia RAM of claim 14, wherein the multimedia RAM package incorporates special function parts into a standard memory package suitable for replacing a standard memory product in a wireless device, thereby eliminating the need for additional special function ICs, stronger baseband chips, or significant changes to the hardware, software, system architecture, and printed circuit design of the wireless device on which the individual packages in the wireless device are mounted.

22. The multimedia RAM of claim 14, wherein said memory array portion and special function portion are monolithically formed together as a single integrated circuit chip.

23. A method of enhancing memory capability of an integrated circuit, the method comprising the steps of:

packaging a memory array portion with a special function portion in a single smart memory integrated circuit package; and

combining all memory functions of a standard memory provided by the memory array portion with special functions provided by the special function portion in a single smart memory integrated circuit package; wherein

The individual smart memory integrated circuit packages are suitable for replacing standard memory products in a wireless device and for incorporating special function components into the smart memory integrated circuit packages without the need for additional special function ICs, without the need for a stronger baseband chip, or without significantly altering the hardware, software, system architecture, and printed circuit design of the wireless device on which the individual packages are mounted.

24. The method of claim 23, wherein said method comprises the steps of: the need for the memory array portion to communicate with an external baseband integrated circuit via a common external bus, which has significant propagation delays, parasitic capacitances, inductances and resistances, necessitating high current interface driver circuitry driving, is greatly reduced by connecting the special function portion to the memory array portion via a common internal bus in the smart memory integrated circuit package.

25. The method of claim 23, wherein the method includes packaging the memory array portion and the special function portion in separate smart memory integrated circuit packages that are identical, identically configured, and identically configured to a conventional standard memory package having only the memory array portion and no special function portion.

26. The method of claim 23, wherein the method includes forming the memory array portion and the special function portion together as a single integrated circuit.

27. The method of claim 26, wherein the method includes forming the memory array portion and the special function portion on a single die using the same fabrication method.

28. The method of claim 23, wherein the method includes forming the memory array portion and the special function portion as separate integrated circuit chips and packaging the chips together in a separate smart memory integrated circuit package.

29. The method of claim 23, wherein the method includes operating at an internal supply voltage level that is lower than an external supply voltage level of the smart memory integrated circuit package.

30. The method of claim 23, wherein the special features are selected from the group consisting of high fidelity audio systems, codecs, wireless local communication systems, streaming video systems, wireless LANs, global positioning systems, and a video display.

31. The method of claim 23 wherein said memory array portion is selected from the group consisting of an SRAM, a pseudo SRAM, DRAM, EEPROM, EPROM, flash, DRAM/flash combinations, ferroelectric RAM, and magnetized RAM.