HK1068742B

HK1068742B - Demultiplexer for channel interleaving

Info

Publication number: HK1068742B
Application number: HK05100876.4A
Authority: HK
Inventors: 龄富云; J．P．奥登沃尔德
Original assignee: 高通股份有限公司
Priority date: 1998-12-10
Filing date: 2002-04-25
Publication date: 2009-10-16

Description

Demultiplexer for channel interleaved access

This application is a divisional application of the patent application No. 99814320.0 filed on 9.12.1999.

Technical Field

The present invention relates generally to the field of communication systems, and more particularly to demultiplexing of channel interlaces for communication systems with multiple carriers and/or transmitter diversity.

Background

Communication systems often use channel coding and channel interleavers associated therewith. The channel interleaver is particularly important for communication over fading channels. The interleaver is typically formed as a matrix of rows and columns of bit locations for storing data elements, or bits. These bits are written into the interleaver row by row and read out of the interleaver column by column. The interleaver mixes the order of the bits generated in the encoding process. One particularly useful form of interleaver is a bit-reversal interleaver (bit-reversal interleaver) which rearranges the rows as part of the interleaving process, thereby maximizing the time interval between adjacent write bits.

The main purpose of the channel interleaver is to maximize the achievable diversity gain on fading channels. In a single channel communication system, i.e. a communication system with a single carrier (i.e. a single frequency band) and a single antenna, diversity may be achieved by time-spacing consecutively transmitted bits by interleaving, thereby producing reduced correlation between the transmitted bits. When a convolutional encoder, or a multi-element encoder (i.e., a turbo encoder) using a convolutional code as its constituent code, is used for channel coding, bits close to each other may cause multiple error events. The bit-reversal interleaver is particularly efficient because after bit-reversal interleaving the distance between two bits will be roughly inversely proportional to the distance between two bits before interleaving.

As an example, consider a 384-bit interleaver that is constructed as a matrix of 64 rows and 6 columns. A data unit, or a column and column of bits, is written into the interleaver matrix. Before transmission, the bits are read out row by row with the row number reversed in bit order. An exemplary interleaver matrix that appears in the relevant section is as follows:

in transmission, line 0 is transmitted first, then line 32, then line 16, and so on. Line 1, the line with cells 1, 65, 129, 193, 267 and 321, is sent as line 32. Thus, the 0 bit is separated from the 1 bit by 191 other bits. Bits 0 to 6 will be sent in the following positions: 0 is bit 0, 192 is bit 1, 96 is bit 2,288 is bit 3, and 48 is bit 4,240 is bit 5,144 is bit 6. One skilled in the art will readily recognize that after interleaving, any two adjacent bits are separated by at least 96 other bits, and any two bits separated by one bit are themselves separated by at least 48 other bits. Thus, the bit-reversal interleaver is widely applied to, for example, a wireless communication system in which communication occurs over a fading channel.

However, the conventional bit-order reversal interleaving technique is less effective in achieving diversity gain in a system when antenna diversity or multiple carriers (frequency bands) are used. For example, when antenna diversity is used, the transmitted bits are split into two bit streams, which are transmitted from two antennas, respectively. The natural choice of separation is to pass even bits to the first antenna (antenna 1) and odd bits to the second antenna (antenna 2). However, as can be seen from the above example, the first seven bits are all even and will therefore be transmitted by antenna 1, a pattern that degrades receiver performance. That is, in the decoding process at the receiver, the bits will be more likely to affect multiple error events than if they were transmitted by different antennas. Therefore, the advantages of antenna diversity are not fully exploited.

Similar analysis can be performed for a radio communication system using a plurality of carriers. In such a system, the bits would be passed to two or more modulators of different frequencies, rather than to two different antennas. Accordingly, there is a need for an apparatus that enhances the ability of a channel interleaver to provide diversity gain in a communication system that uses transmitter diversity and/or multiple carriers.

Disclosure of Invention

The present invention is directed to an apparatus that enhances the ability of a channel interleaver to provide diversity in a communication system that uses transmitter diversity and/or multiple carriers. Accordingly, in one aspect of the present invention, a demultiplexer for channel interleaving advantageously comprises: a distribution module configured to continuously distribute a plurality of data units to a plurality of locations, wherein each data unit is distributed to a location different from the location to which a preceding data unit is distributed; a conversion module coupled to the distribution module and configured to control the distribution module to skip allocation to a location once after a predetermined number of data units are distributed.

In another aspect of the invention, a demultiplexer is advantageously configured to distribute a plurality of data units to a plurality of locations in succession, wherein each data unit is distributed to a location different from the location to which a previous data unit was distributed, the demultiplexer being further configured to skip allocation to a location once after a predetermined number of data units have been distributed.

In another aspect of the present invention, a transmitting part of a digital radio communication system advantageously comprises a channel encoder, a channel interleaver coupled to said channel encoder, and a demultiplexer coupled to said channel interleaver and configured to successively distribute data units to a plurality of locations, wherein each data unit is distributed to a location different from the location to which a preceding data unit was distributed, the demultiplexer further configured to skip allocation to a location once after distributing a predetermined number of data units.

In another aspect of the present invention, a method of demultiplexing data units advantageously comprises the steps of: continuously transmitting the data units to a plurality of positions, so that each data unit is transmitted to a position different from the position transmitted by the previous data unit; one position is bypassed once each time a predetermined number of data units are transferred.

In another aspect of the invention, a demultiplexer advantageously comprises means for successively passing data units to a plurality of successive locations, such that each of said data units is passed to a location different from the location passed by the preceding data unit; means for bypassing a location once each time a predetermined number of data elements are transferred.

In another aspect of the present invention, a demultiplexer for channel interleaving advantageously comprises a distribution module configured to successively distribute a plurality of data units to a plurality of locations, each of the data units being distributed to a location different from a location to which a previous data unit was distributed; a conversion module coupled to the distribution module and configured to control the distribution module to repeat a location once after a predetermined number of data units are distributed.

In another aspect of the invention, a demultiplexer is advantageously configured to distribute a plurality of data units successively to a plurality of locations, each data unit being distributed to a different location than a previous data unit, the demultiplexer being further configured to repeat a location once after a predetermined number of data units have been distributed.

In another aspect of the invention, the transmitting part of the digital radio communication system advantageously comprises a channel encoder, a channel interleaver coupled to said channel encoder, and a demultiplexer coupled to said channel interleaver and configured to successively distribute data units to a plurality of locations, each data unit being distributed to a location different from the location to which the previous data unit was distributed, the demultiplexer being further configured to repeat a location once after distributing a predetermined number of data units.

In another aspect of the present invention, a method of demultiplexing data units advantageously comprises the steps of: continuously transmitting the data units to a plurality of continuous positions, so that each data unit is transmitted to a position different from the position transmitted by the previous data unit; and repeating one position each time after a predetermined number of data units have been transmitted.

In another aspect of the invention, a demultiplexer advantageously comprises means for successively passing data units to successive locations, each of said data units being passed to a location different from the location passed by the preceding data unit; means for repeating a position once each time a predetermined number of data units are transmitted.

A demultiplexer according to a first aspect of the present invention is a demultiplexer for channel interleaving a data unit, comprising:

a distribution module for receiving a plurality of data units in sequence; the allocation module successively allocates each of the plurality of received data units to one of a plurality of output positions such that the output position to which each received data unit is allocated is different from the output position used by the immediately preceding received data unit in the sequence; and

a conversion module, connected to the allocation module, for reassembling the allocation of the plurality of received data units after the allocation of the predetermined number of received data units.

A method of demultiplexing a data unit according to a second aspect of the present invention comprises the steps of:

receiving a plurality of data units in sequence;

successively assigning each of the plurality of received data units to one of a plurality of output positions such that the output position to which each received data unit is assigned is different from the output position to which the previously received data unit is assigned; and

the allocation of the plurality of received data units is reassembled each time a predetermined number of received data units are allocated.

An apparatus for channel interleaving a data unit according to a third aspect of the present invention includes:

means for assigning each of the plurality of received data units successively to one of a plurality of output positions that is different from the output position to which the previously received data unit was assigned; and

means for reassembling the allocation of the received data units each time a predetermined number of received data units are allocated.

Drawings

Fig. 1 is a block diagram of a transmit portion of a communication system.

Fig. 2 is a block diagram of a conventional demultiplexer used in conjunction with a channel interleaver in a single antenna, single carrier communication system.

Fig. 3 is a block diagram of a conventional demultiplexer used in a communication system using transmitter antenna diversity.

Fig. 4 is a block diagram of a conventional demultiplexer used in a communication system using a plurality of carriers.

Fig. 5 is a block diagram of a demultiplexer for use in a communication system using transmitter antenna diversity.

Fig. 6 is a block diagram of a demultiplexer used in a communication system using a plurality of carriers.

Fig. 7A is an overview of a demultiplexer used in a communication system using transmitter antenna diversity.

Fig. 7B is a timing diagram for the demultiplexer of fig. 7A.

Fig. 8A is an overview of a demultiplexer used in a communication system using a plurality of carriers. Fig. 8B is a timing diagram associated with the demultiplexer of fig. 8A.

Fig. 9 is a block diagram of a pseudo-random noise spreader for generating complex I and Q signals.

Detailed Description

According to one embodiment, as shown in fig. 1, a transmit section 10 of a communication system (not shown) includes a channel encoder 12, a channel interleaver 14, a spreading module 16, a demultiplexer (demux)18, and first and second transmit antennas 28, 30. The data bits are input in successive frames to a channel encoder 12, which encoder 12 encodes the data bits in accordance with conventional coding techniques, such as convolutional coding or turbo coding.

The channel encoder 12 is coupled to a channel interleaver 14 and provides data symbols to the channel interleaver 14. The channel interleaver 14 may be a block interleaver 14 configured as a matrix of rows and columns. The data symbols are written into the interleaver 14 row by row and read out of the interleaver 14 column by column. The interleaver 14 is advantageously configured to use a bit-reversal pattern whereby the individual row addresses are rearranged, or shuffled, in the interleaver 14. The bit-reversal technique allows interleaver 14 to interleave adjacent input symbols to produce the most temporally spaced output symbols.

The channel interleaver 14 is coupled to a spreading module 16 and provides the interleaved data symbols to the spreading module 16. The spreading module 16 is also configured to receive a spreading code. The spreading module 16 may also advantageously be an orthogonal spreading module 16, which receives orthogonal spreading codes. In this case, the communication system is advantageously a digital radio communication system, which is configured in accordance with a code division multiple access air interface, as described below. The spreading module 16 spreads the data symbols with the received spreading codes to generate groups of data chips, each group of data chips representing a data symbol. It is advantageous to perform M-ary orthogonal spreading, where M is 2^mFor example, M equals 16, 32, 64, or 128.

The spreading module 16 is coupled to a demultiplexer 18 and provides the data slices to the demultiplexer 18. The demultiplexer 18 demultiplexes the data slice, divides or parses the stream of data slices into first and second streams of data slices, which are sent to first and second complex I and Q spreaders 20, 22, respectively. Each set of data chips, advantageously representing one data symbol, is alternately sent to complex I and Q spreaders 20, 22, as will be explained below. In addition, as will be described in greater detail below, switching logic (not shown) in demultiplexer 18 is used to skip one of the complex I and Q spreaders 20, 22 for each predetermined number of data symbols per given frame that have been transmitted. Alternatively, and as will be described in greater detail below, conversion logic may be used to cause one of the complex I and Q spreaders 20, 22 to operate repeatedly once a predetermined number of data symbols of a given frame have been transmitted. In the embodiment shown in fig. 1, switching logic controls demultiplexer 18 to skip one of complex I and Q spreaders 20, 22 after half of the symbols of a frame are transmitted by demultiplexer 18. As a result, the symbol segments are effectively reversed, i.e., at the midpoint of the frame, one complex I and Q spreader 20 receives two consecutive sets of data chips (each set representing a data symbol), while the other complex I and Q spreader 22 skips over or repeats receiving a set of data chips representing a data symbol. After the mid-point of the frame, transmission continues in the alternating fashion described above.

In another embodiment, demultiplexer 18 is configured to send groups of data slices along three data paths, and the switching logic is configured to skip (or repeat) one data path each time 1/3 symbols for one frame have been sent. In another embodiment, demultiplexer 18 is configured to send groups of data slices along three data paths and the switching logic is configured to skip (or repeat) one data path each time 1/4 symbols for one frame have been sent. Thus, the last fourth of the symbols is transmitted as the first fourth of the symbols. Those skilled in the art will readily appreciate that the number of data paths from demultiplexer 18 and the number of "skips" or "repeats" performed are not subject to any limitations other than physical design and temporal design limitations. In addition, those skilled in the art will also appreciate that controlled skipping or repeating of a particular data path (i.e., a particular antenna or carrier band) transmission route occurs after a predetermined number of data units have been processed by the demultiplexer 18, where a "data unit" represents a data symbol (i.e., in effect one bit, but represents multiple data bits), or a group of data chips (i.e., in effect multiple bits, but represents one data symbol).

Those skilled in the art will appreciate that the demultiplexer 18 can also be coupled directly to the channel interleaver 14. The first and second spreading modules may then be coupled to the output data path of the demultiplexer 18.

In the embodiment shown in fig. 1, the first complex I and Q spreader 20 is configured to receive a pseudorandom noise spreading code. The first complex I and Q spreader 20 generates complex I and Q signals from the received data chips by the pseudo-random spreading code. Likewise, the second complex I and Q spreader 22 is configured to receive a pseudorandom noise spreading code. With the pseudo-random spreading code, the second complex I and Q spreader 22 generates complex I and Q signals from the received data chips.

The first and second complex I and Q spreaders 20, 22 are coupled to first and second upconverters 24, 26, respectively. First and second complex I and Q spreaders 20, 22 provide complex I and Q signals to respective first and second upconverters 24, 26. The first and second upconverters 24, 26 are coupled to first and second antennas 28, 30, respectively. The upconverters 24, 26 upconvert the signals to an appropriate carrier frequency, such as 800MHz (cellular system) or 1900MHz (PCS system), and convert the signals to analog form for over-the-air RF transmission.

It is advantageous to use two antennas 28, 30 to provide antenna diversity. Alternatively, the antennas 28, 30 may be coupled to upconverters configured to upconvert the respective signals to different carrier frequency bands. In one embodiment, three carrier frequencies are provided using three antennas. In another embodiment, the use of multiple antennas provides the benefits of diversity and multi-carrier.

The telecommunications industry association has promulgated "TIA/EIA interim standard 95 (IS-95)" and its derivatives, such as IS-95B (hereinafter collectively referred to as IS-95), as an air interface standard, which defines Code Division Multiple Access (CDMA) digital radio communication systems. Systems and methods for processing Radio Frequency (RF) signals substantially in accordance with the use of the IS-95 standard are described in U.S. patent No. 5,103,459, which IS assigned to the assignee of the present invention and IS hereby fully incorporated by reference. In the embodiment of fig. 1, the communication system IS advantageously a digital radio communication system configured in accordance with the IS-95 standard, such as a cellular or PCS telephone system.

In fig. 2, a conventional demultiplexer 100 is configured for use in a communication system (not shown) using a single transmit antenna and a single carrier. The splitter 18 receives an X input and produces two Y outputs, specifically Y_IOutput sum Y_QAnd (6) outputting.

In fig. 3, a conventional demultiplexer 200 is configured for use in a two-antenna spread spectrum digital radio communication system including a first demultiplexer 202, second and third demultiplexers 204, 206, and four symbol repeaters 208, 210, 212, 214. The first demultiplexer 202 receives data symbols at the X input. The first demultiplexer 202 demultiplexes the data symbols, provides an even number of symbols through the YI output to the second demultiplexer 204, and provides an odd number of symbols through 206 through the YQ output. Second and third demultiplexers 204,206 receive and demultiplex the symbols. The second demultiplexer 204 provides the first symbol stream to a symbol repeater 208 and the second symbol stream to a symbol repeater 210. Third demultiplexer 206 provides the first symbol stream to symbol repeater 212 and the second symbol stream to symbol repeater 214. The first and third symbol repeaters 208, 212 each produce two identical output symbols for each received input symbol. The second and fourth symbol repeaters 210, 214 each generate an output symbol and its complement for each received symbol. Symbol repeater 208 generates Y_I1Output, symbol repeater 210 generates Y_I2Output, symbol repeater 212 generates Y_Q1Output, symbol repeater 214 generates Y_Q2And (6) outputting. Thus, for four symbols received successively at the X input, the first symbolAs an I symbol transmitted by the first antenna, a second symbol as an I symbol transmitted by the second antenna, a third symbol as a Q symbol transmitted by the first antenna, and a fourth symbol as a Q symbol transmitted by the second antenna. As described above, the demultiplexer 200 cannot maximize orthogonal transmit diversity in a two-antenna system using in combination with a bit-order reversed channel interleaver.

In fig. 4, a conventional demultiplexer 300 (configured for use in a three-carrier spread spectrum digital radio communication system) includes a first demultiplexer 302 and a second demultiplexer 304. The first demultiplexer 302 receives digital symbols at the X input. The first demultiplexer 302 demultiplexes the received symbols, provides even-numbered symbols to the second demultiplexer 304 through YI output, and provides odd-numbered symbols to the second demultiplexer 304 through YQ output. A second demultiplexer 302 receives and demultiplexes the two input symbol streams, thereby at an output Y_I1，Y_Q1，Y_I2，Y_Q2，Y_I3And Y_Q3Six output symbol streams are generated. Thus, for six symbols received successively at the X input, a first symbol is routed as an I symbol transmitted at a first carrier frequency, a second symbol is routed as a Q symbol transmitted at the first carrier frequency, a third symbol is routed as an I symbol transmitted at a second carrier frequency, a fourth symbol is routed as a Q symbol transmitted at the second carrier frequency, a fifth symbol is routed as an I symbol transmitted at a third carrier frequency, and a sixth symbol is routed as a Q symbol transmitted at a third carrier frequency. As described above, the demultiplexer 300 cannot maximize the diversity gain in the three-carrier system using in combination with the bit-order reversal channel interleaver.

According to one embodiment, a demultiplexer 400 (configured for use in a two antenna spread spectrum digital radio communication system) includes a demultiplexer 402 modified by switching logic (not shown) and four symbol repeaters 404, 406, 408, 410, as shown in fig. 5. Demultiplexer 402 is coupled to four symbol repeaters 404, 406, 408, 410. Demultiplexer 402 receives the data symbols at the X input and demultiplexes the received symbols to produce four output symbol streams. A first output symbol stream (comprising the first of every four symbols received at the X input) is provided to a first symbol repeater 404. A second output symbol stream (comprising the second of every four symbols received at the X input) is provided to a second symbol repeater 406. A third output symbol stream (comprising the third of every four symbols received at the X input) is provided to a third symbol repeater 408. A fourth output symbol stream (comprising the fourth of every four symbols received at the X input) is provided to a fourth symbol repeater 410. The first and second symbol repeaters 404,406 each produce two identical output symbols for each received symbol. The third and fourth symbol repeaters 408, 410 each generate an output symbol and its complement for each received symbol.

The symbols received at the X input are received in frames, where each frame has a predetermined number of symbols. For each frame, when the first half of the symbols are processed by the demultiplexer 400, the output of the first symbol repeater 404 is routed as an I symbol transmitted by the first antenna (i.e., the output is represented by Y I1), the output of the second symbol repeater 406 is routed as a Q symbol transmitted by the first antenna (i.e., the output is represented by Y Q1), the output of the third symbol repeater 408 is routed as an I symbol transmitted by the second antenna (i.e., the output is represented by Y I2), and the output of the fourth symbol repeater 410 is routed as a Q symbol transmitted by the second antenna (i.e., the output is represented by Y Q2). The output symbols from demultiplexer 400 are routed through conversion logic as the first symbol in the second half of the frame is processed, as will be described below. Accordingly, for the duration of the frame, the output of the first symbol repeater 404 is instead routed as an I symbol transmitted by the second antenna (i.e., the output is represented as Y I2), the output of the second symbol repeater 406 is instead routed as a Q symbol transmitted by the second antenna (i.e., the output is represented as Y Q2), the output of the third symbol repeater 408 is instead routed as an I symbol transmitted by the first antenna (i.e., the output is represented as Y I1), and the output of the fourth symbol repeater 410 is routed as a Q symbol transmitted by the first antenna (i.e., the output is represented as Y Q1). Used in conjunction with the bit-order reversed channel interleaver, the demultiplexer 400 maximizes orthogonal transmit diversity in a two antenna system.

According to one embodiment, as shown in fig. 6, a demultiplexer 500 (configured for use in a three-carrier spread spectrum digital radio communication system) includes a demultiplexer 502 modified by switching logic (not shown). Demultiplexer 502 receives data symbols at the X input. Demultiplexer 502 demultiplexes the received symbols six ways to produce six output symbol streams. The first output symbol stream contains the first of every six symbols received at the X input. The second output symbol stream contains the second of every six symbols received at the X input. The third output symbol stream contains the third of every six symbols received at the X input. The fourth output symbol stream contains the fourth of every six symbols received at the X input. The fifth output symbol stream contains the fifth of every six symbols received at the X input. The sixth output symbol stream contains the sixth of every six symbols received at the X input.

The symbols received at the X input are received in frames, each frame having a predetermined number of symbols. For each frame, the first output of demultiplexer 502 is instead routed as an I symbol transmitted at the first carrier frequency (i.e., the output is represented by Y I1) while the first quarter of the symbols are processed by demultiplexer 500, the second output of demultiplexer 502 is routed as a Q symbol transmitted at the first carrier frequency (i.e., the output is represented by Y Q1), the third output of demultiplexer 502 is instead routed as an I symbol transmitted at the second carrier frequency (i.e., the output is represented by Y I2), the fourth input of demultiplexer 502 is routed as a Q symbol transmitted at the second carrier frequency (i.e., the output is represented by Y Q2), the fifth output of demultiplexer 502 is instead routed as an I symbol transmitted at the third carrier frequency (i.e., the output is represented by Y I3), the sixth output of demultiplexer 502 is instead routed as a Q symbol transmitted at the third carrier frequency (i.e., the output is represented as Y Q3).

The routing of the output symbols of demultiplexer 500 is converted by the conversion logic when processing the first symbol in the second quarter of the frame, as will be described below. Accordingly, for the second quarter of the duration of the frame, the first output of demultiplexer 502 is instead routed as an I symbol transmitted at the third carrier frequency number 3 (i.e., the output is represented as Y I3), the second output of demultiplexer 502 is instead routed as a Q symbol transmitted at the third carrier frequency (i.e., the output is represented as Y Q3), the third output of demultiplexer 502 is instead routed as an I symbol transmitted at the first carrier frequency (i.e., the output is represented as Y I1), the fourth output of demultiplexer 502 is routed as a Q symbol transmitted at the first carrier frequency (i.e., the output is represented as Y Q1), the fifth output of demultiplexer 502 is instead routed as an I symbol transmitted at the second carrier frequency (i.e., the output is represented as Y I2), the sixth output of demultiplexer 502 is instead routed as a Q symbol transmitted at the second carrier frequency (i.e., the output is represented as Y Q2).

The output symbols of demultiplexer 500 are again routed by the switching logic when the first symbol in the third quarter of the frame is processed. Accordingly, for the duration of the third quarter of the frame, the first output of demultiplexer 502 is instead routed as an I symbol transmitted at the second carrier frequency (i.e., the output is represented as Y I2), the second output of demultiplexer 502 is instead routed as a Q symbol transmitted at the second carrier frequency (i.e., the output is represented as Y Q2), the third output of demultiplexer 502 is instead routed as an I symbol transmitted at the third carrier frequency (i.e., the output is represented as Y I3), the fourth output of demultiplexer 502 is instead routed as a Q symbol transmitted at the third carrier frequency (i.e., the output is represented as Y Q3), the fifth output of demultiplexer 502 is instead routed as an I symbol transmitted at the first carrier frequency (i.e., the output is represented as Y Q1), the sixth output of demultiplexer 502 is instead routed as a Q symbol transmitted at the first carrier frequency (i.e., the output is represented as Y Q1).

The output symbols of demultiplexer 500 are rerouted again by the switching logic when the first symbol in the last quarter of the frame is processed. At this point, the transition logic returns the transmit mode to the state it was in the initial quarter of the frame. Accordingly, for the duration of a frame, the first output of demultiplexer 502 is instead routed as an I symbol transmitted at carrier frequency number 1 (i.e., the output is represented as Y I1), the second output of demultiplexer 502 is instead routed as a Q symbol transmitted at carrier frequency number 1 (i.e., the output is represented as Y Q1), the third output of demultiplexer 502 is instead routed as an I symbol transmitted at carrier frequency number 2 (i.e., the output is represented as Y I2), the fourth output of demultiplexer 502 is instead routed as a Q symbol transmitted at carrier frequency number 2 (i.e., the output is represented as Y Q2), the fifth output of demultiplexer 502 is instead routed as an I symbol transmitted at carrier frequency number 3 (i.e., the output is represented as Y I3), the sixth output of demultiplexer 502 is instead routed as a Q symbol transmitted at carrier frequency number 3 (i.e., the output is represented as Y Q3).

As described above, the demultiplexer 500 maximizes the diversity gain in a three-carrier system, used in conjunction with a bit-order reversed channel interleaver. Those skilled in the art will appreciate that demultiplexer 500 for a three carrier system includes switching logic that routes the switching symbols four times per frame for ease of implementation only. In another embodiment, a demultiplexer that modifies the symbol routing to convert three times per frame may be used in a three carrier system.

According to one embodiment, as shown in fig. 7A, the demultiplexer 600 includes a symbol (i.e., bit or data unit) allocation module 603 and a conversion module 602. The conversion module 602 is shown by a dashed line and the assignment module 603 contains all elements not in the conversion module 602. The various signals belonging to the demultiplexer 600 are illustrated in the timing diagram of fig. 7B. Demultiplexer 600 is configured to provide maximum diversity gain in a communication system that provides transmit diversity using two antennas. Demultiplexer 600 is advantageously implemented in hardware with discrete gate logic, as shown. In another embodiment, the demultiplexer may be implemented as a software module (or firmware instructions) residing in a conventional storage medium and being executed by a conventional microprocessor.

In demultiplexer 600, a switch module 602 includes an AND gate configured to receive the CLOCK INHIBIT PULSE signal and the PULSE waveform. The output of the conversion module 602 is provided to a flip-flop (FF) 606. The output of FF606 is a pulse inhibit SQUARE waveform, as shown in FIG. 7B. The pulse disable SQUARE waveform is provided as a control input to AND gate 608 and inverter 610. The output of inverter 610 is provided to and gate 612. And gates 608, 612 also receive the data symbol streams input to demultiplexer 600.

The output of and gate 608 is provided to and gate 614 and to and gate 616. The 2 x SQUARE waveform is provided as an input to AND gate 614 and to the control input of inverter 618. The output of inverter 618 is provided to and gate 616. The output of and gate 612 is provided to and gate 620 and gate 622. The 2 SQUARE waveform is provided as a control input to AND gate 620 and inverter 624. The output of inverter 624 is provided to and gate 622.

The output of and gate 614 is provided to buffer 626. The output of and gate 616 is provided to buffer 628. The output of and gate 620 is provided to buffer 630. The output of and gate 622 is provided to buffer 632.

The 2 x PULSE waveform is provided as data input to and gates 634, 636. The output of FF606 (pulse disable SQUARE waveform) is coupled as a control input to and gate 634 and inverter 638. The output of inverter 638 is provided to and gate 636. The outputs of and gate 634 are provided to and gates 640, 642. The 2 x SQUARE waveform is provided as a control input to AND gate 640 and to inverter 644. The output of inverter 644 is provided to and gate 642. The output of and gate 636 is provided to and gates 646, 648. The 2 x SQUARE waveform is provided as a control input to AND gate 646 and to inverter 650. The output of inverter 650 is provided to and gate 648.

The output of and gate 640 (shown as an I1_ LOAD waveform) is provided to buffer 626. The output of and gate 642 (shown in fig. 7B as a Q1__ load waveform) is provided to buffer 626. The I2_ LOAD waveform shown in FIG. 7B, i.e., the output of AND gate 646, is provided to buffer 630. The waveform of Q2 _ LOAD shown in FIG. 7B, i.e., the output of AND gate 648, is provided to buffer 632.

The I1 signal, i.e., the output of buffer 626, as shown in fig. 7B is provided to buffer 652. The Q1 signal, shown in fig. 7B, i.e., the output of buffer 628, is provided to buffer 654. The I2 signal, shown in fig. 7B, i.e., the output of buffer 630, is provided to buffer 656. The Q2 signal shown in fig. 7B, i.e., the output of buffer 632, is provided to buffer 658. Buffers 652, 654, 656, 658 each receive a LOAD _ PULSE waveform as input. As illustrated in fig. 7B, the output symbol streams from buffers 652, 654, 656, 658, I1_ OUT, Q1_ OUT, I2_ OUT and Q2 _ OUT, respectively, are time synchronized due to the respective buffers 652, 654, 656, 658.

According to one embodiment, as shown in fig. 8A, the demultiplexer 700 includes a symbol (i.e., bit or data unit) allocation module 703 and a conversion module 702. The conversion module 702 is shown by a dashed line and the distribution module 703 encloses all elements not in the conversion module 702. The various signals belonging to the demultiplexer 700 are illustrated in the timing diagram shown in fig. 8B. Demultiplexer 700 is configured to provide maximum diversity gain in a communication system having three carrier bands. As shown, it is advantageous to implement demultiplexer 700 in hardware with discrete gate logic. In another embodiment, the demultiplexer may be implemented as a software module (or firmware instructions) residing on a conventional storage medium and executable by a conventional microprocessor.

In demultiplexer 700, a conversion module 702 is configured to receive the CLOCK _ INHIBIT _ PULSE signal and the PULSE waveform. A CLOCK _ INHIBIT _ PULSE signal is provided after each quarter frame is processed to achieve the desired route conversion. However, after the fourth quarter frame is processed (i.e., between subsequent frames), the CLOCK _ PNHIBIT _ PULSE signal is not provided. The output of the conversion module 702 is provided to a modulo-3 counter 706. The dual output of modulo-3 counter 706 is provided to modulo-3 counter 708. Decoder logic 708 is advantageously implemented by a combination of logic and FF. The first output from the decoder logic 708, the C0 waveform, is provided to an and gate 710. The second output from the decoder logic 708, the C1 waveform, is provided to an and gate 712. The third output from decoder logic 708, the C2 waveform, is provided to and gate 714. And gates 710, 712, 714 also receive data symbol streams, which are input to demultiplexer 700.

The output of and gate 710 is provided to and gate 716 and gate 718. The 2 x SQUARE waveform is provided as a control input to AND gate 716 and to inverter 720. The output of inverter 720 is provided to and gate 718. The output of and gate 712 is provided to and gate 722 and to and gate 724. The 2 SQUARE waveform is provided as a control input to AND gate 722 and inverter 726. The output of inverter 726 is provided to and gate 724. The output of and gate 714 is provided to and gate 728 and gate 730. The 2 x SQUARE waveform is provided as a control input to AND gate 728 and to inverter 732. The output of inverter 732 is provided to and gate 730.

The output of and gate 716 is provided to buffer 734. The output of and gate 718 is provided to buffer 736. The output of and gate 722 is provided to buffer 738. The output of and gate 724 is provided to buffer 740. The output of and gate 728 is provided to buffer 742. The output of and gate 730 is provided to buffer 744.

The 2 x PULSE waveform is provided as data input to and gates 746, 748, 750. And gate 746 also receives as input the C0 waveform. And gate 748 also receives as input the C1 waveform. And gate 750 also receives as input the C2 waveform. The output of and gate 746 is provided to and gates 752, 754. The 2 x SQUARE waveform is provided as a control input to AND gate 754 and to inverter 756. The output of inverter 756 is provided to and gate 752. The output of and gate 748 is provided to and gates 758, 760. The 2 x SQUARE waveform is provided as a control input to AND gate 760 and to inverter 762. The output of inverter 762 is provided to and gate 758. The output of and gate 750 is provided to and gates 764, 766. The 2 × SQUARE waveform is provided as a control input to AND gate 766 and inverter 768. The output of inverter 768 is provided to and gate 764.

The output of AND gate 752, i.e., the I1_ LOAD waveform shown in FIG. 8B, is provided to buffer 734. The output of AND gate 754, the Q1_ LOAD waveform as shown in FIG. 8B, is provided to buffer 736. The output of AND gate 758, i.e., the I2_ LOAD waveform as shown in FIG. 8B, is provided to buffer 738. The output of and gate 760, the Q2 _ LOAD waveform as shown in fig. 8B, is provided to buffer 740. The output of AND gate 764, i.e., the I3 _ LOAD waveform as shown in FIG. 8B, is provided to buffer 742. The output of and gate 766, the Q3 _ LOAD waveform shown in fig. 8B, is provided to buffer 744.

The output of buffer 734, i.e., the I1 signal as shown in FIG. 8B, is provided to buffer 770. The output of buffer 736, i.e., the Q1 signal as shown in fig. 8B, is provided to buffer 772. The output of buffer 738, the I2 signal shown in FIG. 8B, is provided to buffer 774. The output of long term 740, the Q2 signal shown in fig. 8B, is provided to a buffer 776. The output of buffer 742, i.e., the I3 signal shown in fig. 8B, is provided to buffer 778. The output of buffer 744, i.e., the Q3 signal as shown in fig. 8B, is provided to buffer 780. Buffers 770, 772, 774, 776, 778, 780 each receive a LOAD _ PULSE waveform as an input. As shown in FIG. 8B, the output symbol streams from buffers 770, 772, 774, 776, 778, 780, which are I1_ OUT, Q1_ OUT, I2_ OUT, Q2 _ OUT, I3 _ OUT and Q3 _ OUT, respectively, are time synchronized due to the respective buffers 770, 772, 774, 776, 778, 780.

In fig. 9, a symbol I and Q spreader 800 that can be used in the transmit section 10 of fig. 1 includes a complex multiplier 802 (shown in dashed lines as needed for illustration), first and second baseband filters 804 and 806, first and second multipliers 808, 810, and an adder 812, according to one embodiment. Complex multiplier 802 includes four multipliers 814, 816, 818, 820 and two adders 822, 824. Complex multiplier 802' multipliers 808, 810 and adder 812 are advantageously conventional in the art.

It must be noted that the notation for input and output in the following description includes the subscript 1 indicating that the composite I and Q spreader 800 is intended for use in connection with a first transmitter antenna. In communication systems using more than two antennas, such as multiple carrier systems, the composite I and Q spreader 800 can be equivalently used in connection with a second transmitter antenna or any transmitter antenna.

It should be noted that composite Q and I spreader 800 includes up-conversion circuitry, as described below. Thus, if the composite I and Q spreader 800 were to replace the composite I and Q spreader 20 in the transmit section 10 of fig. 1, the up-converter 24 in the transmit section 10 of fig. 1 would be unnecessary. Is included in the output of the complex I and Q signal S from the complex I and Q spreader 800₁The data slice in the I component of (t) is received by composite I and Q spreader 800 at the input Y I1. The input terminal Y I1 is coupled to multipliers 814 and 816. The data slice to be included in the Q component of output signal S1(t) is received by composite I and Q spreader 800 at input Y Q1. The input terminal Y Q1 is coupled to multipliers 818 and 820. The pseudo-random noise (PN) code of the I component is coupled through the input terminal P N1 to each of the four multipliers 814, 816, 818, 820. The PN code for the Q component is coupled through the PNQ input to each of four multipliers 814, 816, 818, 820. The output generated from multiplier 814 is provided to adder 822. The output generated from multiplier 816 is provided to adder 824. The output generated from multiplier 818 is provided to adder 822. The output generated from multiplier 820 is provided to adder 824.

Summer 824 is configured to sum the two received inputs and provide the Q-chip output stream to second baseband filter 806. Adder 822 is configured to subtract the input received by multiplier 814 from the input received by multiplier 818 and provide the I-slice output stream to first baseband filter 804. Adders 802 and 804 may be programmed to be configured to add or subtract as desired.

A first baseband filter 804, advantageously a conventional digital filter 804, filters the received I-chip stream and provides the I-chip stream at baseband frequency to a multiplier 808. A second baseband filter 806 (also advantageously a conventional digital filter 806) filters the received Q data slice stream to provide the Q data slice stream at baseband frequency to a multiplier 810.

The multiplier 808 is configured to receive cos (2 π f) at a second input_ct) signal, where fc is the carrier frequency, e.g. 800MHz in a cellular system and 1900MHz in a PCS system, and t denotes time. Multiplier 808 multiplies the two received signals, thereby on-chip converting the I data to a carrier frequency, and provides the resulting output signal to adder 812. The multiplier 810 is configured to receive sin (2 π f) at a second input_ct) signal. Multiplier 810 multiplies the two received signals, thereby on-chip converting the Q data to a carrier frequency, and provides the resulting output signal to adder 812. Summer 812 sums the two received signals to produce a composite I and Q output signal S1(t), which is substantially converted to analog RF form and transmitted.

The above embodiments illustrate a scheme for achieving improved antenna diversity in conjunction with a bit-order reversed channel interleaver. Thus, in the exemplary embodiment, when a 384-bit interleaver (arranged as a matrix having 6 rows and 64 columns) is coupled (directly or indirectly) to a demultiplexer that is configured to optimize the above-described antenna diversity, the antenna assignments are unchanged during the first half of the transmission of each frame. However, when the second half data bits of the frame, i.e., the 192 th bit to the 383 th bit (assuming one 0 th bit), are transmitted, the even-numbered bits are passed to the antenna 2 and the odd-numbered bits are passed to the antenna 1. That is, the data path is switched so that antenna 1 is "skipped" before the 192 th bit is transmitted, and antenna 2 is selected instead when the 192 th bit is transmitted. Alternatively, antenna 2 is used "repeatedly" so that the antenna is selected instead when the 192 th bit is transmitted. Thus, two adjacent bits in the bit-order reversed channel interleaver will be transmitted from different antennas.

In another exemplary embodiment, the channel interleaver is coupled (directly or indirectly) to a demultiplexer, which is minimally modified in the above-described demultiplexer (i.e., the two antenna diversity embodiment). The demultiplexer is configured to optimize 3x multicarrier transmission or to optimize three antenna diversity. Assuming that three frequency bands, or carriers (or three antennas), are denoted as 1, 2 and 3, each block or frame data is divided into three substantially identical blocks. For the first block of data, the bits are sent in the following order: 1, 2, 3, 1, 2, 3, etc. At the end of the block, one carrier (or one antenna) is "skipped" and the transmission starts with the next carrier (or antenna). For example, if at the end of a block of data, transmission occurs in band (or antenna) 1, 2, 3, 1, 2, 3, and ends in band 3, the first bit of the next block of data is transmitted on band (or antenna) 2, but not band (or antenna) 1. Then, the sending data blocks are in order: 3, 1, 2, 3, etc. in that order. Alternatively, one carrier (or one antenna) is retransmitted and started from the carrier (or antenna). For example, if at the end of a data block, transmission occurs in band (or antenna) 1, 2, 3, and at the end of band 3, the first bit of the next data block is again transmitted in band (or antenna) 3. Then according to the sequence: 1, 2, 3, etc. continue to transmit data blocks.

Those skilled in the art will appreciate that the described embodiments allow for the application of a single channel interleaver design that has optimized diversity gain for a variety of different transmission systems. The bit-order reversed channel interleaver can be used to achieve optimized diversity gain over any number of antennas or carriers by a simple modification of the demultiplexer switching scheme.

Those skilled in the art will also appreciate that the interleaver, according to one embodiment, may be generally described as follows: if the interleaver input symbols are written sequentially from 0 to block length N-1 to address N_INThen the symbols are read from the interleaver by the following addresses：

N_0UT＝(2^m)(N_INmodN)+Bit Rev_m([N_IN/N])，

Wherein [ N ]_INIs less than or equal to N_INMaximum integer of/N, Bit _ Rev_m(〔N_IN/N) represents m bits_INthe/N value bit order is reversed.

Thus, a demultiplexer has been described for channel interleaving in a communication system with multiple carriers and/or transmitter diversity. Those skilled in the art will appreciate that while the embodiments disclosed herein are described in the context of an IS-95 based digital radio cellular telephone system, the present invention IS equally well suited for use in any type of communication system, including, for example, satellite communication systems. Those skilled in the art will also appreciate that the embodiments described herein may be used for channel coding of data or voice communications. It will also be appreciated that the data, instructions, commands, information, signals, bits, symbols, and data chips that may be referenced throughout the above description may advantageously be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Those of skill would further appreciate that the various illustrative logical blocks and algorithm steps described in connection with the embodiments disclosed herein may be implemented or performed with a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), discrete gate or transistor logic, discrete hardware (such as registers, FIFO), a processor implementing a set of firmware instructions, or a conventional programmable software module and processor. The processor is preferably a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The software modules may reside in RAM memory, flash memory, registers, or any other form of writable storage medium known in the art.

Thus, the preferred embodiments of the present invention have been shown and described. It will be apparent to those of ordinary skill in the art that various modifications can be made to the embodiments disclosed herein without departing from the spirit or scope of the invention. Accordingly, the invention is limited only by the following claims.

Claims

1. An apparatus for channel interleaving a data unit, comprising:

means for controlling the allocation of received data units by skipping the use of n of the plurality of output positions for the allocation of one of the plurality of received data units each time a predetermined number of received data units are allocated, where n is a positive integer less than the number of output positions.

2. The apparatus of claim 1, wherein the received data units are divided into frames prior to allocation.

3. The apparatus of claim 2, wherein the predetermined number of received data units is equal to a fraction of the number of received data units in a frame.

4. The apparatus of claim 1, wherein the received data units further comprise data units that are bit-order reverse interleaved.

5. A method for channel interleaving a data unit, comprising the steps of:

assigning each of the plurality of received data units successively to an output position of the plurality of output positions that is different from the output position to which the previously received data unit was assigned; and

controlling the allocation of the received data units by skipping the use of n of the plurality of output positions for the allocation of one of the plurality of received data units each time a predetermined number of received data units are allocated, where n is a positive integer less than the number of output positions.

6. The method of claim 5, wherein the received data units are divided into frames prior to allocation.

7. The method of claim 6, wherein the predetermined number of received data units is equal to a fraction of the number of received data units in a frame.

8. The method of claim 5, wherein the received data units further comprise data units that are bit-order reverse interleaved.