HK1066321B - Printed circuit boards with plated resistors and process for the manufacturing the same - Google Patents

Description

Printed circuit board with plated resistor and method of manufacturing the same

Technical Field

The invention relates to a method for producing double-sided or multilayer printed circuit boards with printed plated resistors. The provided method can produce a printed circuit with an integral resistor that is printed and plated on the surface of the printed circuit board, or on the inner core of a multilayer printed circuit board, thus preserving a larger surface area of the circuit board for placement of active components. The method produces printed circuit boards with resistors in a more efficient and economical manner than previously.

Background

In the manufacture of printed circuits, it is common to provide a planar board having a circuit pattern on each side (e.g., a double-sided circuit board), and likewise, to manufacture a board comprised of an integral planar laminate of an insulating substrate and a conductive metal, wherein one or more parallel inner or planar layers of conductive metal separated by the insulating substrate are in a configuration along an interior plane with an exposed outer surface which is the outer surface of the laminate (e.g., a multilayer circuit board) containing the printed circuit pattern.

In double-sided and multilayer circuit boards, it is necessary to provide interconnections between the layers and/or sides of the board containing the conductive circuit pattern. The interconnection is made by metallization, conductive vias in the board that connect the sides and layers that need to be electrically interconnected. The main method used for providing conductive vias is electroless deposition of metal on the non-conductive surface of the via, which is obtained by drilling or punching in a plate. Typically, electroless deposition is followed by electroplating to deposit the metal in the holes to achieve the desired thickness of the conductive metal. More recently, certain methods allow electroplating to be performed directly in the via without the need for prior electroless deposition.

A common manufacturing sequence for manufacturing printed circuit boards begins with a copper clad laminate. The copper clad laminate used comprises a glass reinforced epoxy resin insulating substrate and copper foil bonded to both planar surfaces of the substrate, although other types of insulating substrates such as paper-based phenolic and polyimide resin substrates may also be used. First, a via hole is drilled or punched in the copper clad laminate to reveal the via surface of the insulating base material. The holes are then subjected to an electroless plating process which deposits conductive metal in the holes and on the copper surface. The plating resist is applied to the outer surface in the form of a negative image of the desired circuit pattern. Copper is then electroplated to a predetermined thickness on all surfaces not covered by the plating resist, and a thin layer of tin is then deposited as an etch-resistant layer. The plating resist is then stripped and the exposed copper surfaces (e.g., those not covered by the etch resist) are etched away. Finally, the etch resist is removed and the printed circuit board is finished in a known manufacturing process, for example by solder mask coating and then soldering with hot air. The foregoing process is generally referred to as a pattern plating method and is suitable for manufacturing a double-sided printed circuit board or a multilayer board. However, in the case of a multilayer board, the starting material is a copper clad laminate comprising a circuit pattern inner plane called an inner layer.

Simple printed circuit boards and the inner layers of multilayer circuit boards are manufactured by a technique called printing and etching. In this way, the photopolymer is laminated or dried onto the copper surface of the copper clad laminate. The photopolymer is then selectively imaged and developed using a negative to produce a positive image of the desired circuit pattern on the surface of the copper clad laminate. The exposed copper is then etched away and the photopolymer removed to reveal the desired circuit pattern.

A semi-additive process may be used in conjunction with the printing and etching process to produce double-sided or multilayer printed and etched plates with plated through holes. In this process a copper clad laminate or a multi-layer package with copper foil on the outer surface is processed through a printing and etching process as shown above. The holes are then drilled in the plate in the desired arrangement. A plating resist is then applied to cover substantially all of the outer surface of the board (removing the holes and circuit portions). Typically, a separate desensitization mask is applied, the vias are activated, and the desensitization mask is removed in a manner that does not affect activation. The exposed areas are then electrolessly plated.

In addition, many other methods are used to manufacture printed circuit boards. Certain processes are described in detail in U.S. Pat. Nos. 3,982,045, 4,847,114, and 5,246,817, the teachings of which are incorporated herein by reference. However, in the prior art methods, the circuit being fabricated requires that the resistors be provided external to the circuit board itself (e.g., mounted on the surface of the circuit board as an attachment), if desired.

A method is disclosed for printing and plating a reliable resistor as an integral part of a circuit pattern of a printed circuit board. This method provides an efficient and economical way to provide the necessary resistors. In addition, the method provides a printed circuit board that is further miniaturized compared to that manufactured by prior art methods. In this regard, the general prior art is U.S. Pat. Nos. 3,808,576 and 2,662,957, the teachings of both of which are incorporated herein by reference. The present invention produces a printed circuit with an integral resistor having a particularly constant resistance as required for most applications.

Summary of the invention

The present invention provides a method of printing and plating resistors as an integral part of a printed circuit board. The method is described in its basic form by the following sequence of process steps.

a) An etch-resistant layer 12 is applied in a desired pattern on the surface of the copper foil 11 of the metal clad laminate (or multi-layer package). The desired pattern preferably forms the desired conductive circuit in a positive manner and the area between the circuit and the resistor location in a negative manner;

b) etching away the exposed copper and preferably removing the etch-resistant layer to form unconnected copper conductors (13 and 14);

c) activating each surface to receive plating thereon;

d) applying a plating resist 15 covering substantially all of the surface except for the areas where the resistors are to be plated;

e) electroplating the exposed areas with resistive material 16; and

f) and removing the electroplating protective layer.

As a method equivalent to the aforementioned method, the aforementioned steps a) and b) may be replaced by an additional method having the following steps:

a.1.) activating a surface of the hollow dielectric substrate to receive plating thereon;

a.2.) applying a plating resist to the dielectric substrate to form the desired circuit in negative image and to form the area between the circuit and the location of the resistor in positive image;

a.3.) the circuitry required for electroplating;

a.4.) stripping of the plating resist; and

the previously described steps c) to f) are followed.

In a preferred embodiment, the substrate is subjected to a dielectric etchant after step b) but before step c) in order to homogenize the dielectric surface. The etching at this point homogenizes the dielectric surface, providing a plated resistor with a more constant and predictable resistance.

In another preferred embodiment, the plating-resistant layer material is contacted with an oxidizing agent either between steps e) and f) or after step f). Contacting the plating-resistant layer material with an oxidizing agent and then oxidizing the plating-resistant layer material in a controlled manner can provide plated resistors having a more constant and predictable resistance, and optionally, a higher resistance. The internal resistance is increased by controlled oxidation. Alternatively, or as an additional step, the resistor may be baked after step f) to stabilize the resistance of the resistor.

In a third preferred embodiment, after step f), the printed circuit board is subjected to a cleaning step in order to remove any residual activator species from step c), and generally in order to improve the surface insulation resistance of the board. The printed circuit board manufactured by including this step has high reliability.

It is suggested to use the final trimming as a method of adjusting the insulation resistance value of the plating resistor so that the resistance value is within a predetermined insulation resistance (ohm) range. A particularly suitable trimming method is to use a laser to melt away a partial area of the plated resistor.

Drawings

The figures show the steps of the basic method of the invention.

Fig. 1A represents one side of a copper clad laminate with an insulating dielectric substrate 10 and attached copper foil 11 (although both sides would most likely be treated in the same manner).

Fig. 1B shows imaged etch resist layer 12 on copper foil 11. The etch resist layer 12 has been formed and developed so as to cover only a desired portion of the copper foil 11.

Fig. 1C shows the exposed copper being etched away leaving copper conductors 13 and 14 on the substrate 10 covered by an unconnected etch-resistant layer.

Fig. 1D shows that the etch-resistant layer has been completely stripped, leaving only the desired copper lines 13 and 14 on the substrate 10.

Fig. 1E shows the application of an anti-plating layer 15 covering the entire area of the plate except for the portion of the resistor that is to be plated.

Fig. 1F shows a plated resistor 16 connecting the previously unconnected copper conductors 13 and 14.

Fig. 1G shows the circuit after the plating resist layer 15 is peeled off.

Detailed description of the invention

The processes described herein provide a method of forming a resistor between two conductive regions on and separated by an insulating substrate. The method can plate a resistive material onto the insulating substrate between the conductive regions to connect the resistive material to the conductive regions. The method is particularly useful for manufacturing printed circuit boards having plated resistors integral with the circuit. The most basic processing sequence is described below:

a) applying an etch-resistant layer to the surface of the metal clad laminate such that the etch-resistant layer forms the desired circuit pattern in a positive image and forms the areas between the circuits (including the locations of the resistors) in a negative image;

b) etching away the exposed copper surface and stripping the etch-resistant layer;

c) optionally, the exposed dielectric surface is treated using a method selected from the group consisting of: chemical etching, plasma etching, laser normalization, steam blasting, sanding, shot blasting, and sand blasting;

d) activating the exposed dielectric surface to receive plating thereon;

e) a plating resist is applied so that the plating resist covers all or substantially all of the surface except in the areas where the resistors are to be plated (i.e.: forming the resistor area in a negative manner);

f) electroplating the exposed area;

g) optionally, contacting the plated area with an oxidizing agent;

h) stripping the electroplating protective layer;

i) optionally, cleaning the surface of the printed circuit board;

j) optionally, baking the resistor;

k) optionally, trimming the partially plated resistor material such that a final insulation resistance value of the resistor falls within a predetermined range of insulation resistance values; and

l) optionally, covering the resistor with a protective coating.

Steps a) and b) together require the creation of a formed circuit pattern (or multilayer package-a multilayer of circuit patterns containing one or more circuitry innerlayers that are laminated into a single planar package) on the surface of a metal clad dielectric laminate. Each inner layer may or may not contain the plated resistors of the present invention. If so, the inner layer can be manufactured by the methods described herein. All metal-clad dielectric laminates and multi-layer packages are referred to as metal-clad laminates. The metal clad laminate may optionally have through holes therein arranged as desired. The vias may or may not be plated at this time. The key here is to form and create a circuit pattern on the surface of the metal clad laminate along the specific open circuit formed and created in the circuit pattern where the resistor is plated ("resistor area"). The length and width of a particular resistor region obviously directly affects the resistance obtained after plating.

The formation and creation of the circuit diagram and resistor areas can be achieved in many ways. The most common way is by a subtraction process as described in steps a) and b) above. In this subtractive process, a metal-clad (typically copper-clad) laminate is used. The metal clad laminate includes a planar dielectric substrate and metal foil bonded to both exterior surfaces. As noted, the dielectric matrix is typically a glass-reinforced epoxy, but may be a variety of other insulating materials as are well known in the art. In any case, a resist pattern is applied to the metal surface of the metal clad laminate so that the resist layer forms a circuit in a positive image and a region between the circuit and the resistor region in a negative image. The most common way to achieve this is to use photoresist. In this case, the photoresist is applied to the metal surface in liquid or dry form. The photoresist is then selectively exposed to actinic radiation through the negative. The unexposed areas of the resist layer are developed to develop the desired pattern. Alternatively, a resist layer may be screen printed directly onto the metal surface in the desired pattern. After the circuitry is formed with the resist, the exposed copper areas are etched away and the resist is removed to reveal the circuitry. Thus, the region between the circuit and the resistor region is now almost dielectrically free.

Step c) is not necessary, but is recommended. In order for the resistor to be usable and reliable, the resistance must be predictable, relatively constant, and reliable. In order to obtain a plated resistor having a predictable, relatively constant and reliable resistance, the dielectric surface that is plated with the resistive material to form the resistor must be uniform. Dielectric surface uniformity and predictable, relatively constant and reliable resistance of plated resistors are achieved by homogenizing the dielectric surface on which the resistor is to be plated. Homogenization can be achieved in a number of ways, such as vapor blasting, chemical etching, plasma etching, laser correction, or mechanical correction. Mechanical correction can be achieved via sanding, grit blasting or shot blasting. Surface homogenization by chemical etching is the most reliable and efficient method. The particular etchant used in this regard must be matched to the dielectric used. However, if a glass reinforced epoxy resin is used, the inventors found that: alkaline permanganate, concentrated sulfuric acid, chromic acid, or plasma are particularly useful for etching and homogenizing the surface of the dielectric. In this regard, it is preferred that a solution of sodium or potassium permanganate at a concentration in excess of 50 grams per liter be subjected to a period of 2 to 20 minutes in 10 weight percent caustic solution at a temperature in excess of 140F. In this regard, if permanganate is used, a swelling agent or sensitizer may be used to make the dielectric more receptive to permanganate etching. A typical swelling agent suitable for epoxy resins is meta-pyrrole, full strength pressed at from 90 to 120 ℃ F. for 1 to 5 minutes. In addition, an acidic reducing solution is typically used to remove permanganate residues after the permanganate etch.

Step d) comprises activating the surface to be plated. The activation of the surface can be carried out in a complex manner: such as from a single impregnation in a noble metal activator (or a non-noble metal or other activator as is well known in the art) to an all-plating cycle involving multiple steps. Typically, the activation procedure starts with a conditioner (surfactant or other type) followed by an activator (PdCl)₂/SnCl₂Colloid) and accelerator. If an accelerator is used, the inventors have found that it is preferable to apply the accelerator solution immediately prior to step f) (i.e., the electroplating of the resistor). Electroless plating accelerators are well known in the art and include simple solutions of hydrochloric or fluoroboric acid, or alkaline solutions of sodium chlorite. Between each chemical treatment a clean water rinse is arranged. Regardless of the activation cycle chosen, its primary purpose is to treat the surface to initiate and receive plating. Various methods of accomplishing this are known in the art, and any of these may be advantageously utilized herein. Please refer to us patent nos. 5,032,427(Kukanskis et al), 4,976,990(Bach et al) and 4,863,758(Rhodenizer), the teachings of which are incorporated herein by reference. The inventors have found that it is advantageous to dry the metal clad laminate after the activation cycle of step d).

In step e), a solid or liquid plating resist is applied so that the resistor area is formed in negative form. Typically, to achieve this, the plating resist covers all or substantially all of the surface, except for the resistor area. Plated resistors are more reliable if the plating resist allows some plating overlap, which occurs where the resistive plating layer coincides with the conductive circuit, as opposed to covering all of the circuit with the plating resist, so that the resistive plating layer only abuts the conductive circuit. In any case, the plating resist may be any conventional plating resist known in the art so long as it maintains its integrity in the subsequent plating bath. The electroplated protective layer may be screen printed onto the surface in the desired pattern or offset coated, photoimaged and developed. In applying a solid electroplated protective layer to a surface, the inventors have found that vacuum lamination is particularly useful in ensuring that the protective layer conforms closely to the three-dimensional features of the surface.

Step f) includes electroplating the resistor. At this stage, plating only occurs in areas not covered by the plating resist (step e) (e.g., resistor areas, preferably with some overlap where the resistor is connected to the circuit). Various electroplating baths may be advantageously utilized. In this regard, electroless nickel-phosphorus (or alloys thereof), electroless noble metal plating baths, including palladium-phosphorus or ruthenium-phosphorus (or alloys of any of the foregoing) electroless plating baths are particularly useful. Optionally, it may be desirable to clean and/or accelerate the surface prior to electroplating.

Clearly, the thickness of the plated metal has a direct effect on the resistivity of the resulting resistor. The inventor finds that: generally, the thickness of the plated metal is advantageously in the range of 0.05 to 2.5 microns, preferably 0.10 to 1.0 microns and more preferably 0.10 to 0.50 microns. Depending on the plating bath used and the final resistance required, the plating is advantageously continued for 2 to 3 minutes, more advantageously 5 to 10 minutes.

Based on the final resistance required, the following factors can be adjusted to alter the resistivity of the resulting resistance: the type of metal plated, the thickness of the metal plated, the length of the resistor, the width of the resistor and the subsequent processing of the resistor. With respect to the type of metal plated, the phosphorous content in nickel-phosphorous, palladium-phosphorous, or ruthenium-phosphorous can affect the resistivity of the final deposit. All of the foregoing factors may be varied to achieve the desired final resistance. The inventor finds that: the internal resistance of electroplated nickel, palladium or ruthenium increases with the phosphorus content of the metal. It was also found that: it is most advantageous to use nickel having a phosphorus content of 10 to 13 wt.% and palladium having a phosphorus content of 2 to 8 wt.% to plate the resistor. The inventor finds that: metals with high phosphorus content, especially nickel or palladium, produce electroplated coatings with very high internal resistance. Thus, for any given desired final resistance of the resistor, a greater thickness of material can be plated (maintaining the length and width constant), resulting in a more reliable plated resistor. This approach also allows commercially acceptable plating times in the range of 2 to 3 minutes. Plating times of less than 2 to 3 minutes are too short to be easily controlled in a commercial process with reliability, resulting in relatively unreliable plated resistors. If resistors with different resistances are required on the same circuit board, steps e) and f) or d), e) and f) may be repeated to electroplate different resistors with different thicknesses of resistive material or with different resistive materials. Of course, other variables such as the length and width of the resistor may be altered in another manner without repeating any steps.

Optionally, step g) provides a controlled oxidation of the plated resistor metal, preferably by controlled chemical oxidation. Controlled oxidation is a method for increasing the resistivity of plated resistors and more importantly can provide more predictable resistance on a consistent basis. In this regard, various oxidizing agents may be used, including the preferred use of potassium iodate. If potassium iodate is used, it has proven effective to use an aqueous solution of 10 to 75gr/l potassium iodate at a temperature of 90 c for a period of 5 minutes. Here, a higher internal resistance material allows for a greater thickness of plated material (other variables constant), more reliable plated resistors, and commercially acceptable plating times. The increase in internal resistance of the plated metal that can be obtained is 20 to 400% based on the internal resistance of the same unoxidized metal.

Step h) includes removing the plating resist. The stripping solution must be selected to match the plating resist used. Typical electroplated protective layers can be removed in alkaline solutions, however, certain operations require organic solvents.

In step i), it is optional and desirable to clean the surface of the printed circuit board in order to remove any residual activator and to increase the surface insulation resistance of the board. U.S. patent nos. 5,221,418, 5,207,867 and 4,978,422, the teachings of which are incorporated herein by reference, all teach different methods of cleaning and increasing the surface insulation resistance of a board as shown in said step i). It must be noted that the resistance of the plated resistor is not affected by the aforementioned cleaning. As previously mentioned, it is advantageous to protect the plated resistors by using the same type of coating, either permanently or non-permanently, before cleaning the circuit. Thus, step i) can be performed after step h) as shown, or after step 1) in the case of a resistor which has been coated with a suitable protective coating. However, unless the resistor is protected, no further chemical processes will occur after trimming, as further processes will affect the insulation resistance of the resistor.

As previously mentioned, it is generally important that the resistivity of plated resistors be predictable and invariant over time. The inventors have found that subsequent processing of the printed circuit board may cause the resistance value of the plated resistor to change. In particular, the lamination and soldering processes can permanently change the resistance value of the resistor. Furthermore, the inventors have found that baking the plated resistor stabilizes the resistance value of the resistor, thus minimizing changes in the resistance value caused by subsequent processing. Therefore, the inventors bake the plated resistor at a temperature of 100 ° f to 400 ° f for 30 minutes to 3 hours, more preferably at a temperature of 300 ° f to 400 ° f for 30 minutes to 1.5 hours, to stabilize the resistance value of the resistor and minimize the subsequent change thereof. In designing a resistor, any change in resistance value due to baking the resistor or other subsequent processing must be expected. The resulting change in the insulation resistance value of the plated resistor can be achieved through trimming.

After baking or after plating (if the baking process is not desired), the resistance of the plated resistor can be measured and adjusted by trimming, if necessary. Trimming is a process of increasing the insulation resistance of a plated resistor to a predetermined or specified magnitude by trimming or removing a portion of the plated resistor in a controlled manner to achieve a specified insulation resistance of the device. Removal under trim or controlled conditions is typically accomplished by the use of a laser. In this regard, a laser is used to melt away portions of the plated resistor under precise and controlled conditions to achieve a desired resistance value. Plated resistors are particularly suited to this form of laser ablation because the plated film layer is typically quite thin (i.e., about 5 to 25 microinches). Alternatively, the plated resistors may be trimmed using any method that reliably removes portions of the plated resistors in a controlled manner. Most preferably, the trimming step is performed as close to the end of the printed circuit manufacturing process as possible to minimize the possibility of variations in resistance values.

Finally, it is often desirable to cover the surface of the board (including the plated resistor) with a protective coating such as solder resist. In order to protect the board and enhance the durability of the resulting product in subsequent processing, it is necessary to use a solder resist layer. A typical solder mask process is described in U.S. patent No. 5,296,334, the teachings of which are incorporated herein by reference.

Resistivity is the reciprocal value of conductivity. Typically expressed in terms of volume resistivity, surface resistivity, and/or insulation resistance, as specified by ASTM D257. The volume resistivity is the resistance between the faces of the unit cube and is equal to V ═ AR/X, where V is the volume resistivity in ohms-cm, a is the cross-sectional area of the electrical path (square centimeters), R is the measured resistance (ohms), and X is the length of the electrical path. The volume resistivity of the plated resistors as described in the present invention can range in value from about 500 to about 1 x 10^-4Ohm-cm, preferably in the range of about 5 to about 5 x 10^-4Ohm-cm, most preferably at about 1X 10^-2To about 1X 10^-3In ohm cm. Surface resistivity is the ability of an insulator to resist the flow of current in its surface and is equal to S ═ PR/D, where S is the surface resistivity in ohms/square, P is the parameter (cm) of the protective electrode shown in ASTM D257, R is the measured resistance (ohms), and D is the distance (cm) between the electrodes. Insulation resistance is measured on a particular device or configuration and is the overall effect of volume and surface resistivity. Insulation resistance is often expressed in ohms and is related to a particular device or configuration. The plated resistors as described in the present invention have an insulation resistance ranging from about 1 to about 10,000 ohms, preferably about 10 to about 1,000 ohms.

Applying the foregoing principles to a particular plated resistor having a particular desired design resistance (e.g., insulation resistance), the following equations are useful:

R＝VX/A

where R is the total required resistance (e.g., its insulation resistance) of the particular plated resistor.

V-the volume resistivity of the plated deposit, and is generally approximately constant for a particular plating solution.

X is the length of the plated resistor.

A is the cross-sectional area (width x thickness) of the plated resistor.

Typical embodiments may require plated resistors having a width of 0.005 inches, a length of 0.005 inches, and a total required resistance of 275 ohms + -15 ohms. Using an electroplating solution, the deposit has a thickness of about 7X 10^-3Modified electroless nickel-phosphorus deposits of ohmic-cm volume resistance and deposition of the aforementioned electroless nickel at a thickness of 10 microinches yield resistors with the desired overall resistance as follows:

r ═ 0.007 ohm cm (0.005 inch)/(5 × 10 cm)^-8Inch (L)²) XXX (1 inch/2.54 cm)

276 ohm

If further increases in resistance are desired, the deposits so electroplated may be oxidized as described herein. It should be noted in this regard that the key to obtaining reproducible results is to calibrate the surface as described herein before plating the surface. Post-oxidation of the deposits can also increase resistance and improve reproducibility. The desired adjustment of the resistance of the plated resistor can be made by trimming as previously described.

For comparison purposes, the volume resistivity of copper-plated circuit patterns or copper-plated through-holes on printed circuit boards is typically less than about 5 x 10^-5Ohm-cm, which may preferably range from about 1X 10^-6To about 1X 10^-8Ohm cm. The volume resistivity of the dielectric substrate of FR-4 epoxy glass printed circuit boards is typically greater than about 10⁹Ohm-cm, which may preferably range from about 10⁹To about 10²⁰Ohm cm.

As miniaturization of electronic devices progresses, the surface area of printed circuit boards becomes more compact and valuable. As a result, the overall size of resistors plated in accordance with the present invention must match the size requirements of printed circuit boards that are always being reduced. Having a thickness of 500 to 1X 10^-4Plated resistors prepared in accordance with the present invention having an ohm-centimeter volume resistivity can be formed having a length of about 0.002 inches to about 1.0 inches, preferably about 0.005 to about 0.20 inches, most preferably about 0.005 to about 0.080 inches, and a width of about 0.002 to about 1.0 inches, preferably about 0.005 to about 0.20 inches, most preferably about 0.005 to 0.080 inches, and a thickness of about 2 to about 300 microinches, preferably about 5 to about 100 microinches, and most preferably about 5 to about 25 microinches. Typically, the aforementioned length and width dimensions are imaged dimensions (e.g., dimensions of the imaged plating resist in areas plated with the resistive material). The actual size of the plated resistors may vary slightly.

The following examples are for illustrative purposes only and should not be construed as limiting the invention in any way.

Example I

The copper-clad glass reinforced epoxy laminate was treated by the following sequence:

1. a dry film protective layer (supplied by mcdermad ltd., aquamer cf-1.5) was laminated to both copper surfaces of the laminate. The protective layer is then exposed through a negative film, optionally to ultraviolet light. The negative is designed such that the uv light only affects the circuit areas (i.e., the circuit is formed in a positive manner and the area between the circuit and the resistor area is formed in a negative manner). The unexposed portion of the protective layer was developed using a 1 wt% potassium carbonate solution at 90 deg.F for 30 seconds.

2. The exposed copper surface was etched by spraying ammoniacal copper chloride etchant at 110 ° f until the exposed copper was completely etched away. The protective layer was then peeled in 10 wt% caustic solution.

3. The surface is activated to receive plating thereon by the following sequence of treatments:

a) McMed M-conditioner, 110 ℃ F., 2 min

b) McMed M-preactivator, 75 ℃ F. for 2 min

c) McMed M-activator at 100 ℃ for 5 min

Clean water rinse was used between each of the foregoing steps.

4. A macdermad Viatek PM #4 plating resist is then applied to the surface through a screen so that it covers all surfaces except the areas where the resistors are to be plated (the resistor areas) (i.e., so that the resistor areas are formed in negative). The electroplated protective layer was then cured by baking at 250 ℃ for 5 minutes. The width and length of the resistor area, the resistivity of the electroless palladium-phosphorus and the thickness of the palladium-phosphorus plating are used to design and predict the final resistance of the plated resistor.

5. The resistor area was then electroplated by immersion in a Mickmidd Pallas 52 electroless palladium-phosphorus plating bath prepared for each of the data sheets provided at 150 degrees Fahrenheit for 5 minutes. About 0.1 to 0.2 microns of electroless palladium-phosphorus is plated.

6. The electroplated protective layer was then peeled off using a 10 wt% caustic solution at 150 ° f for 2 minutes and then rinsed thoroughly.

The laminate is then passed through electrical testing to determine the actual resistance of the plated resistor and the actual resistance is compared to the design resistance. A deviation of 25 to 30% was recorded.

Example II

A copper clad glass reinforced epoxy laminate was processed by the same sequence as in example I except that the following additional processes were inserted after step 2 and before step 3:

a) M-Pyrol, 100% by weight, 90 ℃ F. for 2 minutes

b) Potassium permanganate, 60gr/l, 10 wt% caustic soda, 160 ° F, 10 minutes

c)10 weight percent hydrochloric acid, 5gr/l hydroxylamine sulfate, 110 ℃ F. for 5 minutes

The laminate is then passed through electrical testing to determine the actual resistance of the plated resistor and the actual resistance is compared to the design resistance. A deviation of 8 to 10% was recorded.

The laminates were further processed to obtain a multilayer package by interleaving glass reinforced epoxy prepregs between multiple laminates and between a laminate and a copper foil clad. The multi-layer package is then subjected to heat and pressure treatment to melt and cure the interposed prepreg layer. The actual laminate is again electrically tested after isolating the resistors to determine the actual resistance of the plated resistors, which is then compared to the design resistance. A deviation of 20 to 30% was recorded.

Example III

The copper clad glass reinforced epoxy laminate was processed by the same sequence as in example II except that the following process was performed at the end of the step of example II:

the resistors were oxidized by immersing the plates in 40gr/l aqueous potassium iodate solution at 90 ℃ for 5 minutes.

The laminate was then passed through an electrical test to determine the actual resistance of the plated resistor (without subsequent lamination). The actual resistance increased by 300% compared to the unoxidized resistor of example II. Deviations of 5 to 10% were recorded.

Example IV

The copper clad glass reinforced epoxy laminate was processed through the same sequence as in example II except that the laminate was baked at 350 ℃ F. for 1 hour after step 6.

The laminate is then passed through electrical testing to determine the actual resistance of the plated resistor and the actual resistance is compared to the design resistance. Deviations of 5 to 10% were recorded.

The laminates were further processed to obtain a multilayer package by interleaving glass reinforced epoxy prepregs between multiple laminates and between a laminate and a copper foil clad. The multi-layer package is then subjected to heat and pressure treatment to melt and cure the interposed prepreg layer. The actual laminate is again electrically tested after isolating the resistors to determine the actual resistance of the plated resistors, which is then compared to the design resistance. Deviations of 5 to 10% were recorded.

Claims (43)

1. A method of forming a resistor between two metal circuit conductors, the circuit conductors having a resistance of less than 5 x 10^-6Ohm-cm, and the circuit wires are on and separated by an insulating substrate having a volume resistivity of greater than 1 x 10⁹Ohm-cm, the method comprising subjecting the alloy to a temperature of from 500 to 1 x 10^-4Plating a resistive material having a volume resistivity of ohm-cm onto the insulating substrate region between the previously formed circuit conductors to connect the resistive material to the circuit conductors, and then trimming the power loss on the insulating substrateA portion of the material is blocked so that the resistor has an insulation resistance value equal to a predetermined number of ohms.

2. The method of claim 1, wherein the insulating base region between the circuit conductors is treated using a method selected from the group consisting of: chemical etching, plasma etching, laser alignment, steam blasting, sanding, shot blasting, and sand blasting.

3. The method of claim 1, wherein the resistive material is treated after electroplating by a method selected from one of: chemical oxidation, baking, and the two methods.

4. The method of claim 1, wherein the resistive material comprises a material selected from one of: electroless nickel-phosphorus, electroless palladium-phosphorus, electroless ruthenium-phosphorus, and alloys of any of the foregoing.

5. The method of claim 1, wherein the trimming is accomplished by contacting at least a portion of the resistive material with a laser such that at least a portion of the resistive material is ablated or otherwise removed by the contacting.

6. The method of claim 2, wherein the resistive material is treated after electroplating by a method selected from one of: chemical oxidation, baking, and the two methods.

7. The method of claim 2, wherein the resistive material comprises a material selected from one of: electroless nickel-phosphorus, electroless palladium-phosphorus, electroless ruthenium-phosphorus, and alloys of any of the foregoing.

8. The method of claim 2, wherein the resistive material is plated to a thickness of 2 to 300 microinches.

9. The method of claim 4, wherein the resistive material is selected from the group consisting of: electroless nickel-phosphorus having a phosphorus content of at least 10 wt.% in the plated resistive material, and electroless palladium-phosphorus having a phosphorus content of at least 2 wt.% in the plated resistive material.

10. A method of manufacturing a printed circuit board having integral plated resistors, the method comprising:

a) applying an etch-resistant layer to portions of the metal surfaces of a metal-clad laminate, the laminate comprising a polymer-based core having metal clad thereon, such that the etch-resistant layer positively forms the desired circuitry pattern and negatively forms the inter-circuit areas including the resistor sites, thereby providing exposed metal surfaces and metal surfaces covered by the etch-resistant layer;

b) etching away the exposed metal surface, thereby creating metal circuits separated by exposed areas of the polymer-based core;

c) stripping the etching-resistant layer;

d) activating at least a portion of the exposed areas of the polymer-based core to receive electroplating thereon;

e) applying a plating resist such that the plating resist covers all or substantially all of the surface of the metal-clad laminate except for the area where the resistor is to be plated;

f) using a catalyst having a molecular weight of from 500 to 1X 10^-4Electroplating the area which is not covered by the electroplating protective layer by using the resistance material with the volume resistivity of ohm-cm;

g) stripping the electroplating protective layer; and

h) trimming at least a portion of the resistive material from the insulating substrate such that the resistor has an insulation resistance value equal to a predetermined number of ohms.

11. The method of claim 10, wherein the resistive material is treated after electroplating by a method selected from one of: chemical oxidation, baking, and the two methods.

12. The method of claim 10, wherein the trimming is accomplished by contacting at least a portion of the resistive material with a laser such that at least a portion of the resistive material is ablated or otherwise removed by the contacting.

13. The method of claim 10, wherein after step g), the printed circuit board is cleaned.

14. The method of claim 10, wherein after step h), a permanent protective coating is applied to the printed circuit board.

15. The method of claim 10, wherein the resistive material is plated to a thickness of 2 to 300 microinches.

16. The method of claim 10, wherein the resistive material comprises a material selected from one of: electroless nickel-phosphorus, electroless palladium-phosphorus, electroless ruthenium-phosphorus, and alloys of any of the foregoing.

17. The method of claim 16, wherein the resistive material is selected from the group consisting of: electroless nickel-phosphorus having a phosphorus content of at least 10 wt.% in the plated resistive material, and electroless palladium-phosphorus having a phosphorus content of at least 2 wt.% in the plated resistive material.

18. A printed circuit board comprises metal circuits on and separated by an insulating substrate, and a circuit board having a width of 500 to 1 × 10^-4An ohm-centimeter volume resistivity resistor formed by trimming at least a portion of a resistive material selectively plated on a polymer-based matrix such that each resistor independently has an insulation resistance value equal to a predetermined number of ohms, wherein the metal circuitThrough which connection is made at a designated point.

19. The printed circuit board of claim 18, wherein the resistive material is chemically oxidized or baked.

20. The printed circuit board of claim 18, wherein the resistive material comprises a material selected from one of: electroless nickel-phosphorus, electroless palladium-phosphorus, electroless ruthenium-phosphorus, and alloys of any of the foregoing.

21. The printed circuit board of claim 20, wherein the resistive material is selected from the group consisting of: electroless nickel-phosphorus having a phosphorus content of at least 10 wt.% in the plated resistive material, and electroless palladium-phosphorus having a phosphorus content of at least 2 wt.% in the plated resistive material.

22. A method of forming a resistor between two metal regions on and separated by an insulating substrate having a thickness of from 10⁹To 10²⁰Ohm-cm and the method comprises that the volume resistivity is from 500 to 1 x 10^-4Ohmic-centimeter volume resistivity resistive material is plated onto a portion of the insulating substrate between the pre-formed metal regions such that the resistive material is connected to the metal regions, and then trimming at least a portion of the resistive material from the insulating substrate such that the resistor has an insulation resistance value equal to a predetermined number of ohms.

23. The method of claim 22, wherein the conductive area is a circuit located on a printed circuit board.

24. The method of claim 22, wherein the resistive material comprises a material selected from one of: electroless nickel-phosphorus, electroless palladium-phosphorus, electroless ruthenium-phosphorus, and alloys of any of the foregoing.

25. The method of claim 22, wherein the trimming is accomplished by contacting at least a portion of the resistive material with a laser such that at least a portion of the resistive material is ablated or otherwise removed by the contacting.

26. The method of claim 24, wherein the resistive material is selected from the group consisting of: electroless nickel-phosphorus having a phosphorus content of at least 10 wt.% in the plated resistive material, and electroless palladium-phosphorus having a phosphorus content of at least 2 wt.% in the plated resistive material.

27. A method of manufacturing a printed circuit board having integral plated resistors, the method comprising:

a) applying an etch-resistant layer to the metal surface portions of the metal-clad laminate, the laminate comprising a polymer-based core having metal clad thereon, such that the etch-resistant layer positively forms the desired circuitry pattern and negatively forms the inter-circuit areas including the resistor sites, thereby providing exposed metal surfaces and metal surfaces covered by the etch-resistant layer;

b) etching away the exposed metal surface, thereby creating metal circuits separated by exposed areas of the polymer-based core;

c) stripping the etching-resistant layer;

d) activating at least a portion of the exposed areas of the polymer-based core to receive electroplating thereon;

e) applying a plating resist such that the plating resist covers all or substantially all of the surface of the metal-clad laminate except for the area where the resistor is to be plated;

f) electroplating the area not covered by the electroplating protective layer by using a resistance material to form a resistor; and

g) trimming off at least a portion of the resistive material such that the resistor has a resistance equal to 10 to 1000 ohms, a length of 0.005 to 0.20 inches, a width of 0.005 to 0.20 inches, and a thickness of 5 to 100 microinches.

28. The method of claim 27, wherein the resistor is treated after plating by a method selected from one of: chemical oxidation, baking, and the two methods.

29. The method of claim 27, wherein after step f), the printed circuit board is cleaned.

30. The method of claim 27, wherein the resistive material comprises a material selected from one of: electroless nickel-phosphorus, electroless palladium-phosphorus, electroless ruthenium-phosphorus, and alloys of any of the foregoing.

31. The method of claim 27 wherein after step g), a permanent protective coating is applied to the printed circuit board.

32. The method of claim 27, wherein the resistor is overlaid onto the metal circuit.

33. The method of claim 27, wherein the resistor has a length of 0.005 to 0.080 inches, a width of 0.005 to 0.080 inches, and a thickness of 5 to 25 microinches.

34. The method of claim 27, wherein the trimming is accomplished by contacting at least a portion of the resistive material with a laser such that at least a portion of the resistive material is ablated or otherwise removed by the contacting.

35. The method of claim 27, wherein the resistive material is treated after electroplating by a method selected from one of: chemical oxidation, baking, and the two methods.

36. The method of claim 30, wherein the resistive material is selected from the group consisting of: electroless nickel-phosphorus having a phosphorus content of at least 10 wt.% in the plated resistive material, and electroless palladium-phosphorus having a phosphorus content of at least 2 wt.% in the plated resistive material.

37. A method of forming a resistor between two metal regions on and separated by an insulating substrate having a thickness of from 10⁹To 10²⁰Ohm-cm and the method comprises mixing a mixture of a monomer having a volume resistivity of from 500 to 1 x 10^-4An ohmic-centimeter volume resistivity resistive material is plated onto a portion of the insulating substrate between the pre-formed metallic regions such that the resistive material is connected to the metallic regions, and then the resistive material is heated at least 100 degrees Fahrenheit for at least 30 minutes.

38. The method of claim 37, wherein the resistive material comprises a material selected from one of: electroless nickel-phosphorus, electroless palladium-phosphorus, electroless ruthenium-phosphorus, and alloys of any of the foregoing.

39. The method of claim 37, wherein said insulating substrate between said metal regions is treated prior to electroplating said resistive material thereon using a method selected from the group consisting of: chemical etching, plasma etching, laser alignment, steam blasting, sanding, shot blasting, and sand blasting.

40. The method of claim 37, wherein at least a portion of the resistive material is trimmed from the insulating substrate such that the resistor has an insulation resistance value equal to a predetermined number of ohms.

41. The method of claim 38, wherein the resistive material is selected from the group consisting of: electroless nickel-phosphorus having a phosphorus content of at least 10 wt.% in the plated resistive material, and electroless palladium-phosphorus having a phosphorus content of at least 2 wt.% in the plated resistive material.

42. The method of claim 40, wherein the resistive material is trimmed by contacting at least a portion of the resistive material with a laser such that at least a portion of the resistive material is ablated or otherwise removed by the contacting.

43. The method of claim 42, wherein the resistive material is selected from the group consisting of: electroless nickel-phosphorus having a phosphorus content of at least 10 wt.% in the plated resistive material, and electroless palladium-phosphorus having a phosphorus content of at least 2 wt.% in the plated resistive material.