HK1065184B - Physical layer processing for a wireless communication system using code division multiple access - Google Patents

Description

Physical layer processing in a wireless communication system using code division multiple access

(1) Field of the invention

This application claims priority from U.S. patent provisional application serial No. 60/284062, filed on day 4, month 16, 2001.

The present invention relates generally to wireless Time Division Duplex (TDD) communication systems using Code Division Multiple Access (CDMA), and more particularly to physical layer processing of data in such systems.

(2) Background of the invention

In a CDMA communication system, communication content is transmitted over a wireless air interface in the same frequency spectrum, identified by channel codes. To further increase spectrum usage, CDMA/TDD communication systems divide the spectrum into repeating frames with a fixed number of time slots (time slots), e.g., fifteen (15) slots per frame, over time. In TDD, each time slot is used only for uplink or downlink.

Data to be transferred over the air interface is processed prior to transmission by the Universal Mobile Telecommunications System (UMTS) terrestrial radio access network (UTRAN). A simplified wireless communication system is depicted in fig. 1. Wireless subscriber (user equipment) 38₁-38_N(38) And a base station 36₁-36_N(36) And (6) communicating. Generally, a node-B34₁-34_N(34) Controls a group of base stations 36. A Radio Network Controller (RNC)32₁-32_N(32) Controls a group of node-bs 34. The RNC 32, node-B34 and other accompanying components are part of the UTRAN 30. The UTRAN30 communicates with other users through the core network 40.

Data processing within the UTRAN30 is standardized, such as by the third Generation partnership project (3GPP), UMTS Terrestrial Radio Access (UTRA) TDD system. The UTRAN30 handles transport channels to be used for air interface transfer. Fig. 2 is a block diagram of this UTRAN process.

Transport blocks arrive to be transported over the air interface. The transport blocks arrive in groups (transport block groups). Each group is received at a specified time interval [ Transmission Time Interval (TTI) ]. In the case of 3GPP UTRA TDD, possible TTI lengths are 10, 20, 40 and 80 milliseconds, which correspond to 1, 2, 4 and 8 radio frames, respectively.

A Cyclic Redundancy Code (CRC) attachment block 42 attaches CRC bits to each transport block. These CRC bits are used for error detection by the receiver. The CRC bit length is signaled by higher layers.

Transport blocks (TrBks) are serially connected by a TrBk concatenation/code block segmentation block 44. If the number of bits of the concatenated block is greater than the maximum allowable number of a code block, the concatenated block is segmented. The size of the code block group is based on the type of error correction coding to be used, such as convolutional coding (maximum 504 bits), turbo coding (maximum 5114 bits), or no coding (without limitation). The concatenation block is divided into at least equal size segments (code blocks). If the original number of concatenated bits is not an integer multiple of the minimum number of segments, padding bits are used to ensure that the segments are equal in size.

A channel coding block 46 performs error correction coding on the code blocks, for example, by convolutional coding, turbo coding, or no coding. After encoding, the code blocks are concatenated together. If the concatenated code block cannot be segmented into at least equal size segments (frames), Radio Frame equalization (Radio Frame equalization) is performed by concatenating additional arbitrary bits.

A first interleaver 48 interleaves all of the concatenated bits. The interleaved data is then segmented into radio frames in a radio frame segmentation block 50. A rate matching block 52 punctures or repeats the bits. This puncturing or repetition ensures that the data transmitted on each physical channel (resource unit) is equal to the maximum bit rate for that channel. The rate matching attribute for each transport channel (TrCH) is signaled by higher layers.

The TrCH mux block 54 receives one frame of data from each transport channel. Each TrCH data received is serially multiplexed to a coded composite transport channel (CCTrCH). A bit scrambling block 56 scrambles the CCTrCH bits.

A physical channel block 58 maps the scrambled bits to physical channels. A second interleaver 60 interleaves the scrambled bits over the entire radio frame or each time slot. The type of interleaving used is specified by higher layers. After the second interleaving, the interleaved data is split into physical channels for transmission over the air interface by a physical channel mapping block 62. Physical channel data is then transmitted, for example, from a base station 36 or UE 38. At the receiver (e.g., at a UE 38 or base station 36), the same procedure is reversed to recover the transmitted data.

To process the data shown in fig. 2, multiple levels of buffering (buffers 64, 66, 68, 70, 72) are necessary, for example, after the first interleaver 48, the rate matching block 52, the transport channel multiplexing block, the bit scrambling block 56, and the second interleaver 60. Such extended buffering is undesirable. Which requires heavy memory usage and additional Application Specific Integrated Circuits (ASICs) to the memory to accommodate such buffering.

Accordingly, alternative data processing architectures are desired.

(3) Summary of the invention

According to an aspect of the present invention, there is provided a physical layer processing method for a wireless communication system, the method including: providing a first interleaver buffer having bits stored at a first interleaver address; determining a physical channel address of the bit corresponding to the bit address after rate matching, bit scrambling, second interleaving and physical channel mapping using the first interleaver address; and wherein determining a physical channel address comprises determining a rate matching address corresponding to the bit and bit address after rate matching using the first interleaver address; determining a second interleaving address corresponding to the bit and the bit address after second interleaving by using the rate matching address; and determining the physical channel address corresponding to the bit and the bit address after the physical channel mapping; reading the bits directly from the first interleaver buffer and writing the bits to a physical channel buffer using the determined physical channel address; and transmitting the bits in the physical channel buffer over an air interface.

According to another aspect of the present invention, there is provided a physical layer processing method for a wireless communication system, the method comprising: providing a physical channel buffer capable of storing bits at physical channel addresses; determining a first interleaver address of the bit corresponding to the bit address after reverse physical channel mapping, reverse second interleaving, reverse bit scrambling and reverse rate matching by using the physical channel address; and directly reading bits from the determined first interleaver address of the first interleaver buffer and writing the bits into the address of the physical channel buffer for the address of the physical channel buffer.

According to still another aspect of the present invention, there is provided a physical layer processing method for a wireless communication system, the method comprising: first interleaving bits received in a time transmission interval having bits for a plurality of frames; and for a first interleaved bit of a first frame of the plurality of frames, performing physical channel processing prior to buffering the first interleaved bit of the first frame, the physical channel processing including rate matching; and buffering frames other than the first frame after the first interleaving and before the physical channel processing.

According to still another aspect of the present invention, there is provided a user equipment for physical layer processing, the user equipment comprising: means for first interleaving a plurality of bits received in a time transmission interval having a plurality of bits for a plurality of frames; means for performing physical channel processing, including rate matching, on a first interleaved plurality of bits of a first frame of the plurality of frames prior to buffering the first interleaved bits of the first frame; and means for buffering frames other than the first frame after the first interleaving and before physical channel processing.

According to another aspect of the present invention, there is provided a user equipment for physical layer processing, comprising: a first interleaver for first interleaving bits received during a time transmission interval having bits for at least one frame; a first multiplexer for directing a first interleaved bit of a first frame to a second multiplexer and directing first interleaved bits of frames other than the first frame to a memory; a second multiplexer for outputting bits selected from bits of the first frame and bits of other frames stored in the memory for physical channel processing; and a physical channel processing block for performing physical channel processing on the outputted selected bits.

According to another aspect of the present invention, there is provided a base station for physical layer processing, the base station comprising: means for first interleaving bits received in a time transmission interval having bits for a plurality of frames; and means for performing physical channel processing, including rate matching, on a first interleaved bit of a first frame of the plurality of frames prior to buffering the first interleaved bit of the first frame; and means for buffering frames other than the first frame after the first interleaving and before physical channel processing.

According to yet another aspect of the present invention, there is provided a base station for physical layer processing, the base station comprising: a first interleaver for first interleaving bits received during a time transmission interval having bits for at least one frame; a first multiplexer for directing a first interleaved bit of a first frame to a second multiplexer and directing first interleaved bits of frames other than the first frame to a memory; a second multiplexer for outputting bits selected from bits of the first frame and bits of other frames stored in the memory for physical channel processing; and a physical channel processing block for performing physical channel processing on the outputted selected bits.

To further illustrate the above objects, structural features and effects of the present invention, the present invention will be described in detail below with reference to the accompanying drawings.

(4) Description of the drawings

Fig. 1 is a schematic diagram of a wireless TDD/CDMA communication system.

FIG. 2 is a schematic representation of a physical layer process.

FIG. 3 is a flow chart of the "push" approach.

FIG. 4 is a diagram of one embodiment of a "push" approach.

FIG. 5 is a flow chart of "push" rate matching.

FIG. 6 is a flow chart of "push" bit scrambling.

FIG. 7 is a simplified diagram of an alternative embodiment of the "push" approach.

FIG. 8 is a flow diagram of an alternative embodiment of a "push" bit scrambling.

FIG. 9 is a flow chart for "pushing" the second interlace.

Fig. 10 is an example of "push" second interleaving.

FIG. 11 is a flow chart of "pushing" physical channel mapping.

Fig. 12 is an example of "push" physical channel mapping for case 2.

FIG. 13 is an example of "push" physical channel mapping for case 3.

FIG. 14 is an example of "push" physical channel mapping for case 4.

FIG. 15 is a flow chart for the "pull" approach.

FIG. 16 is a diagram of one embodiment of a "pull" approach.

FIG. 17 is a flow chart of "pull" reverse physical channel mapping.

FIG. 18 is an example of "pull" reverse physical channel mapping for case 2.

FIG. 19 is an example of "pull" inverse physical channel mapping for case 3.

FIG. 20 is an example of "pull" reverse physical channel mapping for case 4.

Fig. 21 is a flow chart of "pull" reverse second interleaving.

Fig. 22 is an example of "pull" reverse second interleaving.

FIG. 23 is a flow chart of "pull" reverse rate matching.

Fig. 24 and 25 are flow diagrams of two perspectives of "pulling" reverse rate matching with respect to a punctured turbo code sequence.

FIG. 26 is a flow diagram of an embodiment of "pull" reverse bit scrambling.

FIG. 27 is a simplified diagram of an alternative embodiment of the "pull" approach.

FIG. 28 is a flow chart of an alternative embodiment of a "pull" bit scrambling.

Fig. 29 is a schematic of a "reduced first interleaver buffer".

Fig. 30A and 30B are examples of a "reduced first interleaver buffer" for a 10 ms TTI.

Fig. 31A and 31B are examples of a "reduced first interleaver buffer" for a 10 ms TTI.

(5) Detailed description of the preferred embodiments

Although the preferred embodiment of the present invention is described in terms of a preferred application in a 3GPP UTRA TDD communication system, the embodiment is also applicable to other standards, such as code division multiple Access 2000(CDMA 2000), Time Division Synchronous Code Division Multiple Access (TDSCDMA), and frequency division Duplex code division multiple Access (FDD/CDMA), and applications above. The preferred embodiment is in three general perspectives: the views "push", "pull" and "reduced first interleaver buffering" describe. However, the embodiments of the engine of each perspective may be modified for use in other perspectives or other applications.

One approach to physical channel processing is referred to as the "push" approach, as shown in the flow diagram of FIG. 3 and the block diagram of FIG. 4. On the transmit side of the "push" approach, each bit output from the first interleaver output buffer 82 is mapped (step 74) and written (step 76) into a bit of a physical channel buffer 84. The data in the physical channel buffer 84 is sent to chip rate processing for transmission over the air interface. For example, a given bit of the first interleaver buffer 82 is mapped to no location, a single location, or multiple locations within the physical channel buffer 84, as shown in FIG. 4. After this bit mapping, it is inserted into the corresponding location in the physical layer buffer 84. On the receive side, bits are read from the physical channel buffer 84 and written to the first interleaver buffer 82. Thus, the transmit-side "push" view is performed in reverse order of the "push" view on the receive side. In the following, the "push" point of view is mainly explained from the transmission side. The receiving side proceeds in a similar reverse order.

FIG. 4 is a block diagram of an embodiment of a push approach. For bits in the first interleaver buffer 82, a push bit generation engine determines their destination address in a resource unit of the physical channel buffer 84. The value of the bits of a frame is processed one by one. If the TTI is greater than 10 ms, other frame bits are taken sequentially after the first frame, e.g., from frame 1 to frame 2 to frame 3, etc. The bits may be taken first, or in groups, such as 8 bits, 16 bits, or 32 bits. The push address generation engine 86 determines whether each bit is to be written to a single address, multiple addresses, or no address of the physical channel buffer 84. The push address generation engine 86 uses control parameters (which are normalized or signaled) to determine the correct address.

The push address generation engine 86 sends a control signal to a read/write controller 78. The read/write controller 78 reads one or more bits from corresponding addresses in the first interleaver buffer 82 and writes these bits to the addresses indicated by the push bit generation engine 86. All of these operations are controlled by the physical map controller 104, which also uses control parameters to oversee physical layer processing operations.

The push address generation engine 86 has four main sub-engines: a rate matching engine 88, a bit scrambling engine 90, a second interleaving engine 92, and a physical channel mapping engine 94.

There are three other sub-engines feeding the four main engines: a radio frame segmentation calculation engine 96, a TrCH Multiplexing (MUX) calculation engine 98, and a physical channel segmentation calculation engine 100. These three sub-engines do not functionally change the bit order during physical layer processing. These engines effectively mark bits.

The radio frame segmentation engine 96 determines which bit addresses of the first interleaver buffer 82 to send in each frame. The TrCH MUX engine 98 determines which of the in-frame data is to be transmitted on which CCTrCH. The physical channel segmentation engine 100 decides which of the cctrchs are located for transmission on that physical channel (resource unit). Although the three engines 96, 98, 100 are shown in fig. 1 as being functionally performed prior to the step of requesting information, in practice they may be performed earlier, and possibly prior to the action of any of the primary engines 88, 90, 92, 94.

The four primary engines 88, 90, 92, 94 operate on the transmit side in the order shown in fig. 3. Rate matching is performed first. Followed by bit scrambling and then a second interleaving. And finally, carrying out physical channel mapping.

In rate matching, bits are punctured and repeated to minimize the number of required channels and to ensure that each channel is fully utilized. For example, if a channel has 110 bits in the first interleaver buffer, but the channel requires 100 bits due to the physical channel configuration, 10 bits are punctured. Conversely, if the same channel has only 90 bits in the buffer, then 10 bits would need to be repeated. Because of puncturing and repetition, some of the first interleaver buffer bits may be written without address, with a single address, or with multiple addresses.

The rate matching engine 88 determines the address at which each address of the first interleaver buffer will be rate matched and is described with reference to fig. 5. Rate matching uses mainly three variables: e-ini, e-plus and e-minus. e-ini is the initial value of e in the rate matching algorithm. e-plus is the increment of e in the rate matching algorithm. e-minus is the decrement of e in the rate matching algorithm.

Rate matching engine 88 selects either step 108 or 110 depending on whether a particular channel is convolutionally encoded or turbo encoded (step 106). This selection is signaled by control information. If the channel is not turbo coded, the bits are processed as a single sequence (step 110). Turbo coding adds one of three labels to each bit: systematic (S), isotopoly 1(P1) and isotopoly 2 (P2). No puncturing is done to the systematic bits. The rate matching engine treats each of these bit types as an independent sequence (step 108). Processing the bits independently eliminates the extensive need for bit separation and bit collection as described by this standard.

A preferred rate matching algorithm for push address mapping is as follows (step 112).

Parameter definition:

e_iniinitial error between current and desired breakdown ratio

e_minusReduction of variable e

e_pjusIncrement of variable e

Number of bits before X-rate matching (transmission point of view)

P addresses that are to be bitmapped after puncturing or repeating

Bit address before U rate matching (transmission point of view)

E temporary variable which keeps the "error" at the standard

I sequence identifier (i.e., S, P1 or P2)

F represents a function of the rest of the push processing engine, which further solves the address p and writes the bit u to the appropriate physical channel

If a breakdown is to be made, the following algorithm is used.

e_i＝e_ini，i

p＝0

u＝0

When u < X

e_i＝e_i-e_minus，i

If e_iGreater than 0- -normal non-breakdown site

Performing function f (u, p)

u＝u+1

p＝p+1

Else- -else breakdown

u＝u+1

e_i＝e_i+e_plus，I

End if circulating

End simultaneous cycle

If a repeat is to be made, the following algorithm is used.

e_i＝e_ini，i

p＝0

u＝0

When u < X

e_i＝e_i-e_plis，i

If e_i> 0 then- -normal non-repeat bit

Performing function f (u, p)

u＝u+1

p＝p+1

Else-else this is a repetition bit

Performing function f (u, p)

p＝p+1

e_i＝e_i-e_plis，i

End if circulating

End simultaneous cycle

Although "push" rate matching is described above in connection with a preferred TDD/CDMA communication system, it can be used in a variety of applications, such as in a UE, base station or node-B with a TDD/CDMA, FDD/CDMA and TDSCDMA system.

The next step in this process is bit scrambling. In bit scrambling, the bit order is rearranged to remove a DC bias. The bit scrambling engine determines a bit scrambling address for the address output by the rate matching engine.

In bit scrambling, bits are scrambled using a scrambling code. Bit scrambling is used to remove a DC bias. The bit before bit scrambling is represented by h₁，h₂，h₃，...，h_S. S is the number of bits in a CCTrCH channel, otherwise referred to as a scrambling block. Determining a k of S bits from equations 1 and 2^thA bit.

S_k＝h_k⊕p_kWherein k 1, 2.., S equation 1

img id="idf0001" file="C0280829300131.GIF" wi="183" he="47" img-content="drawing" img-format="GIF"/k < 1 then p_k＝0；p_i＝1；

g {0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1} equation 2

p_kIs a k of the scrambling code^thA bit. g_iIs one i of g^thA bit.

The procedure of bit scrambling will be described in conjunction with the flow chart of FIG. 6. Determining a scrambling code p using a bit position k in the CCTrCH_kAnd a corresponding bit, step 300. Bit hk is scrambled, e.g., exclusive-ORed with pk, step 302.

In an alternative embodiment as shown in fig. 7 and described with respect to the flow diagram of fig. 8, the bit scrambling engine 90 is located after the other engines 88, 92, 94 (rate matching, second interleaving and physical channel mapping). This embodiment allows all address mapping to be performed prior to any operation of the bit values. The bit scrambling engine determines the address of a given bit after rate matching, step 304. Determining p for scrambling the bit using the address after the given bit rate match_kStep 306. The given bit uses the decided p_kScrambling, e.g., by exclusive-or, step 308.

In a UE, base station, or node-B.

Although "push" bit scrambling is described above in connection with a preferred TDD/CDMA communication system, it can be used in a variety of applications, such as in a UE, base station or node-B of a TDD/CDMA system.

The rate matched bits are interleaved using a second interleaving engine 92. Initially, the second interleaving engine 92 must know whether the second interleaving is to be performed for an entire CCTrCH channel or a single time slot of the CCTrCH. This information is signaled from higher layers. In the second interleaving, the bits are read in the column direction, for example, 30 rows. After being read into the array, the rows are arranged. Bits are then read out of the arranged rows.

The second interleaving will be described with reference to fig. 9 and 10. The address p after the second interleaving is determined using the address u of one bit before the second interleaving (after bit scrambling). The rows and columns of bits within the array are determined (step 114) using the known number of rows (e.g., 30 rows) of the array. Taking FIG. 10 as an example, the bit at address 58 after a bit scrambling is analyzed. By dividing the address and rounding down, the column number of the bit is determined (column 1: 58/30 ═ 1 and 29). The row number is determined by the remainder of the division. In this example, the column number is determined as the remainder minus one, column 28 (29-1). The new column number for the bit is determined using the known column arrangement (step 116). For this example, row 28 replaces row 11. The number of bits in the CCTrCH channel or CCTrCH timeslot and the column offset determine the bit address p after the second interleaving (step 118). In this example, seven rows have 3 bits and four rows have 2 bits before row 11. Thus, the bit is at address 30 after the second interleaving.

Although "push" second interleaving is described above in connection with a preferred TDD/CDMA communication system, it can be used in a variety of applications, such as in a UE, base station or node-B with a TDD/CDMA, FDD/CDMA and TDSCDMA system.

After the second interleaving, the bits of each CCTrCH are mapped into physical channels/resource units. Physical channel mapping is described in conjunction with fig. 11. Physical channel mapping uses different mapping perspectives for four different cases. In the first case, a timeslot has only one resource unit for use by the CCTrCH. In a second case, more than one resource unit is used in a downlink time slot. In a third case, more than one resource unit is used in the uplink and the spreading factor of the data within the first resource unit is greater than or equal to the spreading factor of the second resource unit. In a fourth case, more than one resource unit is used in the uplink and the spreading factor of the first resource unit is smaller than the spreading factor of the second resource unit. In the uplink, only two resource units can be used for a CCTrCH in a timeslot. The physical channel mapping engine 100 classifies the address u of the input bit into one of four categories (step 120).

For the first case (a single resource unit in a slot), bits are assigned to the resource units sequentially. Thus, the second interleaved bit address u directly corresponds to the address p within the resource unit (step 122).

For the second case (downlink for multiple resource units), bits are assigned to each resource unit in sequence. A first bit to resource unit 1, a second bit to resource unit 2, and so on until the last resource unit. When the last resource unit is reached, the next bit is assigned to resource unit 1.

The assignment of each resource unit can be considered a modulo count. Taking fig. 12 as an example, where there are three resource units to fill the resource units is a modulo 3 count. For the general state of N resource units, the resource units are filled using a modulo N count.

The odd plurality of resource units is filled from left to right, and the even plurality of resource units is filled from right to left in reverse order. As shown in fig. 12, resource units 1 and 3 are filled from left to right and resource unit 2 is filled from right to left.

The bits are filled in this manner until a resource unit is filled. This point is called the switching point. At this switching point, the modulus is subtracted by the number of filled resource units. Taking fig. 12 as an example, resource unit 1 is filled at bit 681. After the remaining resource units are filled, resource units 2 and 3 are filled starting from bit 684 (the switch point) using a modulo-2 count.

The physical channel mapping engine classifies bits into one of four categories: forward before the switch point, reverse before the switch point, forward after the switch point, and reverse after the switch point (step 124). The forward representative positions are filled from left to right, and the reverse representative positions are filled from right to left. The address of a bit is determined based on its classification (step 126).

The switching point is derived from the length of the shortest resource unit and multiplying the length by the number of resource units. Referring to fig. 12, the first resource unit is 228 bits long. The switch point is 228 x 3 resource units or 684. After the switch point is determined, the bit is determined to be either forward or reverse. For bits not reaching the switch point, the address is determined as the remainder of the division of the bit address by the modulus. Taking address 682 as an example, 682 divided by the modulus 3 equals 227 to 1. Since resource units are numbered from one to three, rather than from zero to two, adding one to the remainder results in this bit being in resource unit 2. With respect to the sorting, the bits within the odd plurality of resource units are straight-going and the bits within the even plurality of resource units are reverse-going.

After the switch point, a similar approach is used. The address is subtracted from the switch point and the remainder of the division by the new modulus is used to determine the resource unit of the bit.

After the bits are sorted, one of four formulas is used to determine their addresses. For forward before the switch point, equation 3 is used.

p ═ Start + u/mod equation 3

Start is the first address in the resource unit, e.g., bit 0. u is the address of the bit after physical channel mapping. p is the determined resource unit address. mod is the modulus before the switch point, which in this example is 3.

For reverse before the switch point, equation 4 is used.

p-End-u/mod equation 4

End is the final address within the resource unit.

For forward after the switch point, equation 5 is used.

p＝Start+SP/mod+(u-SP)/mod_SPEquation 5

SP is mod at the switching point_SPThe modulus after the over-switch point.

For reverse after the switch point, equation 6 is used.

p＝End-SP/mod-(u-SP)/mod_sp-1 equation 6

For case 3 (uplink where the spreading factor of the first resource unit is greater than the second resource unit), the bits are filled into the resource units using a modulus based on the two resource unit spreading factors. Equation 7 is used to determine the modulus.

mod 1+ max [ (SF1, SF2)/min (SF1, SF2) ] equation 7

SF1 is the spreading factor for resource unit 1 and SF2 is the spreading factor for resource unit 2.

Taking fig. 13 as an example, resource unit 1 has a spreading factor of 16 and resource unit 1 has a spreading factor of 4. Thus, the resource unit is filled using a modulo-5 count. Thus, resource unit 1 has bits 0 and 5 and resource unit 2 has bits 1 through 4. After resource unit 1 is filled, the remaining bits are sequentially filled into resource unit 2. The point at which resource unit 1 fills up is the switch point. Resource unit 1 is always filled from left to right and resource unit 2 is filled in reverse.

The physical channel mapping engine classifies bits into one of three categories: forward before switch point, reverse before switch point, and reverse after switch point (step 128). The address of a bit is determined based on its class (step 130).

The switch point is derived from the length of the first resource unit in equation 8.

Equation 8 for SP-mod × length of first resource unit

After the switching point is determined, it is determined whether the bit is going straight or going backward. For bits prior to the switch point, if there is a remainder of dividing the modulo by the bit address, the bit is in the second resource unit. Taking bit 4 as an example, dividing 4 by the modulus 5 yields a remainder of 4. As shown in fig. 10, bit 4 is as expected within resource unit 2. If there is no remainder, the bit is in the first resource unit. After the switch point is passed, all bits are in the second resource unit.

After the bits are sorted, one of three formulas is used to determine their addresses. For forward before the switch point, equation 9 is used.

p＝S_tart+ u/mod equation 9

For reverse before the switch point, equation 10 is used.

p ═ End- [ (mod-1) × (u/mod) ] -BN% mod equation 10

BN% mod is the bit number modulo the mod value. For example, where mod5, BN% mod is mod5 (bit number).

For reverse after the switch point, equation 11 is used.

p-End-mod × SP/(mod +1) - (u-SP) equation 11

For case 4 (uplink where the spreading factor of the first resource unit is smaller than the second resource unit), the bits are also filled into the resource units with a modulus based on the two resource unit spreading factors. Equation 7 is used to determine the modulus.

Taking fig. 14 as an example, resource unit 2 has a spreading factor of 16 and resource unit 1 has a spreading factor of 4. Thus, the resource unit is filled using a modulo-5 count. Thus, resource unit 1 has bits 0 through 3 and resource unit 2 has bit 4. After resource unit 1 is filled, the remaining bits are sequentially filled into resource unit 2. The point at which resource unit 1 fills up is the switch point. Resource unit 1 is always filled from left to right and resource unit 2 is filled in reverse.

The physical channel mapping engine classifies bits into one of three categories: forward before switch point, reverse before switch point, and reverse after switch point (step 132). The address of a bit is determined based on its class (step 134).

The switch point is derived from the length of the first resource unit in equation 12.

SP ═ mod × first resource unit length/(mod-1) equation 12

After the switching point is determined, it is determined whether the bit is going straight or going backward. For bits prior to the switch point, if there is a remainder of adding one to the bit address and dividing by the modulus, the bit is in the first resource unit. Otherwise it is in the second resource unit. After the switch point is passed, all bits are in the second resource unit.

After the bits are sorted, one of three formulas is used to determine their addresses. For forward before the switch point, equation 13 is used.

p＝S_tart+[(mod-1)×(u/mod)]+ BN% mod equation 13

For reverse before the switch point, equation 14 is used.

p-End-u/mod equation 14

For reverse after the switch point, equation 15 is used.

p-End-SP/(mod +1) - (u-SP) equation 15

Using the equations for these four cases, the physical channel mapping engine 94 determines the resource unit address p for a given address u prior to physical channel mapping.

Although "push" channel mapping is described above in connection with a preferred TDD/CDMA communication system, it can be used in a variety of applications, such as in a UE, base station, or node-B of a TDD/CDMA system.

Another view of physical channel processing is referred to as the "pull" view, as shown in fig. 15. On the transmit side of the "pull" approach, each bit to be input into the physical channel buffer 146 is mapped into one or more bits of the first interleaver buffer 144 (step 136). For example, an address in the physical channel buffer 146 is mapped to an address in the first interleaver buffer 144. After this bit mapping, it is inserted into the physical channel buffer 146 by reading the corresponding location in the first interleaver buffer 144 (step 138). The data from the physical channel buffer 146 is sent to chip rate processing for transmission over the air interface. On the receive side, bits are read from the physical channel buffer 146 and written to the first interleaver buffer 144. Thus, the "pull" view on the receive side is the reverse of the transmit side. In the following, the "pull" point of view is mainly described from the transmission side. The receiving side proceeds in a similar reverse order.

FIG. 16 is a block diagram of one embodiment of a "pull" approach. A pull address generation engine 148 determines the bits to be written to the physical channel buffer 146. One advantage of the "pull" approach is that resource units can be filled on demand, eliminating the need to buffer physical channel data for multiple slots. For example, if only one resource unit is transmitted in the first slot of a frame, the "pull" aspect can selectively "pull" only the bits given to that resource unit. Thus, the pull-out perspective can be used to reduce the physical channel buffering process to only a single timeslot.

The bits in the "pull" approach may be taken first, or in groups, such as 8 bits, 16 bits, or 32 bits. The bits are preferably taken sequentially from the first bit to the last bit of a resource unit, although the bits may be taken in other sequences. The pull address generation engine 148 determines the address at which bits are to be read from the first interleaver buffer 144. The pull address generation engine 148 uses control parameters (which are normalized or signaled) to determine the correct address.

The pull address generation engine 148 sends a control signal to a read/write controller 140. The read/write controller 140 reads a bit from the determined address in the first interleaver buffer 144 and writes the bit to the address of the physical channel buffer 146. All of these operations are controlled by the physical map controller 166, which also uses the control parameters to supervise the physical layer processing operations.

Similar to the "push" approach, the pull address generation engine 148 has four main sub-engines: a rate matching engine 150, a bit scrambling engine 152, a second interleaving engine 154, and a physical channel mapping engine 156.

Likewise, there are three other sub-engines feeding the four main engines: a radio frame segmentation calculation engine 158, a TrCH Multiplexing (MUX) calculation engine 160, and a physical channel segmentation calculation engine 162.

Unlike the "push" approach, the four primary engines 150, 152, 154, 156 operate on the transmit side in the order shown in FIG. 16. Reverse physical channel mapping is first performed. Followed by an inverse second interleaving and then an inverse bit scrambling. And finally, carrying out reverse rate matching.

Physical channel mapping engine 156 performs a reverse physical channel mapping. For each bit address in a resource unit, a corresponding address prior to physical channel mapping is determined.

Physical channel mapping uses different mapping perspectives for four different cases. Physical channel mapping is described in conjunction with fig. 17. In the first case, a timeslot has only one resource unit for use by the CCTrCH. In a second case, more than one resource unit is used in a downlink time slot. In a third case, more than one resource unit is used in the uplink and the spreading factor of the data within the first resource unit is greater than or equal to the spreading factor of the second resource unit. In a fourth case, more than one resource unit is used in the uplink and the spreading factor of the first resource unit is smaller than the spreading factor of the second resource unit.

The physical channel mapping engine 156 determines which case each resource unit bit address applies (step 168). For the first case (a single resource unit in a slot), bits are assigned to the resource units sequentially. Thus, the address p of the bit in the resource unit directly corresponds to the address u before the physical channel mapping (step 170). For the second case (downlink for multiple resource units), the physical channel mapping engine 156 classifies the bits into one of four categories: forward before the switch point, reverse before the switch point, forward after the switch point and reverse after the switch point (step 172). The forward representative positions are filled from left to right, and the reverse representative positions are filled from right to left. The address of a bit is determined based on its classification (step 174).

The switching point of the odd resource units is the length of the shortest resource unit. Taking fig. 18 as an example, the switching point is 228 (the length of the shortest resource unit). For the second plurality of resource units, the switch point is the final bit within the resource unit minus the length of the shortest resource unit. After the switch point is determined, it is determined whether it is forward or reverse based on the resource unit of the bit. The odd plurality of resource units are straightforward and the even plurality of resource units are retrograde.

After the bits are sorted, one of four formulas is used to determine their addresses. For forward before the switch point, equation 16 is used.

u-p × mod + ru% mod equation 16

u is the bit address of the reverse physical channel map. p is the resource unit address. mod is the modulus count before the switch point. ru% mod is the resource unit bit number modulo the mod value.

For reverse before the switch point, equation 17 is used.

u-End-p × mod +1 equation 17

End is the final address within the resource unit.

For forward after the switch point, equation 18 is used.

u＝SP×mod+(p-SP)×(mod_SP) Equation 18

SP is the switching point and modsp is the modulus after the over-switching point.

For reverse after the switch point, equation 19 is used.

u＝SP×mod-(End-SP-p)×(mod_SPEquation 19 for-1) + RU-2

RU is the resource unit number of the bit.

For case 3 (uplink where the spreading factor of the first resource unit is greater than the second resource unit), the bits are filled into the resource units as described above using a modulus based on the two resource unit spreading factors.

Physical channel mapping engine 156 classifies bits into one of three categories: forward before switch point, reverse before switch point, and reverse after switch point (step 176). The address of a bit is determined based on its class (step 178).

Case 3 physical channel mapping uses two switch points: a forward Switching Point (SPF) and a reverse Switching Point (SPR). The forward switching point is the switching point of the first resource unit, which is equal to its length, e.g., 228 in fig. 19. The reverse switch point is the switch point for the second resource unit, which is determined by equation 20.

SPR ═ End- (mod-1) × SPF equation 20

End is the last bit in the resource unit.

After the bits are sorted, one of three formulas is used to determine their addresses. For forward before the switch point, equation 21 is used.

Equation 21 of u-mod × p

For reverse before the switch point, equation 22 is used.

u＝mod×INT[(LP2-ruPOS)/(mod-1)+

MOD (LP2-ruPOS)/(MOD-1) ] +1 equation 22

INT is an integer operator. MOD is the modulo operator. LP2 is the last point within resource unit 2. ruPOS is the bit position number of a bit within a resource unit.

For reverse after the switch point, equation 23 is used.

u-mod + SPF + SPR-p-1 equation 23

For case 4 (uplink where the spreading factor of the first resource unit is smaller than the second resource unit), the bits are also filled into the resource units as described above using a modulus based on the two resource unit spreading factors.

Physical channel mapping engine 156 classifies bits into one of three categories: forward before the switch point, reverse before the switch point, and reverse after the switch point (step 180). The address of a bit is determined based on its class (step 182).

Case 4 physical channel mapping uses only one reverse Switching Point (SPR). The reverse switch point is the switch point for the second resource unit, which is determined by equation 24.

Length of SPR-End-resource unit 1/(mod-1) equation 24

End is the last bit in resource unit 2.

After the bits are sorted, one of three formulas is used to determine their addresses. For forward before the switch point, equation 25 is used.

u-mod × INT [ p/(mod-1) ] + ruPOS% (mod-1) equation 25

ruPOS% (mod-1) is the bit position in the resource unit modulo the value of (mod-1).

For reverse before the switch point, equation 26 is used.

u-mod x (LP2-p) + (mod-1) equation 26

For reverse after the switch point, equation 27 is used.

u-mod x (LP2-SPR +1) + (LP 2-p)% modminisl equation 27

Using the equations for these four cases, the physical channel mapping engine 156 determines the resource unit address p for a particular second interleaver bit address u.

Although "pull" physical channel mapping is described above in connection with a preferred TDD/CDMA communication system, it can be used in a variety of applications, such as in a UE, base station or node-B of a TDD/CDMA system.

The physical channel mapped bits are deinterleaved using a second interleaving engine 154. Initially, the second interleaving engine 154 must know whether the second interleaving is to be performed for an entire CCTrCH or a single time slot of the CCTrCH. This information is signaled from higher layers.

The second interleaving is described in conjunction with fig. 21. The bit specific address p after physical channel mapping is used to determine the address u after reverse second interleaving. The number of bits in each row is determined using the total number of bits in the CCTrCH or CCTrCH time slot and the row offset. Using the address p, the row and column numbers of the bit in the permuted array are determined (step 184). Taking fig. 22 as an example, an address at address p 61 in the physical channel buffer is analyzed. Using the total number of bits and the column offset, it is known that column 0 has five bits and the other columns have four bits. With the known number of bits per row, the row and column numbers (row 12, column 1) of the bit are determined.

Using the known column arrangement, the unbiased column is determined (step 186). In the above example, offset column 12 corresponds to non-offset column 1. The address of the bit is determined using the row and column numbers of the bit in the unbiased array (step 188). In the foregoing example, the address of the bit is address 6.

Although "pull" second interleaving is described above in connection with a preferred TDD/CDMA communication system, it can be used in a variety of applications, such as in a UE, base station or node-B with a TDD/CDMA, FDD/CDMA and TDSCDMA system.

As previously described, in rate matching, bits are punctured and repeated to minimize the number of channels required and to ensure that each channel is fully utilized. The rate matching engine 150 determines the address where each bit of the first interleaver buffer will be after reverse rate matching. Rate matching uses mainly three variables: e-ini, e-plus and e-minus. e-ini is the initial value of e in the rate matching algorithm. e-plus is the increment of e in the rate matching algorithm. e-minus is the decrement of e in the rate matching algorithm.

Rate matching is described in conjunction with the flow diagrams of fig. 23-25. The rate matching engine 150 determines whether the data for a particular channel is non-turbo coded (e.g., convolutional coded) or turbo coded. If the channel is not turbo coded, the bits are processed as a single sequence.

Accelerated coding uses three bits: systematic (S), isotopoly 1(P1) and isotopoly 2 (P2). No puncturing is done to the systematic bits. The rate matching engine 150 treats each of these bit types as a separate string (step 190). The exhaustive requirement for bit separation and bit collection as described in this standard is eliminated by treating the bits as independent strings. This functionality is handled by processing each sequence independently.

Excluding the need to accelerate code puncturing (step 192), the address calculation for the sequence is to perform the puncturing function by equation 28 and the repeating function by equation 29 (step 194).

img id="idf0002" file="C0280829300221.GIF" wi="165" he="49" img-content="drawing" img-format="GIF"/Equation 28

img id="idf0003" file="C0280829300231.GIF" wi="110" he="48" img-content="drawing" img-format="GIF"/Equation 29

u is the address in the first interleaver buffer for the bit difference calculated. p is the bit address before reverse rate matching.

The breakdown of the accelerated code sequence is handled in different ways. Two general approaches can be used to determine the addresses of these bits, as shown in fig. 24 and 25. In a first perspective as shown in fig. 24, the sequences of S, P1 and P2 are processed independently. Thus, a large system of linearly indeterminate equations results. These equations can be solved with specific constraints on the unknown variables (step 198), i.e., the addresses u and p are constrained to integer values. With these constraints, the solution space is narrowed to have only one solution of u for any given p. To do this, the number of punctures before the u address is approximated. A search is performed around the approximation with a sufficient space to determine the effective solution. The valid solution is determined using known constraints on intermediate variables (step 202).

The following is a preferred technique for applying the first aspect. The systematic bit (S) never breaks down. Equation 30 describes the state of the "e" variable at any given address u in the punch-through operation at bit P1.

img id="idf0004" file="C0280829300232.GIF" wi="155" he="20" img-content="drawing" img-format="GIF"/Equation 30

e₁Variable e for P1. Similarly, eini, e1 and e1+ are eini, e of P1, respectively^-And e⁺. u1 is the number of P1 sequence bits before address u is determined. n is₁Is inherent in the P1 sequence₁The number of punctured bits before the current value.

Equation 31 describes the state of the "e" variable at any given address u in the punch-through operation at bit P2.

img id="idf0005" file="C0280829300233.GIF" wi="160" he="19" img-content="drawing" img-format="GIF"/Equation 31

e₂Variable e for P2. Similarly, e2ini, e 2-and e2+ are eini, e of P2, respectively^-And e⁺. u2 is the number of P2 sequence bits before address u is determined. n is₂Is inherent in the P2 sequence₂The number of punctured bits before the current value.

Under a given p condition, equation 32 is used.

u-p＝n₁+n₂Equation 32

Equations 33 and 34 are known to verify true via the rate matching algorithm of this standard.

0＜e₁≤e₁ ⁺Equation 33

0＜e₂≤e₂ ⁺Equation 34

The above linear inequality includes three equations and five unknowns (u, e)₁、e₂、n₁、n₂). Is composed ofimg id="idf0006" file="C0280829300241.GIF" wi="122" he="41" img-content="drawing" img-format="GIF"/Determining the solution of these equations, approximating n₁And n₂The value of (c). A sufficient space around the approximation is searched. The solution is determined based on the limits of equations 33 and 34.

n₁And n₂The approximation of (d) is determined by replacing u in equation 32 with equation 35.

img id="idf0007" file="C0280829300242.GIF" wi="41" he="36" img-content="drawing" img-format="GIF"/Equation 35

Equation 36 results.

img id="idf0008" file="C0280829300243.GIF" wi="124" he="47" img-content="drawing" img-format="GIF"/Equation 36

γ is the breakdown ratio, which is determined by equation 37.

Equation 37

The rate matching parameter decision algorithm derived from this criterion distributes the punctures of the P1 and P2 bits evenly, except when odd punctures are required. When odd number breakdown is required, P1 will have one more bit breakdown. The rate matching algorithm also allows more than two P1 bit punctures within a column without one P2 bit puncture. In addition, no more than two P2 bit punctures can occur with a P1 bit puncture. Thus, equations 38 and 39 result.

n₁-n₂Equation 38 ≦ 3

n₂-n₁Equation 39 ≦ 2

Using equations 38, 39, and 36, equations 40 and 41 result.

img id="idf0009" file="C0280829300244.GIF" wi="235" he="67" img-content="drawing" img-format="GIF"/Equation 40

img id="idf0010" file="C0280829300245.GIF" wi="237" he="68" img-content="drawing" img-format="GIF"/Equation 41

These equations are used to determine a small subspace containing the solution.

To the extent that any p corresponding to a write address u is being determined, the bits at that address are not punctured (otherwise they will not eventually enter the physical channel mapping buffer). Therefore, the value of e must be greater than e-and result in equation 42.

e_x-＜e_x≤e_x+ equation 42

The subscript word x is commonly used because the inequality is true for x either 1 or 2 (for either P1 or P2). Equation 43 is derived using equations 30 and 31.

0＜e_x ⁱⁿⁱ-(u_x+1)e_x ^-+n_xe_x ⁺≤e_x ⁺-e_x ^-Equation 43

Equation 43 is true only if u is a Px bit. If u is not a Px bit, equation 44 applies.

0＜e_x ⁱⁿⁱ-(u_x+1)e_x ^-+n_xe_x ⁺≤e_x ⁺Equation 44

To identify a valid solution, equations 45 and 46 are used.

img id="idf0011" file="C0280829300251.GIF" wi="196" he="24" img-content="drawing" img-format="GIF"/Equation 45

img id="idf0012" file="C0280829300252.GIF" wi="198" he="25" img-content="drawing" img-format="GIF"/Equation 46

A range check is then performed. If u is a P1 bit, equation 47 is used.

img id="idf0013" file="C0280829300253.GIF" wi="124" he="41" img-content="drawing" img-format="GIF"/And isimg id="idf0014" file="C0280829300254.GIF" wi="111" he="45" img-content="drawing" img-format="GIF"/Equation 47

If u is a P2 bit, equation 48 is used.

img id="idf0015" file="C0280829300255.GIF" wi="91" he="42" img-content="drawing" img-format="GIF"/And isimg id="idf0016" file="C0280829300256.GIF" wi="125" he="39" img-content="drawing" img-format="GIF"/Equation 48

If u is an S bit, equation 49 is used.

img id="idf0017" file="C0280829300257.GIF" wi="92" he="42" img-content="drawing" img-format="GIF"/And isimg id="idf0018" file="C0280829300258.GIF" wi="93" he="42" img-content="drawing" img-format="GIF"/Equation 49

The second point of view shown in fig. 25 is as follows. Based on the u position, a rate matching input bit position p is determined. A system ratio is determined (step 204). The system ratio is based on the breakdown ratio of the P1 and P2 sequences. The number of systematic bits Sbits is estimated, for example, by equation 50 (step 206).

img id="idf0019" file="C0280829300259.GIF" wi="194" he="25" img-content="drawing" img-format="GIF"/Equation 50

Is an estimate of the systematic bits. P1_PRBreakdown ratio of P1 sequence and P2_PRIs the breakdown ratio of the P2 sequence.

Four cases are assumed depending on the order of the bits (S, P1, P2 are straight and S, P2, P1 are reverse). S isIs estimated. The case values are shown in Table 1.

TABLE 1

Walking top	Straight S P1P 2			Retrograde S P1P 2
							S	S	S-1	S-1	S	S-1	S-1
S	S	S-1	S	S-1	S
						S		S	S	S	S	S
S+1	S	S	S+1	S	S

P1	S	S	S	S	S	S
							S	S+1	S	S	S+1	S
	S	S+1	S+1	S+1	S+1	S
							S+1	S+1	S+1	S+1	S+1	S+1
	P2	S	S	S	S	S							S
S							S	S+1	S	S	S+1
		S+1	S	S+1	S	S+1						S+1
S+1							S+1	S+1	S+1	S+1	S+1

The correct four columns of table 1 were selected based on the type of bit (top of row) being analyzed. Taking the P2 bit as an example, it selects the last four columns (row top P2). If the bit is a column, then the leftmost column is used. If the bit is retrograde, the rightmost row is used. An output pointer for each row is determined using the appropriate four rows and the appropriate three columns of the row. Using a column at position P2 as an example, four cases (case 1-S, S, S; case 2-S, S, S + 1; case 3-S +1, S, S + 1; case 4-S +1, S +1, S +1) are used.

Four candidate output positions are calculated using these four cases (step 208). The number of punctured bits is determined for each candidate location shown in table 2. Table 2 also lists the calculation of candidate output bit positions.

TABLE 2

P1bits	(e1 ini-Plbits×e1 -)/e1 +
		P2bits	(e2 ini-P2bits×e2 -)/e2 +
Candidate output bit position	Sbits-1+P1bits+P1Pbits-P1Pbit sin I+P2Pbits-P2Pbit sin I

P1_PbitsThe punctured P1 bit number. P2_PbitsThe punctured P2 bit number. P1_{Pbit sin I}The initial P1 bit number. P2_{Pbit sin I}The initial P2 bit number.

The first candidate output bit position that matches the true output bit position exhibits S, P1 and P2 bit numbers. Using this information, the input bit position p is determined (step 210).

Although "pull" rate matching is described above in connection with a preferred TDD/CDMA communication system, it can be used in a variety of applications, such as in a UE, base station or node-B with a TDD/CDMA, FDD/CDMA and TDSCDMA system.

The next step in the process is reverse bit scrambling. The bit scrambling engine determines a bit scrambling address of the address output by the second interleaver.

The reverse bit scrambling procedure is described in conjunction with the flowchart of FIG. 26. Determining a scrambling code p using a bit position k in the CCTrCH_kA corresponding bit (step 400). Bit h_kScrambled, e.g. with p_kThe bit is exclusive-ored (step 402).

Although bit scrambling is performed prior to reverse rate matching, it is preferably performed after reverse rate matching, as shown in FIG. 27 and described in the flow chart of FIG. 28. This embodiment allows all address mapping to be performed prior to any operation of the bit values. The address after reverse second interleaving (before reverse rate matching) is determined for a given bit after reverse rate matching (step 404). Determining p to scramble the bit using the reverse second interleaved address of the given bit_k(step 406). The given bit uses the decided p_kScrambling, e.g. by p_kThe bit is exclusive-ored (step 408).

Although "pull" bit scrambling is described above in connection with a preferred TDD/CDMA communication system, it can be used in a variety of applications, such as in a UE, base station or node-B of a TDD/CDMA system.

Another approach reduces the first interleaver buffering and is referred to as "reduced first interleaver buffering". Fig. 29 is a block diagram of a "reduced first interleaver buffer".

As shown in fig. 29, the output of the first interleaver 212 is not directed to an interleaver buffer. All physical layer buffering is shown in fig. 29 as being performed by a single common memory 220. Transport channel data blocks are provided for one frame or a plurality of frames, and this attribute is expressed in terms of TTI parameters. The TTI can be one of four possible values 10, 20, 40 and 80 milliseconds. A TTI of 10 indicates that the data is for 1 frame, a TTI of 20 indicates that the data is for 2 frames, a TTI of 40 indicates that the data is for 4 frames and 80 indicates that the data is for 8 frames. The data for the first frame of a TTI is sent directly to the physical channel processor 218. Other frames of the TTI are buffered for later processing. Thus, the overall first interleaver buffering is reduced by one frame. For example, if the TTI is 10 ms, this single frame is stored directly in the physical channel buffer and the first interleaving buffer is not needed. For a TTI of 80 milliseconds, there are seven, rather than eight, data frames to store.

The "reduced first interleaver buffering" is preferably applied in the "push" view of the physical layer processing. Thus, while the data is output from the first interleaver 212, it is written to the corresponding address of the physical channel mapping buffer, although other physical layer processing perspectives may be used. If a physical layer processing perspective is used where intermediate buffering is used in physical channel processing (e.g., after rate matching and second interleaving), reduced interleaving buffering can still be used. The data of the first frame is sent directly to the physical layer for processing and storage in an intermediate buffer.

As shown in FIG. 23, all bits of a frame are input into a first MUX 214. The first MUX 214 sends the bits of the first frame to a second MUX 216 for physical channel processing by the set of physical channel processing blocks 218. If the TTI is greater than 10 ms, the bits of the other frame are sent to the memory 220 (first interleaver buffer) via the first MUX 214. After the bits of the first frame have been sent for chip rate processing for transmission over the air interface, the bits of the subsequent frame are fetched from memory 220 via second MUX 216 for physical channel processing. All of these operations are supervised by a physical channel controller 222.

Fig. 30A and 30B depict a "reduced first interleaver buffer" data flow for a transport channel data block group for a 10 ms TTI (one frame). The transport channel data bits are sent directly to the physical channel processor 218 and then to the physical channel buffer for subsequent chip rate processing, without using the first interleaver buffer. As shown in fig. 30A, frame N is delivered directly to physical channel processor 218. As shown in fig. 30B, the next frame (frame N +1) is also directly delivered to the physical channel processor 218.

Fig. 31A and 31B depict a "reduced first interleaver buffer" data flow for a transport channel data block set for an 80 ms TTI. The transport channel data for the first frame (frame N) is sent for physical layer processing and stored in a physical channel buffer (memory 220). The other frames (frames N +1 to N +7) are stored in the physical channel buffer bypassing the physical layer processing. In the next frame shown in fig. 31B, (frame N +1) is delivered to physical layer processing and stored in the physical channel buffer. The other frames (frames N +2 to N +7) are processed sequentially in a similar manner during the next six frames. The chip rate processor reads the data bits of a frame one frame after the current frame from the physical channel buffer. For example, if the physical layer processor is processing (frame N +1), then the chip rate processor is reading frame N. The data processing view for TTIs of 20 and 40 milliseconds is the same as the 80 millisecond view previously described. The only difference is the number of frames buffered before the physical channel is buffered.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are illustrative only, and that various changes and modifications may be made therein without departing from the invention in its broader aspects and, therefore, the present invention is not to be considered as limited thereto, as modifications and variations of the above described embodiments are intended to fall within the scope of the appended claims, which fall within the true spirit and scope of the invention.

Claims (21)

1. A physical layer processing method for a wireless communication system, the method comprising:

providing a first interleaver buffer having bits stored at a first interleaver address;

determining a physical channel address of the bit corresponding to the bit address after rate matching, bit scrambling, second interleaving and physical channel mapping using the first interleaver address; and

wherein determining the physical channel address comprises determining a rate matching address corresponding to the bit and bit address after rate matching using the first interleaver address;

determining a second interleaving address corresponding to the bit and the bit address after second interleaving by using the rate matching address; and

after the physical channel mapping, determining the physical channel address corresponding to the bit and the bit address;

reading the bits directly from the first interleaver buffer and writing the bits to a physical channel buffer using the determined physical channel address; and

the bits in the physical channel buffer are transmitted over an air interface.

2. A physical layer processing method for a wireless communication system, the method comprising:

providing a physical channel buffer capable of storing bits at physical channel addresses;

determining a first interleaver address of the bit corresponding to the bit address after reverse physical channel mapping, reverse second interleaving, reverse bit scrambling and reverse rate matching by using the physical channel address; and

for the address of the physical channel buffer, reading a bit directly from the determined first interleaver address of the first interleaver buffer and writing the bit into the address of the physical channel buffer.

3. The method of claim 2 wherein determining the first interleaving address comprises:

determining an inverse physical channel mapping address corresponding to an address in the physical channel buffer;

determining an inverse second interleaving address corresponding to the determined inverse physical channel mapping address; and

an inverse rate matching address corresponding to the determined inverse second interleaved address is determined.

4. A physical layer processing method for a wireless communication system, the method comprising:

first interleaving bits received in a time transmission interval having bits for a plurality of frames; and

performing physical channel processing on a first interleaved bit of a first frame of the plurality of frames before buffering the first interleaved bit of the first frame, the physical channel processing including rate matching; and

frames other than the first frame are buffered after the first interleaving and before physical channel processing.

5. The method of claim 4 wherein performing physical channel processing further comprises bit scrambling, second interleaving, and physical channel mapping.

6. The method of claim 4, wherein no buffering is performed during physical channel processing.

7. The method of claim 5, wherein no buffering is performed during physical channel processing.

8. A user equipment for physical layer processing, the user equipment comprising:

means for first interleaving a plurality of bits received in a time transmission interval having a plurality of bits for a plurality of frames;

means for performing physical channel processing, including rate matching, on a first interleaved plurality of bits of a first frame of the plurality of frames prior to buffering the first interleaved bits of the first frame; and

means for buffering frames other than the first frame after the first interleaving and before physical channel processing.

9. The user equipment of claim 8 wherein the means for performing physical channel processing further comprises bit scrambling, second interleaving, and physical channel mapping.

10. The user equipment of claim 8 wherein no buffering is performed during physical channel processing.

11. The user equipment of claim 9 wherein no buffering is performed during physical channel processing.

12. A user equipment for physical layer processing, comprising:

a first interleaver for first interleaving bits received during a time transmission interval having bits for at least one frame;

a first multiplexer for directing a first interleaved bit of a first frame to a second multiplexer and directing first interleaved bits of frames other than the first frame to a memory;

a second multiplexer for outputting bits selected from bits of the first frame and bits of other frames stored in the memory for physical channel processing; and

a physical channel processing block for performing physical channel processing on the outputted selected bits.

13. The user equipment of claim 12 wherein the physical channel processing block performs rate matching, bit scrambling, second interleaving and physical channel mapping.

14. The user equipment of claim 12 wherein the physical channel processing block generates an output, the output being stored in the memory.

15. A base station for physical layer processing, the base station comprising:

means for first interleaving bits received in a time transmission interval having bits for a plurality of frames; and

means for performing physical channel processing, including rate matching, on a first interleaved bit of a first frame of the plurality of frames prior to buffering the first interleaved bit of the first frame; and

means for buffering frames other than the first frame after the first interleaving and before physical channel processing.

16. The base station of claim 15 wherein the means for performing physical channel processing further comprises bit scrambling, second interleaving, and physical channel mapping.

17. The base station of claim 15 wherein no buffering is performed during physical channel processing.

18. The base station of claim 16 wherein no buffering is performed during physical channel processing.

19. A base station for physical layer processing, the base station comprising:

a first interleaver for first interleaving bits received during a time transmission interval having bits for at least one frame;

a first multiplexer for directing a first interleaved bit of a first frame to a second multiplexer and directing first interleaved bits of frames other than the first frame to a memory;

a second multiplexer for outputting bits selected from bits of the first frame and bits of other frames stored in the memory for physical channel processing; and

a physical channel processing block for performing physical channel processing on the outputted selected bits.

20. The base station of claim 19 wherein the physical channel processing block performs rate matching, bit scrambling, second interleaving, and physical channel mapping.

21. The base station of claim 19 wherein the physical channel processing block generates an output, the output being stored in memory.