HK1063230B - Memory system, buffering device and method operating a memory system - Google Patents

Description

Memory system, buffer device and method for operating the same

Technical Field

The present invention relates generally to memory systems that utilize buffer structures to isolate memory controllers from memory devices, and more particularly to systems and methods for providing reliable transfer of information, such as data, status, commands, and addresses, in a buffered memory system. The memory device may be, for example, a Dynamic Random Access Memory (DRAM) device.

Background

A conventional memory system includes a memory controller and a memory device, such as a DRAM, connected thereto. In some systems, a processor performs the function of a memory controller. As used herein, the term memory controller includes such processors. The memory controller and the memory device are coupled together using a memory interface. The memory interface provides communication between the memory controller and the memory devices. The memory interface may contain an address bus, instruction signal lines, and a data bus. The increasing demand for higher computer performance and capacity has resulted in the need for larger and faster memories. However, as operating speeds and the number of memory modules connected to a chipset increase, the resulting increased capacitive loading may substantially limit the size and speed of the memory.

A drawback of a memory device directly connected to the memory bus is that there is no voltage level isolation between the memory device and the memory controller and no capacitive load isolation between the memory bus and the memory device. Thus, each element is required to operate with the same interface voltage and frequency. Thus, the memory controller is manufactured to operate with a particular memory device that satisfies these parameters. In contrast, memory devices can only be used with memory controllers having the same interface voltage and operating frequency. Thus, memory devices used with memory controllers are limited to those devices having the same interface voltage and operating frequency as the memory controller.

Moreover, as the frequency of signals transmitted through the memory increases, the inherent delay between the external, system or reference clock and the timing data available to the memory controller or memory device becomes a critical limitation. When the memory controller expects data from the memory device, the time data that is valid for the memory controller is important. When the memory device expects data from the memory controller, time data that is valid for the memory device is important. The delay may be large enough for the next clock cycle to overlap with the data. That is, the delay becomes large enough during one cycle to make the data for the memory controller or memory device not ready, and this essentially becomes "out of sync".

In other storage systems, solutions have been proposed to address the "out of sync" issue. The registered double ("registered DIMM") systems in prior art designs such as line memory modules access this challenge by utilizing independent phase locked loop chips. The input clock to the registered DIMM module enters the independent chip, and the output of the independent chip is used to drive registers in the registered DIMM system. However, the memory controller and memory devices in a registered DIMM system are limited to have the same interface voltage and operating frequency. The need for specially designed memory devices to match the cost of registering the memory controller in a DIMM system and vice versa incurs significant development costs and limits the interchangeability of various existing memory components.

Disclosure of Invention

Therefore, in response to the above-described problems in the prior art, there is a need to provide a system and method for a memory system that not only provides reliable transmission and reduces clock-insertion and propagation delays, but also does not require that each element operate with the same interface voltage and frequency.

According to an aspect of the present invention, there is provided a storage system including: at least one memory device storing data; a memory controller to send information to and receive data from the at least one memory device; a first buffer interconnecting the at least one memory device and the memory controller; and a clock circuit embedded in the first buffer, wherein the clock circuit receives an input clock and outputs a first output clock to the at least one memory device to control clock skew to the at least one memory device.

According to another aspect of the present invention, there is provided a storage system including; at least one memory device storing data; a memory controller that transmits data, address information, and command information to the at least one memory device and receives data from the at least one memory device; at least one data buffer interconnecting the at least one memory device and the memory controller; an address and command buffer (addr/cmd buffer) interconnecting the at least one memory device and the memory controller; and a clock circuit embedded in the address and instruction buffers, wherein the clock circuit receives an input clock and outputs an output clock to the at least one data buffer to control clock skew to the at least one data buffer.

According to yet another aspect of the present invention, there is provided a buffer device interconnecting a memory controller and a memory device, comprising: at least one data buffer; address and command buffers to facilitate transfer of command information and address information from the memory controller to the memory devices; and clock circuitry embedded in the address and instruction buffers, wherein the clock circuitry receives an input clock and provides an output clock to the at least one data buffer to control clock skew to the at least one data buffer.

According to yet another aspect of the present invention, there is provided a method of operating a memory system including a memory controller, a memory device, a data buffer, and an address/instruction buffer, the method comprising: transferring data from the memory controller to the memory device through the data buffer or from the memory device to the memory controller through the data buffer; transferring address information and command information from the memory controller to the memory device through the address/command buffer; receiving an input clock in an address/instruction buffer; generating a first output clock in an address/instruction buffer based on an input clock; a first output clock is provided from the address/instruction buffer to the data buffer.

The present invention is based on the use of high speed, low cost buffers to isolate the memory devices from the memory controller. Data and instruction/address clocking is performed by using clock circuits embedded in buffers, preferably in address and instruction buffers. This clocking scheme allows data and instructions/addresses to be reliably transferred across the buffer. The advantage of this clocking scheme is that the clock skew to the data buffer and/or memory device is precisely controlled; while providing the ability to operate the memory system at high frequencies.

Drawings

FIG. 1 shows a schematic diagram of a cache memory system according to an embodiment of the invention;

FIG. 2 shows a schematic example of a cache system in which embodiments of the present invention may perform their functions;

FIG. 3 shows a buffer structure including an embedded clock circuit according to an embodiment of the invention;

FIG. 4 shows a schematic example of a phase-locked loop of an embedded clock circuit according to an embodiment of the invention;

FIG. 5 illustrates a cache memory system according to an embodiment of the present invention; and

fig. 6 shows a program for operating a memory system according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention relate to systems and methods for providing reliable transfer of information, such as data, status, instructions, and addresses, in a buffered memory system. FIG. 1 shows a schematic diagram of a cache memory system according to an embodiment of the invention. Buffered memory system 100 includes memory controller 110, buffer 120, embedded clock circuit 300, and memory device 130 and 145. The buffer 120 is an external buffer or register having a function of reducing the impedance detected by the memory controller 110. Memory controller 110 is coupled to buffer 120 and buffer 120 is coupled to memory device 130 and 145, such as a DRAM device. By placing buffer 120 between memory controller 110 and memory devices 130 and 145, the transfer of data and information between memory controller 110 and memory devices 130 and 145 is facilitated. The electrical characteristics of the memory system 100 are also improved and allow for wider tuning. Although the connecting lines are shown as single lines to buffer 120 and to memory devices 130 and 145, each of the illustrative lines may actually be multiple lines. Memory controller 110 may be, for example, a chipset central processing unit and may be adapted to transmit various information, such as data, status information, address information, command information, to memory device 130 via buffer 120 and 145. Memory controller 110 is also adapted to receive data from memory device 130 and 145 via buffer 120.

In this example, buffer 120 includes a plurality of dedicated buffers or registers: a data buffer 123 for buffering data and an address and command buffer 122 for buffering address information and command information transferred from memory controller 110 and/or status information transferred from memory device 130 and 145. Within ADDR/CMD buffer 122, clock circuit 300 is embedded. ADDR/CMD buffer 122 receives an input clock or strobe (strobe) applied to embedded clock circuit 300. The embedded clock circuit 300 provides an output clock to the data buffers 123, 124. An embedded clock circuit 300 is employed to provide reliable transmission in a buffered memory system. In particular, the timing of data buffers 123, 124 is synchronized with the timing of ADDR/CMD buffer 122. The combination of placing buffer 120 between memory controller 110 and memory device 130 and 145 and embedding clock circuit 300 in ADDR/CMD buffer 122 may further improve the electrical characteristics of memory system 10 while providing reliable transfer.

FIG. 2 shows a schematic example of a cache system in which embodiments of the present invention may perform functions. In this example, memory controller 110 is located on motherboard 200. Memory devices 130, 145, 170, 185 are located on memory modules 150, 155. The memory modules 150, 155 are connected to the motherboard 200 by connectors 160, 165. Storage device 130 and 145 are located on first storage module 150 and storage device 170 and 185 are located on second storage module 155. In other embodiments, the configuration of memory devices 130, 170, 185 on memory modules 150, 155 may be different, and memory controller 110 may control more or fewer memory devices than those shown in FIG. 2.

In this example, buffers 120 and 125 are located on memory modules 150 and 155, respectively, and generate buffer modules in which clock circuits are embedded to provide reliable transmission in the buffered memory system. However, buffers 120, 125 and the individual components of buffers 120, 125, such as data buffers 123, 124 and ADDR/CMD buffer 122, are not limited to the arrangement shown in FIG. 2. That is, they are not limited to being provided on the memory module. Buffering of data and instructions/addresses may also be performed on the motherboard device 200 or on an external (stand-alone) buffer. In one embodiment, external (independent) buffers are employed to allow different voltages and frequencies to be used for memory controller 110 and memory devices 130, 145, 170, 185.

By embedding a clock circuit in ADDR/CMD buffer 122 and controlling the clock skew (skew) to data buffers 123, 124, data buffers 123, 124 and ADDR/CMD buffer 122 in a buffered memory system can be accurately clocked without introducing errors due to propagation delays. Fig. 3 shows a buffer structure including an embedded clock circuit 300 according to an embodiment of the present invention. The buffer structure interconnects the memory controller and the memory devices. In this example, the buffer structure includes two data buffers 123, 124 and an ADDR/CMD buffer 122. In other embodiments, the buffer structure may include more or fewer data buffers and/or ADDR/CMD buffers. Among other components, data buffers 123, 124 are employed to facilitate the transfer of data between the memory controller and the memory devices. Among other things, the use of ADDR/CMD buffer 122 facilitates the transfer of command information and address information from the memory controller to the memory devices. Embedded in ADDR/CMD buffer 122 is embedded clock circuit 300. Input clock 10 is applied to ADDR/CMD buffer 122. The input clock 10 is driven by the memory controller 110 or by an external source. The clock driven by the memory controller 110 or an external source may be, for example, the base clock for a computer containing a buffered memory system or the base clock for the memory controller 110. In clock circuit 200, clock skew, which is typically caused in source synchronous systems by clock signals arriving at data buffers 123, 124 and ADDR/CMD buffers at different times, is eliminated. After the clock skew is eliminated, the output clock 20 is output from the clock circuit 300. The clock circuit 300 controls the output clock 20 to have the same phase as the input clock 10. The clock circuit 300 is also coupled to a clock driver 310, and the clock driver 310 drives the output clock 20 to the data buffers 123, 124. Thus, the data buffers 123, 124 and the ADDR/CMD buffer 122 are clocked by clock signals having the same phase relationship (clocking), allowing the memory device to successfully receive the required signals within one clock command.

Various methods may be employed to implement clock circuit 300. For example, a first exemplary method utilizes a Delay Locked Loop (DLL). A second exemplary method utilizes a Phase Locked Loop (PLL). A third exemplary method utilizes a delay chain. DLLs are well known in the art. The DLL in ADDR/CMD buffer 122 basically receives input clock 10 and offsets (i.e., time delays) the input clock 10 in ADDR/CMD buffer 122. The time delayed clock, i.e. the output clock 20, is fed to the data buffers 123, 124 as their input clock. This allows the data buffers 123, 124 to synchronize with the ADDR/CMD buffer 122. The data and command and address information are retimed and the memory device receives all the information in a clock command. The general architecture of a DLL may include the following components: a phase detector composed of a D-type flip-flop, a cross-coupled NAND gate forming an RS flip-flop, an AND gate, AND a fixed delay circuit; a digital delay line comprising a series of identical delay elements; each delay element has a left/right shift register of one stage; internal clock input and output buffers. In operation, a DLL introduces more or fewer delay line elements in a delay line (connected in series) to control the timing of the output signal.

According to embodiments of the present invention, a DLL is employed in the clock circuit 300 to control clock skew to the data buffers 123, 124 and reduce clock-insertion and propagation delays. The DLL has an input signal and a feedback output signal. The DLL compares the delay between the two signals and digitally sets the delay chain to synchronize the two signals. The delay chain has a large number of stages, and each stage may introduce, for example, a ten picosecond delay. The phase difference between the output signal and the input signal is continuously detected and adjusted to maintain the proper delay. In this example, the input signal to the DLL is the input clock 10 and the output signal of the DLL is the output clock 20. The DLL employs an input clock 10, which provides clocking to the ADDR/CMD buffer 122 and controls the phase of the output clock 20 generated from the input clock 20. The DLL thus controls the relative phase relationship of the output clock 20 and the input clock 10. In one embodiment, the DLL artificially adds sufficient delay to the input signal of the DLL, i.e., input clock 10, such that the phase of the output signal of the DLL, i.e., output clock 20, is 360 degrees behind the input signal of the DLL. In this way, the output clock 20 is in reverse (back) alignment with the input clock 10. The output clock 20 is driven out to the data buffers 123, 124 and serves as an input clock for the data buffers 123, 124. As a result, the clocks detected by the data buffers 123, 124 have exactly the same phase relationship as the clocks into the ADDR/CMD buffer 122. Without a DLL, clock-insertion and propagation delays may be added to the clock signal as it passes through the ADDR/CMD buffer 122, shifting the phase of the output clock.

According to another embodiment of the invention, the clock circuit 300 is implemented using a PLL for synchronization. A PLL is a closed-loop frequency control system based on phase-sensitive detection of the phase difference between the input signal to the PLL and the output signal of a voltage controlled oscillator in the feedback loop of the PLL. The PLL provides clock circuit 300 with the ability to precisely control clock skew to the data buffer and reduce clock insertion and propagation delays. FIG. 4 shows a schematic example of a phase-locked loop of an embedded clock circuit according to an embodiment of the invention. The PLL includes a phase comparator 400, a low pass filter 410, an amplifier 420, and a Voltage Controlled Oscillator (VCO) 430. VCO430 is in a feedback loop. The PLL receives an input signal and provides an output signal. In this example, the input signal is the input clock 10 and the output signal is the output clock 20. The phase comparator 400 compares the phase of the input clock 10 with the output phase of the VCO 430. If the two phases are different, the phase comparator 400 generates a phase error signal which, after being low-pass filtered by the low-pass filter 400 and amplified by the amplifier 420, is used to drive the VCO frequency in the input frequency direction. When the PLL is "locked on," the frequency and phase of the output signal are the same as the frequency and phase of the input signal. If the phase of the input signal changes, the phase of the output signal follows.

VCO430 may be, for example, a ring oscillator type or a multivibrator type. The phase comparator may be, for example, a set of balanced buffers and highly balanced D-type flip-flops. The advantage of using a PLL compared to a DLL is that the PLL is more accurate. Unlike the 10 or 50 picosecond incremental delays that occur when using a DLL, a PLL has better accuracy. However, in digital systems such as memories, PLLs with analog characteristics may introduce analog design complexity in the main digital design. A PLL is a larger and more complex circuit than a DLL, but it provides finer control to clock circuit 300.

In another embodiment, instead of having a DLL or PLL in the embedded clock circuit, a delay chain is used to introduce the delay in the same way as a DLL or PLL. Delay chains are well known in the art. In one embodiment, the delay is a compensation delay. The delay chain includes a number of delay elements, each having a fixed time period. The delay may be adjusted by adjusting the number of delay elements within the circuit, depending on the conditions of the buffer memory system. The conditions of the buffer storage system that have an effect on the propagation of the signal are continuously monitored and the delay is adjusted accordingly.

FIG. 5 illustrates a buffer memory according to another embodiment of the present invention in which an ADDR/CMD buffer is used to drive clocks to memory devices. In this example, a buffer structure including data buffers 123, 124 and an ADDR/CMD buffer 122 and a memory device such as a DRAM are mounted in the memory module 150. The memory controller is adapted to transfer information, such as data, status information, address information and command information, to the memory devices 1-8 via the buffer structure. The memory controller is adapted to receive data from the memory devices 1-8 via the buffer structure. Within ADDR/CMD buffer 122, clock circuit 300 and clock driver 310 are embedded therein. The input clock or strobe enters ADDR/CMD buffer 122 and passes through embedded clock circuit 300. The embedded clock circuit 300 then outputs an output clock to the data buffers 123, 124 and the memory devices 1-8. An embedded clock circuit 300 is implemented to provide reliable transfers, such as synchronizing the timing of data buffers 123, 124 and memory devices 1-8 with the timing of ADDR/CMD buffer 122.

In this example, not only does clock driver 310 drive output clock 20 from clock circuit 300 to data buffers 123, 124, clock driver 310 also drives output clock 20 to memory devices 1-8. Clock driver 310 is preferably made up of several output clock drivers. In effect, the clock circuit buffers the clock entering the module and provides multiple copies of the clock to the memory devices 1-8, thereby improving the timing accuracy to the memory devices 1-8. Clock circuit 300 may be implemented using, for example, a PLL, DLL or delay chain. In the case of a PLL, the memory devices 1-8 are provided with buffered PLL control clocks, thereby providing timing integrity and avoiding clock insertion delays. Alternatively, an alternative clocking scheme may be provided in which the clock circuit 300 sets different delays for the clock entering the memory devices 1-8 and the clock entering the data buffers 123, 124. For example, the clock experienced by the memory devices 1-8 may be set 100 picoseconds later than the clock experienced by the data buffers 123, 124. This provides the memory devices 1-8 with more mounting time of 100 picoseconds.

Fig. 6 shows a program for operating a memory system according to an embodiment of the present invention. The memory system includes a memory controller, a data buffer, an ADDR/CMD buffer, an embedded clock circuit, and a memory device. In block P600, data is transferred from the memory controller to the memory device through the data buffer. In other embodiments, data is transferred from the memory device to the memory controller through a data buffer. In block P610, address information and command information are transferred from the memory controller to the memory device through the ADDR/CMD buffer. In block P620, the ADDR/CMD buffer receives an input clock. On the basis of the input clock, the ADDR/CMD buffer generates an output clock in block P630. In block P640, the ADDR/CMD buffer provides the output clock to the data buffer as the input clock to the data buffer. In other embodiments of the present invention, the process extension includes an ADDR/CMD buffer to further provide an output clock to the memory device.

The present invention is based on the use of high speed, low cost buffers to isolate the memory devices from the memory controller. The above-described embodiments and methods of the present invention allow for data and instruction/address clocking to be performed using clock circuits embedded in the buffers, preferably in the address and instruction buffers. This clocking scheme allows data and instructions/addresses to be reliably transferred across the buffer. The advantage of this clocking scheme is that the clock skew to the data buffer and/or memory device is accurately controlled. This in turn provides the ability to operate the memory system at high frequencies. In addition to improving timing accuracy and maintaining timing integrity, additional cost and module space are saved by embedding clock circuits in address and instruction buffers 122. A PLL or DLL that meets the system requirements is integrated in the embedded clock circuit. No external PLL or DLL is required to drive the clock to the memory device.

The foregoing description relates to particular embodiments of the present invention, and it will be understood that many modifications may be made without departing from the spirit thereof. For example, clock circuit 300 may be placed in a data buffer and operate independently. It is intended that the appended claims cover such modifications as fall within the spirit and scope of the invention. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (25)

1. A storage system, comprising:

at least one memory device storing data;

a memory controller to send information to and receive data from the at least one memory device;

a first buffer interconnecting the at least one memory device and the memory controller; and

a clock circuit embedded in the first buffer, wherein the clock circuit receives an input clock and outputs a first output clock to the at least one memory device to control clock skew to the at least one memory device.

2. The memory system of claim 1, further comprising a second buffer interconnecting the at least one memory device and the memory controller, wherein the clock circuit outputs a second output clock to the second buffer to control clock skew to the second buffer.

3. The memory system of claim 2, wherein the first output clock to the at least one memory device and the second output clock to the second buffer are the same in frequency and phase.

4. The memory system of claim 1, wherein the clock circuit comprises a Delay Locked Loop (DLL).

5. The memory system of claim 1, wherein the clock circuit comprises a phase-locked loop (PLL).

6. The memory system of claim 1, wherein the clock circuit comprises a delay chain.

7. A storage system, comprising;

at least one memory device storing data;

a memory controller that transmits data, address information, and command information to the at least one memory device and receives data from the at least one memory device;

at least one data buffer interconnecting the at least one memory device and the memory controller;

an address and command buffer (addr/cmd buffer) interconnecting the at least one memory device and the memory controller; and

a clock circuit embedded in the address and instruction buffers, wherein the clock circuit receives an input clock and outputs an output clock to the at least one data buffer to control clock skew to the at least one data buffer.

8. The memory system of claim 7, wherein the embedded clock circuit comprises a Delay Locked Loop (DLL).

9. The memory system of claim 7, wherein the embedded clock circuit comprises a phase-locked loop (PLL).

10. The memory system of claim 7, wherein the embedded clock circuit comprises a delay chain.

11. The memory system of claim 7, wherein said at least one memory device is a dynamic random access memory.

12. The memory system of claim 7, wherein the at least one memory device and the buffer are packaged in a memory module.

13. The memory system of claim 7, wherein the buffer is located on a motherboard of the computer system, the at least one memory device being mounted within the memory module.

14. A buffer device interconnecting a memory controller and a memory device, comprising:

at least one data buffer;

address and command buffers to facilitate transfer of command information and address information from the memory controller to the memory devices; and

clock circuitry embedded in the address and instruction buffers, wherein the clock circuitry receives an input clock and provides an output clock to the at least one data buffer to control clock skew to the at least one data buffer.

15. The buffer device of claim 14, wherein the clock circuit further provides an output clock to the memory device to control clock skew to the memory device.

16. A buffer device according to claim 14, further comprising a clock driver for driving an output clock to said at least one data buffer.

17. The buffer device of claim 14, wherein the clock circuit comprises a Delay Locked Loop (DLL).

18. The buffer device of claim 14, wherein the clock circuit comprises a phase-locked loop (PLL).

19. The buffer device of claim 14, wherein the clock circuit comprises a delay chain.

20. A method of operating a memory system, the memory system including a memory controller, a memory device, a data buffer, and an address/instruction buffer, the method comprising:

transferring data from the memory controller to the memory device through the data buffer or from the memory device to the memory controller through the data buffer;

transferring address information and command information from the memory controller to the memory device through the address/command buffer;

receiving an input clock in an address/instruction buffer;

generating a first output clock in an address/instruction buffer based on an input clock;

a first output clock is provided from the address/instruction buffer to the data buffer.

21. The method of claim 20, further comprising:

generating a second output clock in the address/instruction buffer based on the input clock;

the generated second output clock is output from the address/command buffer to the memory device.

22. The method of claim 21, wherein the first output clock and the second output clock are the same in frequency and phase.

23. The method of claim 20, wherein the first output clock is generated by a Delay Locked Loop (DLL) embedded in one of the at least one data buffer and the address/instruction buffer.

24. The method of claim 20, wherein the first output clock is generated by a Phase Locked Loop (PLL) embedded in one of the at least one data buffer and the address/instruction buffer.

25. The method of claim 20, wherein the first output clock is generated by a delay chain embedded in one of the at least one data buffer and the address/instruction buffer.