HK1063130B - Sequential burst mode activation circuit - Google Patents

Description

Sequential burst mode activation circuit

Technical Field

The invention relates to a sequential burst mode activation circuit. More particularly, the present invention provides a circuit topology to improve performance stability during activation and brightness variations of multiple loads. The invention has general utility where multiple loads are used for varying the intensity. Also, the invention has particular utility where multiple fluorescent lamps, particularly multiple Cold Cathode Fluorescent Lamps (CCFLs), are used, for example, in televisions and computer screens, and in the backlighting of Liquid Crystal Displays (LCDs).

Background

Brightness enhancing and dimming circuits and techniques for lighting or dimming or changing the brightness of a lamp are known. Methods for dimming fluorescent lamps, particularly backlights for Liquid Crystal Displays (LCDs), are known as voltage-controlled dimming systems. The voltage controlled dimming system includes current control and current feedback control. According to the voltage-controlled dimming system, dimming is achieved by varying the input voltage to the inverter in order to adjust the output voltage from the inverter (i.e., the voltage applied to the fluorescent tube). Since the fluorescent lamp emits light using discharge energy, when a voltage applied to the fluorescent lamp is too low, the discharge becomes unstable. For this reason, a large dimming range cannot be obtained by voltage-controlled dimming systems, and the possible dimming ratio, which is an indication of the dimming range of the lighting system, is only around 2: 1.

Another technique for dimming fluorescent lamps is "burst mode" dimming systems, in which a variable width notch (notch) is used to cut off the alternating signal to the lamp power in order to reduce the power applied to the lamp and thereby provide the desired dimming. The narrower the (temporal) width of the ac power supplied to the lamp, the lower the brightness emitted by the lamp. A common device that provides the function of varying the pulse width is a commercially available pulse width modulator ("PWM").

In burst mode dimming, dimming is achieved by periodically flashing the light source with a variable time ratio between the on time and the off time. Thus, this system provides a large dimming ratio, perhaps greater than 100: 1, in contrast to the voltage-controlled dimming approach described above, thereby allowing for large brightness variations.

U.S. patent No. 5,844,540 provides a lighting/dimming circuit for a backlight control function in a Liquid Crystal Display (LCD). A PWM dimmer drive circuit adjusts the amount of current to be supplied to the fluorescent lamp on the back side of the liquid crystal display panel via a current transformer. One goal of such circuits is to avoid brightness instability or flicker between the backlight or fluorescent tube and the LCD, and another goal is to reduce noise. The PWM and inverter circuits regulate the light source driver to enable the light source to periodically flash the light source with a variable time ratio between the on and off times, thereby producing different average light levels. The turn-on time is determined by a "pulse counting circuit" which provides an input to the PWM circuit; the pulse counting circuit counts the number of pulses of a horizontal synchronization signal of an LCD display screen and provides a light-on time which allows a light-emitting signal of a backlight to be synchronized with a light-emitting signal of the LCD. Furthermore, the light and dark frequencies of the light source are a frequency division of the horizontal driving frequency of the horizontal synchronization signal of the LCD panel. Thereby making the LCD display and the backlight in phase with each other. This topology provides a "burst mode" dimming system, but only for a single fluorescent lamp. It is also proposed to synchronize the backlight with the LCD to avoid light instabilities between the LCD and the backlight. It is noted that various fluorescent lamps, particularly cold cathode fluorescent lamps, are in a high impedance state at the time of initial power-up. If multiple Cold Cathode Fluorescent Lamps (CCFLs) are used, current ripple will result when all lamps are synchronized to one light source; these current ripples will hamper the performance of the converter and will cause flicker. This is because when multiple CCFLs are synchronized, the power supply needs to provide sufficient power to illuminate all of the CCFLs simultaneously. Due to the limited dynamic response, the instantaneous power supplied from the power supply may cause the supply voltage to drop. Thus, using PWM signals, i.e., "burst mode" dimming, is not practical in itself to provide a solution for flicker/noise for multi-lamp configurations.

One technique for compensating for flicker or noise in the burst mode dimming of multiple CCFLs is to use a capacitor in series with the power supply to absorb the power surge that causes current ripple. One disadvantage of this technique is that when the light is extinguished in each burst mode cycle, the power supply line with its inherent inductance will continue to carry current, thereby charging the capacitor, resulting in an increase in the output voltage.

The prior art technique of activating multiple loads when the loads are not fluorescent lamps does not address the problem of flicker and noise arising from the simultaneous illumination of multiple lamps.

Disclosure of Invention

Accordingly, the present invention solves the problems of the prior art by providing a sequential burst mode activation circuit for a plurality of loads by generating a phase shift between a plurality of burst mode signals. These burst mode signals are used to regulate power to the loads, where each load is regulated by a separate phase shifted burst signal so that at least two loads are not turned on simultaneously. The circuit of the present invention is superior to prior art regulation circuits by eliminating the instantaneous large current ripple and noise that are generated by multiple loads turning on simultaneously.

The invention provides a phased load regulation system comprising a phase delay array adapted to generate a plurality of phase shifted burst mode signals, wherein each of said phase shifted burst mode signals regulates power to a corresponding load.

The invention also provides a computer system comprising a liquid crystal display panel, a plurality of cold cathode fluorescent lamps for illuminating said liquid crystal display panel, and a lamp driving system comprising a phase delay array adapted to generate a plurality of phase shifted burst mode signals, wherein each of said phase shifted burst mode signals adjusts the power to each of said plurality of cold cathode fluorescent lamps.

The present invention also provides a liquid crystal display panel comprising a plurality of cold cathode fluorescent lamps for illuminating said liquid crystal display panel, and a lamp driving system comprising a phase delay array adapted to generate a plurality of phase shifted burst mode signals, wherein each of said phase shifted burst mode signals adjusts the power to each of said plurality of cold cathode fluorescent lamps.

In an exemplary embodiment, a plurality of phased burst signals are used to regulate power to a plurality of loads. In addition, a constant or variable phase delay is created between each phased burst. In one exemplary system, the present invention provides a sequential burst mode dimming circuit for a plurality of lamps. In particular, the exemplary system provides a sequential burst mode dimming circuit for a plurality of cold cathode fluorescent screen lamps (CCFLs). The user or software input changes the pulse width of the PWM signal, thereby determining the power being delivered to each lamp. The reference signal is multiplied to select the frequency of the PWM signal. This selected frequency determines the frequency at which the lamps are lit and extinguished. Using one counter and one clock, a plurality of phased burst signals can be generated from the above burst signals for a plurality of CCFLs. Each phased burst is shifted by a constant phase so that at least two lamps receive bursts of different phases. Thus, a sequential burst mode activation of each lamp is achieved. Finally, in the exemplary system, a plurality of phased array drivers, each of which uses feedback from a respective lamp in conjunction with a respective phased burst signal, provide power to and adjust the brightness of a respective plurality of lamps.

Another exemplary system of the present invention includes a frequency selector that generates a frequency selection signal for a backlight load that follows a conventional screen refresh frequency of a Cathode Ray Tube (CRT) in a television set as a reference. In yet another exemplary system, a phased delay array generates a plurality of phased bursts such that no two phased bursts have different start times. In one example of such an embodiment, a phased delay array produces a constant or variable phase delay such that each phased burst signal is delayed by such a phase delay relative to another phased burst signal.

Those skilled in the art will appreciate that although the following detailed description will proceed with reference being made to exemplary systems and methods of use, the present invention is not intended to be limited to these exemplary systems and methods of use. The present invention is of broad scope and is limited only as set forth in the following claims.

Other features and advantages of the present invention will become more apparent as the detailed description proceeds, and upon reference to the drawings, wherein like numerals depict like parts, and in which:

drawings

FIG. 1 is a top-level block diagram of an exemplary sequential burst mode signal generation system of the present invention;

FIG. 2 is a more detailed block diagram of an exemplary sequential burst mode signal generation system of the present invention;

FIG. 3 is a signal representation of a pulse width modulator of an exemplary sequential burst mode signal generation system of the present invention;

FIG. 4 is a signal representation of a phase delay array of an exemplary sequential burst mode signal generation system of the present invention;

FIGS. 5(a) and 5(b) are two tables showing the relationship between the "select" signals input to the circuit and the resulting load numbers;

FIG. 6 provides a summary of the various signals discussed in connection with FIGS. 1 through 5;

FIG. 7 is an exemplary IC implementation of the sequential burst mode signal generation system of the present invention;

FIG. 8 is a top level diagram of the phased array driver of the present invention;

FIG. 9 is an example circuit showing how a phased array driver generates power adjust signals in the present invention;

FIG. 9a is a signal diagram of load current;

FIG. 10 is a timing diagram illustrating how a phased array driver generates power adjust signals in accordance with the present invention;

FIG. 11 is a power adjustment signal generated by an exemplary phased array driver of the present invention;

FIG. 12 is an exemplary IC implementation of a phased array driver IC in the present invention;

FIG. 13 is an example circuit showing how a phased array driver generates a voltage clamp signal in an exemplary IC of the present invention;

14(a) and 14(b) provide examples of circuits for half-bridge and full-bridge (H-bridge) topologies, respectively;

fig. 15 provides an example of signal generation showing the generation of cross-switch signals in a full-bridge topology.

Detailed description of the specific embodiments

The following description will refer to a burst mode regulating circuit for a plurality of Cold Cathode Fluorescent Lamps (CCFLs). For example, CCFLs are deployed in large displays. Typically, each of the large CCFL displays uses at least 6 lamps, and the invention will describe a burst mode activation circuit with 6 or more CCFLs. Of course, the present invention is not limited to a minimum number of loads, nor to CCFLs or any particular type of load.

Fig. 1 is a top-level block diagram of an exemplary sequential burst mode signal generation system 10 of the present invention. In overview, the sequential burst mode signal generation system 10 operates to generate a phase shifted burst mode signal 50. And sends these burst mode signals to driver 100 to provide time delayed power regulation to plurality of loads 18. "burst mode," as used herein and understood in the art, generally refers to the use of a Pulse Width Modulation (PWM) signal to modulate the power being delivered to a load based on the pulse width of the PWM signal. System 10 generally includes a modulator 12 for generating a set of pulse modulated signals 36; a frequency selector 14 which generates a frequency selection signal 40 for setting a frequency of the pulse modulation signal; and a phase delay array 16 to generate a plurality of phase shifted burst signals 50, thereby replacing the need for a single high power input along with a plurality of suitably low power inputs; the system 10 of the present invention solves the above-described problems of conventional multiple load power regulation circuits.

Fig. 2 is a more detailed block diagram of the system 10 of the present invention. Pulse modulator 12 generates a Pulse Width Modulated (PWM) signal 36 having a pulse width L whose duty cycle (i.e., pulse width) determines the power delivered to load 18. The frequency selector 14 selects the frequency of the PWM signal 36 based on an independent reference signal 38 of period T. In an exemplary embodiment, the frequency selector 14 includes a frequency multiplier to multiply the frequency of the reference signal 38 (with period T) k times and generate a multiplied signal 40 (with period T/k) for the following reasons, wherein the multiplied signal 40 is used to set the frequency of the PWM signal 36. For example, where system 10 is used to regulate multiple CCFLs, a synchronization signal, or Vsync, may be used as reference signal 38. In the example where a CCFL is used for a television, video, or LCD screen, Vsync38 is an active video signal that is used to refresh the display on the screen. The use of Vsync is desirable because a "beat" may occur if an arbitrary reference signal is selected that is independent of the screen refresh frequency. As is well understood by those skilled in the art, the "beat frequency" manifests itself in the following manner. On a television monitor, video display is provided by a Cathode Ray Tube (CRT). After the completion of the transfer of one frame of display, the CRT returns to the initial position and further transfers the next frame of display. The display screen is refreshed at a frequency specified by Vsync. During the time between the completion of the transmission of one display frame and the start of the next display frame, there is no information being broadcast and the television screen remains dark. During this time, if light is introduced, the transition of the CRT back to its starting position may appear as a visible line superimposed with different display content. Referred to in the industry as "beat frequency". If the burst-mode adjustment of each lamp does not follow the frequency of Vsync, there will be an introduction of light during the above time, thereby causing the appearance of a beat frequency. Also, since the screen refresh frequency is multiplied if the frequency of one CCFL is equal to the screen refresh frequency rather than an integer multiple thereof, the brightness of the concurrent light may cause flicker. Therefore, for the above exemplary application, Vsync is the required reference signal.

In the exemplary embodiment, reference signal Vsync38 is multiplied to produce a multiplied signal 40, it being noted that each burst signal 50 will contain a different pulse when the period T/k (k being the number of multiples of signal Vsync 38) of multiplied signal 40 is greater than L of signal 36, that is, when the period T of signal Vsync38 is greater than k L. If the period T is equal to or less than k x L, each burst signal 50 will be a high (level) dc signal (i.e., each burst signal 50 will represent a full power setting). As will be discussed further below. In the example of fig. 2, the frequency selector 14 multiplies the independent reference signal Vsync38 by 2 (i.e., k is 2), thereby generating a frequency selection signal 40 having a period T/2. Both signals 36 and 40 are input to the phased delay array 16 to generate a plurality of phased burst signals 50, as discussed below.

The phase delay array 16 includes a phase delay generator 52 for phasing the burst signals 50 in successive phases₁，50₂，…，50_nDetermining a phase delay value D; the load selection circuit is used for determining the number n of the load; and a circuit 54. For generating a plurality of phase-delayed pulse width modulated signals 50_n. Each of these components will be described in detail below.

Referring briefly to fig. 5(a) and 5(b), depicted are tables of "select" signals input to the select circuit 58. These inputs are used to quantify the number of loads 18 connected to the circuit 10 of the present invention. Note that n also quantizes the number of phased bursts 50. In an exemplary embodiment, selection circuit 58 operates as a state machine to generate the appropriate signals based on the binary values of the "select" signal that have been input and directed to phase delay generator 52. Fig. 5(a) shows the generation of a "select" signal for an exemplary embodiment, where at least 6 CCFLs are used. This table includes two inputs: sel 0 and Sel 1, each produce a binary value representing the CCFL number. In this table, 6 CCFLs are represented by Sel 0 ═ 0 and Sel 1 ═ 0. More CCFLs (added in increments of 2) are also defined in this table. The table of fig. 5(b) generalizes the example of fig. 5(a) above to include less than the minimum number 6 and more than the maximum number 12 CCFLs. In general, more select signal inputs 58 allow a greater number (i.e., a greater value of n) of loads 18 to be used. In this example, an additional input signal is provided: sel 2, which allows additional load to be defined. In the example of using CCFLs as the load, an odd number of lamps need to be defined in the circuit for the following reasons. Of course, those skilled in the art will recognize that the tables of fig. 5(a) and 5(b) and the selection circuit 58 may be adapted to define any number of loads.

Fig. 3 provides a signal representation of the pulse width modulator 12. The pulse width modulator 12 generates a set of pulse width modulated signals 36 whose pulse widths L are set by the variable selector 24. The variable selector 24 is provided to provide variable power to (i.e., dim) the load by varying the pulse width L of the PWM signal. The variable selector 24 varies the value of the dc signal 30 proportional to the desired dimming setting. In an exemplary embodiment, the variable selector 24 includes a dimming selector 26 and a polarity selector 28. The dimmer selector 26 determines the desired dimmer setting by increasing or decreasing the dc signal 30. The polarity selector 28 will be discussed further below. The oscillator 22 generates a set of triangular waveforms 34 of predetermined frequency as inputs to the pulse width modulator 12. The dc signal 30 is superimposed on a triangular waveform 34. In the exemplary embodiment shown in fig. 3, the segment defined by the intersection of the dc voltage 30 and the rising edge 25a and falling edge 25b of each triangular waveform determines the rising edge and falling edge of each pulse, and thus the pulse width L of the pulse width modulated signal 36. In this embodiment, a larger value of the dc signal 30 will result in a smaller pulse width L, and a smaller value of the dc signal 30 will result in a larger pulse width L. In an alternative embodiment, the segment defined by each falling edge 25b and the next rising edge 25c is used to generate the pulse width L. In this alternative embodiment, a larger value of the dc signal 30 will result in a larger pulse width L, and a smaller value of the dc signal 30 will result in a smaller pulse width L. The polarity selector 28 determines which segment of the intersection of the dc signal 30 and the triangular waveform 34 is used to generate the pulse width L. The pulse width modulator 12 thus generates the pulse width L of the PWM signal 36 as determined by the user selection 24.

Fig. 4 is a detailed block diagram and signal representation of the phased delay array 16. The phase delay array 16 generates a phase delay value D and produces phased burst signals 50 as a function of L, T/2 and number n). The phase delay array 16 receives as inputs the clock signal 15, the PWM signal 36 having a pulse width L, the select signal input 58, and the multiplied reference signal 40 (i.e., having a period of T/2). Most preferably, the value of D is determined such that the phase shift between each phasing burst 50 is constant, i.e., D is constant. Also, the phase delay D is used to phase the burst signal 50 at the last (nth) phase_nAnd the 1 st phased burst signal 50₁Repeating itself in between. Here, it is assumed that there are n phased bursts 50, wherein each phased burst p preferably precedes the next pulse p +1 by a phase shift D. To accommodate this, in a preferred embodiment, the phase delay D is equal to (T/2)/n, where T is the period of the reference signal Vsync38, T/2 is the period of the signal 40, n is the number of the phasing bursts 50, and the frequency of each phasing burst 50 is equal to the frequency of the signal 40. Those skilled in the art will recognize that the present invention may alternatively include a variable phase delay such that the value of the phase delay is not constant, but still some or all of the loads 18 are turned on at different times. Such alternative embodiments are also included within the scope of the present invention.

In an exemplary embodiment, circuit 54 includes a counter 56 having a clock input 15 to generate n phased burst signals 50 that provide the inputs. In particular, counter 56 may be implemented with a series of flip-flops, wherein one pulse triggers the 1 st phased burst 50 at time t₁While a clock pulse triggers the 2 nd phased burst signal 50 at time t + D₂1 st pulse p. Similarly, the clock pulse triggers the 3 rd phased burst 50 at time t +2D₃1 st pulse of (1), and oneThe clock pulse triggers the nth phased burst 50 at time t + (n-1) × D_n1 st pulse of (2). The clock pulse then triggers the 1 st phased burst 50 at time t + (n) × D₁The 2 nd pulse of (1). Since each signal has a period of T/2, where T is the period of the independent signal Vsync38, it follows [ (T + nD) -T]Equal to T/2. In other words, n × D equals T/2, or D equals (T/2)/n.

Furthermore, each phased burst signal 50 has a pulse width L. To accommodate this, the mth phased burst signal 50 is generated by sampling the clock signal starting from clock signal t + (m-1) D within a time interval determined by a variable pulse width_mWherein m is more than or equal to 1 and less than or equal to n. Subsequent phased bursts 50 are also processed as such. Thus, the 1 st pulse of the 1 st phased burst 50 may be generated from clock pulses t, t +1, t +2, …, t + (L-1) such that L clock pulse counts constitute the pulse width L of each phased burst pulse p. As previously mentioned, L must be less than T/2 in order to produce a different pulse for each phased burst 50. That is, if L is not less than T/2, each phasing burst 50 will be a dc signal with no distinguishable pulses.

Fig. 6 summarizes the various signals discussed with respect to one exemplary embodiment from fig. 1-5. Signal 34 is a triangular waveform generated by oscillator 22 (fig. 3). The dc signal 30 is superimposed on the signal 34 and moved up and down, i.e. increased or decreased, to produce the desired dimming (effect). The intersection of the signal 34 with the dc signal 30 determines the rising and falling edges of each pulse of the pwm signal 36, and thus the pulse width L of each pulse of the pwm signal 36. Signal 36 follows the frequency of signal 34. The pulse width L of signal 36 is used to generate phased burst signals 50 (i.e., 50)₁To 50_n) And the frequency of signal 36 is not. The frequency of the phasing burst signal 50 depends on the independent reference signal Vsync38 with a period T. Vsync38 is multiplied to produce a signal 40 having a period of T/2 (i.e., a frequency of 2/T). The number of phased bursts 50 depends on the intended useThe input of the number of the load of (2). In this example, 6 loads are used. Thus, 6 sets of phased burst signals 50 are shown. In which each set of phased bursts, e.g. 50₂Comparing the preceding set of phased bursts, e.g. 50₁Lags by (T/2)/6-T/12.

Fig. 7 is an exemplary Integrated Circuit (IC)60 implementation of the sequential burst mode signal generation system of the present invention. IC 60 includes a PWM generator 12, Vsync and phase shift detector 13, frequency multiplier 14, and a phase delay array 16. The components 12, 14 and 16 have been described above with reference to fig. 1-5. Exemplary IC 60 also includes a clock 15; an oscillator 22 for generating a triangular waveform 34; buffers 19 for increasing the current driving capability of the phased burst signals; and an undervoltage lockout protection circuit 2.

The PWM generator 12 receives as inputs the DIM, polarity, LCT and clock (100kHz generator) signals. The PWM generator 12 generates the PWM signal 36 as described above. Also, as described above, the pulse width of the PWM signal generated by generator 12 is selected using DIM and polarity inputs. The LCT of exemplary IC 60 is the input to oscillator 22 which generates the aforementioned triangular waveform having a predetermined frequency. The clock 15 is used to measure the time increment so that variable pulse widths can be counted.

Vsync detector and phase shift detector 13 receives Vsync38, Sel 1, Sel 2, and clock 15 as inputs. Vsync38 is an independent reference signal as discussed previously. The Vsync detector and phase-shift detector 13 detects the presence of the independent reference signal Vsync38, and calculates a phase delay value D as described above. In the exemplary IC, if Vsync is not detected, detector 13 uses the frequency of oscillator 22 to generate reference signal 38. When detector 13 detects Vsync signal 38, detector 13 discards the frequency of oscillator 22 and uses the frequency of Vsync for signal 38. The detector 13 outputs the phase delay value D and an independent reference signal Vsync 38. Signal Vsync38 is fed to multiplier 14 along with clock 15, where the frequency of Vsync is multiplied to produce a burst frequency.

In the exemplary IC, the inputs to the phase delay array 16 include the PWM signal 36 from the PWM generator 12, a burst frequency value from the frequency multiplier 14, and a clock 15. As described above, the phase delay array 16 utilizes a counter to generate a plurality of phase delayed bursts, wherein each phased burst operates to regulate power to the load 18. Each phased burst signal is driven through a buffer 19 to increase its current drive capability, and then through a respective phased array driver 100, as discussed further below.

The protection circuit 2 is used to sense the voltage level of the power supply (Vcc). When Vcc indicated by pin 26 of fig. 6 increases from low to high, the protection circuit 2 resets the entire IC so that the IC is functionally in an initial state. When Vcc becomes low, the protection circuit 2 turns off the IC so as not to possibly damage the IC.

Fig. 8 is a top-level diagram of an exemplary phased array driver 100. In one exemplary configuration, each phased array driver, driver 1, driver 2, …, driver n/2, receives as inputs two phased burst signals and outputs power to two respective loads. The power regulation for each load is independent of the power regulation for the other loads. Thus, various alternative configurations allow each phased array driver 100 to adjust any number of loads, the total of which may be greater or less than the number shown in the figure. In an exemplary system, each phased array driver 100 receives two phased burst signals 50 that are 180 ° out of phase with each other and generates two power adjust signals that are 180 ° out of phase with each other. The phased array driver 100 converts each variable pulse width L into a time interval during which the respective load is on during each cycle. Thus, the longer the pulse width of the phased burst signals, the greater the power to the respective load in each cycle. Likewise, each load is switched on or off at a burst frequency defined by the respective phased burst signal 50. In the exemplary system, since driver 100 receives complementary signals, the number of phasing bursts 50 is odd in this embodiment.

Fig. 9 provides an exemplary circuit 200 illustrating the generation of load current control signal ICMP in phased array driver 100. Fig. 10 is a timing diagram accompanying fig. 9. In the discussion that follows, fig. 9 and 10 are considered concurrently. See also fig. 1-5.

Circuit 200 includes an error amplifier 120 for generating a current control signal ICMP, a sense resistor Rsense 138 in series with load 18, a switch 134 connecting circuit 200 to phase delay array 16, and a feedback capacitor CFB 139. In addition, the exemplary circuit 200 includes an RC low pass filter 136 to filter out noise and uses the transformer 160 to apply the current control signal ICMP to the load 18, as discussed further below.

In general, in both modes of operation, circuit 200 receives a feedback signal VIFB and generates a current control signal ICMP. The first mode is soft start and the 2 nd mode is burst mode. In the soft start mode, the load 18 is gradually powered from a power-off state to an on-state on-stream state for a warm-up period using an external soft start controller (not shown). The soft start controller will be discussed further below. In burst mode, the duty cycle of the above-described phased burst signal 50(PWM) is used to regulate the load current IL in the on-state of operation of the load 18. That is, in one exemplary embodiment, IL will be proportional to [ L/(T/K) ]. times ILmax, where L is the pulse width of signal 50, T/K is the period of signal 50, and ILmax is the load current when fully powered. Thus, load 18 will dim in burst mode. As will be discussed further below. Note that the soft start mode precedes the burst mode in sequence. In burst mode, but not in soft start mode, the current control signal ICMP regulates the load current IL. During soft start, the ICMP is monitored to determine when to transition from soft start mode to burst mode. This will be further explained below.

In both modes, the error amplifier 120 compares the feedback signal VIFB with the reference signal ADJ and generates the control signal ICMP. In an exemplary embodiment, the error amplifier 120 is a negative feedback operational amplifier. ADJ is a predetermined constant reference voltage representing the operating current of load 18. As will be discussed further below. By changing the ICMP, VIFB is increased or decreased until it equals ADJ. That is, if VIFB is less than ADJ, the error amplifier 120 increases ICMP. Conversely, if VIFB is greater than ADJ, error amplifier 120 decrements ICMP. If VIFB is ADJ, ICMP is a constant to maintain VIFB at ADJ. The operation of the exemplary circuit 200 in the soft start mode and in the burst mode will be discussed in greater detail in order below.

As described above, in the soft start mode, the load 18 is powered from an off state to an on state in operation. The circuit 200 generates the control signal ICMP in dependence on the load current IL, but not in dependence on the respective phased burst signal PWM 50. That is, in the soft start mode, the circuit 200 is disconnected from the phase delay array 16 by the switch 134. As will be discussed further below. The discussion below is with reference to ILrms and ILrms (spec). Ilmms refers to the root mean square value of the load current IL at any instant. Ilrms (spec), as used herein, is the manufacturer's load specification when the load 18 is operating at full power.

In the soft-start mode, the feedback signal VIFB is a function of the load current IL. IL is typically a sinusoidal waveform. According to ohm's law, VIFB is proportional to Rsense IL. VIFB is approximately equal to 0.45 Rsense ILmax and can be derived as follows.

In the formula, T_LPeriod of sine wave, t₁And T + T_LDefining the start and end of a cycle of the sine wave, respectively, and ILpeak is the peak load current. Diode 137 removes the negative half cycle of IL, thereby producing waveform IL (+), an example of which is given in fig. 9a by signal 400, which depicts a half-wave rectified waveform to the load. In the condition where the phased burst signal PWM 50 is disconnected from the circuit 200, the VIFB is actually the voltage across the resistor Rsense. That is to say that the first and second electrodes,

due to the fact thatTherefore, it is not only easy to use

The invention is not limited to this method of determining the feedback VIFB. In an exemplary embodiment, the constant reference voltage ADJ is equal to 0.45 irrms (spec) Rsense in both soft start and burst modes, where ilrms (spec) is a constant generally defined by the operating specification of the load as described above. Thus, when the load 18 is in a full power state, i.e., in a conducting state according to operating specifications, VIFB will be equal to ADJ. Since load 18 is turned on from the off state, IL is effectively 0 at the beginning of the soft start mode. Thus, VIFB is also actually 0, i.e., less than ADJ. Therefore, ICMP is high. As the soft start controller (not shown) increases IL, VIFB increases, thereby decreasing the difference between VIFB and ADJ. As a result, ICMP is reduced. When VIFB ADJ, as described above, the load 18 is in an operationally on state and the ICMP carries energy to regulate the operating current of the load 18. Thus, the warm-up phase defined by the soft start mode is declared to be over when the energy provided by the soft start controller (not shown) has increased to match the energy provided by the ICMP. At this point, the soft start controller (not shown) stops control and the load current is regulated by ICMP. The burst mode is started.

In burst mode, circuit 200 generates control signal ICMP based on both load current IL and PWM signal 50. Thus, VIFB no longer uniquely follows the equation VIFB ═ (0.45) × (Rsense) ilmms. Instead, the above equation supplements a factor determined by the presence of the PWM signal 50. Thus, in burst mode, the ICMP will follow PWM signal 50 and drive load 18, as will be further described below.

In burst mode, switch 134 connects circuit 200 to phase delay array 16. In an exemplary embodiment, the switch 134 is a PNP transistor 134 having a reference power supply REF at its source (or emitter) and a respective phased burst signal (PWM)50 at its gate (or base). The reference power supply REF may be derived, for example, from the power supply Vcc (not shown) of the exemplary IC via a voltage divider circuit (not shown). When triggered by PWM 50, switch 134 connects its drain (or collector) to REF at its source, sending a signal PWM _52 to circuit 200. In the preferred embodiment, switch 134 is triggered by a low signal at its gate, so PWM _52 is complementary to PWM 50. In an exemplary embodiment, when the PWM 50 is high, the transistor 134 is off and the PWM _52 is isolated from the PNP 134; that is, no burst mode information is sent to the circuit 200, and the VIFB follows the equation 0.45 irrms Rsense. When PWM 50 is low, transistor 134 is on and PWM _52 is high. The Rlimit 135 converts the PWM _52 current to a voltage. This voltage is superimposed to VIFB. Rlimit is selected such that the voltage added to VIFB affects ICMP, changing the load current from an on-state to an off-state on operation. As will be discussed further below.

As described above, the PWM signal 50 is introduced and PWM _52 is generated. When PWM 50 goes low, PWM _52 goes good, so VIFB exceeds ADJ. To lower and match the VIFB to the ADJ, the ICMP must be brought low. Since the ICMP drives the load 18, the load 18 is effectively turned off. Those skilled in the art will recognize that turning off load 18 does not require a current or voltage at load 18 of 0, but that when it is turned off, a very small current or voltage may still be provided to load 18. When PWM 50 goes high, PWM _52 is disconnected from reference voltage REF. In this exemplary embodiment, VIFB returns to the equation VIFB 0.45 ilmms Rsense. Since the load is effectively turned off, ILrms is approximately 0. The ICMP goes high to establish a VIFB similar to ADJ. Thus, the load current IL becomes high and the load 18 is turned on. As can be seen from fig. 10, the result is that the load current IL follows the respective phasing burst PWM 50. However, the load current IL likewise lags behind the respective burst signal PWM 50.

Fig. 11 shows oscilloscope signal readouts of PWM _52, ICMP and load current IL during burst mode operation of an exemplary system of the present invention. PWM _52 is timed by the respective phased burst signal PWM determination 50; that is, there is no significant delay between the transition of PWM 50 from low to high or high to low and the transition of PWM _52 from low to high or high to low. Since the error amplifier has limited charge and discharge currents, it takes time to charge or discharge the CFB 139 when the VIFB goes above or below ADJ, respectively. Thus, as seen in FIG. 11, ICMP lags PWM _ 52. In burst mode operation, load current IL also similarly lags PWM _52 since ICMP drives load 18.

Fig. 12 provides an exemplary IC implementation 300 of phased array driver 100. The IC300 consists of a break-before-make line 130 with a half-bridge switching topology. As will be discussed further below. In alternative IC implementations, switching topologies such as "full bridge," "forward," or "push-pull" may be used without departing from the scope of the invention. With continued reference to fig. 9, certain operational aspects of the IC300 are explained. The exemplary IC300 receives two phased burst signals (PWM signals) 50 that are 180 ° out of phase, and the exemplary IC300 uses the two phased burst signals to drive a load whose two signals are 180 ° out of phase. Thus, those skilled in the art will recognize that certain components (e.g., selectors 122, 124, 126) present in pairs are used to drive two separate loads. Of course, the IC300 is only an example, and it can be easily configured as a circuit that drives 3 or more loads (or a single load). The selectors 122, 124, 126, which may be composed of general purpose comparison circuitry and/or application specific circuitry to accomplish detection of signals, are described below.

The exemplary IC300 is comprised of an error amplifier 121 for voltage sensing, an error amplifier 120 for current sensing, a current or voltage feedback selector 122, a burst mode or soft start mode selector 124, and a minimum voltage selector 126. The selectors 122, 124, 126 may have the same structure, consisting of one comparator and two pass gates, or may be implemented with multiplexers.

As described above, each error amplifier 120 generates a current control signal ICMP (shown at pin 4 of exemplary IC 300) by comparing ADJ to feedback VIFB (shown at pin 3 of exemplary IC 300). VIFB is determined by the load current IL in the soft start mode and by both the phasing burst signals PWM 50 and IL in the burst mode.

Similarly, fig. 13 provides an exemplary circuit 350 that represents the error amplifier 121 by comparing a reference voltage (e.g., 2V) to a voltage feedback signal VFB that is determined by the load voltage. To generate a voltage control signal VCMP (at pin 5 of the exemplary IC 300). In an exemplary embodiment, when the load begins to power up, the voltage applied to the load (now referred to as SST) by the soft start controller (at input 132) is low. That is, the load voltage V on the secondary side of the transformer 160_xIs very low. Thus, VFB is also low. Because the difference between VFB and the reference signal (e.g., 2V) is much larger than the comparison threshold, the error amplifier 121 generates a high VCMP signal. The relationship between VFB and load voltage will be discussed below. As SST increases, VFB also increases and approaches the reference voltage (e.g., 2V), and VCMP decreases. When VFB matches the reference voltage (e.g., 2V), VCMP is selected to drive the load voltage instead of SST, effectively clamping the load voltage to a predetermined value, thereby matching VFB to the reference voltage (e.g., 2V). Circuit 360 illustrates VFB and actual load voltage V_x(in the exemplary circuit 350, provided by the secondary side of the transformer 160):

VFB＝V_x*C1/(C1+C2)

therefore, C1 and C2 are selected such that voltage feedback signal VFB reflects load voltage V_xA specific factor of (a). For example, if C2 ═ C1000C 1, then VFB ═ V_x/1000, i.e., VFB is the load voltage V_xIs a load voltage V_xOne thousandth of (a). In this example, if the reference voltage is 2V, the load voltage will be clamped at 2000V. In addition, diode 365 produces a half-wave rectified voltage signal similar to the half-wave rectification of diode 137 (FIG. 9). Ry and Cy are peak voltage detectors for detecting the peak voltage of the rectified waveform.

The current or voltage feedback selector 122(I _ or V _ feedback) selects the voltage control signal VCMP or the current control signal ICMP as the load driving signal in the burst mode. In the exemplary IC300, the selector 122 selects VCMP when the load current is less than the run current (e.g., VIFB < ADJ) and the load voltage exceeds the predetermined value mentioned above. Otherwise, the selector 122 selects ICMP. Selector 122 determines the selection of the control signal by an alternative comparison, for example, selector 122 may be configured to compare ADJ and VIFB to determine whether the load has reached operating power or a predetermined full load power. The following discussion is with reference to control signals CMP, which may be ICMP as discussed above, or VCMP.

In the exemplary IC300, the selector 122 is connected to a burst mode OR soft start mode selector 124(CMP _ OR _ SST). The selector 124 in the exemplary IC300 determines one of the above-mentioned soft start and burst modes and transitions from the soft start mode to the burst mode when appropriate (as described below). Selector 124 determines which mode to apply and generates signal CMPR by comparing CMP and SST (the load power control energy generated by the soft start controller). The CMPR may be a soft start signal in a soft start mode or may be a control signal in a burst mode. As described above, once load 18 reaches the on-state of operation, the system jumps to burst mode. Therefore, before SST equals CMP, CMPR is SST; once SST reaches or exceeds CMP, CMPR is CMP. A soft start controller providing a soft Start Signal (SST) may be implemented with an external capacitor (not shown) connected between pins 13, 132, the rate at which this capacitor is charged determining the rate at which the load is powered up. In this example, the SST voltage Is equal to Is/(C T), where Is the current provided by the power supply 133 and C Is the capacitance of an external capacitor (not shown). The rate of increase of the load current IL in the soft-start mode can be changed by changing the capacitance of an external capacitor (not shown). After the CMP is matched to SST, the soft start mode ends and burst mode begins, with the CMP adjusting the load power in burst mode, but SST continues to increase to Vcc.

In the exemplary IC300, the selector 124 is connected to a minimum voltage selector CMPP _ or _ MIN 126. The output of the selector is called RESCOMP. The further selector 126 ensures that a predetermined minimum power is supplied to the load even when the load is in the off state. That is, when the power supplied to the load is less than a predetermined minimum value, RESCOMP is a minimum voltage, e.g., 740 mV. And when the load voltage is above a predetermined minimum voltage, RESCOMP is CMPR (i.e., CMP or SST as described above).

Thus, in burst mode, a predetermined minimum voltage will appear across the load whenever the PWM 50 goes low or the load is off as described above. The satisfaction of maintaining a minimum voltage across the load will be described with reference to a Cold Cathode Fluorescent Lamp (CCFL) as an exemplary load.

A CCFL that is off has a high impedance and therefore only a high voltage will cause current to flow through the CCFL to ignite the lamp. In the exemplary IC300, a high voltage is applied to the CCFL from the secondary side of the transformer 160 to cause it to illuminate. Once current passes through the CCFL, its impedance decreases and, ultimately, the voltage decreases to an operational level. The lamp is ignited without repeatedly applying a high voltage while maintaining a predetermined minimum voltage across the load.

When the selector 126 selects a predetermined minimum voltage, the sawtooth generator 128 acts as a Pulse Width Modulator (PWM) to generate a PWM signal whose pulse width determines the power delivered to the load. The function of the sawtooth generator 128 is comparable to the function of the pulse width modulator 12 described in figure 3. Likewise, the dc voltage used by the sawtooth generator 128 to generate the PWM signal is the predetermined minimum voltage. The predetermined minimum voltage, when intersected by the triangular wave signal 34 discussed in fig. 3, produces a PWM pulse width that is a minimum value suitable for maintaining the signal. In effect, the sawtooth generator 128 charges the load slowly at turn-off, effectively with a predetermined minimum voltage selected by the selector 126, during each burst cycle. The power signal determined by the above-mentioned burst signal PWM 50 will be enabled when the load voltage exceeds a predetermined minimum value.

Break-before-make circuit 130 turns transformer 160 on or off using appropriate signals as described above, it being noted that any suitable switch may be used herein. The exemplary IC300 has two switches for a half-bridge topology, i.e., as a general DC/AC converter, the outputs NDRI, PORI of the break-before-make circuit 130 turn on or off the NMOSFET and the PMOSFEF, respectively, thereby switching the transformer 160 to GND or VCC, respectively. Notably, the break-before-make circuit ensures that only one of the NMOSFETs and PMOSFETs is turned on. That is, the NMOSFET and PMOSFET generate a pair of non-overlapping signals. Specifically, in a full-bridge (H-bridge) topology, 4 switches are used to switch the transformer 160 to either GND or Vcc. This switch converts the direct current voltage (Vcc) to an alternating current signal that is sent to the primary side of the transformer, as is well known in the industry.

Fig. 14(a) and 14(b) are conventional DC/AC converter topologies using half-bridge and full-bridge switching schemes, respectively. Shown in fig. 14(a) is the half-bridge topology in an exemplary IC300 as described above. An alternative embodiment uses a full-bridge (H-bridge) topology as shown in fig. 14 (b). The full-bridge topology typically uses two NMOSFET and PMOSFET pairs to generate two pairs of non-overlapping signals. This will be explained below with reference to fig. 15. The switching on and off of the transformer 160 can be controlled by changing the conduction conditions of the crossbar pairs a and d (ad), B and d (bd). The break-before-make circuit 130 ensures that AD and BC are not turned on at the same time.

Fig. 15 provides an example of signal generation showing how cross-over switching signals are generated in a full-bridge topology of an exemplary embodiment of the present invention. As shown in fig. 3, oscillator 22 generates a triangular wave signal 34. The signal 34 is inverted to produce 34'. RESCOMP is the output of selector 126, that is, RESCOMP may be any one of ICMP, VCMP, SST, or MIN (e.g., 740 mV). Therefore, RESCOMP is variable. The reference signal CLK is used to independently control switches a and B. In an exemplary embodiment, CLK has a 50% space ratio and follows signal 34. The 2 nd reference signal PS _ CLK is used to independently switch switches C and D. In this exemplary embodiment, PS _ CLK is a delay D that is adjustable_CLKThe CLK signal whose phase is determined. RESCOMP determination of D_CLKThis will be discussed below. The positive and negative edges of each PSCLK pulse are generated by the intersection of the rising edge of signal 34 and RESCOMP and the rising edge of signal 34' and RESCOMP, respectively. Thus, when RESCOMP increases, for example, in burst mode, when the respective phased burst signal 50 rises, the phase delay D between CLK and PS _ CLK is_CLKAnd also increases. The on-time of each switch pair AD and BC is determined by the overlap of CLK and PS _ CLK. Therefore, when D_CLKWhen increased, the on-time of AD and BC also increases, causing more power to be directed to the respective loads. It is noted, however, that the present invention is not limited to any particular driver configuration and, thus, is not limited to half-bridge or full-bridge topologies.

Returning to IC300 of fig. 12, in this exemplary embodiment, when the supply voltage of transformer 160 exceeds the supply voltage of IC300, break-before-make IC300 will use a "high voltage level shift" mechanism. The following example will explain the "high voltage level shift" mechanism. The Vcc voltage is 5V, i.e., the gate control signal level of the PMOSFET changes from GND (0V) to Vcc (5V). If the transformer 160 is applied with a 15V voltage, the break-before-make circuit 130 will provide a 10V DC voltage offset to the PDRI output, thereby allowing the gate control signal voltage of the PMOSFET to reach 15V (10V plus 5V Vcc via DC voltage level offset).

Exemplary IC300 also includes a protection circuit 140, and circuit 140 is an under voltage lockout circuit (UVLO). At the end of the soft start mode, if the voltage delivered to transformer 160 has not dropped, or if load current IL has not reached the illustrated full load operating level, then line 140 will shut down IC 300. Generally, in burst mode operation, when maximum power is applied to the load, if VIFB is below ADJ, circuit 140 can sense the load current and turn off IC 300. It is noted that when VIFB is below ADJ, error amplifier 120 will increase the power to the load, and therefore circuit 140 turns off the IC under the conditions described above to prevent excessive power from being supplied and damaging the components. Also, the protection circuit 140 will not function when performing the soft start described above.

It is apparent that the present invention provides a sequential burst mode adjustment circuit that can meet the stated objectives. Those skilled in the art will recognize that many modifications may be made thereto, and all such modifications are within the spirit and scope of the present invention, which is limited only by the appended claims.

Claims (22)

1. A phased load regulation system comprising a phased delay array adapted to generate a plurality of phase shifted burst mode signals, wherein each of said phase shifted burst mode signals regulates power to a corresponding load.

2. The phased load regulation system of claim 1 further comprising a modulator that generates a pulse width modulated signal, said phase delay array receiving said pulse width modulated signal, and wherein the power to each load is determined by the pulse width of said pulse width modulated signal.

3. The phased load adjustment system of claim 1, further comprising a frequency selector for receiving a reference signal and generating a frequency select signal based on said reference signal, wherein said phased delay array receives said frequency select signal and sets the frequency of said phase shifted burst mode signal based on said frequency select signal.

4. The phased load adjustment system of claim 2, wherein said modulator further comprises a variable selector for setting a pulse width of said pulse width modulated signal.

5. The phased load regulation system of claim 1, wherein each of said loads comprises a cold cathode fluorescent lamp.

6. The phased load regulation system of claim 1, further comprising a phased array driver circuit to receive the plurality of phase shifted burst mode signals and to generate at least one power regulation signal for each load.

7. The phased load regulation system of claim 6, further comprising a half-bridge switching circuit for receiving the at least one power regulation signal and generating an ac signal based on the at least one power regulation signal to power up the load.

8. The phased load regulation system of claim 6, further comprising a full bridge switching circuit for receiving the at least one power regulation signal and generating an ac signal based on the at least one power regulation signal to energize the load.

9. A computer system comprising a liquid crystal display panel, a plurality of cold cathode fluorescent lamps for illuminating said liquid crystal display panel, and a lamp driving system comprising a phase delay array adapted to generate a plurality of phase shifted burst mode signals, wherein each of said phase shifted burst mode signals adjusts power to each of said plurality of cold cathode fluorescent lamps.

10. The computer system of claim 9 further comprising a modulator that generates a pulse width modulated signal, said phase delay array receiving said pulse width modulated signal, and wherein power to each cold cathode fluorescent lamp is determined by a pulse width of said pulse width modulated signal.

11. The computer system of claim 9, further comprising a frequency selector for receiving a reference signal and generating a frequency selection signal based on the reference signal, wherein the phased delay array receives the frequency selection signal and sets the frequency of the phase shifted burst mode signal based on the frequency selection signal.

12. The computer system of claim 10 wherein said modulator further comprises a variable selector for setting a pulse width of said pulse width modulated signal to set a brightness of each of said cold cathode fluorescent lamps.

13. The computer system of claim 9, further comprising a phased array driver circuit for receiving the plurality of phase shifted burst mode signals and generating at least one power adjustment signal for each cold cathode fluorescent lamp.

14. The computer system of claim 13 further comprising a half-bridge switching circuit for receiving the at least one power adjustment signal and generating an ac signal based on the at least one power adjustment signal to power the ccfl.

15. The computer system of claim 13, further comprising a full bridge switching circuit for receiving the at least one power adjustment signal and generating an ac signal to power the ccfl based on the at least one power adjustment signal.

16. A liquid crystal display panel comprising a plurality of cold cathode fluorescent lamps for illuminating said liquid crystal display panel, and a lamp driving system comprising a phase delay array adapted to generate a plurality of phase shifted burst mode signals, wherein each of said phase shifted burst mode signals adjusts the power to each of said plurality of cold cathode fluorescent lamps.

17. The liquid crystal display panel of claim 16, further comprising a modulator that generates a pulse width modulated signal, the phase delay array receiving the pulse width modulated signal, and wherein the power to each cold cathode fluorescent lamp is determined by the pulse width of the pulse width modulated signal.

18. The liquid crystal display panel of claim 16, further comprising a frequency selector for receiving a reference signal and generating a frequency selection signal based on the reference signal, wherein the phase delay array receives the frequency selection signal and sets the frequency of the phase-shifted burst mode signal based on the frequency selection signal.

19. The liquid crystal display panel of claim 17, wherein the modulator further comprises a variable selector for setting a pulse width of the pulse width modulated signal to set a brightness of each of the cold cathode fluorescent lamps.

20. The liquid crystal display panel of claim 16, further comprising a phased array driver circuit for receiving the plurality of phase shifted burst mode signals and generating at least one power adjustment signal for each cold cathode fluorescent lamp.

21. The liquid crystal display panel of claim 20, further comprising a half-bridge switching circuit for receiving the at least one power adjustment signal and generating an ac signal based on the at least one power adjustment signal to power the ccfl.

22. The lcd panel of claim 20, further comprising a full bridge switching circuit for receiving the at least one power adjustment signal and generating an ac signal based on the at least one power adjustment signal to power up the ccfl.